source: rtems/c/src/libchip/network/sonic.h @ b7111263

4.104.114.84.9
Last change on this file since b7111263 was c9c67390, checked in by Joel Sherrill <joel.sherrill@…>, on Feb 5, 1999 at 12:34:17 AM

Split SONIC chip into appropriate files for libchip'ing. The portable
portion is now in the libchip tree and the dmv177 configuration is in
the dmv177 bsp. The performance impact of libchip'ing this driver
was minimal.

  • Property mode set to 100644
File size: 13.6 KB
Line 
1/*
2 *       RTEMS NETWORK DRIVER FOR NATIONAL DP83932 `SONIC'
3 *         SYSTEMS-ORIENTED NETWORK INTERFACE CONTROLLER
4 *
5 *                REUSABLE CHIP DRIVER CONFIGURATION
6 *
7 * References:
8 *
9 *  1) DP83932C-20/25/33 MHz SONIC(TM) Systems-Oriented Network Interface
10 *     Controller data sheet.  TL/F/10492, RRD-B30M105, National Semiconductor,
11 *     1995.
12 *
13 *  2) Software Driver Programmer's Guide for the DP83932 SONIC(TM),
14 *     Application Note 746, Wesley Lee and Mike Lui, TL/F/11140,
15 *     RRD-B30M75, National Semiconductor, March, 1991.
16 *
17 *  COPYRIGHT (c) 1989-1997.
18 *  On-Line Applications Research Corporation (OAR).
19 *  Copyright assigned to U.S. Government, 1994.
20 *
21 *  The license and distribution terms for this file may be
22 *  found in the file LICENSE in this distribution or at
23 *  http://www.OARcorp.com/rtems/license.html.
24 *
25 *  $Id$
26 */
27
28#ifndef _SONIC_DP83932_
29#define _SONIC_DP83932_
30
31/*
32 *  Configuration Information
33 */
34
35typedef void (*sonic_write_register_t)(
36  void       *base,
37  unsigned32  regno,
38  unsigned32  value
39);
40
41typedef unsigned32 (*sonic_read_register_t)(
42  void       *base,
43  unsigned32  regno
44);
45
46typedef struct {
47  unsigned32              base_address;
48  unsigned32              vector;
49  unsigned32              dcr_value;
50  unsigned32              dc2_value;
51  unsigned32              tda_count;
52  unsigned32              rda_count;
53  sonic_write_register_t  write_register;
54  sonic_read_register_t   read_register;
55} sonic_configuration_t;
56
57/*
58 ******************************************************************
59 *                                                                *
60 *                        Device Registers                        *
61 *                                                                *
62 ******************************************************************
63 */
64#define SONIC_REG_CR      0x00 /* Command */
65#define SONIC_REG_DCR     0x01 /* Data configuration */
66#define SONIC_REG_RCR     0x02 /* Receive control */
67#define SONIC_REG_TCR     0x03 /* Transmit control */
68#define SONIC_REG_IMR     0x04 /* Interrupt mask */
69#define SONIC_REG_ISR     0x05 /* Interrupt status */
70#define SONIC_REG_UTDA    0x06 /* Upper transmit descriptor address */
71#define SONIC_REG_CTDA    0x07 /* Current transmit descriptor address */
72#define SONIC_REG_URDA    0x0D /* Upper receive descriptor address */
73#define SONIC_REG_CRDA    0x0E /* Current receive descriptor address */
74#define SONIC_REG_EOBC    0x13 /* End of buffer word count */
75#define SONIC_REG_URRA    0x14 /* Upper receive resource */
76#define SONIC_REG_RSA     0x15 /* Resource start address */
77#define SONIC_REG_REA     0x16 /* Resource end address */
78#define SONIC_REG_RRP     0x17 /* Resouce read pointer */
79#define SONIC_REG_RWP     0x18 /* Resouce write pointer */
80#define SONIC_REG_CEP     0x21 /* CAM entry pointer */
81#define SONIC_REG_CAP2    0x22 /* CAM address port 2 */
82#define SONIC_REG_CAP1    0x23 /* CAM address port 1 */
83#define SONIC_REG_CAP0    0x24 /* CAM address port 0 */
84#define SONIC_REG_CE      0x25 /* CAM enable */
85#define SONIC_REG_CDP     0x26 /* CAM descriptor pointer */
86#define SONIC_REG_CDC     0x27 /* CAM descriptor count */
87#define SONIC_REG_SR      0x28 /* Silicon revision */
88#define SONIC_REG_WT0     0x29 /* Watchdog timer 0 */
89#define SONIC_REG_WT1     0x2A /* Watchdog timer 1 */
90#define SONIC_REG_RSC     0x2B /* Receive sequence counter */
91#define SONIC_REG_CRCT    0x2C /* CRC error tally */
92#define SONIC_REG_FAET    0x2D /* FAE tally */
93#define SONIC_REG_MPT     0x2E /* Missed packet tally */
94#define SONIC_REG_MDT     0x2F /* TX Maximum Deferral */
95#define SONIC_REG_DCR2    0x3F /* Data configuration 2 */
96
97/*
98 * Command register
99 */
100#define CR_LCAM         0x0200
101#define CR_RRRA         0x0100
102#define CR_RST          0x0080
103#define CR_ST           0x0020
104#define CR_STP          0x0010
105#define CR_RXEN         0x0008
106#define CR_RXDIS        0x0004
107#define CR_TXP          0x0002
108#define CR_HTX          0x0001
109
110/*
111 * Data configuration register
112 */
113#define DCR_EXBUS       0x8000
114#define DCR_LBR         0x2000
115#define DCR_PO1         0x1000
116#define DCR_PO0         0x0800
117#define DCR_SBUS        0x0400
118#define DCR_USR1        0x0200
119#define DCR_USR0        0x0100
120#define DCR_WC1         0x0080
121#define DCR_WC0         0x0040
122#define DCR_DW          0x0020
123#define DCR_BMS         0x0010
124#define DCR_RFT1        0x0008
125#define DCR_RFT0        0x0004
126#define DCR_TFT1        0x0002
127#define DCR_TFT0        0x0001
128
129/* data configuration register aliases */
130#define DCR_SYNC        DCR_SBUS  /* synchronous (memory cycle 2 clocks) */
131#define DCR_ASYNC       0         /* asynchronous (memory cycle 3 clocks) */
132
133#define DCR_WAIT0       0                 /* 0 wait states added */
134#define DCR_WAIT1       DCR_WC0           /* 1 wait state added */
135#define DCR_WAIT2       DCR_WC1           /* 2 wait states added */
136#define DCR_WAIT3       (DCR_WC1|DCR_WC0) /* 3 wait states added */
137
138#define DCR_DW16        0       /* use 16-bit DMA accesses */
139#define DCR_DW32        DCR_DW  /* use 32-bit DMA accesses */
140
141#define DCR_DMAEF       0       /* DMA until TX/RX FIFO has emptied/filled */
142#define DCR_DMABLOCK    DCR_BMS /* DMA until RX/TX threshold crossed */
143
144#define DCR_RFT4        0               /* receive threshold 4 bytes */
145#define DCR_RFT8        DCR_RFT0        /* receive threshold 8 bytes */
146#define DCR_RFT16       DCR_RFT1        /* receive threshold 16 bytes */
147#define DCR_RFT24       (DCR_RFT1|DCR_RFT0) /* receive threshold 24 bytes */
148
149#define DCR_TFT8        0               /* transmit threshold 8 bytes */
150#define DCR_TFT16       DCR_TFT0        /* transmit threshold 16 bytes */
151#define DCR_TFT24       DCR_TFT1        /* transmit threshold 24 bytes */
152#define DCR_TFT28       (DCR_TFT1|DCR_TFT0) /* transmit threshold 28 bytes */
153
154/*
155 * Receive control register
156 */
157#define RCR_ERR         0x8000
158#define RCR_RNT         0x4000
159#define RCR_BRD         0x2000
160#define RCR_PRO         0x1000
161#define RCR_AMC         0x0800
162#define RCR_LB1         0x0400
163#define RCR_LB0         0x0200
164#define RCR_MC          0x0100
165#define RCR_BC          0x0080
166#define RCR_LPKT        0x0040
167#define RCR_CRS         0x0020
168#define RCR_COL         0x0010
169#define RCR_CRCR        0x0008
170#define RCR_FAER        0x0004
171#define RCR_LBK         0x0002
172#define RCR_PRX         0x0001
173
174/*
175 * Transmit control register
176 */
177#define TCR_PINT        0x8000
178#define TCR_POWC        0x4000
179#define TCR_CRCI        0x2000
180#define TCR_EXDIS       0x1000
181#define TCR_EXD         0x0400
182#define TCR_DEF         0x0200
183#define TCR_NCRS        0x0100
184#define TCR_CRSL        0x0080
185#define TCR_EXC         0x0040
186#define TCR_OWC         0x0020
187#define TCR_PMB         0x0008
188#define TCR_FU          0x0004
189#define TCR_BCM         0x0002
190#define TCR_PTX         0x0001
191
192/*
193 * Interrupt mask register
194 */
195#define IMR_BREN        0x4000
196#define IMR_HBLEN       0x2000
197#define IMR_LCDEN       0x1000
198#define IMR_PINTEN      0x0800
199#define IMR_PRXEN       0x0400
200#define IMR_PTXEN       0x0200
201#define IMR_TXEREN      0x0100
202#define IMR_TCEN        0x0080
203#define IMR_RDEEN       0x0040
204#define IMR_RBEEN       0x0020
205#define IMR_RBAEEN      0x0010
206#define IMR_CRCEN       0x0008
207#define IMR_FAEEN       0x0004
208#define IMR_MPEN        0x0002
209#define IMR_RFOEN       0x0001
210
211/*
212 * Interrupt status register
213 */
214#define ISR_BR          0x4000
215#define ISR_HBL         0x2000
216#define ISR_LCD         0x1000
217#define ISR_PINT        0x0800
218#define ISR_PKTRX       0x0400
219#define ISR_TXDN        0x0200
220#define ISR_TXER        0x0100
221#define ISR_TC          0x0080
222#define ISR_RDE         0x0040
223#define ISR_RBE         0x0020
224#define ISR_RBAE        0x0010
225#define ISR_CRC         0x0008
226#define ISR_FAE         0x0004
227#define ISR_MP          0x0002
228#define ISR_RFO         0x0001
229
230/*
231 * Data configuration register 2
232 */
233#define DCR2_EXPO3      0x8000
234#define DCR2_EXPO2      0x4000
235#define DCR2_EXPO1      0x2000
236#define DCR2_EXPO0      0x1000
237#define DCR2_PH         0x0010
238#define DCR2_PCM        0x0004
239#define DCR2_PCNM       0x0002
240#define DCR2_RJCM       0x0001
241
242/*
243 *  Known values for the Silicon Revision Register
244 */
245
246#define SONIC_REVISION_B   4
247#define SONIC_REVISION_C   6
248
249/*
250 ******************************************************************
251 *                                                                *
252 *                   Transmit Buffer Management                   *
253 *                                                                *
254 ******************************************************************
255 */
256
257/*
258 * Transmit descriptor area entry.
259 * There is one transmit descriptor for each packet to be transmitted.
260 * Statically reserve space for up to MAXIMUM_FRAGS_PER_PACKET fragments
261 * per descriptor.
262 */
263#define MAXIMUM_FRAGS_PER_DESCRIPTOR    6
264struct TransmitDescriptor {
265  rtems_unsigned32        status;
266  rtems_unsigned32        pkt_config;
267  rtems_unsigned32        pkt_size;
268  rtems_unsigned32        frag_count;
269
270  /*
271   * Packet fragment pointers
272   */
273  struct TransmitDescriptorFragLink {
274      rtems_unsigned32 frag_lsw;  /* LSW of fragment address */
275#define                      frag_link frag_lsw
276      rtems_unsigned32 frag_msw;  /* MSW of fragment address */
277      rtems_unsigned32 frag_size;
278  }                       frag[MAXIMUM_FRAGS_PER_DESCRIPTOR];
279
280  /*
281   * Space for link if all fragment pointers are used.
282   */
283  rtems_unsigned32        link_pad;
284
285  /*
286   * Extra RTEMS stuff
287   */
288  struct TransmitDescriptor       *next;  /* Circularly-linked list */
289  struct mbuf                     *mbufp; /* First mbuf in packet */
290  volatile rtems_unsigned32       *linkp; /* Pointer to un[xxx].link */
291};
292typedef struct TransmitDescriptor TransmitDescriptor_t;
293typedef volatile TransmitDescriptor_t *TransmitDescriptorPointer_t;
294
295/*
296 * Transmit Configuration.
297 * For standard Ethernet transmission, all bits in the transmit
298 * configuration field are set to 0.
299 */
300#define TDA_CONFIG_PINT 0x8000
301#define TDA_CONFIG_POWC 0x4000
302#define TDA_CONFIG_CRCI 0x2000
303#define TDA_CONFIG_EXDIS        0x1000
304
305/*
306 * Transmit status
307 */
308#define TDA_STATUS_COLLISION_MASK       0xF800
309#define TDA_STATUS_COLLISION_SHIFT      11
310#define TDA_STATUS_EXD          0x0400
311#define TDA_STATUS_DEF          0x0200
312#define TDA_STATUS_NCRS         0x0100
313#define TDA_STATUS_CRSL         0x0080
314#define TDA_STATUS_EXC          0x0040
315#define TDA_STATUS_OWC          0x0020
316#define TDA_STATUS_PMB          0x0008
317#define TDA_STATUS_FU           0x0004
318#define TDA_STATUS_BCM          0x0002
319#define TDA_STATUS_PTX          0x0001
320
321#define TDA_LINK_EOL      0x0001
322#define TDA_LINK_EOL_MASK 0xFFFE
323
324
325
326/*
327 ******************************************************************
328 *                                                                *
329 *                    Receive Buffer Management                   *
330 *                                                                *
331 ******************************************************************
332 */
333
334/*
335 * Receive resource area entry.
336 * There is one receive resource entry for each receive buffer area (RBA).
337 * This driver allows only one packet per receive buffer area, so one
338 * receive resource entry corresponds to one correctly-received packet.
339 */
340struct ReceiveResource {
341  rtems_unsigned32        buff_ptr_lsw;   /* LSW of RBA address */
342  rtems_unsigned32        buff_ptr_msw;   /* MSW of RBA address */
343  rtems_unsigned32        buff_wc_lsw;    /* LSW of RBA size (16-bit words) */
344  rtems_unsigned32        buff_wc_msw;    /* MSW of RBA size (16-bit words) */
345};
346typedef struct ReceiveResource ReceiveResource_t;
347typedef volatile ReceiveResource_t *ReceiveResourcePointer_t;
348
349/*
350 * Receive descriptor area entry.
351 * There is one receive descriptor for each packet received.
352 */
353struct ReceiveDescriptor {
354  rtems_unsigned32        status;
355  rtems_unsigned32        byte_count;
356  rtems_unsigned32        pkt_lsw;        /* LSW of packet address */
357  rtems_unsigned32        pkt_msw;        /* MSW of packet address */
358  rtems_unsigned32        seq_no;
359  rtems_unsigned32        link;
360  rtems_unsigned32        in_use;
361
362  /*
363   * Extra RTEMS stuff
364   */
365  volatile struct ReceiveDescriptor  *next;  /* Circularly-linked list */
366  struct mbuf                        *mbufp; /* First mbuf in packet */
367};
368typedef struct ReceiveDescriptor ReceiveDescriptor_t;
369typedef volatile ReceiveDescriptor_t *ReceiveDescriptorPointer_t;
370
371typedef struct {
372  rtems_unsigned32  cep;  /* CAM Entry Pointer */
373  rtems_unsigned32  cap0; /* CAM Address Port 0 xx-xx-xx-xx-YY-YY */
374  rtems_unsigned32  cap1; /* CAM Address Port 1 xx-xx-YY-YY-xxxx */
375  rtems_unsigned32  cap2; /* CAM Address Port 2 YY-YY-xx-xx-xx-xx */
376  rtems_unsigned32  ce;
377} CamDescriptor_t;
378
379typedef volatile CamDescriptor_t *CamDescriptorPointer_t;
380
381/*
382 * Receive status
383 */
384#define RDA_STATUS_ERR          0x8800
385#define RDA_STATUS_RNT          0x4000
386#define RDA_STATUS_BRD          0x2000
387#define RDA_STATUS_PRO          0x1000
388#define RDA_STATUS_AMC          0x0800
389#define RDA_STATUS_LB1          0x0400
390#define RDA_STATUS_LB0          0x0200
391#define RDA_STATUS_MC           0x0100
392#define RDA_STATUS_BC           0x0080
393#define RDA_STATUS_LPKT         0x0040
394#define RDA_STATUS_CRS          0x0020
395#define RDA_STATUS_COL          0x0010
396#define RDA_STATUS_CRCR         0x0008
397#define RDA_STATUS_FAER         0x0004
398#define RDA_STATUS_LBK          0x0002
399#define RDA_STATUS_PRX          0x0001
400
401#define RDA_LINK_EOL        0x0001
402#define RDA_LINK_EOL_MASK   0xFFFE
403#define RDA_IN_USE          0x0000  /* SONIC has finished with the packet */
404                                    /*   and the driver can process it */
405#define RDA_FREE            0xFFFF  /* SONIC can use it */
406 
407/*
408 *  Attatch routine
409 */
410
411int rtems_sonic_driver_attach (
412  struct rtems_bsdnet_ifconfig *config,
413  sonic_configuration_t *chip
414);
415
416#endif /* _SONIC_DP83932_ */
Note: See TracBrowser for help on using the repository browser.