1 | /* |
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2 | * $Id$ |
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3 | */ |
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4 | |
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5 | #ifndef _SMC91111_H_ |
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6 | #define _SMC91111_H_ |
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7 | |
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8 | #include <libchip/smc91111exp.h> |
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9 | #include <rtems/bspIo.h> |
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10 | |
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11 | #define LAN91CXX_TCR 0x00 |
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12 | #define LAN91CXX_EPH_STATUS 0x01 |
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13 | #define LAN91CXX_RCR 0x02 |
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14 | #define LAN91CXX_COUNTER 0x03 |
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15 | #define LAN91CXX_MIR 0x04 |
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16 | #define LAN91CXX_MCR 0x05 /* Other than 91C111*/ |
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17 | #define LAN91CXX_RPCR 0x05 /* 91C111 only*/ |
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18 | #define LAN91CXX_RESERVED_0 0x06 |
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19 | #define LAN91CXX_BS 0x07 |
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20 | #define LAN91CXX_CONFIG 0x08 |
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21 | #define LAN91CXX_BASE_REG 0x09 |
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22 | #define LAN91CXX_IA01 0x0a |
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23 | #define LAN91CXX_IA23 0x0b |
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24 | #define LAN91CXX_IA45 0x0c |
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25 | #define LAN91CXX_GENERAL 0x0d /* 91C96 - was "RESERVED_1" for others*/ |
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26 | #define LAN91CXX_CONTROL 0x0e |
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27 | #define LAN91CXX_BS2 0x0f |
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28 | #define LAN91CXX_MMU_COMMAND 0x10 |
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29 | #define LAN91CXX_PNR 0x11 |
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30 | #define LAN91CXX_FIFO_PORTS 0x12 |
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31 | #define LAN91CXX_POINTER 0x13 |
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32 | #define LAN91CXX_DATA_HIGH 0x14 |
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33 | #define LAN91CXX_DATA 0x15 |
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34 | #define LAN91CXX_INTERRUPT 0x16 |
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35 | #define LAN91CXX_BS3 0x17 |
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36 | #define LAN91CXX_MT01 0x18 |
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37 | #define LAN91CXX_MT23 0x19 |
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38 | #define LAN91CXX_MT45 0x1a |
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39 | #define LAN91CXX_MT67 0x1b |
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40 | #define LAN91CXX_MGMT 0x1c |
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41 | #define LAN91CXX_REVISION 0x1d |
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42 | #define LAN91CXX_ERCV 0x1e |
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43 | #define LAN91CXX_BS4 0x1f |
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44 | |
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45 | #define LAN91CXX_RCR_SOFT_RST 0x8000 /* soft reset*/ |
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46 | #define LAN91CXX_RCR_FILT_CAR 0x4000 /* filter carrier*/ |
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47 | #define LAN91CXX_RCR_ABORT_ENB 0x2000 /* abort on collision*/ |
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48 | #define LAN91CXX_RCR_STRIP_CRC 0x0200 /* strip CRC*/ |
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49 | #define LAN91CXX_RCR_RXEN 0x0100 /* enable RX*/ |
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50 | #define LAN91CXX_RCR_ALMUL 0x0004 /* receive all muticasts*/ |
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51 | #define LAN91CXX_RCR_PRMS 0x0002 /* promiscuous*/ |
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52 | #define LAN91CXX_RCR_RX_ABORT 0x0001 /* set when abort due to long frame*/ |
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53 | |
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54 | #define LAN91CXX_TCR_SWFDUP 0x8000 /* Switched Full Duplex mode*/ |
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55 | #define LAN91CXX_TCR_ETEN_TYPE 0x4000 /* ETEN type (91C96) 0 <=> like a 91C94*/ |
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56 | #define LAN91CXX_TCR_EPH_LOOP 0x2000 /* loopback mode*/ |
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57 | #define LAN91CXX_TCR_STP_SQET 0x1000 /* Stop transmission on SQET error*/ |
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58 | #define LAN91CXX_TCR_FDUPLX 0x0800 /* full duplex*/ |
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59 | #define LAN91CXX_TCR_MON_CSN 0x0400 /* monitor carrier during tx (91C96)*/ |
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60 | #define LAN91CXX_TCR_NOCRC 0x0100 /* does not append CRC to frames*/ |
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61 | #define LAN91CXX_TCR_PAD_EN 0x0080 /* pads frames with 00 to min length*/ |
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62 | #define LAN91CXX_TCR_FORCOL 0x0004 /* force collision*/ |
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63 | #define LAN91CXX_TCR_LLOOP 0x0002 /* local loopback (91C96)*/ |
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64 | #define LAN91CXX_TCR_TXENA 0x0001 /* enable*/ |
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65 | |
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66 | #define LAN91CXX_POINTER_RCV 0x8000 |
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67 | #define LAN91CXX_POINTER_AUTO_INCR 0x4000 |
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68 | #define LAN91CXX_POINTER_READ 0x2000 |
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69 | #define LAN91CXX_POINTER_ETEN 0x1000 |
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70 | #define LAN91CXX_POINTER_NOT_EMPTY 0x0800 |
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71 | |
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72 | |
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73 | #define LAN91CXX_INTERRUPT_TX_IDLE_M 0x8000 /* (91C96)*/ |
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74 | #define LAN91CXX_INTERRUPT_ERCV_INT_M 0x4000 |
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75 | #define LAN91CXX_INTERRUPT_EPH_INT_M 0x2000 |
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76 | #define LAN91CXX_INTERRUPT_RX_OVRN_INT_M 0x1000 |
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77 | #define LAN91CXX_INTERRUPT_ALLOC_INT_M 0x0800 |
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78 | #define LAN91CXX_INTERRUPT_TX_EMPTY_INT_M 0x0400 |
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79 | #define LAN91CXX_INTERRUPT_TX_INT_M 0x0200 |
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80 | #define LAN91CXX_INTERRUPT_RCV_INT_M 0x0100 |
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81 | #define LAN91CXX_INTERRUPT_TX_IDLE 0x0080 /* (91C96)*/ |
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82 | #define LAN91CXX_INTERRUPT_ERCV_INT 0x0040 /* also ack*/ |
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83 | #define LAN91CXX_INTERRUPT_EPH_INT 0x0020 |
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84 | #define LAN91CXX_INTERRUPT_RX_OVRN_INT 0x0010 /* also ack*/ |
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85 | #define LAN91CXX_INTERRUPT_ALLOC_INT 0x0008 |
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86 | #define LAN91CXX_INTERRUPT_TX_EMPTY_INT 0x0004 /* also ack*/ |
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87 | #define LAN91CXX_INTERRUPT_TX_INT 0x0002 /* also ack*/ |
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88 | #define LAN91CXX_INTERRUPT_RCV_INT 0x0001 |
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89 | |
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90 | #define LAN91CXX_INTERRUPT_TX_SET 0x0006 /* TX_EMPTY + TX*/ |
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91 | #define LAN91CXX_INTERRUPT_TX_SET_ACK 0x0004 /* TX_EMPTY and not plain TX*/ |
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92 | #define LAN91CXX_INTERRUPT_TX_FIFO_ACK 0x0002 /* TX alone*/ |
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93 | #define LAN91CXX_INTERRUPT_TX_SET_M 0x0600 /* TX_EMPTY + TX*/ |
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94 | |
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95 | #define LAN91CXX_CONTROL_RCV_BAD 0x4000 |
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96 | #define LAN91CXX_CONTROL_AUTO_RELEASE 0x0800 |
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97 | #define LAN91CXX_CONTROL_LE_ENABLE 0x0080 |
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98 | #define LAN91CXX_CONTROL_CR_ENABLE 0x0040 |
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99 | #define LAN91CXX_CONTROL_TE_ENABLE 0x0020 |
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100 | |
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101 | /* These are for setting the MAC address in the 91C96 serial EEPROM*/ |
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102 | #define LAN91CXX_CONTROL_EEPROM_SELECT 0x0004 |
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103 | #define LAN91CXX_CONTROL_RELOAD 0x0002 |
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104 | #define LAN91CXX_CONTROL_STORE 0x0001 |
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105 | #define LAN91CXX_CONTROL_EEPROM_BUSY 0x0003 |
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106 | #define LAN91CXX_ESA_EEPROM_OFFSET 0x0020 |
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107 | |
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108 | #define LAN91CXX_STATUS_TX_UNRN 0x8000 |
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109 | #define LAN91CXX_STATUS_LINK_OK 0x4000 |
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110 | #define LAN91CXX_STATUS_CTR_ROL 0x1000 |
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111 | #define LAN91CXX_STATUS_EXC_DEF 0x0800 |
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112 | #define LAN91CXX_STATUS_LOST_CARR 0x0400 |
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113 | #define LAN91CXX_STATUS_LATCOL 0x0200 |
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114 | #define LAN91CXX_STATUS_WAKEUP 0x0100 |
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115 | #define LAN91CXX_STATUS_TX_DEFR 0x0080 |
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116 | #define LAN91CXX_STATUS_LTX_BRD 0x0040 |
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117 | #define LAN91CXX_STATUS_SQET 0x0020 |
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118 | #define LAN91CXX_STATUS_16COL 0x0010 |
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119 | #define LAN91CXX_STATUS_LTX_MULT 0x0008 |
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120 | #define LAN91CXX_STATUS_MUL_COL 0x0004 |
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121 | #define LAN91CXX_STATUS_SNGL_COL 0x0002 |
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122 | #define LAN91CXX_STATUS_TX_SUC 0x0001 |
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123 | |
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124 | #define LAN91CXX_MMU_COMMAND_BUSY 0x0001 |
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125 | |
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126 | #define LAN91CXX_MMU_noop 0x0000 |
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127 | #define LAN91CXX_MMU_alloc_for_tx 0x0020 |
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128 | #define LAN91CXX_MMU_reset_mmu 0x0040 |
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129 | #define LAN91CXX_MMU_rem_rx_frame 0x0060 |
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130 | #define LAN91CXX_MMU_rem_tx_frame 0x0070 /* (91C96) only when TX stopped*/ |
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131 | #define LAN91CXX_MMU_remrel_rx_frame 0x0080 |
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132 | #define LAN91CXX_MMU_rel_packet 0x00a0 |
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133 | #define LAN91CXX_MMU_enq_packet 0x00c0 |
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134 | #define LAN91CXX_MMU_reset_tx_fifo 0x00e0 |
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135 | |
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136 | #define LAN91CXX_CONTROLBYTE_CRC 0x1000 |
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137 | #define LAN91CXX_CONTROLBYTE_ODD 0x2000 |
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138 | #define LAN91CXX_CONTROLBYTE_RX 0x4000 |
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139 | |
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140 | #define LAN91CXX_RX_STATUS_ALIGNERR 0x8000 |
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141 | #define LAN91CXX_RX_STATUS_BCAST 0x4000 |
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142 | #define LAN91CXX_RX_STATUS_BADCRC 0x2000 |
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143 | #define LAN91CXX_RX_STATUS_ODDFRM 0x1000 |
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144 | #define LAN91CXX_RX_STATUS_TOOLONG 0x0800 |
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145 | #define LAN91CXX_RX_STATUS_TOOSHORT 0x0400 |
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146 | #define LAN91CXX_RX_STATUS_HASHVALMASK 0x007e /* MASK*/ |
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147 | #define LAN91CXX_RX_STATUS_MCAST 0x0001 |
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148 | #define LAN91CXX_RX_STATUS_BAD \ |
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149 | (LAN91CXX_RX_STATUS_ALIGNERR | \ |
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150 | LAN91CXX_RX_STATUS_BADCRC | \ |
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151 | LAN91CXX_RX_STATUS_TOOLONG | \ |
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152 | LAN91CXX_RX_STATUS_TOOSHORT) |
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153 | |
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154 | #define LAN91CXX_RX_STATUS_IS_ODD(__cpd,__stat) ((__stat) & LAN91CXX_RX_STATUS_ODDFRM) |
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155 | #define LAN91CXX_CONTROLBYTE_IS_ODD(__cpd,__val) ((__val) & LAN91CXX_CONTROLBYTE_ODD) |
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156 | |
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157 | /* Attribute memory registers in PCMCIA mode*/ |
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158 | #define LAN91CXX_ECOR 0x8000 |
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159 | #define LAN91CXX_ECOR_RESET (1<<7) |
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160 | #define LAN91CXX_ECOR_LEVIRQ (1<<6) |
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161 | #define LAN91CXX_ECOR_ATTWR (1<<2) |
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162 | #define LAN91CXX_ECOR_ENABLE (1<<0) |
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163 | |
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164 | #define LAN91CXX_ECSR 0x8002 |
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165 | #define LAN91CXX_ECSR_IOIS8 (1<<5) |
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166 | #define LAN91CXX_ECSR_PWRDWN (1<<2) |
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167 | #define LAN91CXX_ECSR_INTR (1<<1) |
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168 | |
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169 | /* These are for manipulating the MII interface*/ |
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170 | #define LAN91CXX_MGMT_MDO 0x0001 |
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171 | #define LAN91CXX_MGMT_MDI 0x0002 |
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172 | #define LAN91CXX_MGMT_MCLK 0x0004 |
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173 | #define LAN91CXX_MGMT_MDOE 0x0008 |
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174 | |
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175 | /* Internal PHY registers (91c111)*/ |
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176 | #define LAN91CXX_PHY_CTRL 0 |
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177 | #define LAN91CXX_PHY_STAT 1 |
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178 | #define LAN91CXX_PHY_ID1 2 |
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179 | #define LAN91CXX_PHY_ID2 3 |
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180 | #define LAN91CXX_PHY_AUTO_AD 4 |
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181 | #define LAN91CXX_PHY_AUTO_CAP 5 |
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182 | #define LAN91CXX_PHY_CONFIG1 16 |
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183 | #define LAN91CXX_PHY_CONFIG2 17 |
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184 | #define LAN91CXX_PHY_STATUS_OUT 18 |
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185 | #define LAN91CXX_PHY_MASK 19 |
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186 | |
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187 | /* PHY control bits*/ |
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188 | #define LAN91CXX_PHY_CTRL_COLTST (1 << 7) |
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189 | #define LAN91CXX_PHY_CTRL_DPLX (1 << 8) |
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190 | #define LAN91CXX_PHY_CTRL_ANEG_RST (1 << 9) |
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191 | #define LAN91CXX_PHY_CTRL_MII_DIS (1 << 10) |
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192 | #define LAN91CXX_PHY_CTRL_PDN (1 << 11) |
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193 | #define LAN91CXX_PHY_CTRL_ANEG_EN (1 << 12) |
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194 | #define LAN91CXX_PHY_CTRL_SPEED (1 << 13) |
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195 | #define LAN91CXX_PHY_CTRL_LPBK (1 << 14) |
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196 | #define LAN91CXX_PHY_CTRL_RST (1 << 15) |
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197 | |
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198 | /* PHY Configuration Register 1 */ |
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199 | #define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */ |
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200 | #define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */ |
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201 | #define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */ |
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202 | #define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */ |
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203 | #define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */ |
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204 | #define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */ |
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205 | #define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */ |
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206 | #define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */ |
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207 | #define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */ |
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208 | #define PHY_CFG1_TLVL_MASK 0x003C |
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209 | #define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */ |
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210 | |
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211 | /* PHY Configuration Register 2 */ |
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212 | #define PHY_CFG2_REG 0x11 |
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213 | #define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */ |
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214 | #define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */ |
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215 | #define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */ |
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216 | #define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */ |
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217 | |
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218 | /* PHY Status Output (and Interrupt status) Register */ |
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219 | #define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */ |
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220 | #define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */ |
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221 | #define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */ |
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222 | #define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */ |
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223 | #define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */ |
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224 | #define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */ |
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225 | #define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */ |
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226 | #define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */ |
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227 | #define PHY_INT_JAB 0x0100 /* 1=Jabber detected */ |
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228 | #define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */ |
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229 | #define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */ |
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230 | |
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231 | /* PHY Interrupt/Status Mask Register */ |
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232 | #define PHY_MASK_REG 0x13 /* Interrupt Mask */ |
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233 | |
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234 | #define LAN91CXX_RPCR_LEDA_LINK (0 << 2) |
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235 | #define LAN91CXX_RPCR_LEDA_TXRX (4 << 2) |
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236 | #define LAN91CXX_RPCR_LEDA_RX (6 << 2) |
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237 | #define LAN91CXX_RPCR_LEDA_TX (7 << 2) |
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238 | #define LAN91CXX_RPCR_LEDB_LINK (0 << 5) |
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239 | #define LAN91CXX_RPCR_LEDB_TXRX (4 << 5) |
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240 | #define LAN91CXX_RPCR_LEDB_RX (6 << 5) |
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241 | #define LAN91CXX_RPCR_LEDB_TX (7 << 5) |
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242 | #define LAN91CXX_RPCR_ANEG (1 << 11) |
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243 | #define LAN91CXX_RPCR_DPLX (1 << 12) |
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244 | #define LAN91CXX_RPCR_SPEED (1 << 13) |
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245 | |
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246 | /* PHY Control Register */ |
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247 | #define PHY_CNTL_REG 0x00 |
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248 | #define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */ |
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249 | #define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */ |
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250 | #define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */ |
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251 | #define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */ |
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252 | #define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */ |
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253 | #define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */ |
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254 | #define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */ |
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255 | #define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */ |
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256 | #define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */ |
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257 | |
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258 | /* PHY Status Register */ |
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259 | #define PHY_STAT_REG 0x01 |
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260 | #define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */ |
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261 | #define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */ |
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262 | #define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */ |
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263 | #define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */ |
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264 | #define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */ |
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265 | #define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */ |
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266 | #define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */ |
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267 | #define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */ |
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268 | #define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */ |
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269 | #define PHY_STAT_LINK 0x0004 /* 1=valid link */ |
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270 | #define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */ |
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271 | #define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */ |
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272 | #define PHY_STAT_RESERVED 0x0780 /* Reserved bits mask. */ |
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273 | |
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274 | /* PHY Identifier Registers */ |
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275 | #define PHY_ID1_REG 0x02 /* PHY Identifier 1 */ |
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276 | #define PHY_ID2_REG 0x03 /* PHY Identifier 2 */ |
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277 | |
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278 | /* PHY Auto-Negotiation Advertisement Register */ |
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279 | #define PHY_AD_REG 0x04 |
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280 | #define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */ |
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281 | #define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */ |
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282 | #define PHY_AD_RF 0x2000 /* 1=advertise remote fault */ |
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283 | #define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */ |
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284 | #define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */ |
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285 | #define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */ |
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286 | #define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */ |
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287 | #define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */ |
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288 | #define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */ |
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289 | |
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290 | |
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291 | static int debugflag_out = 0; |
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292 | |
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293 | #define dbc_printf(lvl,format, args...) do { \ |
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294 | if (!debugflag_out) { \ |
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295 | if (lvl & DEBUG) { \ |
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296 | printk(format,##args); \ |
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297 | } \ |
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298 | } \ |
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299 | } while(0) |
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300 | |
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301 | #define db64_printf(format, args...) dbc_printf(64,format,##args); |
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302 | #define db16_printf(format, args...) dbc_printf(16,format,##args); |
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303 | #define db9_printf(format, args...) dbc_printf(9,format,##args); |
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304 | #define db4_printf(format, args...) dbc_printf(4,format,##args); |
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305 | #define db2_printf(format, args...) dbc_printf(2,format,##args); |
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306 | #define db1_printf(format, args...) dbc_printf(1,format,##args); |
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307 | #define db_printf(format, args...) dbc_printf(0xffff,format,##args); |
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308 | |
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309 | #if DEBUG & 1 |
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310 | #define DEBUG_FUNCTION() do { db_printf("# %s\n", __FUNCTION__); } while (0) |
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311 | #else |
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312 | #define DEBUG_FUNCTION() do {} while(0) |
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313 | #endif |
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314 | |
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315 | |
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316 | /* ------------------------------------------------------------------------*/ |
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317 | |
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318 | struct smsc_lan91cxx_stats { |
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319 | unsigned int tx_good ; |
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320 | unsigned int tx_max_collisions ; |
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321 | unsigned int tx_late_collisions ; |
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322 | unsigned int tx_underrun ; |
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323 | unsigned int tx_carrier_loss ; |
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324 | unsigned int tx_deferred ; |
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325 | unsigned int tx_sqetesterrors ; |
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326 | unsigned int tx_single_collisions; |
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327 | unsigned int tx_mult_collisions ; |
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328 | unsigned int tx_total_collisions ; |
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329 | unsigned int rx_good ; |
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330 | unsigned int rx_crc_errors ; |
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331 | unsigned int rx_align_errors ; |
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332 | unsigned int rx_resource_errors ; |
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333 | unsigned int rx_overrun_errors ; |
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334 | unsigned int rx_collisions ; |
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335 | unsigned int rx_short_frames ; |
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336 | unsigned int rx_too_long_frames ; |
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337 | unsigned int rx_symbol_errors ; |
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338 | unsigned int interrupts ; |
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339 | unsigned int rx_count ; |
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340 | unsigned int rx_deliver ; |
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341 | unsigned int rx_resource ; |
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342 | unsigned int rx_restart ; |
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343 | unsigned int tx_count ; |
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344 | unsigned int tx_complete ; |
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345 | unsigned int tx_dropped ; |
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346 | }; |
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347 | #define INCR_STAT(c,n) (((c)->stats.n)++) |
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348 | |
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349 | struct lan91cxx_priv_data; |
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350 | |
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351 | typedef struct lan91cxx_priv_data { |
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352 | |
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353 | /* frontend */ |
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354 | struct arpcom arpcom; |
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355 | rtems_id rxDaemonTid; |
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356 | rtems_id txDaemonTid; |
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357 | |
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358 | scmv91111_configuration_t config; |
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359 | |
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360 | /* backend */ |
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361 | int rpc_cur_mode; |
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362 | int autoneg_active; |
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363 | int phyaddr; |
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364 | unsigned int lastPhy18; |
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365 | |
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366 | int txbusy; /* A packet has been sent*/ |
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367 | unsigned long txkey; /* Used to ack when packet sent*/ |
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368 | unsigned short* base; /* Base I/O address of controller*/ |
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369 | /* (as it comes out of reset)*/ |
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370 | int interrupt; /* Interrupt vector used by controller*/ |
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371 | unsigned char enaddr[6]; /* Controller ESA*/ |
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372 | /* Function to configure the ESA - may fetch ESA from EPROM or */ |
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373 | /* RedBoot config option. Use of the 'config_enaddr()' function*/ |
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374 | /* is depreciated in favor of the 'provide_esa()' function and*/ |
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375 | /* 'hardwired_esa' boolean*/ |
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376 | void (*config_enaddr)(struct lan91cxx_priv_data* cpd); |
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377 | int hardwired_esa; |
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378 | int txpacket; |
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379 | int rxpacket; |
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380 | int within_send; |
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381 | int c111_reva; /* true if this is a revA LAN91C111*/ |
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382 | struct smsc_lan91cxx_stats stats; |
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383 | } lan91cxx_priv_data; |
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384 | |
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385 | /* ------------------------------------------------------------------------*/ |
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386 | |
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387 | #ifdef LAN91CXX_32BIT_RX |
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388 | typedef unsigned int rxd_t; |
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389 | #else |
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390 | typedef unsigned short rxd_t; |
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391 | #endif |
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392 | |
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393 | typedef struct _debug_regs_pair { |
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394 | int reg; char *name; struct _debug_regs_pair *bits; |
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395 | } debug_regs_pair; |
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396 | |
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397 | static debug_regs_pair debug_regs[] = { |
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398 | {LAN91CXX_TCR , "LAN91CXX_TCR" ,0}, |
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399 | {LAN91CXX_EPH_STATUS , "LAN91CXX_EPH_STATUS",0}, |
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400 | {LAN91CXX_RCR , "LAN91CXX_RCR" ,0}, |
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401 | {LAN91CXX_COUNTER , "LAN91CXX_COUNTER" ,0}, |
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402 | {LAN91CXX_MIR , "LAN91CXX_MIR" ,0}, |
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403 | {LAN91CXX_MCR , "LAN91CXX_MCR" ,0}, |
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404 | {LAN91CXX_RPCR , "LAN91CXX_RPCR" ,0}, |
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405 | {LAN91CXX_RESERVED_0 , "LAN91CXX_RESERVED_0",0}, |
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406 | {LAN91CXX_BS , "LAN91CXX_BS" ,0}, |
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407 | {LAN91CXX_CONFIG , "LAN91CXX_CONFIG" ,0}, |
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408 | {LAN91CXX_BASE_REG , "LAN91CXX_BASE_REG" ,0}, |
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409 | {LAN91CXX_IA01 , "LAN91CXX_IA01" ,0}, |
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410 | {LAN91CXX_IA23 , "LAN91CXX_IA23" ,0}, |
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411 | {LAN91CXX_IA45 , "LAN91CXX_IA45" ,0}, |
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412 | {LAN91CXX_GENERAL , "LAN91CXX_GENERAL" ,0}, |
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413 | {LAN91CXX_CONTROL , "LAN91CXX_CONTROL" ,0}, |
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414 | {LAN91CXX_BS2 , "LAN91CXX_BS2" ,0}, |
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415 | {LAN91CXX_MMU_COMMAND, "LAN91CXX_MMU_COMMAND",0}, |
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416 | {LAN91CXX_PNR , "LAN91CXX_PNR" ,0}, |
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417 | {LAN91CXX_FIFO_PORTS , "LAN91CXX_FIFO_PORTS" ,0}, |
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418 | {LAN91CXX_POINTER , "LAN91CXX_POINTER" ,0}, |
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419 | {LAN91CXX_DATA_HIGH , "LAN91CXX_DATA_HIGH" ,0}, |
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420 | {LAN91CXX_DATA , "LAN91CXX_DATA" ,0}, |
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421 | {LAN91CXX_INTERRUPT , "LAN91CXX_INTERRUPT" ,0}, |
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422 | {LAN91CXX_BS3 , "LAN91CXX_BS3" ,0}, |
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423 | {LAN91CXX_MT01 , "LAN91CXX_MT01" ,0}, |
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424 | {LAN91CXX_MT23 , "LAN91CXX_MT23" ,0}, |
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425 | {LAN91CXX_MT45 , "LAN91CXX_MT45" ,0}, |
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426 | {LAN91CXX_MT67 , "LAN91CXX_MT67" ,0}, |
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427 | /*{LAN91CXX_MGMT , "LAN91CXX_MGMT" ,0}, */ |
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428 | {LAN91CXX_REVISION , "LAN91CXX_REVISION" ,0}, |
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429 | {LAN91CXX_ERCV , "LAN91CXX_ERCV" ,0}, |
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430 | {LAN91CXX_BS4 , "LAN91CXX_BS4" ,0}, |
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431 | |
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432 | |
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433 | |
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434 | {-1,0} |
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435 | }; |
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436 | |
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437 | static char *dbg_prefix = ""; |
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438 | |
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439 | #ifndef SMSC_PLATFORM_DEFINED_GET_REG |
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440 | static __inline__ unsigned short |
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441 | get_reg(struct lan91cxx_priv_data *cpd, int regno) |
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442 | { |
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443 | unsigned short val; debug_regs_pair *dbg = debug_regs; int c; |
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444 | uint32_t Irql; |
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445 | |
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446 | /*rtems_interrupt_disable(Irql);*/ |
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447 | |
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448 | HAL_WRITE_UINT16(cpd->base+(LAN91CXX_BS), CYG_CPU_TO_LE16(regno>>3)); |
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449 | HAL_READ_UINT16(cpd->base+((regno&0x7)), val); |
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450 | val = CYG_LE16_TO_CPU(val); |
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451 | |
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452 | /*rtems_interrupt_enable(Irql);*/ |
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453 | |
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454 | #ifdef DEBUG & 32 |
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455 | while ((c = dbg->reg) != -1) { |
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456 | if (c == regno) { |
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457 | db_printf("%sread reg [%d:%x] -> 0x%04x (%-20s)\n", dbg_prefix, regno>>3,(regno&0x7)*2, val, dbg->name); |
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458 | break; |
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459 | } |
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460 | dbg++; |
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461 | } |
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462 | #else |
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463 | db2_printf("%sread reg %d:%x -> 0x%04x\n", dbg_prefix, regno>>3,(regno&0x7)*2, val); |
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464 | #endif |
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465 | |
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466 | return val; |
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467 | } |
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468 | #endif /* SMSC_PLATFORM_DEFINED_GET_REG*/ |
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469 | |
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470 | #ifndef SMSC_PLATFORM_DEFINED_PUT_REG |
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471 | static __inline__ void |
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472 | put_reg(struct lan91cxx_priv_data *cpd, int regno, unsigned short val) |
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473 | { |
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474 | debug_regs_pair *dbg = debug_regs; int c; |
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475 | uint32_t Irql; |
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476 | |
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477 | #ifdef DEBUG & 32 |
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478 | while ((c = dbg->reg) != -1) { |
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479 | if (c == regno) { |
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480 | db_printf("%swrite reg [%d:%x] <- 0x%04x (%-20s)\n", dbg_prefix, regno>>3, (regno&0x07)*2, val, dbg->name); |
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481 | break; |
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482 | } |
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483 | dbg++; |
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484 | } |
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485 | #else |
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486 | db2_printf("%swrite reg %d:%x <- 0x%04x\n", dbg_prefix, regno>>3,(regno&0x7)*2, val); |
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487 | #endif |
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488 | |
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489 | /*rtems_interrupt_disable(Irql);*/ |
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490 | |
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491 | HAL_WRITE_UINT16(cpd->base+(LAN91CXX_BS), CYG_CPU_TO_LE16(regno>>3)); |
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492 | HAL_WRITE_UINT16(cpd->base+((regno&0x7)), CYG_CPU_TO_LE16(val)); |
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493 | |
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494 | /*rtems_interrupt_enable(Irql);*/ |
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495 | |
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496 | } |
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497 | #endif /* SMSC_PLATFORM_DEFINED_PUT_REG*/ |
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498 | |
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499 | #ifndef SMSC_PLATFORM_DEFINED_PUT_DATA |
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500 | /* ------------------------------------------------------------------------*/ |
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501 | /* Assumes bank2 has been selected*/ |
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502 | static __inline__ void |
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503 | put_data(struct lan91cxx_priv_data *cpd, unsigned short val) |
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504 | { |
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505 | db2_printf("%s[wdata] <- 0x%04x\n", dbg_prefix, val); |
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506 | |
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507 | HAL_WRITE_UINT16(cpd->base+((LAN91CXX_DATA & 0x7)), val); |
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508 | |
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509 | } |
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510 | |
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511 | /* Assumes bank2 has been selected*/ |
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512 | static __inline__ void |
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513 | put_data8(struct lan91cxx_priv_data *cpd, unsigned char val) |
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514 | { |
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515 | db2_printf("%s[bdata] <- 0x%02x\n", dbg_prefix, val); |
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516 | |
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517 | HAL_WRITE_UINT8(((unsigned char *)(cpd->base+((LAN91CXX_DATA & 0x7))))+1, val); |
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518 | |
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519 | } |
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520 | |
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521 | #endif /* SMSC_PLATFORM_DEFINED_PUT_DATA*/ |
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522 | |
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523 | #ifndef SMSC_PLATFORM_DEFINED_GET_DATA |
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524 | /* Assumes bank2 has been selected*/ |
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525 | static __inline__ rxd_t |
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526 | get_data(struct lan91cxx_priv_data *cpd) |
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527 | { |
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528 | rxd_t val; |
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529 | |
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530 | #ifdef LAN91CXX_32BIT_RX |
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531 | HAL_READ_UINT32(cpd->base+((LAN91CXX_DATA_HIGH & 0x7)), val); |
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532 | #else |
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533 | HAL_READ_UINT16(cpd->base+((LAN91CXX_DATA & 0x7)), val); |
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534 | #endif |
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535 | |
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536 | db2_printf("%s[rdata] -> 0x%08x\n", dbg_prefix, val); |
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537 | return val; |
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538 | } |
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539 | #endif /* SMSC_PLATFORM_DEFINED_GET_DATA*/ |
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540 | |
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541 | /* ------------------------------------------------------------------------*/ |
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542 | /* Read the bank register (this one is bank-independent)*/ |
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543 | #ifndef SMSC_PLATFORM_DEFINED_GET_BANKSEL |
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544 | static __inline__ unsigned short |
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545 | get_banksel(struct lan91cxx_priv_data *cpd) |
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546 | { |
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547 | unsigned short val; |
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548 | |
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549 | HAL_READ_UINT16(cpd->base+(LAN91CXX_BS), val); |
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550 | val = CYG_LE16_TO_CPU(val); |
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551 | db2_printf("read bank sel val 0x%04x\n", val); |
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552 | return val; |
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553 | } |
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554 | #endif |
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555 | |
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556 | |
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557 | |
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558 | |
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559 | |
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560 | #endif /* _SMC_91111_H_ */ |
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561 | |
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562 | |
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