source: rtems/c/src/libchip/network/smc91111.h @ b00e693

4.104.114.84.95
Last change on this file since b00e693 was b00e693, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 17, 2007 at 2:10:57 PM

2007-09-17 Joel Sherrill <joel.sherrill@…>

  • libchip/network/smc91111.h: Eliminate DEBUG_puts.
  • Property mode set to 100644
File size: 21.3 KB
Line 
1/*
2 *  $Id$
3 */
4
5#ifndef _SMC91111_H_
6#define _SMC91111_H_
7
8#include <libchip/smc91111exp.h>
9#include <rtems/bspIo.h>
10
11#define LAN91CXX_TCR         0x00
12#define LAN91CXX_EPH_STATUS  0x01
13#define LAN91CXX_RCR         0x02
14#define LAN91CXX_COUNTER     0x03
15#define LAN91CXX_MIR         0x04
16#define LAN91CXX_MCR         0x05 /* Other than 91C111*/
17#define LAN91CXX_RPCR        0x05 /* 91C111 only*/
18#define LAN91CXX_RESERVED_0  0x06
19#define LAN91CXX_BS          0x07
20#define LAN91CXX_CONFIG      0x08
21#define LAN91CXX_BASE_REG    0x09
22#define LAN91CXX_IA01        0x0a
23#define LAN91CXX_IA23        0x0b
24#define LAN91CXX_IA45        0x0c
25#define LAN91CXX_GENERAL     0x0d /* 91C96 - was "RESERVED_1" for others*/
26#define LAN91CXX_CONTROL     0x0e
27#define LAN91CXX_BS2         0x0f
28#define LAN91CXX_MMU_COMMAND 0x10
29#define LAN91CXX_PNR         0x11
30#define LAN91CXX_FIFO_PORTS  0x12
31#define LAN91CXX_POINTER     0x13
32#define LAN91CXX_DATA_HIGH   0x14
33#define LAN91CXX_DATA        0x15
34#define LAN91CXX_INTERRUPT   0x16
35#define LAN91CXX_BS3         0x17
36#define LAN91CXX_MT01        0x18
37#define LAN91CXX_MT23        0x19
38#define LAN91CXX_MT45        0x1a
39#define LAN91CXX_MT67        0x1b
40#define LAN91CXX_MGMT        0x1c
41#define LAN91CXX_REVISION    0x1d
42#define LAN91CXX_ERCV        0x1e
43#define LAN91CXX_BS4         0x1f
44
45#define LAN91CXX_RCR_SOFT_RST   0x8000    /* soft reset*/
46#define LAN91CXX_RCR_FILT_CAR   0x4000    /* filter carrier*/
47#define LAN91CXX_RCR_ABORT_ENB  0x2000    /* abort on collision*/
48#define LAN91CXX_RCR_STRIP_CRC  0x0200    /* strip CRC*/
49#define LAN91CXX_RCR_RXEN       0x0100    /* enable RX*/
50#define LAN91CXX_RCR_ALMUL      0x0004    /* receive all muticasts*/
51#define LAN91CXX_RCR_PRMS       0x0002    /* promiscuous*/
52#define LAN91CXX_RCR_RX_ABORT   0x0001    /* set when abort due to long frame*/
53
54#define LAN91CXX_TCR_SWFDUP     0x8000    /* Switched Full Duplex mode*/
55#define LAN91CXX_TCR_ETEN_TYPE  0x4000    /* ETEN type (91C96) 0 <=> like a 91C94*/
56#define LAN91CXX_TCR_EPH_LOOP   0x2000    /* loopback mode*/
57#define LAN91CXX_TCR_STP_SQET   0x1000    /* Stop transmission on SQET error*/
58#define LAN91CXX_TCR_FDUPLX     0x0800    /* full duplex*/
59#define LAN91CXX_TCR_MON_CSN    0x0400    /* monitor carrier during tx (91C96)*/
60#define LAN91CXX_TCR_NOCRC      0x0100    /* does not append CRC to frames*/
61#define LAN91CXX_TCR_PAD_EN     0x0080    /* pads frames with 00 to min length*/
62#define LAN91CXX_TCR_FORCOL     0x0004    /* force collision*/
63#define LAN91CXX_TCR_LLOOP      0x0002    /* local loopback (91C96)*/
64#define LAN91CXX_TCR_TXENA      0x0001    /* enable*/
65
66#define LAN91CXX_POINTER_RCV        0x8000
67#define LAN91CXX_POINTER_AUTO_INCR  0x4000
68#define LAN91CXX_POINTER_READ       0x2000
69#define LAN91CXX_POINTER_ETEN       0x1000
70#define LAN91CXX_POINTER_NOT_EMPTY  0x0800
71
72
73#define LAN91CXX_INTERRUPT_TX_IDLE_M      0x8000 /* (91C96)*/
74#define LAN91CXX_INTERRUPT_ERCV_INT_M     0x4000
75#define LAN91CXX_INTERRUPT_EPH_INT_M      0x2000
76#define LAN91CXX_INTERRUPT_RX_OVRN_INT_M  0x1000
77#define LAN91CXX_INTERRUPT_ALLOC_INT_M    0x0800
78#define LAN91CXX_INTERRUPT_TX_EMPTY_INT_M 0x0400
79#define LAN91CXX_INTERRUPT_TX_INT_M       0x0200
80#define LAN91CXX_INTERRUPT_RCV_INT_M      0x0100
81#define LAN91CXX_INTERRUPT_TX_IDLE        0x0080 /* (91C96)*/
82#define LAN91CXX_INTERRUPT_ERCV_INT       0x0040 /* also ack*/
83#define LAN91CXX_INTERRUPT_EPH_INT        0x0020
84#define LAN91CXX_INTERRUPT_RX_OVRN_INT    0x0010 /* also ack*/
85#define LAN91CXX_INTERRUPT_ALLOC_INT      0x0008
86#define LAN91CXX_INTERRUPT_TX_EMPTY_INT   0x0004 /* also ack*/
87#define LAN91CXX_INTERRUPT_TX_INT         0x0002 /* also ack*/
88#define LAN91CXX_INTERRUPT_RCV_INT        0x0001
89
90#define LAN91CXX_INTERRUPT_TX_SET         0x0006 /* TX_EMPTY + TX*/
91#define LAN91CXX_INTERRUPT_TX_SET_ACK     0x0004 /* TX_EMPTY and not plain TX*/
92#define LAN91CXX_INTERRUPT_TX_FIFO_ACK    0x0002 /* TX alone*/
93#define LAN91CXX_INTERRUPT_TX_SET_M       0x0600 /* TX_EMPTY + TX*/
94
95#define LAN91CXX_CONTROL_RCV_BAD       0x4000
96#define LAN91CXX_CONTROL_AUTO_RELEASE  0x0800
97#define LAN91CXX_CONTROL_LE_ENABLE     0x0080
98#define LAN91CXX_CONTROL_CR_ENABLE     0x0040
99#define LAN91CXX_CONTROL_TE_ENABLE     0x0020
100
101/* These are for setting the MAC address in the 91C96 serial EEPROM*/
102#define LAN91CXX_CONTROL_EEPROM_SELECT 0x0004
103#define LAN91CXX_CONTROL_RELOAD        0x0002
104#define LAN91CXX_CONTROL_STORE         0x0001
105#define LAN91CXX_CONTROL_EEPROM_BUSY   0x0003
106#define LAN91CXX_ESA_EEPROM_OFFSET     0x0020
107
108#define LAN91CXX_STATUS_TX_UNRN        0x8000
109#define LAN91CXX_STATUS_LINK_OK        0x4000
110#define LAN91CXX_STATUS_CTR_ROL        0x1000
111#define LAN91CXX_STATUS_EXC_DEF        0x0800
112#define LAN91CXX_STATUS_LOST_CARR      0x0400
113#define LAN91CXX_STATUS_LATCOL         0x0200
114#define LAN91CXX_STATUS_WAKEUP         0x0100
115#define LAN91CXX_STATUS_TX_DEFR        0x0080
116#define LAN91CXX_STATUS_LTX_BRD        0x0040
117#define LAN91CXX_STATUS_SQET           0x0020
118#define LAN91CXX_STATUS_16COL          0x0010
119#define LAN91CXX_STATUS_LTX_MULT       0x0008
120#define LAN91CXX_STATUS_MUL_COL        0x0004
121#define LAN91CXX_STATUS_SNGL_COL       0x0002
122#define LAN91CXX_STATUS_TX_SUC         0x0001
123
124#define LAN91CXX_MMU_COMMAND_BUSY      0x0001
125
126#define LAN91CXX_MMU_noop              0x0000
127#define LAN91CXX_MMU_alloc_for_tx      0x0020
128#define LAN91CXX_MMU_reset_mmu         0x0040
129#define LAN91CXX_MMU_rem_rx_frame      0x0060
130#define LAN91CXX_MMU_rem_tx_frame      0x0070 /* (91C96) only when TX stopped*/
131#define LAN91CXX_MMU_remrel_rx_frame   0x0080
132#define LAN91CXX_MMU_rel_packet        0x00a0
133#define LAN91CXX_MMU_enq_packet        0x00c0
134#define LAN91CXX_MMU_reset_tx_fifo     0x00e0
135
136#define LAN91CXX_CONTROLBYTE_CRC       0x1000
137#define LAN91CXX_CONTROLBYTE_ODD       0x2000
138#define LAN91CXX_CONTROLBYTE_RX        0x4000
139
140#define LAN91CXX_RX_STATUS_ALIGNERR    0x8000
141#define LAN91CXX_RX_STATUS_BCAST       0x4000
142#define LAN91CXX_RX_STATUS_BADCRC      0x2000
143#define LAN91CXX_RX_STATUS_ODDFRM      0x1000
144#define LAN91CXX_RX_STATUS_TOOLONG     0x0800
145#define LAN91CXX_RX_STATUS_TOOSHORT    0x0400
146#define LAN91CXX_RX_STATUS_HASHVALMASK 0x007e /* MASK*/
147#define LAN91CXX_RX_STATUS_MCAST       0x0001
148#define LAN91CXX_RX_STATUS_BAD     \
149    (LAN91CXX_RX_STATUS_ALIGNERR | \
150     LAN91CXX_RX_STATUS_BADCRC   | \
151     LAN91CXX_RX_STATUS_TOOLONG  | \
152     LAN91CXX_RX_STATUS_TOOSHORT)
153
154#define LAN91CXX_RX_STATUS_IS_ODD(__cpd,__stat) ((__stat) & LAN91CXX_RX_STATUS_ODDFRM)
155#define LAN91CXX_CONTROLBYTE_IS_ODD(__cpd,__val) ((__val) & LAN91CXX_CONTROLBYTE_ODD)
156
157/* Attribute memory registers in PCMCIA mode*/
158#define LAN91CXX_ECOR                  0x8000
159#define LAN91CXX_ECOR_RESET            (1<<7)
160#define LAN91CXX_ECOR_LEVIRQ           (1<<6)
161#define LAN91CXX_ECOR_ATTWR            (1<<2)
162#define LAN91CXX_ECOR_ENABLE           (1<<0)
163
164#define LAN91CXX_ECSR                  0x8002
165#define LAN91CXX_ECSR_IOIS8            (1<<5)
166#define LAN91CXX_ECSR_PWRDWN           (1<<2)
167#define LAN91CXX_ECSR_INTR             (1<<1)
168
169/* These are for manipulating the MII interface*/
170#define LAN91CXX_MGMT_MDO              0x0001
171#define LAN91CXX_MGMT_MDI              0x0002
172#define LAN91CXX_MGMT_MCLK             0x0004
173#define LAN91CXX_MGMT_MDOE             0x0008
174
175/* Internal PHY registers (91c111)*/
176#define LAN91CXX_PHY_CTRL              0
177#define LAN91CXX_PHY_STAT              1
178#define LAN91CXX_PHY_ID1               2
179#define LAN91CXX_PHY_ID2               3
180#define LAN91CXX_PHY_AUTO_AD           4
181#define LAN91CXX_PHY_AUTO_CAP          5
182#define LAN91CXX_PHY_CONFIG1          16
183#define LAN91CXX_PHY_CONFIG2          17
184#define LAN91CXX_PHY_STATUS_OUT       18
185#define LAN91CXX_PHY_MASK             19
186
187/* PHY control bits*/
188#define LAN91CXX_PHY_CTRL_COLTST      (1 << 7)
189#define LAN91CXX_PHY_CTRL_DPLX        (1 << 8)
190#define LAN91CXX_PHY_CTRL_ANEG_RST    (1 << 9)
191#define LAN91CXX_PHY_CTRL_MII_DIS     (1 << 10)
192#define LAN91CXX_PHY_CTRL_PDN         (1 << 11)
193#define LAN91CXX_PHY_CTRL_ANEG_EN     (1 << 12)
194#define LAN91CXX_PHY_CTRL_SPEED       (1 << 13)
195#define LAN91CXX_PHY_CTRL_LPBK        (1 << 14)
196#define LAN91CXX_PHY_CTRL_RST         (1 << 15)
197
198/* PHY Configuration Register 1 */
199#define PHY_CFG1_LNKDIS         0x8000  /* 1=Rx Link Detect Function disabled */
200#define PHY_CFG1_XMTDIS         0x4000  /* 1=TP Transmitter Disabled */
201#define PHY_CFG1_XMTPDN         0x2000  /* 1=TP Transmitter Powered Down */
202#define PHY_CFG1_BYPSCR         0x0400  /* 1=Bypass scrambler/descrambler */
203#define PHY_CFG1_UNSCDS         0x0200  /* 1=Unscramble Idle Reception Disable */
204#define PHY_CFG1_EQLZR          0x0100  /* 1=Rx Equalizer Disabled */
205#define PHY_CFG1_CABLE          0x0080  /* 1=STP(150ohm), 0=UTP(100ohm) */
206#define PHY_CFG1_RLVL0          0x0040  /* 1=Rx Squelch level reduced by 4.5db */
207#define PHY_CFG1_TLVL_SHIFT     2       /* Transmit Output Level Adjust */
208#define PHY_CFG1_TLVL_MASK      0x003C
209#define PHY_CFG1_TRF_MASK       0x0003  /* Transmitter Rise/Fall time */
210
211/* PHY Configuration Register 2 */
212#define PHY_CFG2_REG            0x11
213#define PHY_CFG2_APOLDIS        0x0020  /* 1=Auto Polarity Correction disabled */
214#define PHY_CFG2_JABDIS         0x0010  /* 1=Jabber disabled */
215#define PHY_CFG2_MREG           0x0008  /* 1=Multiple register access (MII mgt) */
216#define PHY_CFG2_INTMDIO        0x0004  /* 1=Interrupt signaled with MDIO pulseo */
217
218/* PHY Status Output (and Interrupt status) Register */
219#define PHY_INT_REG             0x12    /* Status Output (Interrupt Status) */
220#define PHY_INT_INT             0x8000  /* 1=bits have changed since last read */
221#define PHY_INT_LNKFAIL         0x4000  /* 1=Link Not detected */
222#define PHY_INT_LOSSSYNC        0x2000  /* 1=Descrambler has lost sync */
223#define PHY_INT_CWRD            0x1000  /* 1=Invalid 4B5B code detected on rx */
224#define PHY_INT_SSD             0x0800  /* 1=No Start Of Stream detected on rx */
225#define PHY_INT_ESD             0x0400  /* 1=No End Of Stream detected on rx */
226#define PHY_INT_RPOL            0x0200  /* 1=Reverse Polarity detected */
227#define PHY_INT_JAB             0x0100  /* 1=Jabber detected */
228#define PHY_INT_SPDDET          0x0080  /* 1=100Base-TX mode, 0=10Base-T mode */
229#define PHY_INT_DPLXDET         0x0040  /* 1=Device in Full Duplex */
230
231/* PHY Interrupt/Status Mask Register */
232#define PHY_MASK_REG            0x13    /* Interrupt Mask */
233
234#define LAN91CXX_RPCR_LEDA_LINK       (0 << 2)
235#define LAN91CXX_RPCR_LEDA_TXRX       (4 << 2)
236#define LAN91CXX_RPCR_LEDA_RX         (6 << 2)
237#define LAN91CXX_RPCR_LEDA_TX         (7 << 2)
238#define LAN91CXX_RPCR_LEDB_LINK       (0 << 5)
239#define LAN91CXX_RPCR_LEDB_TXRX       (4 << 5)
240#define LAN91CXX_RPCR_LEDB_RX         (6 << 5)
241#define LAN91CXX_RPCR_LEDB_TX         (7 << 5)
242#define LAN91CXX_RPCR_ANEG            (1 << 11)
243#define LAN91CXX_RPCR_DPLX            (1 << 12)
244#define LAN91CXX_RPCR_SPEED           (1 << 13)
245
246/* PHY Control Register */
247#define PHY_CNTL_REG            0x00
248#define PHY_CNTL_RST            0x8000  /* 1=PHY Reset */
249#define PHY_CNTL_LPBK           0x4000  /* 1=PHY Loopback */
250#define PHY_CNTL_SPEED          0x2000  /* 1=100Mbps, 0=10Mpbs */
251#define PHY_CNTL_ANEG_EN        0x1000 /* 1=Enable Auto negotiation */
252#define PHY_CNTL_PDN            0x0800  /* 1=PHY Power Down mode */
253#define PHY_CNTL_MII_DIS        0x0400  /* 1=MII 4 bit interface disabled */
254#define PHY_CNTL_ANEG_RST       0x0200 /* 1=Reset Auto negotiate */
255#define PHY_CNTL_DPLX           0x0100  /* 1=Full Duplex, 0=Half Duplex */
256#define PHY_CNTL_COLTST         0x0080  /* 1= MII Colision Test */
257
258/* PHY Status Register */
259#define PHY_STAT_REG            0x01
260#define PHY_STAT_CAP_T4         0x8000  /* 1=100Base-T4 capable */
261#define PHY_STAT_CAP_TXF        0x4000  /* 1=100Base-X full duplex capable */
262#define PHY_STAT_CAP_TXH        0x2000  /* 1=100Base-X half duplex capable */
263#define PHY_STAT_CAP_TF         0x1000  /* 1=10Mbps full duplex capable */
264#define PHY_STAT_CAP_TH         0x0800  /* 1=10Mbps half duplex capable */
265#define PHY_STAT_CAP_SUPR       0x0040  /* 1=recv mgmt frames with not preamble */
266#define PHY_STAT_ANEG_ACK       0x0020  /* 1=ANEG has completed */
267#define PHY_STAT_REM_FLT        0x0010  /* 1=Remote Fault detected */
268#define PHY_STAT_CAP_ANEG       0x0008  /* 1=Auto negotiate capable */
269#define PHY_STAT_LINK           0x0004  /* 1=valid link */
270#define PHY_STAT_JAB            0x0002  /* 1=10Mbps jabber condition */
271#define PHY_STAT_EXREG          0x0001  /* 1=extended registers implemented */
272#define PHY_STAT_RESERVED   0x0780  /* Reserved bits mask. */
273
274/* PHY Identifier Registers */
275#define PHY_ID1_REG             0x02    /* PHY Identifier 1 */
276#define PHY_ID2_REG             0x03    /* PHY Identifier 2 */
277
278/* PHY Auto-Negotiation Advertisement Register */
279#define PHY_AD_REG              0x04
280#define PHY_AD_NP               0x8000  /* 1=PHY requests exchange of Next Page */
281#define PHY_AD_ACK              0x4000  /* 1=got link code word from remote */
282#define PHY_AD_RF               0x2000  /* 1=advertise remote fault */
283#define PHY_AD_T4               0x0200  /* 1=PHY is capable of 100Base-T4 */
284#define PHY_AD_TX_FDX           0x0100  /* 1=PHY is capable of 100Base-TX FDPLX */
285#define PHY_AD_TX_HDX           0x0080  /* 1=PHY is capable of 100Base-TX HDPLX */
286#define PHY_AD_10_FDX           0x0040  /* 1=PHY is capable of 10Base-T FDPLX */
287#define PHY_AD_10_HDX           0x0020  /* 1=PHY is capable of 10Base-T HDPLX */
288#define PHY_AD_CSMA             0x0001  /* 1=PHY is capable of 802.3 CMSA */
289
290
291static int debugflag_out = 0;
292
293#define dbc_printf(lvl,format, args...) do { \
294  if (!debugflag_out) { \
295    if (lvl & DEBUG) { \
296      printk(format,##args); \
297    } \
298  } \
299} while(0)
300
301#define db64_printf(format, args...) dbc_printf(64,format,##args);
302#define db16_printf(format, args...) dbc_printf(16,format,##args);
303#define db9_printf(format, args...) dbc_printf(9,format,##args);
304#define db4_printf(format, args...) dbc_printf(4,format,##args);
305#define db2_printf(format, args...) dbc_printf(2,format,##args);
306#define db1_printf(format, args...) dbc_printf(1,format,##args);
307#define db_printf(format, args...) dbc_printf(0xffff,format,##args);
308
309#if DEBUG & 1
310#define DEBUG_FUNCTION() do { db_printf("# %s\n", __FUNCTION__); } while (0)
311#else
312#define DEBUG_FUNCTION() do {} while(0)
313#endif
314
315
316/* ------------------------------------------------------------------------*/
317
318struct smsc_lan91cxx_stats {
319    unsigned int tx_good             ;
320    unsigned int tx_max_collisions   ;
321    unsigned int tx_late_collisions  ;
322    unsigned int tx_underrun         ;
323    unsigned int tx_carrier_loss     ;
324    unsigned int tx_deferred         ;
325    unsigned int tx_sqetesterrors    ;
326    unsigned int tx_single_collisions;
327    unsigned int tx_mult_collisions  ;
328    unsigned int tx_total_collisions ;
329    unsigned int rx_good             ;
330    unsigned int rx_crc_errors       ;
331    unsigned int rx_align_errors     ;
332    unsigned int rx_resource_errors  ;
333    unsigned int rx_overrun_errors   ;
334    unsigned int rx_collisions       ;
335    unsigned int rx_short_frames     ;
336    unsigned int rx_too_long_frames  ;
337    unsigned int rx_symbol_errors    ;
338    unsigned int interrupts          ;
339    unsigned int rx_count            ;
340    unsigned int rx_deliver          ;
341    unsigned int rx_resource         ;
342    unsigned int rx_restart          ;
343    unsigned int tx_count            ;
344    unsigned int tx_complete         ;
345    unsigned int tx_dropped          ;
346};
347#define INCR_STAT(c,n) (((c)->stats.n)++)
348
349struct lan91cxx_priv_data;
350
351typedef struct lan91cxx_priv_data {
352
353    /* frontend */
354    struct arpcom arpcom;
355    rtems_id rxDaemonTid;
356    rtems_id txDaemonTid;
357
358    scmv91111_configuration_t config;
359 
360    /* backend */
361    int rpc_cur_mode;
362    int autoneg_active;
363    int phyaddr;
364    unsigned int lastPhy18;
365 
366    int txbusy;                         /* A packet has been sent*/
367    unsigned long txkey;                /* Used to ack when packet sent*/
368    unsigned short* base;               /* Base I/O address of controller*/
369                                        /* (as it comes out of reset)*/
370    int interrupt;                      /* Interrupt vector used by controller*/
371    unsigned char enaddr[6];            /* Controller ESA*/
372    /* Function to configure the ESA - may fetch ESA from EPROM or */
373    /* RedBoot config option.  Use of the 'config_enaddr()' function*/
374    /* is depreciated in favor of the 'provide_esa()' function and*/
375    /* 'hardwired_esa' boolean*/
376    void (*config_enaddr)(struct lan91cxx_priv_data* cpd);
377    int hardwired_esa;
378    int txpacket;
379    int rxpacket;
380    int within_send;
381    int c111_reva;                      /* true if this is a revA LAN91C111*/
382    struct smsc_lan91cxx_stats stats;
383} lan91cxx_priv_data;
384
385/* ------------------------------------------------------------------------*/
386
387#ifdef LAN91CXX_32BIT_RX
388typedef unsigned int rxd_t;
389#else
390typedef unsigned short rxd_t;
391#endif
392
393typedef struct _debug_regs_pair {
394  int reg; char *name; struct _debug_regs_pair *bits;
395} debug_regs_pair;
396
397static debug_regs_pair debug_regs[] = {
398  {LAN91CXX_TCR        , "LAN91CXX_TCR"       ,0}, 
399  {LAN91CXX_EPH_STATUS , "LAN91CXX_EPH_STATUS",0}, 
400  {LAN91CXX_RCR        , "LAN91CXX_RCR"       ,0},         
401  {LAN91CXX_COUNTER    , "LAN91CXX_COUNTER"   ,0},     
402  {LAN91CXX_MIR        , "LAN91CXX_MIR"       ,0},         
403  {LAN91CXX_MCR        , "LAN91CXX_MCR"       ,0},         
404  {LAN91CXX_RPCR       , "LAN91CXX_RPCR"      ,0},       
405  {LAN91CXX_RESERVED_0 , "LAN91CXX_RESERVED_0",0}, 
406  {LAN91CXX_BS         , "LAN91CXX_BS"        ,0},         
407  {LAN91CXX_CONFIG     , "LAN91CXX_CONFIG"    ,0},     
408  {LAN91CXX_BASE_REG   , "LAN91CXX_BASE_REG"  ,0},   
409  {LAN91CXX_IA01       , "LAN91CXX_IA01"      ,0},       
410  {LAN91CXX_IA23       , "LAN91CXX_IA23"      ,0},       
411  {LAN91CXX_IA45       , "LAN91CXX_IA45"      ,0},       
412  {LAN91CXX_GENERAL    , "LAN91CXX_GENERAL"   ,0},     
413  {LAN91CXX_CONTROL    , "LAN91CXX_CONTROL"   ,0},     
414  {LAN91CXX_BS2        , "LAN91CXX_BS2"       ,0},         
415  {LAN91CXX_MMU_COMMAND, "LAN91CXX_MMU_COMMAND",0}, 
416  {LAN91CXX_PNR        , "LAN91CXX_PNR"        ,0},         
417  {LAN91CXX_FIFO_PORTS , "LAN91CXX_FIFO_PORTS" ,0}, 
418  {LAN91CXX_POINTER    , "LAN91CXX_POINTER"    ,0},     
419  {LAN91CXX_DATA_HIGH  , "LAN91CXX_DATA_HIGH"  ,0},   
420  {LAN91CXX_DATA       , "LAN91CXX_DATA"       ,0},       
421  {LAN91CXX_INTERRUPT  , "LAN91CXX_INTERRUPT"  ,0},
422  {LAN91CXX_BS3        , "LAN91CXX_BS3"        ,0},
423  {LAN91CXX_MT01       , "LAN91CXX_MT01"       ,0},
424  {LAN91CXX_MT23       , "LAN91CXX_MT23"       ,0},   
425  {LAN91CXX_MT45       , "LAN91CXX_MT45"       ,0},     
426  {LAN91CXX_MT67       , "LAN91CXX_MT67"       ,0},
427/*{LAN91CXX_MGMT       , "LAN91CXX_MGMT"       ,0},      */
428  {LAN91CXX_REVISION   , "LAN91CXX_REVISION"   ,0}, 
429  {LAN91CXX_ERCV       , "LAN91CXX_ERCV"       ,0},     
430  {LAN91CXX_BS4        , "LAN91CXX_BS4"        ,0},             
431
432
433 
434  {-1,0}
435};
436
437static char *dbg_prefix = "";
438
439#ifndef SMSC_PLATFORM_DEFINED_GET_REG
440static __inline__ unsigned short
441get_reg(struct lan91cxx_priv_data *cpd, int regno)
442{
443    unsigned short val; debug_regs_pair *dbg = debug_regs; int c;
444    uint32_t              Irql;
445
446    /*rtems_interrupt_disable(Irql);*/
447
448    HAL_WRITE_UINT16(cpd->base+(LAN91CXX_BS), CYG_CPU_TO_LE16(regno>>3));
449    HAL_READ_UINT16(cpd->base+((regno&0x7)), val);
450    val = CYG_LE16_TO_CPU(val);
451   
452    /*rtems_interrupt_enable(Irql);*/
453
454#ifdef DEBUG & 32
455    while ((c = dbg->reg) != -1) {
456      if (c == regno) {
457        db_printf("%sread  reg [%d:%x] -> 0x%04x (%-20s)\n", dbg_prefix, regno>>3,(regno&0x7)*2, val, dbg->name);
458        break;
459      }
460      dbg++;
461    }
462#else
463    db2_printf("%sread  reg %d:%x -> 0x%04x\n", dbg_prefix, regno>>3,(regno&0x7)*2, val);
464#endif
465   
466    return val;
467}
468#endif /* SMSC_PLATFORM_DEFINED_GET_REG*/
469
470#ifndef SMSC_PLATFORM_DEFINED_PUT_REG
471static __inline__ void
472put_reg(struct lan91cxx_priv_data *cpd, int regno, unsigned short val)
473{
474    debug_regs_pair *dbg = debug_regs; int c;
475    uint32_t              Irql;
476
477#ifdef DEBUG & 32
478    while ((c = dbg->reg) != -1) {
479      if (c == regno) {
480        db_printf("%swrite reg [%d:%x] <- 0x%04x (%-20s)\n", dbg_prefix, regno>>3, (regno&0x07)*2, val, dbg->name);
481        break;
482      }
483      dbg++;
484    }
485#else
486    db2_printf("%swrite reg %d:%x <- 0x%04x\n", dbg_prefix, regno>>3,(regno&0x7)*2, val);
487#endif
488   
489    /*rtems_interrupt_disable(Irql);*/
490   
491    HAL_WRITE_UINT16(cpd->base+(LAN91CXX_BS), CYG_CPU_TO_LE16(regno>>3));
492    HAL_WRITE_UINT16(cpd->base+((regno&0x7)), CYG_CPU_TO_LE16(val));
493   
494    /*rtems_interrupt_enable(Irql);*/
495
496}
497#endif /* SMSC_PLATFORM_DEFINED_PUT_REG*/
498
499#ifndef SMSC_PLATFORM_DEFINED_PUT_DATA
500/* ------------------------------------------------------------------------*/
501/* Assumes bank2 has been selected*/
502static __inline__ void
503put_data(struct lan91cxx_priv_data *cpd, unsigned short val)
504{
505    db2_printf("%s[wdata] <- 0x%04x\n", dbg_prefix, val);
506   
507    HAL_WRITE_UINT16(cpd->base+((LAN91CXX_DATA & 0x7)), val);
508
509}
510
511/* Assumes bank2 has been selected*/
512static __inline__ void
513put_data8(struct lan91cxx_priv_data *cpd, unsigned char val)
514{
515    db2_printf("%s[bdata] <- 0x%02x\n", dbg_prefix, val);
516   
517    HAL_WRITE_UINT8(((unsigned char *)(cpd->base+((LAN91CXX_DATA & 0x7))))+1, val);
518
519}
520
521#endif /* SMSC_PLATFORM_DEFINED_PUT_DATA*/
522
523#ifndef SMSC_PLATFORM_DEFINED_GET_DATA
524/* Assumes bank2 has been selected*/
525static __inline__ rxd_t
526get_data(struct lan91cxx_priv_data *cpd)
527{
528    rxd_t val;
529       
530#ifdef LAN91CXX_32BIT_RX
531    HAL_READ_UINT32(cpd->base+((LAN91CXX_DATA_HIGH & 0x7)), val);
532#else
533    HAL_READ_UINT16(cpd->base+((LAN91CXX_DATA & 0x7)), val);
534#endif
535
536    db2_printf("%s[rdata] -> 0x%08x\n", dbg_prefix, val);
537    return val;
538}
539#endif /* SMSC_PLATFORM_DEFINED_GET_DATA*/
540
541/* ------------------------------------------------------------------------*/
542/* Read the bank register (this one is bank-independent)*/
543#ifndef SMSC_PLATFORM_DEFINED_GET_BANKSEL
544static __inline__ unsigned short
545get_banksel(struct lan91cxx_priv_data *cpd)
546{
547    unsigned short val;
548   
549    HAL_READ_UINT16(cpd->base+(LAN91CXX_BS), val);
550    val = CYG_LE16_TO_CPU(val);
551    db2_printf("read bank sel val 0x%04x\n", val);
552    return val;
553}
554#endif
555
556
557
558
559
560#endif  /* _SMC_91111_H_ */
561
562
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