source: rtems/c/src/libchip/network/open_eth.h @ 3ffa814

Last change on this file since 3ffa814 was 3ffa814, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 5, 2005 at 7:29:23 PM

2005-10-05 Jiri Gaisler <jiri@…>

Edvin Catovic <edvin@…>
Konrad Eisele <konrad@…>

PR 827/bsps

  • network/Makefile.am, network/open_eth.c, network/open_eth.h: Portion of large update of SPARC BSPs. Includes addition of sis, leon2 and leon3 BSPs, deletion of leon BSP, addition of SMC91111 NIC driver and much more.
  • network/README.smc91111, network/smc91111.c, network/smc91111.h, network/smc91111config.h, network/smc91111exp.h: New files.
  • Property mode set to 100644
File size: 8.3 KB
Line 
1/* Opencores ethernet MAC driver */
2/* adapted from linux driver by Jiri Gaisler */
3
4#ifndef _OPEN_ETH_
5#define _OPEN_ETH_
6
7
8/* Configuration Information */
9
10typedef struct {
11  unsigned32              base_address;
12  unsigned32              vector;
13  unsigned32              txd_count;
14  unsigned32              rxd_count;
15  unsigned32              en100MHz;
16} open_eth_configuration_t;
17
18
19/* Ethernet buffer descriptor */
20
21typedef struct _oeth_rxtxdesc {
22    volatile unsigned32 len_status; /* Length and status */
23    volatile unsigned32 *addr;      /* Buffer pointer */
24} oeth_rxtxdesc;
25
26/* Ethernet configuration registers */
27
28typedef struct _oeth_regs {
29    volatile unsigned32 moder;       /* Mode Register */
30    volatile unsigned32 int_src;     /* Interrupt Source Register */
31    volatile unsigned32 int_mask;    /* Interrupt Mask Register */
32    volatile unsigned32 ipgt;        /* Back to Bak Inter Packet Gap Register */
33    volatile unsigned32 ipgr1;       /* Non Back to Back Inter Packet Gap Register 1 */
34    volatile unsigned32 ipgr2;       /* Non Back to Back Inter Packet Gap Register 2 */
35    volatile unsigned32 packet_len;  /* Packet Length Register (min. and max.) */
36    volatile unsigned32 collconf;    /* Collision and Retry Configuration Register */
37    volatile unsigned32 tx_bd_num;   /* Transmit Buffer Descriptor Number Register */
38    volatile unsigned32 ctrlmoder;   /* Control Module Mode Register */
39    volatile unsigned32 miimoder;    /* MII Mode Register */
40    volatile unsigned32 miicommand;  /* MII Command Register */
41    volatile unsigned32 miiaddress;  /* MII Address Register */
42    volatile unsigned32 miitx_data;  /* MII Transmit Data Register */
43    volatile unsigned32 miirx_data;  /* MII Receive Data Register */
44    volatile unsigned32 miistatus;   /* MII Status Register */
45    volatile unsigned32 mac_addr0;   /* MAC Individual Address Register 0 */
46    volatile unsigned32 mac_addr1;   /* MAC Individual Address Register 1 */
47    volatile unsigned32 hash_addr0;  /* Hash Register 0 */
48    volatile unsigned32 hash_addr1;  /* Hash Register 1 */
49    volatile unsigned32 txctrl;      /* Transmitter control register */
50    unsigned32 empty[235];           /* Unused space */
51    oeth_rxtxdesc xd[128];           /* TX & RX descriptors */
52} oeth_regs;
53
54#define OETH_TOTAL_BD           128
55#define OETH_MAXBUF_LEN         0x610
56                               
57/* Tx BD */                     
58#define OETH_TX_BD_READY        0x8000 /* Tx BD Ready */
59#define OETH_TX_BD_IRQ          0x4000 /* Tx BD IRQ Enable */
60#define OETH_TX_BD_WRAP         0x2000 /* Tx BD Wrap (last BD) */
61#define OETH_TX_BD_PAD          0x1000 /* Tx BD Pad Enable */
62#define OETH_TX_BD_CRC          0x0800 /* Tx BD CRC Enable */
63                               
64#define OETH_TX_BD_UNDERRUN     0x0100 /* Tx BD Underrun Status */
65#define OETH_TX_BD_RETRY        0x00F0 /* Tx BD Retry Status */
66#define OETH_TX_BD_RETLIM       0x0008 /* Tx BD Retransmission Limit Status */
67#define OETH_TX_BD_LATECOL      0x0004 /* Tx BD Late Collision Status */
68#define OETH_TX_BD_DEFER        0x0002 /* Tx BD Defer Status */
69#define OETH_TX_BD_CARRIER      0x0001 /* Tx BD Carrier Sense Lost Status */
70#define OETH_TX_BD_STATS        (OETH_TX_BD_UNDERRUN            | \
71                                OETH_TX_BD_RETRY                | \
72                                OETH_TX_BD_RETLIM               | \
73                                OETH_TX_BD_LATECOL              | \
74                                OETH_TX_BD_DEFER                | \
75                                OETH_TX_BD_CARRIER)
76                               
77/* Rx BD */                     
78#define OETH_RX_BD_EMPTY        0x8000 /* Rx BD Empty */
79#define OETH_RX_BD_IRQ          0x4000 /* Rx BD IRQ Enable */
80#define OETH_RX_BD_WRAP         0x2000 /* Rx BD Wrap (last BD) */
81                               
82#define OETH_RX_BD_MISS         0x0080 /* Rx BD Miss Status */
83#define OETH_RX_BD_OVERRUN      0x0040 /* Rx BD Overrun Status */
84#define OETH_RX_BD_INVSIMB      0x0020 /* Rx BD Invalid Symbol Status */
85#define OETH_RX_BD_DRIBBLE      0x0010 /* Rx BD Dribble Nibble Status */
86#define OETH_RX_BD_TOOLONG      0x0008 /* Rx BD Too Long Status */
87#define OETH_RX_BD_SHORT        0x0004 /* Rx BD Too Short Frame Status */
88#define OETH_RX_BD_CRCERR       0x0002 /* Rx BD CRC Error Status */
89#define OETH_RX_BD_LATECOL      0x0001 /* Rx BD Late Collision Status */
90#define OETH_RX_BD_STATS        (OETH_RX_BD_MISS                | \
91                                OETH_RX_BD_OVERRUN              | \
92                                OETH_RX_BD_INVSIMB              | \
93                                OETH_RX_BD_DRIBBLE              | \
94                                OETH_RX_BD_TOOLONG              | \
95                                OETH_RX_BD_SHORT                | \
96                                OETH_RX_BD_CRCERR               | \
97                                OETH_RX_BD_LATECOL)
98
99/* MODER Register */
100#define OETH_MODER_RXEN         0x00000001 /* Receive Enable  */
101#define OETH_MODER_TXEN         0x00000002 /* Transmit Enable */
102#define OETH_MODER_NOPRE        0x00000004 /* No Preamble  */
103#define OETH_MODER_BRO          0x00000008 /* Reject Broadcast */
104#define OETH_MODER_IAM          0x00000010 /* Use Individual Hash */
105#define OETH_MODER_PRO          0x00000020 /* Promiscuous (receive all) */
106#define OETH_MODER_IFG          0x00000040 /* Min. IFG not required */
107#define OETH_MODER_LOOPBCK      0x00000080 /* Loop Back */
108#define OETH_MODER_NOBCKOF      0x00000100 /* No Backoff */
109#define OETH_MODER_EXDFREN      0x00000200 /* Excess Defer */
110#define OETH_MODER_FULLD        0x00000400 /* Full Duplex */
111#define OETH_MODER_RST          0x00000800 /* Reset MAC */
112#define OETH_MODER_DLYCRCEN     0x00001000 /* Delayed CRC Enable */
113#define OETH_MODER_CRCEN        0x00002000 /* CRC Enable */
114#define OETH_MODER_HUGEN        0x00004000 /* Huge Enable */
115#define OETH_MODER_PAD          0x00008000 /* Pad Enable */
116#define OETH_MODER_RECSMALL     0x00010000 /* Receive Small */
117 
118/* Interrupt Source Register */
119#define OETH_INT_TXB            0x00000001 /* Transmit Buffer IRQ */
120#define OETH_INT_TXE            0x00000002 /* Transmit Error IRQ */
121#define OETH_INT_RXF            0x00000004 /* Receive Frame IRQ */
122#define OETH_INT_RXE            0x00000008 /* Receive Error IRQ */
123#define OETH_INT_BUSY           0x00000010 /* Busy IRQ */
124#define OETH_INT_TXC            0x00000020 /* Transmit Control Frame IRQ */
125#define OETH_INT_RXC            0x00000040 /* Received Control Frame IRQ */
126
127/* Interrupt Mask Register */
128#define OETH_INT_MASK_TXB       0x00000001 /* Transmit Buffer IRQ Mask */
129#define OETH_INT_MASK_TXE       0x00000002 /* Transmit Error IRQ Mask */
130#define OETH_INT_MASK_RXF       0x00000004 /* Receive Frame IRQ Mask */
131#define OETH_INT_MASK_RXE       0x00000008 /* Receive Error IRQ Mask */
132#define OETH_INT_MASK_BUSY      0x00000010 /* Busy IRQ Mask */
133#define OETH_INT_MASK_TXC       0x00000020 /* Transmit Control Frame IRQ Mask */
134#define OETH_INT_MASK_RXC       0x00000040 /* Received Control Frame IRQ Mask */
135 
136/* Control Module Mode Register */
137#define OETH_CTRLMODER_PASSALL  0x00000001 /* Pass Control Frames */
138#define OETH_CTRLMODER_RXFLOW   0x00000002 /* Receive Control Flow Enable */
139#define OETH_CTRLMODER_TXFLOW   0x00000004 /* Transmit Control Flow Enable */
140                               
141/* MII Mode Register */       
142#define OETH_MIIMODER_CLKDIV    0x000000FF /* Clock Divider */
143#define OETH_MIIMODER_NOPRE     0x00000100 /* No Preamble */
144#define OETH_MIIMODER_RST       0x00000200 /* MIIM Reset */
145 
146/* MII Command Register */
147#define OETH_MIICOMMAND_SCANSTAT  0x00000001 /* Scan Status */
148#define OETH_MIICOMMAND_RSTAT     0x00000002 /* Read Status */
149#define OETH_MIICOMMAND_WCTRLDATA 0x00000004 /* Write Control Data */
150 
151/* MII Address Register */
152#define OETH_MIIADDRESS_FIAD    0x0000001F /* PHY Address */
153#define OETH_MIIADDRESS_RGAD    0x00001F00 /* RGAD Address */
154 
155/* MII Status Register */
156#define OETH_MIISTATUS_LINKFAIL 0x00000001 /* Link Fail */
157#define OETH_MIISTATUS_BUSY     0x00000002 /* MII Busy */
158#define OETH_MIISTATUS_NVALID   0x00000004 /* Data in MII Status Register is invalid */
159
160/* Attatch routine */
161
162int rtems_open_eth_driver_attach (
163    struct rtems_bsdnet_ifconfig *config,
164    open_eth_configuration_t *chip
165);
166
167/*
168#ifdef CPU_U32_FIX
169void ipalign(struct mbuf *m);
170#endif
171
172*/
173#endif /* _OPEN_ETH_ */
174
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