[62ff2e4f] | 1 | /* Opencores ethernet MAC driver */ |
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| 2 | /* adapted from linux driver by Jiri Gaisler */ |
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| 3 | |
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| 4 | #ifndef _OPEN_ETH_ |
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| 5 | #define _OPEN_ETH_ |
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| 6 | |
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| 7 | |
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| 8 | /* Configuration Information */ |
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| 9 | |
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| 10 | typedef struct { |
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| 11 | unsigned32 base_address; |
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| 12 | unsigned32 vector; |
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| 13 | unsigned32 txd_count; |
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| 14 | unsigned32 rxd_count; |
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[3ffa814] | 15 | unsigned32 en100MHz; |
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[62ff2e4f] | 16 | } open_eth_configuration_t; |
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| 17 | |
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| 18 | |
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| 19 | /* Ethernet buffer descriptor */ |
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| 20 | |
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| 21 | typedef struct _oeth_rxtxdesc { |
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| 22 | volatile unsigned32 len_status; /* Length and status */ |
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| 23 | volatile unsigned32 *addr; /* Buffer pointer */ |
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| 24 | } oeth_rxtxdesc; |
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| 25 | |
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| 26 | /* Ethernet configuration registers */ |
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| 27 | |
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| 28 | typedef struct _oeth_regs { |
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| 29 | volatile unsigned32 moder; /* Mode Register */ |
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| 30 | volatile unsigned32 int_src; /* Interrupt Source Register */ |
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| 31 | volatile unsigned32 int_mask; /* Interrupt Mask Register */ |
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| 32 | volatile unsigned32 ipgt; /* Back to Bak Inter Packet Gap Register */ |
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| 33 | volatile unsigned32 ipgr1; /* Non Back to Back Inter Packet Gap Register 1 */ |
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| 34 | volatile unsigned32 ipgr2; /* Non Back to Back Inter Packet Gap Register 2 */ |
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| 35 | volatile unsigned32 packet_len; /* Packet Length Register (min. and max.) */ |
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| 36 | volatile unsigned32 collconf; /* Collision and Retry Configuration Register */ |
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| 37 | volatile unsigned32 tx_bd_num; /* Transmit Buffer Descriptor Number Register */ |
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| 38 | volatile unsigned32 ctrlmoder; /* Control Module Mode Register */ |
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| 39 | volatile unsigned32 miimoder; /* MII Mode Register */ |
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| 40 | volatile unsigned32 miicommand; /* MII Command Register */ |
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| 41 | volatile unsigned32 miiaddress; /* MII Address Register */ |
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| 42 | volatile unsigned32 miitx_data; /* MII Transmit Data Register */ |
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| 43 | volatile unsigned32 miirx_data; /* MII Receive Data Register */ |
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| 44 | volatile unsigned32 miistatus; /* MII Status Register */ |
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| 45 | volatile unsigned32 mac_addr0; /* MAC Individual Address Register 0 */ |
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| 46 | volatile unsigned32 mac_addr1; /* MAC Individual Address Register 1 */ |
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| 47 | volatile unsigned32 hash_addr0; /* Hash Register 0 */ |
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| 48 | volatile unsigned32 hash_addr1; /* Hash Register 1 */ |
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| 49 | volatile unsigned32 txctrl; /* Transmitter control register */ |
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| 50 | unsigned32 empty[235]; /* Unused space */ |
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| 51 | oeth_rxtxdesc xd[128]; /* TX & RX descriptors */ |
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| 52 | } oeth_regs; |
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| 53 | |
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| 54 | #define OETH_TOTAL_BD 128 |
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| 55 | #define OETH_MAXBUF_LEN 0x610 |
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| 56 | |
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| 57 | /* Tx BD */ |
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| 58 | #define OETH_TX_BD_READY 0x8000 /* Tx BD Ready */ |
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| 59 | #define OETH_TX_BD_IRQ 0x4000 /* Tx BD IRQ Enable */ |
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| 60 | #define OETH_TX_BD_WRAP 0x2000 /* Tx BD Wrap (last BD) */ |
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| 61 | #define OETH_TX_BD_PAD 0x1000 /* Tx BD Pad Enable */ |
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| 62 | #define OETH_TX_BD_CRC 0x0800 /* Tx BD CRC Enable */ |
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| 63 | |
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| 64 | #define OETH_TX_BD_UNDERRUN 0x0100 /* Tx BD Underrun Status */ |
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| 65 | #define OETH_TX_BD_RETRY 0x00F0 /* Tx BD Retry Status */ |
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| 66 | #define OETH_TX_BD_RETLIM 0x0008 /* Tx BD Retransmission Limit Status */ |
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| 67 | #define OETH_TX_BD_LATECOL 0x0004 /* Tx BD Late Collision Status */ |
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| 68 | #define OETH_TX_BD_DEFER 0x0002 /* Tx BD Defer Status */ |
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| 69 | #define OETH_TX_BD_CARRIER 0x0001 /* Tx BD Carrier Sense Lost Status */ |
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| 70 | #define OETH_TX_BD_STATS (OETH_TX_BD_UNDERRUN | \ |
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| 71 | OETH_TX_BD_RETRY | \ |
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| 72 | OETH_TX_BD_RETLIM | \ |
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| 73 | OETH_TX_BD_LATECOL | \ |
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| 74 | OETH_TX_BD_DEFER | \ |
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| 75 | OETH_TX_BD_CARRIER) |
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| 76 | |
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| 77 | /* Rx BD */ |
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| 78 | #define OETH_RX_BD_EMPTY 0x8000 /* Rx BD Empty */ |
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| 79 | #define OETH_RX_BD_IRQ 0x4000 /* Rx BD IRQ Enable */ |
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| 80 | #define OETH_RX_BD_WRAP 0x2000 /* Rx BD Wrap (last BD) */ |
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| 81 | |
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| 82 | #define OETH_RX_BD_MISS 0x0080 /* Rx BD Miss Status */ |
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| 83 | #define OETH_RX_BD_OVERRUN 0x0040 /* Rx BD Overrun Status */ |
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| 84 | #define OETH_RX_BD_INVSIMB 0x0020 /* Rx BD Invalid Symbol Status */ |
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| 85 | #define OETH_RX_BD_DRIBBLE 0x0010 /* Rx BD Dribble Nibble Status */ |
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| 86 | #define OETH_RX_BD_TOOLONG 0x0008 /* Rx BD Too Long Status */ |
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| 87 | #define OETH_RX_BD_SHORT 0x0004 /* Rx BD Too Short Frame Status */ |
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| 88 | #define OETH_RX_BD_CRCERR 0x0002 /* Rx BD CRC Error Status */ |
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| 89 | #define OETH_RX_BD_LATECOL 0x0001 /* Rx BD Late Collision Status */ |
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| 90 | #define OETH_RX_BD_STATS (OETH_RX_BD_MISS | \ |
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| 91 | OETH_RX_BD_OVERRUN | \ |
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| 92 | OETH_RX_BD_INVSIMB | \ |
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| 93 | OETH_RX_BD_DRIBBLE | \ |
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| 94 | OETH_RX_BD_TOOLONG | \ |
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| 95 | OETH_RX_BD_SHORT | \ |
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| 96 | OETH_RX_BD_CRCERR | \ |
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| 97 | OETH_RX_BD_LATECOL) |
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| 98 | |
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| 99 | /* MODER Register */ |
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| 100 | #define OETH_MODER_RXEN 0x00000001 /* Receive Enable */ |
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| 101 | #define OETH_MODER_TXEN 0x00000002 /* Transmit Enable */ |
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| 102 | #define OETH_MODER_NOPRE 0x00000004 /* No Preamble */ |
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| 103 | #define OETH_MODER_BRO 0x00000008 /* Reject Broadcast */ |
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| 104 | #define OETH_MODER_IAM 0x00000010 /* Use Individual Hash */ |
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| 105 | #define OETH_MODER_PRO 0x00000020 /* Promiscuous (receive all) */ |
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| 106 | #define OETH_MODER_IFG 0x00000040 /* Min. IFG not required */ |
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| 107 | #define OETH_MODER_LOOPBCK 0x00000080 /* Loop Back */ |
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| 108 | #define OETH_MODER_NOBCKOF 0x00000100 /* No Backoff */ |
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| 109 | #define OETH_MODER_EXDFREN 0x00000200 /* Excess Defer */ |
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| 110 | #define OETH_MODER_FULLD 0x00000400 /* Full Duplex */ |
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| 111 | #define OETH_MODER_RST 0x00000800 /* Reset MAC */ |
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| 112 | #define OETH_MODER_DLYCRCEN 0x00001000 /* Delayed CRC Enable */ |
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| 113 | #define OETH_MODER_CRCEN 0x00002000 /* CRC Enable */ |
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| 114 | #define OETH_MODER_HUGEN 0x00004000 /* Huge Enable */ |
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| 115 | #define OETH_MODER_PAD 0x00008000 /* Pad Enable */ |
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| 116 | #define OETH_MODER_RECSMALL 0x00010000 /* Receive Small */ |
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| 117 | |
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| 118 | /* Interrupt Source Register */ |
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| 119 | #define OETH_INT_TXB 0x00000001 /* Transmit Buffer IRQ */ |
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| 120 | #define OETH_INT_TXE 0x00000002 /* Transmit Error IRQ */ |
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| 121 | #define OETH_INT_RXF 0x00000004 /* Receive Frame IRQ */ |
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| 122 | #define OETH_INT_RXE 0x00000008 /* Receive Error IRQ */ |
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| 123 | #define OETH_INT_BUSY 0x00000010 /* Busy IRQ */ |
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| 124 | #define OETH_INT_TXC 0x00000020 /* Transmit Control Frame IRQ */ |
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| 125 | #define OETH_INT_RXC 0x00000040 /* Received Control Frame IRQ */ |
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| 126 | |
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| 127 | /* Interrupt Mask Register */ |
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| 128 | #define OETH_INT_MASK_TXB 0x00000001 /* Transmit Buffer IRQ Mask */ |
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| 129 | #define OETH_INT_MASK_TXE 0x00000002 /* Transmit Error IRQ Mask */ |
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| 130 | #define OETH_INT_MASK_RXF 0x00000004 /* Receive Frame IRQ Mask */ |
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| 131 | #define OETH_INT_MASK_RXE 0x00000008 /* Receive Error IRQ Mask */ |
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| 132 | #define OETH_INT_MASK_BUSY 0x00000010 /* Busy IRQ Mask */ |
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| 133 | #define OETH_INT_MASK_TXC 0x00000020 /* Transmit Control Frame IRQ Mask */ |
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| 134 | #define OETH_INT_MASK_RXC 0x00000040 /* Received Control Frame IRQ Mask */ |
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| 135 | |
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| 136 | /* Control Module Mode Register */ |
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| 137 | #define OETH_CTRLMODER_PASSALL 0x00000001 /* Pass Control Frames */ |
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| 138 | #define OETH_CTRLMODER_RXFLOW 0x00000002 /* Receive Control Flow Enable */ |
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| 139 | #define OETH_CTRLMODER_TXFLOW 0x00000004 /* Transmit Control Flow Enable */ |
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| 140 | |
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| 141 | /* MII Mode Register */ |
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| 142 | #define OETH_MIIMODER_CLKDIV 0x000000FF /* Clock Divider */ |
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| 143 | #define OETH_MIIMODER_NOPRE 0x00000100 /* No Preamble */ |
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| 144 | #define OETH_MIIMODER_RST 0x00000200 /* MIIM Reset */ |
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| 145 | |
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| 146 | /* MII Command Register */ |
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| 147 | #define OETH_MIICOMMAND_SCANSTAT 0x00000001 /* Scan Status */ |
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| 148 | #define OETH_MIICOMMAND_RSTAT 0x00000002 /* Read Status */ |
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| 149 | #define OETH_MIICOMMAND_WCTRLDATA 0x00000004 /* Write Control Data */ |
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| 150 | |
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| 151 | /* MII Address Register */ |
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| 152 | #define OETH_MIIADDRESS_FIAD 0x0000001F /* PHY Address */ |
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| 153 | #define OETH_MIIADDRESS_RGAD 0x00001F00 /* RGAD Address */ |
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| 154 | |
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| 155 | /* MII Status Register */ |
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| 156 | #define OETH_MIISTATUS_LINKFAIL 0x00000001 /* Link Fail */ |
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| 157 | #define OETH_MIISTATUS_BUSY 0x00000002 /* MII Busy */ |
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| 158 | #define OETH_MIISTATUS_NVALID 0x00000004 /* Data in MII Status Register is invalid */ |
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| 159 | |
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| 160 | /* Attatch routine */ |
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| 161 | |
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| 162 | int rtems_open_eth_driver_attach ( |
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| 163 | struct rtems_bsdnet_ifconfig *config, |
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| 164 | open_eth_configuration_t *chip |
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| 165 | ); |
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| 166 | |
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| 167 | /* |
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| 168 | #ifdef CPU_U32_FIX |
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| 169 | void ipalign(struct mbuf *m); |
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| 170 | #endif |
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| 171 | |
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| 172 | */ |
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| 173 | #endif /* _OPEN_ETH_ */ |
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| 174 | |
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