source: rtems/c/src/libchip/network/open_eth.c @ f245c5e

4.104.114.84.95
Last change on this file since f245c5e was 104df63, checked in by Ralf Corsepius <ralf.corsepius@…>, on 01/09/06 at 15:44:11

2006-01-09 Ralf Corsepius <ralf.corsepius@…>

  • libchip/network/open_eth.c, libchip/network/open_eth.h: Merger from rtems-4-6-branch.
  • Property mode set to 100644
File size: 17.0 KB
Line 
1/*
2 *  RTEMS driver for Opencores Ethernet Controller
3 *
4 *  Weakly based on dec21140 rtems driver and open_eth linux driver
5 *  Written by Jiri Gaisler, Gaisler Research
6 *
7 *  The license and distribution terms for this file may be
8 *  found in found in the file LICENSE in this distribution or at
9 *  http://www.rtems.com/license/LICENSE.
10 *
11 */
12
13/*
14 *  This driver current only supports architectures with the old style
15 *  exception processing.  The following checks try to keep this
16 *  from being compiled on systems which can't support this driver.
17 *
18 *  NOTE: The i386, ARM, and PowerPC use a different interrupt API than
19 *        that used by this driver.
20 */
21
22#if defined(__i386__) || defined(__arm__) || defined(__PPC__)
23  #define OPENETH_NOT_SUPPORTED
24#endif
25
26#if !defined(OPENETH_NOT_SUPPORTED)
27#include <bsp.h>
28#include <rtems.h>
29
30#include <bsp.h>
31
32#include <inttypes.h>
33#include <stdlib.h>
34#include <stdio.h>
35#include <stdarg.h>
36#include <errno.h>
37
38#include <rtems/error.h>
39#include <rtems/rtems_bsdnet.h>
40#include <libchip/open_eth.h>
41
42#include <sys/param.h>
43#include <sys/mbuf.h>
44
45#include <sys/socket.h>
46#include <sys/sockio.h>
47#include <net/if.h>
48#include <netinet/in.h>
49#include <netinet/if_ether.h>
50
51#ifdef malloc
52#undef malloc
53#endif
54#ifdef free
55#undef free
56#endif
57
58 /*
59#define OPEN_ETH_DEBUG
60 */
61
62#ifdef CPU_U32_FIX
63extern void ipalign(struct mbuf *m);
64#endif
65
66/* message descriptor entry */
67struct MDTX
68{
69    char  *buf;
70};
71
72struct MDRX
73{
74    struct mbuf *m;
75};
76
77/*
78 * Number of OCs supported by this driver
79 */
80#define NOCDRIVER       1
81
82/*
83 * Receive buffer size -- Allow for a full ethernet packet including CRC
84 */
85#define RBUF_SIZE       1536
86
87#define ET_MINLEN 64            /* minimum message length */
88
89/*
90 * RTEMS event used by interrupt handler to signal driver tasks.
91 * This must not be any of the events used by the network task synchronization.
92 */
93#define INTERRUPT_EVENT RTEMS_EVENT_1
94
95/*
96 * RTEMS event used to start transmit daemon.
97 * This must not be the same as INTERRUPT_EVENT.
98 */
99#define START_TRANSMIT_EVENT    RTEMS_EVENT_2
100
101 /* event to send when tx buffers become available */
102#define OPEN_ETH_TX_WAIT_EVENT  RTEMS_EVENT_3
103
104 /* suspend when all TX descriptors exhausted */
105 /*
106#define OETH_SUSPEND_NOTXBUF
107 */
108
109#if (MCLBYTES < RBUF_SIZE)
110# error "Driver must have MCLBYTES > RBUF_SIZE"
111#endif
112
113/*
114 * Per-device data
115 */
116struct open_eth_softc
117{
118
119    struct arpcom arpcom;
120
121    oeth_regs *regs;
122
123    int acceptBroadcast;
124    rtems_id rxDaemonTid;
125    rtems_id txDaemonTid;
126
127    unsigned int tx_ptr;
128    unsigned int rx_ptr;
129    unsigned int txbufs;
130    unsigned int rxbufs;
131    struct MDTX *txdesc;
132    struct MDRX *rxdesc;
133    rtems_vector_number vector;
134    unsigned int en100MHz;
135
136    /*
137     * Statistics
138     */
139    unsigned long rxInterrupts;
140    unsigned long rxPackets;
141    unsigned long rxLengthError;
142    unsigned long rxNonOctet;
143    unsigned long rxBadCRC;
144    unsigned long rxOverrun;
145    unsigned long rxMiss;
146    unsigned long rxCollision;
147
148    unsigned long txInterrupts;
149    unsigned long txDeferred;
150    unsigned long txHeartbeat;
151    unsigned long txLateCollision;
152    unsigned long txRetryLimit;
153    unsigned long txUnderrun;
154    unsigned long txLostCarrier;
155    unsigned long txRawWait;
156};
157
158static struct open_eth_softc oc;
159
160/* OPEN_ETH interrupt handler */
161
162static rtems_isr
163open_eth_interrupt_handler (rtems_vector_number v)
164{
165    uint32_t status;
166
167    /* read and clear interrupt cause */
168
169    status = oc.regs->int_src;
170    oc.regs->int_src = status;
171
172    /* Frame received? */
173
174    if (status & (OETH_INT_RXF | OETH_INT_RXE))
175      {
176          oc.rxInterrupts++;
177          rtems_event_send (oc.rxDaemonTid, INTERRUPT_EVENT);
178      }
179#ifdef OETH_SUSPEND_NOTXBUF
180    if (status & (OETH_INT_MASK_TXB | OETH_INT_MASK_TXC | OETH_INT_MASK_TXE))
181      {
182          oc.txInterrupts++;
183          rtems_event_send (oc.txDaemonTid, OPEN_ETH_TX_WAIT_EVENT);
184      }
185#endif
186      /*
187#ifdef __leon__
188      LEON_Clear_interrupt(v-0x10);
189#endif
190      */
191}
192
193static uint32_t read_mii(uint32_t addr)
194{
195    while (oc.regs->miistatus & OETH_MIISTATUS_BUSY) {}
196    oc.regs->miiaddress = addr << 8;
197    oc.regs->miicommand = OETH_MIICOMMAND_RSTAT;
198    while (oc.regs->miistatus & OETH_MIISTATUS_BUSY) {}
199    if (!(oc.regs->miistatus & OETH_MIISTATUS_NVALID))
200        return(oc.regs->miirx_data);
201    else {
202        printf("open_eth: failed to read mii\n");
203        return (0);
204    }
205}
206
207static void write_mii(uint32_t addr, uint32_t data)
208{
209    while (oc.regs->miistatus & OETH_MIISTATUS_BUSY) {}
210    oc.regs->miiaddress = addr << 8;
211    oc.regs->miitx_data = data;
212    oc.regs->miicommand = OETH_MIICOMMAND_WCTRLDATA;
213    while (oc.regs->miistatus & OETH_MIISTATUS_BUSY) {}
214}
215/*
216 * Initialize the ethernet hardware
217 */
218static void
219open_eth_initialize_hardware (struct open_eth_softc *sc)
220{
221    struct mbuf *m;
222    int i;
223    int mii_cr = 0;
224
225    oeth_regs *regs;
226
227    regs = sc->regs;
228
229    /* Reset the controller.  */
230
231    regs->ctrlmoder = 0;
232    regs->moder = OETH_MODER_RST;       /* Reset ON */
233    regs->moder = 0;                    /* Reset OFF */
234
235    /* reset PHY and wait for complettion */
236    mii_cr = 0x3300;
237    if (!sc->en100MHz) mii_cr = 0;
238    write_mii(0, mii_cr | 0x8000);
239    while (read_mii(0) & 0x8000) {}
240    if (!sc->en100MHz) write_mii(0, 0);
241    mii_cr = read_mii(0);
242    printf("open_eth: driver attached, PHY config : 0x%04" PRIx32 "\n", read_mii(0));
243
244#ifdef OPEN_ETH_DEBUG
245    printf("mii_cr: %04x\n", mii_cr);
246    for (i=0;i<21;i++)
247      printf("mii_reg %2d : 0x%04x\n", i, read_mii(i));
248#endif
249
250    /* Setting TXBD base to sc->txbufs  */
251
252    regs->tx_bd_num = sc->txbufs;
253
254    /* Initialize rx/tx pointers.  */
255
256    sc->rx_ptr = 0;
257    sc->tx_ptr = 0;
258
259    /* Set min/max packet length */
260    regs->packet_len = 0x00400600;
261
262    /* Set IPGT register to recomended value */
263    regs->ipgt = 0x00000015;
264
265    /* Set IPGR1 register to recomended value */
266    regs->ipgr1 = 0x0000000c;
267
268    /* Set IPGR2 register to recomended value */
269    regs->ipgr2 = 0x00000012;
270
271    /* Set COLLCONF register to recomended value */
272    regs->collconf = 0x000f003f;
273
274    /* initialize TX descriptors */
275
276    sc->txdesc = calloc(sc->txbufs, sizeof(*sc->txdesc));
277    for (i = 0; i < sc->txbufs; i++)
278      {
279          sc->regs->xd[i].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC;
280          sc->txdesc[i].buf = calloc(1, OETH_MAXBUF_LEN);
281#ifdef OPEN_ETH_DEBUG
282          printf("TXBUF: %08x\n", (int) sc->txdesc[i].buf);
283#endif
284      }
285    sc->regs->xd[sc->txbufs - 1].len_status |= OETH_TX_BD_WRAP;
286
287    /* allocate RX buffers */
288
289    sc->rxdesc = calloc(sc->rxbufs, sizeof(*sc->rxdesc));
290    for (i = 0; i < sc->rxbufs; i++)
291      {
292
293          MGETHDR (m, M_WAIT, MT_DATA);
294          MCLGET (m, M_WAIT);
295          m->m_pkthdr.rcvif = &sc->arpcom.ac_if;
296          sc->rxdesc[i].m = m;
297          sc->regs->xd[i + sc->txbufs].addr = mtod (m, uint32_t*);
298          sc->regs->xd[i + sc->txbufs].len_status =
299              OETH_RX_BD_EMPTY | OETH_RX_BD_IRQ;
300#ifdef OPEN_ETH_DEBUG
301          printf("RXBUF: %08x\n", (int) sc->rxdesc[i].m);
302#endif
303      }
304    sc->regs->xd[sc->rxbufs + sc->txbufs - 1].len_status |= OETH_RX_BD_WRAP;
305
306
307    /* set ethernet address.  */
308
309    regs->mac_addr1 = sc->arpcom.ac_enaddr[0] << 8 | sc->arpcom.ac_enaddr[1];
310    regs->mac_addr0 = sc->arpcom.ac_enaddr[2] << 24 | sc->arpcom.ac_enaddr[3] << 16 |
311        sc->arpcom.ac_enaddr[4] << 8 | sc->arpcom.ac_enaddr[5];
312
313    /* install interrupt vector */
314    set_vector (open_eth_interrupt_handler, sc->vector, 1);
315
316    /* clear all pending interrupts */
317
318    regs->int_src = 0xffffffff;
319
320    /* MAC mode register: PAD, IFG, CRCEN */
321
322    regs->moder = OETH_MODER_PAD | OETH_MODER_CRCEN | ((mii_cr & 0x100) << 2);
323
324    /* enable interrupts */
325
326    regs->int_mask = OETH_INT_MASK_RXF | OETH_INT_MASK_RXE | OETH_INT_MASK_RXC;
327
328#ifdef OETH_SUSPEND_NOTXBUF
329    regs->int_mask |= OETH_INT_MASK_TXB | OETH_INT_MASK_TXC | OETH_INT_MASK_TXE | OETH_INT_BUSY;*/
330    sc->regs->xd[(sc->txbufs - 1)/2].len_status |= OETH_TX_BD_IRQ;
331    sc->regs->xd[sc->txbufs - 1].len_status |= OETH_TX_BD_IRQ;
332#endif
333
334    regs->moder |= OETH_MODER_RXEN | OETH_MODER_TXEN;
335}
336
337static void
338open_eth_rxDaemon (void *arg)
339{
340    struct ether_header *eh;
341    struct open_eth_softc *dp = (struct open_eth_softc *) &oc;
342    struct ifnet *ifp = &dp->arpcom.ac_if;
343    struct mbuf *m;
344    unsigned int len, len_status, bad;
345    rtems_event_set events;
346
347
348    for (;;)
349      {
350
351          rtems_bsdnet_event_receive (INTERRUPT_EVENT,
352                                      RTEMS_WAIT | RTEMS_EVENT_ANY,
353                                      RTEMS_NO_TIMEOUT, &events);
354#ifdef OPEN_ETH_DEBUG
355    printf ("r\n");
356#endif
357
358          while (!
359                 ((len_status =
360                   dp->regs->xd[dp->rx_ptr+dp->txbufs].len_status) & OETH_RX_BD_EMPTY))
361            {
362                bad = 0;
363                if (len_status & (OETH_RX_BD_TOOLONG | OETH_RX_BD_SHORT))
364                  {
365                      dp->rxLengthError++;
366                      bad = 1;
367                  }
368                if (len_status & OETH_RX_BD_DRIBBLE)
369                  {
370                      dp->rxNonOctet++;
371                      bad = 1;
372                  }
373                if (len_status & OETH_RX_BD_CRCERR)
374                  {
375                      dp->rxBadCRC++;
376                      bad = 1;
377                  }
378                if (len_status & OETH_RX_BD_OVERRUN)
379                  {
380                      dp->rxOverrun++;
381                      bad = 1;
382                  }
383                if (len_status & OETH_RX_BD_MISS)
384                  {
385                      dp->rxMiss++;
386                      bad = 1;
387                  }
388                if (len_status & OETH_RX_BD_LATECOL)
389                  {
390                      dp->rxCollision++;
391                      bad = 1;
392                  }
393
394                if (!bad)
395                  {
396                      /* pass on the packet in the receive buffer */
397                      len = len_status >> 16;
398                      m = (struct mbuf *) (dp->rxdesc[dp->rx_ptr].m);
399                      m->m_len = m->m_pkthdr.len =
400                          len - sizeof (struct ether_header);
401                      eh = mtod (m, struct ether_header *);
402                      m->m_data += sizeof (struct ether_header);
403#ifdef CPU_U32_FIX
404                      ipalign(m);       /* Align packet on 32-bit boundary */
405#endif
406
407                      ether_input (ifp, eh, m);
408
409                      /* get a new mbuf */
410                      MGETHDR (m, M_WAIT, MT_DATA);
411                      MCLGET (m, M_WAIT);
412                      m->m_pkthdr.rcvif = ifp;
413                      dp->rxdesc[dp->rx_ptr].m = m;
414                      dp->regs->xd[dp->rx_ptr + dp->txbufs].addr =
415                          (uint32_t*) mtod (m, void *);
416                      dp->rxPackets++;
417                  }
418
419                dp->regs->xd[dp->rx_ptr+dp->txbufs].len_status =
420                  (dp->regs->xd[dp->rx_ptr+dp->txbufs].len_status &
421                    ~OETH_TX_BD_STATS) | OETH_TX_BD_READY;
422                dp->rx_ptr = (dp->rx_ptr + 1) % dp->rxbufs;
423            }
424      }
425}
426
427static int inside = 0;
428static void
429sendpacket (struct ifnet *ifp, struct mbuf *m)
430{
431    struct open_eth_softc *dp = ifp->if_softc;
432    unsigned char *temp;
433    struct mbuf *n;
434    unsigned int len, len_status;
435
436    if (inside) printf ("error: sendpacket re-entered!!\n");
437    inside = 1;
438    /*
439     * Waiting for Transmitter ready
440     */
441    n = m;
442
443    while (dp->regs->xd[dp->tx_ptr].len_status & OETH_TX_BD_READY)
444      {
445#ifdef OETH_SUSPEND_NOTXBUF
446          rtems_event_set events;
447          rtems_bsdnet_event_receive (OPEN_ETH_TX_WAIT_EVENT,
448                                      RTEMS_WAIT | RTEMS_EVENT_ANY,
449                                      TOD_MILLISECONDS_TO_TICKS(500), &events);
450#endif
451      }
452
453    len = 0;
454    temp = (unsigned char *) dp->txdesc[dp->tx_ptr].buf;
455    dp->regs->xd[dp->tx_ptr].addr = (uint32_t*) temp;
456
457#ifdef OPEN_ETH_DEBUG
458    printf("TXD: 0x%08x\n", (int) m->m_data);
459#endif
460    for (;;)
461        {
462#ifdef OPEN_ETH_DEBUG
463          int i;
464          printf("MBUF: 0x%08x : ", (int) m->m_data);
465          for (i=0;i<m->m_len;i++)
466            printf("%x%x", (m->m_data[i] >> 4) & 0x0ff, m->m_data[i] & 0x0ff);
467          printf("\n");
468#endif
469          len += m->m_len;
470          if (len <= RBUF_SIZE)
471            memcpy ((void *) temp, (char *) m->m_data, m->m_len);
472          temp += m->m_len;
473          if ((m = m->m_next) == NULL)
474              break;
475        }
476
477    m_freem (n);
478
479    /* don't send long packets */
480
481    if (len <= RBUF_SIZE) {
482
483     /* Clear all of the status flags.  */
484     len_status = dp->regs->xd[dp->tx_ptr].len_status & ~OETH_TX_BD_STATS;
485
486     /* If the frame is short, tell CPM to pad it.  */
487     if (len < ET_MINLEN) {
488        len_status |= OETH_TX_BD_PAD;
489        len = ET_MINLEN;
490     }
491     else
492        len_status &= ~OETH_TX_BD_PAD;
493
494      /* write buffer descriptor length and status */
495      len_status &= 0x0000ffff;
496      len_status |= (len << 16) | (OETH_TX_BD_READY | OETH_TX_BD_CRC);
497      dp->regs->xd[dp->tx_ptr].len_status = len_status;
498      dp->tx_ptr = (dp->tx_ptr + 1) % dp->txbufs;
499
500    }
501    inside = 0;
502}
503
504/*
505 * Driver transmit daemon
506 */
507void
508open_eth_txDaemon (void *arg)
509{
510    struct open_eth_softc *sc = (struct open_eth_softc *) arg;
511    struct ifnet *ifp = &sc->arpcom.ac_if;
512    struct mbuf *m;
513    rtems_event_set events;
514
515    for (;;)
516      {
517          /*
518           * Wait for packet
519           */
520
521          rtems_bsdnet_event_receive (START_TRANSMIT_EVENT,
522                                      RTEMS_EVENT_ANY | RTEMS_WAIT,
523                                      RTEMS_NO_TIMEOUT, &events);
524#ifdef OPEN_ETH_DEBUG
525    printf ("t\n");
526#endif
527
528          /*
529           * Send packets till queue is empty
530           */
531          for (;;)
532            {
533                /*
534                 * Get the next mbuf chain to transmit.
535                 */
536                IF_DEQUEUE (&ifp->if_snd, m);
537                if (!m)
538                    break;
539                sendpacket (ifp, m);
540            }
541          ifp->if_flags &= ~IFF_OACTIVE;
542      }
543}
544
545
546static void
547open_eth_start (struct ifnet *ifp)
548{
549    struct open_eth_softc *sc = ifp->if_softc;
550
551    rtems_event_send (sc->txDaemonTid, START_TRANSMIT_EVENT);
552    ifp->if_flags |= IFF_OACTIVE;
553}
554
555/*
556 * Initialize and start the device
557 */
558static void
559open_eth_init (void *arg)
560{
561    struct open_eth_softc *sc = arg;
562    struct ifnet *ifp = &sc->arpcom.ac_if;
563
564    if (sc->txDaemonTid == 0)
565      {
566
567          /*
568           * Set up OPEN_ETH hardware
569           */
570          open_eth_initialize_hardware (sc);
571
572          /*
573           * Start driver tasks
574           */
575          sc->rxDaemonTid = rtems_bsdnet_newproc ("DCrx", 4096,
576                                                  open_eth_rxDaemon, sc);
577          sc->txDaemonTid = rtems_bsdnet_newproc ("DCtx", 4096,
578                                                  open_eth_txDaemon, sc);
579      }
580
581    /*
582     * Tell the world that we're running.
583     */
584    ifp->if_flags |= IFF_RUNNING;
585
586}
587
588/*
589 * Stop the device
590 */
591static void
592open_eth_stop (struct open_eth_softc *sc)
593{
594    struct ifnet *ifp = &sc->arpcom.ac_if;
595
596    ifp->if_flags &= ~IFF_RUNNING;
597
598    sc->regs->moder = 0;                /* RX/TX OFF */
599    sc->regs->moder = OETH_MODER_RST;   /* Reset ON */
600    sc->regs->moder = 0;                /* Reset OFF */
601}
602
603
604/*
605 * Show interface statistics
606 */
607static void
608open_eth_stats (struct open_eth_softc *sc)
609{
610    printf ("         Rx Packets:%-8lu", sc->rxPackets);
611    printf ("      Rx Interrupts:%-8lu", sc->rxInterrupts);
612    printf ("          Length:%-8lu", sc->rxLengthError);
613    printf ("       Non-octet:%-8lu\n", sc->rxNonOctet);
614    printf ("            Bad CRC:%-8lu", sc->rxBadCRC);
615    printf ("         Overrun:%-8lu", sc->rxOverrun);
616    printf ("            Miss:%-8lu", sc->rxMiss);
617    printf ("       Collision:%-8lu\n", sc->rxCollision);
618
619    printf ("      Tx Interrupts:%-8lu", sc->txInterrupts);
620    printf ("        Deferred:%-8lu", sc->txDeferred);
621    printf (" Missed Hearbeat:%-8lu\n", sc->txHeartbeat);
622    printf ("         No Carrier:%-8lu", sc->txLostCarrier);
623    printf ("Retransmit Limit:%-8lu", sc->txRetryLimit);
624    printf ("  Late Collision:%-8lu\n", sc->txLateCollision);
625    printf ("           Underrun:%-8lu", sc->txUnderrun);
626    printf (" Raw output wait:%-8lu\n", sc->txRawWait);
627}
628
629/*
630 * Driver ioctl handler
631 */
632static int
633open_eth_ioctl (struct ifnet *ifp, u_long command, caddr_t data)
634{
635    struct open_eth_softc *sc = ifp->if_softc;
636    int error = 0;
637
638    switch (command)
639      {
640      case SIOCGIFADDR:
641      case SIOCSIFADDR:
642          ether_ioctl (ifp, command, data);
643          break;
644
645      case SIOCSIFFLAGS:
646          switch (ifp->if_flags & (IFF_UP | IFF_RUNNING))
647            {
648            case IFF_RUNNING:
649                open_eth_stop (sc);
650                break;
651
652            case IFF_UP:
653                open_eth_init (sc);
654                break;
655
656            case IFF_UP | IFF_RUNNING:
657                open_eth_stop (sc);
658                open_eth_init (sc);
659                break;
660
661            default:
662                break;
663            }
664          break;
665
666      case SIO_RTEMS_SHOW_STATS:
667          open_eth_stats (sc);
668          break;
669
670          /*
671           * FIXME: All sorts of multicast commands need to be added here!
672           */
673      default:
674          error = EINVAL;
675          break;
676      }
677
678    return error;
679}
680
681/*
682 * Attach an OPEN_ETH driver to the system
683 */
684int
685rtems_open_eth_driver_attach (struct rtems_bsdnet_ifconfig *config,
686                              open_eth_configuration_t * chip)
687{
688    struct open_eth_softc *sc;
689    struct ifnet *ifp;
690    int mtu;
691    int unitNumber;
692    char *unitName;
693
694      /* parse driver name */
695    if ((unitNumber = rtems_bsdnet_parse_driver_name (config, &unitName)) < 0)
696        return 0;
697
698    sc = &oc;
699    ifp = &sc->arpcom.ac_if;
700    memset (sc, 0, sizeof (*sc));
701
702    if (config->hardware_address)
703      {
704          memcpy (sc->arpcom.ac_enaddr, config->hardware_address,
705                  ETHER_ADDR_LEN);
706      }
707    else
708      {
709          memset (sc->arpcom.ac_enaddr, 0x08, ETHER_ADDR_LEN);
710      }
711
712    if (config->mtu)
713        mtu = config->mtu;
714    else
715        mtu = ETHERMTU;
716
717    sc->acceptBroadcast = !config->ignore_broadcast;
718    sc->regs = (void *) chip->base_address;
719    sc->vector = chip->vector;
720    sc->txbufs = chip->txd_count;
721    sc->rxbufs = chip->rxd_count;
722    sc->en100MHz = chip->en100MHz;
723
724
725    /*
726     * Set up network interface values
727     */
728    ifp->if_softc = sc;
729    ifp->if_unit = unitNumber;
730    ifp->if_name = unitName;
731    ifp->if_mtu = mtu;
732    ifp->if_init = open_eth_init;
733    ifp->if_ioctl = open_eth_ioctl;
734    ifp->if_start = open_eth_start;
735    ifp->if_output = ether_output;
736    ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX;
737    if (ifp->if_snd.ifq_maxlen == 0)
738        ifp->if_snd.ifq_maxlen = ifqmaxlen;
739
740    /*
741     * Attach the interface
742     */
743    if_attach (ifp);
744    ether_ifattach (ifp);
745
746#ifdef OPEN_ETH_DEBUG
747    printf ("OPEN_ETH : driver has been attached\n");
748#endif
749    return 1;
750};
751
752#endif  /* OPENETH_NOT_SUPPORTED */
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