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source: rtems/c/src/libchip/network/open_eth.c @ 845e4f3

4.104.114.84.95

Last change on this file since 845e4f3 was 845e4f3, checked in by Joel Sherrill <joel.sherrill@…>, on 03/05/04 at 18:12:33

2004-03-05 Joel Sherrill <joel@…>

libchipnetwork/open_eth.c: Remove warnings by conditionally compiling this file only only those CPU families with supported exception models.

Property mode set to 100644

File size: 16.9 KB

Line
1	/*
2	* RTEMS driver for Opencores Ethernet Controller
3	*
4	* Weakly based on dec21140 rtems driver and open_eth linux driver
5	* Written by Jiri Gaisler, Gaisler Research
6	*
7	* The license and distribution terms for this file may be
8	* found in found in the file LICENSE in this distribution or at
9	* http://www.rtems.com/license/LICENSE.
10	*
11	*/
12
13	/*
14	* This driver current only supports architectures with the old style
15	* exception processing. The following checks try to keep this
16	* from being compiled on systems which can't support this driver.
17	*/
18
19	#if defined(__i386__)
20	#define OPENETH_NOT_SUPPORTED
21	#endif
22
23	#if defined(__PPC__) && (defined(mpc604) \|\| defined(mpc750) \|\| defined(mpc603e))
24	#define OPENETH_NOT_SUPPORTED
25	#endif
26
27	#if !defined(OPENETH_NOT_SUPPORTED)
28	#include <bsp.h>
29	#include <rtems.h>
30
31	#include <bsp.h>
32
33	#include <stdlib.h>
34	#include <stdio.h>
35	#include <stdarg.h>
36	#include <rtems/error.h>
37	#include <rtems/rtems_bsdnet.h>
38	#include <libchip/open_eth.h>
39
40	#include <sys/param.h>
41	#include <sys/mbuf.h>
42
43	#include <sys/socket.h>
44	#include <sys/sockio.h>
45	#include <net/if.h>
46	#include <netinet/in.h>
47	#include <netinet/if_ether.h>
48
49	#ifdef malloc
50	#undef malloc
51	#endif
52	#ifdef free
53	#undef free
54	#endif
55
56	/*
57	#define OPEN_ETH_DEBUG
58	*/
59
60	#ifdef CPU_U32_FIX
61	extern void ipalign(struct mbuf *m);
62	#endif
63
64	/* message descriptor entry */
65	struct MDTX
66	{
67	char *buf;
68	};
69
70	struct MDRX
71	{
72	struct mbuf *m;
73	};
74
75	/*
76	* Number of OCs supported by this driver
77	*/
78	#define NOCDRIVER 1
79
80	/*
81	* Receive buffer size -- Allow for a full ethernet packet including CRC
82	*/
83	#define RBUF_SIZE 1536
84
85	#define ET_MINLEN 64 /* minimum message length */
86
87	/*
88	* RTEMS event used by interrupt handler to signal driver tasks.
89	* This must not be any of the events used by the network task synchronization.
90	*/
91	#define INTERRUPT_EVENT RTEMS_EVENT_1
92
93	/*
94	* RTEMS event used to start transmit daemon.
95	* This must not be the same as INTERRUPT_EVENT.
96	*/
97	#define START_TRANSMIT_EVENT RTEMS_EVENT_2
98
99	/* event to send when tx buffers become available */
100	#define OPEN_ETH_TX_WAIT_EVENT RTEMS_EVENT_3
101
102	/* suspend when all TX descriptors exhausted */
103	/*
104	#define OETH_SUSPEND_NOTXBUF
105	*/
106
107	#define OETH_RATE_10MHZ
108
109	#if (MCLBYTES < RBUF_SIZE)
110	# error "Driver must have MCLBYTES > RBUF_SIZE"
111	#endif
112
113	/*
114	* Per-device data
115	*/
116	struct open_eth_softc
117	{
118
119	struct arpcom arpcom;
120
121	oeth_regs *regs;
122
123	int acceptBroadcast;
124	rtems_id rxDaemonTid;
125	rtems_id txDaemonTid;
126
127	unsigned int tx_ptr;
128	unsigned int rx_ptr;
129	unsigned int txbufs;
130	unsigned int rxbufs;
131	struct MDTX *txdesc;
132	struct MDRX *rxdesc;
133	rtems_vector_number vector;
134
135
136	/*
137	* Statistics
138	*/
139	unsigned long rxInterrupts;
140	unsigned long rxPackets;
141	unsigned long rxLengthError;
142	unsigned long rxNonOctet;
143	unsigned long rxBadCRC;
144	unsigned long rxOverrun;
145	unsigned long rxMiss;
146	unsigned long rxCollision;
147
148	unsigned long txInterrupts;
149	unsigned long txDeferred;
150	unsigned long txHeartbeat;
151	unsigned long txLateCollision;
152	unsigned long txRetryLimit;
153	unsigned long txUnderrun;
154	unsigned long txLostCarrier;
155	unsigned long txRawWait;
156	};
157
158	static struct open_eth_softc oc;
159
160	/* OPEN_ETH interrupt handler */
161
162	static rtems_isr
163	open_eth_interrupt_handler (rtems_vector_number v)
164	{
165	unsigned32 status;
166
167	/* read and clear interrupt cause */
168
169	status = oc.regs->int_src;
170	oc.regs->int_src = status;
171
172	/* Frame received? */
173
174	if (status & (OETH_INT_RXF \| OETH_INT_RXE))
175	{
176	oc.rxInterrupts++;
177	rtems_event_send (oc.rxDaemonTid, INTERRUPT_EVENT);
178	}
179	#ifdef OETH_SUSPEND_NOTXBUF
180	if (status & (OETH_INT_MASK_TXB \| OETH_INT_MASK_TXC \| OETH_INT_MASK_TXE))
181	{
182	oc.txInterrupts++;
183	rtems_event_send (oc.txDaemonTid, OPEN_ETH_TX_WAIT_EVENT);
184	}
185	#endif
186	/*
187	#ifdef __leon__
188	LEON_Clear_interrupt(v-0x10);
189	#endif
190	*/
191	}
192
193	static unsigned32 read_mii(unsigned32 addr)
194	{
195	while (oc.regs->miistatus & OETH_MIISTATUS_BUSY) {}
196	oc.regs->miiaddress = addr << 8;
197	oc.regs->miicommand = OETH_MIICOMMAND_RSTAT;
198	while (oc.regs->miistatus & OETH_MIISTATUS_BUSY) {}
199	if (!(oc.regs->miistatus & OETH_MIISTATUS_NVALID))
200	return(oc.regs->miirx_data);
201	else {
202	printf("open_eth: failed to read mii\n");
203	return (0);
204	}
205	}
206
207	static void write_mii(unsigned32 addr, unsigned32 data)
208	{
209	while (oc.regs->miistatus & OETH_MIISTATUS_BUSY) {}
210	oc.regs->miiaddress = addr << 8;
211	oc.regs->miitx_data = data;
212	oc.regs->miicommand = OETH_MIICOMMAND_WCTRLDATA;
213	while (oc.regs->miistatus & OETH_MIISTATUS_BUSY) {}
214	}
215	/*
216	* Initialize the ethernet hardware
217	*/
218	static void
219	open_eth_initialize_hardware (struct open_eth_softc *sc)
220	{
221	struct mbuf *m;
222	int i;
223	int mii_cr = 0;
224
225	oeth_regs *regs;
226
227	regs = sc->regs;
228
229	/* Reset the controller. */
230
231	regs->ctrlmoder = 0;
232	regs->moder = OETH_MODER_RST; /* Reset ON */
233	regs->moder = 0; /* Reset OFF */
234
235	/* reset PHY and wait for complettion */
236	mii_cr = read_mii(0);
237	mii_cr = 0x3320;
238	#ifdef OETH_RATE_10MHZ
239	mii_cr = 0;
240	#endif
241	write_mii(0, mii_cr \| 0x8000);
242	while (read_mii(0) & 0x8000) {}
243	write_mii(20, 0x1422);
244	#ifdef OETH_RATE_10MHZ
245	mii_cr = 0;
246	#endif
247	write_mii(0, mii_cr);
248	printf("open_eth: driver attached, PHY config : 0x%04x\n", read_mii(0));
249
250	#ifdef OPEN_ETH_DEBUG
251	printf("mii_cr: %04x\n", mii_cr);
252	for (i=0;i<21;i++)
253	printf("mii_reg %2d : 0x%04x\n", i, read_mii(i));
254	#endif
255
256	/* Setting TXBD base to sc->txbufs */
257
258	regs->tx_bd_num = sc->txbufs;
259
260	/* Initialize rx/tx pointers. */
261
262	sc->rx_ptr = 0;
263	sc->tx_ptr = 0;
264
265	/* Set min/max packet length */
266	regs->packet_len = 0x00400600;
267
268	/* Set IPGT register to recomended value */
269	regs->ipgt = 0x00000015;
270
271	/* Set IPGR1 register to recomended value */
272	regs->ipgr1 = 0x0000000c;
273
274	/* Set IPGR2 register to recomended value */
275	regs->ipgr2 = 0x00000012;
276
277	/* Set COLLCONF register to recomended value */
278	regs->collconf = 0x000f003f;
279
280	/* initialize TX descriptors */
281
282	sc->txdesc = calloc(sc->txbufs, sizeof(*sc->txdesc));
283	for (i = 0; i < sc->txbufs; i++)
284	{
285	sc->regs->xd[i].len_status = OETH_TX_BD_PAD \| OETH_TX_BD_CRC;
286	sc->txdesc[i].buf = calloc(1, OETH_MAXBUF_LEN);
287	#ifdef OPEN_ETH_DEBUG
288	printf("TXBUF: %08x\n", (int) sc->txdesc[i].buf);
289	#endif
290	}
291	sc->regs->xd[sc->txbufs - 1].len_status \|= OETH_TX_BD_WRAP;
292
293	/* allocate RX buffers */
294
295	sc->rxdesc = calloc(sc->rxbufs, sizeof(*sc->rxdesc));
296	for (i = 0; i < sc->rxbufs; i++)
297	{
298
299	MGETHDR (m, M_WAIT, MT_DATA);
300	MCLGET (m, M_WAIT);
301	m->m_pkthdr.rcvif = &sc->arpcom.ac_if;
302	sc->rxdesc[i].m = m;
303	sc->regs->xd[i + sc->txbufs].addr = mtod (m, unsigned32 *);
304	sc->regs->xd[i + sc->txbufs].len_status =
305	OETH_RX_BD_EMPTY \| OETH_RX_BD_IRQ;
306	#ifdef OPEN_ETH_DEBUG
307	printf("RXBUF: %08x\n", (int) sc->rxdesc[i].m);
308	#endif
309	}
310	sc->regs->xd[sc->rxbufs + sc->txbufs - 1].len_status \|= OETH_RX_BD_WRAP;
311
312
313	/* set ethernet address. */
314
315	regs->mac_addr1 = sc->arpcom.ac_enaddr[0] << 8 \| sc->arpcom.ac_enaddr[1];
316	regs->mac_addr0 = sc->arpcom.ac_enaddr[2] << 24 \| sc->arpcom.ac_enaddr[3] << 16 \|
317	sc->arpcom.ac_enaddr[4] << 8 \| sc->arpcom.ac_enaddr[5];
318
319	/* install interrupt vector */
320	set_vector (open_eth_interrupt_handler, sc->vector, 1);
321
322	/* clear all pending interrupts */
323
324	regs->int_src = 0xffffffff;
325
326	/* MAC mode register: PAD, IFG, CRCEN */
327
328	regs->moder = OETH_MODER_PAD \| OETH_MODER_CRCEN \| ((mii_cr & 0x100) << 2);
329
330	/* enable interrupts */
331
332	regs->int_mask = OETH_INT_MASK_RXF \| OETH_INT_MASK_RXE \| OETH_INT_MASK_RXC;
333
334	#ifdef OETH_SUSPEND_NOTXBUF
335	regs->int_mask \|= OETH_INT_MASK_TXB \| OETH_INT_MASK_TXC \| OETH_INT_MASK_TXE \| OETH_INT_BUSY;*/
336	sc->regs->xd[(sc->txbufs - 1)/2].len_status \|= OETH_TX_BD_IRQ;
337	sc->regs->xd[sc->txbufs - 1].len_status \|= OETH_TX_BD_IRQ;
338	#endif
339
340	regs->moder \|= OETH_MODER_RXEN \| OETH_MODER_TXEN;
341	}
342
343	static void
344	open_eth_rxDaemon (void *arg)
345	{
346	struct ether_header *eh;
347	struct open_eth_softc dp = (struct open_eth_softc ) &oc;
348	struct ifnet *ifp = &dp->arpcom.ac_if;
349	struct mbuf *m;
350	unsigned int len, len_status, bad;
351	rtems_event_set events;
352
353
354	for (;;)
355	{
356
357	rtems_bsdnet_event_receive (INTERRUPT_EVENT,
358	RTEMS_WAIT \| RTEMS_EVENT_ANY,
359	RTEMS_NO_TIMEOUT, &events);
360	#ifdef OPEN_ETH_DEBUG
361	printf ("r\n");
362	#endif
363
364	while (!
365	((len_status =
366	dp->regs->xd[dp->rx_ptr+dp->txbufs].len_status) & OETH_RX_BD_EMPTY))
367	{
368	bad = 0;
369	if (len_status & (OETH_RX_BD_TOOLONG \| OETH_RX_BD_SHORT))
370	{
371	dp->rxLengthError++;
372	bad = 1;
373	}
374	if (len_status & OETH_RX_BD_DRIBBLE)
375	{
376	dp->rxNonOctet++;
377	bad = 1;
378	}
379	if (len_status & OETH_RX_BD_CRCERR)
380	{
381	dp->rxBadCRC++;
382	bad = 1;
383	}
384	if (len_status & OETH_RX_BD_OVERRUN)
385	{
386	dp->rxOverrun++;
387	bad = 1;
388	}
389	if (len_status & OETH_RX_BD_MISS)
390	{
391	dp->rxMiss++;
392	bad = 1;
393	}
394	if (len_status & OETH_RX_BD_LATECOL)
395	{
396	dp->rxCollision++;
397	bad = 1;
398	}
399
400	if (!bad)
401	{
402	/* pass on the packet in the receive buffer */
403	len = len_status >> 16;
404	m = (struct mbuf *) (dp->rxdesc[dp->rx_ptr].m);
405	m->m_len = m->m_pkthdr.len =
406	len - sizeof (struct ether_header);
407	eh = mtod (m, struct ether_header *);
408	m->m_data += sizeof (struct ether_header);
409	#ifdef CPU_U32_FIX
410	ipalign(m); /* Align packet on 32-bit boundary */
411	#endif
412
413	ether_input (ifp, eh, m);
414
415	/* get a new mbuf */
416	MGETHDR (m, M_WAIT, MT_DATA);
417	MCLGET (m, M_WAIT);
418	m->m_pkthdr.rcvif = ifp;
419	dp->rxdesc[dp->rx_ptr].m = m;
420	dp->regs->xd[dp->rx_ptr + dp->txbufs].addr =
421	(unsigned32 ) mtod (m, void );
422	dp->rxPackets++;
423	}
424
425	dp->regs->xd[dp->rx_ptr+dp->txbufs].len_status =
426	(dp->regs->xd[dp->rx_ptr+dp->txbufs].len_status &
427	~OETH_TX_BD_STATS) \| OETH_TX_BD_READY;
428	dp->rx_ptr = (dp->rx_ptr + 1) % dp->rxbufs;
429	}
430	}
431	}
432
433	static int inside = 0;
434	static void
435	sendpacket (struct ifnet ifp, struct mbuf m)
436	{
437	struct open_eth_softc *dp = ifp->if_softc;
438	unsigned char *temp;
439	struct mbuf *n;
440	unsigned int len, len_status;
441
442	if (inside) printf ("error: sendpacket re-entered!!\n");
443	inside = 1;
444	/*
445	* Waiting for Transmitter ready
446	*/
447	n = m;
448
449	while (dp->regs->xd[dp->tx_ptr].len_status & OETH_TX_BD_READY)
450	{
451	#ifdef OETH_SUSPEND_NOTXBUF
452	rtems_event_set events;
453	rtems_bsdnet_event_receive (OPEN_ETH_TX_WAIT_EVENT,
454	RTEMS_WAIT \| RTEMS_EVENT_ANY,
455	TOD_MILLISECONDS_TO_TICKS(500), &events);
456	#endif
457	}
458
459	len = 0;
460	temp = (unsigned char *) dp->txdesc[dp->tx_ptr].buf;
461	dp->regs->xd[dp->tx_ptr].addr = (unsigned32 *) temp;
462
463	#ifdef OPEN_ETH_DEBUG
464	printf("TXD: 0x%08x\n", (int) m->m_data);
465	#endif
466	for (;;)
467	{
468	#ifdef OPEN_ETH_DEBUG
469	int i;
470	printf("MBUF: 0x%08x : ", (int) m->m_data);
471	for (i=0;i<m->m_len;i++)
472	printf("%x%x", (m->m_data[i] >> 4) & 0x0ff, m->m_data[i] & 0x0ff);
473	printf("\n");
474	#endif
475	len += m->m_len;
476	if (len <= RBUF_SIZE)
477	memcpy ((void ) temp, (char ) m->m_data, m->m_len);
478	temp += m->m_len;
479	if ((m = m->m_next) == NULL)
480	break;
481	}
482
483	m_freem (n);
484
485	/* don't send long packets */
486
487	if (len <= RBUF_SIZE) {
488
489	/* Clear all of the status flags. */
490	len_status = dp->regs->xd[dp->tx_ptr].len_status & ~OETH_TX_BD_STATS;
491
492	/* If the frame is short, tell CPM to pad it. */
493	if (len < ET_MINLEN) {
494	len_status \|= OETH_TX_BD_PAD;
495	len = ET_MINLEN;
496	}
497	else
498	len_status &= ~OETH_TX_BD_PAD;
499
500	/* write buffer descriptor length and status */
501	len_status \|= (len << 16) \| (OETH_TX_BD_READY \| OETH_TX_BD_CRC);
502	dp->regs->xd[dp->tx_ptr].len_status = len_status;
503	dp->tx_ptr = (dp->tx_ptr + 1) % dp->txbufs;
504
505	}
506	inside = 0;
507	}
508
509	/*
510	* Driver transmit daemon
511	*/
512	void
513	open_eth_txDaemon (void *arg)
514	{
515	struct open_eth_softc sc = (struct open_eth_softc ) arg;
516	struct ifnet *ifp = &sc->arpcom.ac_if;
517	struct mbuf *m;
518	rtems_event_set events;
519
520	for (;;)
521	{
522	/*
523	* Wait for packet
524	*/
525
526	rtems_bsdnet_event_receive (START_TRANSMIT_EVENT,
527	RTEMS_EVENT_ANY \| RTEMS_WAIT,
528	RTEMS_NO_TIMEOUT, &events);
529	#ifdef OPEN_ETH_DEBUG
530	printf ("t\n");
531	#endif
532
533	/*
534	* Send packets till queue is empty
535	*/
536	for (;;)
537	{
538	/*
539	* Get the next mbuf chain to transmit.
540	*/
541	IF_DEQUEUE (&ifp->if_snd, m);
542	if (!m)
543	break;
544	sendpacket (ifp, m);
545	}
546	ifp->if_flags &= ~IFF_OACTIVE;
547	}
548	}
549
550
551	static void
552	open_eth_start (struct ifnet *ifp)
553	{
554	struct open_eth_softc *sc = ifp->if_softc;
555
556	rtems_event_send (sc->txDaemonTid, START_TRANSMIT_EVENT);
557	ifp->if_flags \|= IFF_OACTIVE;
558	}
559
560	/*
561	* Initialize and start the device
562	*/
563	static void
564	open_eth_init (void *arg)
565	{
566	struct open_eth_softc *sc = arg;
567	struct ifnet *ifp = &sc->arpcom.ac_if;
568
569	if (sc->txDaemonTid == 0)
570	{
571
572	/*
573	* Set up OPEN_ETH hardware
574	*/
575	open_eth_initialize_hardware (sc);
576
577	/*
578	* Start driver tasks
579	*/
580	sc->rxDaemonTid = rtems_bsdnet_newproc ("DCrx", 4096,
581	open_eth_rxDaemon, sc);
582	sc->txDaemonTid = rtems_bsdnet_newproc ("DCtx", 4096,
583	open_eth_txDaemon, sc);
584	}
585
586	/*
587	* Tell the world that we're running.
588	*/
589	ifp->if_flags \|= IFF_RUNNING;
590
591	}
592
593	/*
594	* Stop the device
595	*/
596	static void
597	open_eth_stop (struct open_eth_softc *sc)
598	{
599	struct ifnet *ifp = &sc->arpcom.ac_if;
600
601	ifp->if_flags &= ~IFF_RUNNING;
602
603	sc->regs->moder = 0; /* RX/TX OFF */
604	sc->regs->moder = OETH_MODER_RST; /* Reset ON */
605	sc->regs->moder = 0; /* Reset OFF */
606	}
607
608
609	/*
610	* Show interface statistics
611	*/
612	static void
613	open_eth_stats (struct open_eth_softc *sc)
614	{
615	printf (" Rx Packets:%-8lu", sc->rxPackets);
616	printf (" Rx Interrupts:%-8lu", sc->rxInterrupts);
617	printf (" Length:%-8lu", sc->rxLengthError);
618	printf (" Non-octet:%-8lu\n", sc->rxNonOctet);
619	printf (" Bad CRC:%-8lu", sc->rxBadCRC);
620	printf (" Overrun:%-8lu", sc->rxOverrun);
621	printf (" Miss:%-8lu", sc->rxMiss);
622	printf (" Collision:%-8lu\n", sc->rxCollision);
623
624	printf (" Tx Interrupts:%-8lu", sc->txInterrupts);
625	printf (" Deferred:%-8lu", sc->txDeferred);
626	printf (" Missed Hearbeat:%-8lu\n", sc->txHeartbeat);
627	printf (" No Carrier:%-8lu", sc->txLostCarrier);
628	printf ("Retransmit Limit:%-8lu", sc->txRetryLimit);
629	printf (" Late Collision:%-8lu\n", sc->txLateCollision);
630	printf (" Underrun:%-8lu", sc->txUnderrun);
631	printf (" Raw output wait:%-8lu\n", sc->txRawWait);
632	}
633
634	/*
635	* Driver ioctl handler
636	*/
637	static int
638	open_eth_ioctl (struct ifnet *ifp, int command, caddr_t data)
639	{
640	struct open_eth_softc *sc = ifp->if_softc;
641	int error = 0;
642
643	switch (command)
644	{
645	case SIOCGIFADDR:
646	case SIOCSIFADDR:
647	ether_ioctl (ifp, command, data);
648	break;
649
650	case SIOCSIFFLAGS:
651	switch (ifp->if_flags & (IFF_UP \| IFF_RUNNING))
652	{
653	case IFF_RUNNING:
654	open_eth_stop (sc);
655	break;
656
657	case IFF_UP:
658	open_eth_init (sc);
659	break;
660
661	case IFF_UP \| IFF_RUNNING:
662	open_eth_stop (sc);
663	open_eth_init (sc);
664	break;
665
666	default:
667	break;
668	}
669	break;
670
671	case SIO_RTEMS_SHOW_STATS:
672	open_eth_stats (sc);
673	break;
674
675	/*
676	* FIXME: All sorts of multicast commands need to be added here!
677	*/
678	default:
679	error = EINVAL;
680	break;
681	}
682
683	return error;
684	}
685
686	/*
687	* Attach an OPEN_ETH driver to the system
688	*/
689	int
690	rtems_open_eth_driver_attach (struct rtems_bsdnet_ifconfig *config,
691	open_eth_configuration_t * chip)
692	{
693	struct open_eth_softc *sc;
694	struct ifnet *ifp;
695	int mtu;
696	int unitNumber;
697	char *unitName;
698
699	/* parse driver name */
700	if ((unitNumber = rtems_bsdnet_parse_driver_name (config, &unitName)) < 0)
701	return 0;
702
703	sc = &oc;
704	ifp = &sc->arpcom.ac_if;
705	memset (sc, 0, sizeof (*sc));
706
707	if (config->hardware_address)
708	{
709	memcpy (sc->arpcom.ac_enaddr, config->hardware_address,
710	ETHER_ADDR_LEN);
711	}
712	else
713	{
714	memset (sc->arpcom.ac_enaddr, 0x08, ETHER_ADDR_LEN);
715	}
716
717	if (config->mtu)
718	mtu = config->mtu;
719	else
720	mtu = ETHERMTU;
721
722	sc->acceptBroadcast = !config->ignore_broadcast;
723	sc->regs = (void *) chip->base_address;
724	sc->vector = chip->vector;
725	sc->txbufs = chip->txd_count;
726	sc->rxbufs = chip->rxd_count;
727
728
729	/*
730	* Set up network interface values
731	*/
732	ifp->if_softc = sc;
733	ifp->if_unit = unitNumber;
734	ifp->if_name = unitName;
735	ifp->if_mtu = mtu;
736	ifp->if_init = open_eth_init;
737	ifp->if_ioctl = open_eth_ioctl;
738	ifp->if_start = open_eth_start;
739	ifp->if_output = ether_output;
740	ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX;
741	if (ifp->if_snd.ifq_maxlen == 0)
742	ifp->if_snd.ifq_maxlen = ifqmaxlen;
743
744	/*
745	* Attach the interface
746	*/
747	if_attach (ifp);
748	ether_ifattach (ifp);
749
750	#ifdef OPEN_ETH_DEBUG
751	printf ("OPEN_ETH : driver has been attached\n");
752	#endif
753	return 1;
754	};
755
756	#endif /* OPENETH_NOT_SUPPORTED */

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