[398ed76] | 1 | /* |
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| 2 | * RTEMS driver for Opencores Ethernet Controller |
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| 3 | * |
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| 4 | * Weakly based on dec21140 rtems driver and open_eth linux driver |
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| 5 | * Written by Jiri Gaisler, Gaisler Research |
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| 6 | * |
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| 7 | * The license and distribution terms for this file may be |
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| 8 | * found in found in the file LICENSE in this distribution or at |
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[94365d9] | 9 | * http://www.rtems.com/license/LICENSE. |
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[398ed76] | 10 | * |
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| 11 | */ |
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| 12 | |
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[845e4f3] | 13 | /* |
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| 14 | * This driver current only supports architectures with the old style |
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| 15 | * exception processing. The following checks try to keep this |
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| 16 | * from being compiled on systems which can't support this driver. |
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[e11bf43] | 17 | * |
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| 18 | * NOTE: The i386, ARM, and PowerPC use a different interrupt API than |
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| 19 | * that used by this driver. |
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[845e4f3] | 20 | */ |
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| 21 | |
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[e11bf43] | 22 | #if defined(__i386__) || defined(__arm__) || defined(__PPC__) |
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[845e4f3] | 23 | #define OPENETH_NOT_SUPPORTED |
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| 24 | #endif |
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| 25 | |
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| 26 | #if !defined(OPENETH_NOT_SUPPORTED) |
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| 27 | #include <bsp.h> |
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[398ed76] | 28 | #include <rtems.h> |
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| 29 | |
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| 30 | #include <bsp.h> |
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| 31 | |
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[104df63] | 32 | #include <inttypes.h> |
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[398ed76] | 33 | #include <stdlib.h> |
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| 34 | #include <stdio.h> |
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| 35 | #include <stdarg.h> |
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[c8e8f119] | 36 | #include <errno.h> |
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| 37 | |
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[398ed76] | 38 | #include <rtems/error.h> |
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| 39 | #include <rtems/rtems_bsdnet.h> |
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| 40 | #include <libchip/open_eth.h> |
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| 41 | |
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| 42 | #include <sys/param.h> |
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| 43 | #include <sys/mbuf.h> |
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| 44 | |
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| 45 | #include <sys/socket.h> |
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| 46 | #include <sys/sockio.h> |
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| 47 | #include <net/if.h> |
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| 48 | #include <netinet/in.h> |
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| 49 | #include <netinet/if_ether.h> |
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| 50 | |
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| 51 | #ifdef malloc |
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| 52 | #undef malloc |
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| 53 | #endif |
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| 54 | #ifdef free |
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| 55 | #undef free |
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| 56 | #endif |
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| 57 | |
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| 58 | /* |
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| 59 | #define OPEN_ETH_DEBUG |
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| 60 | */ |
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| 61 | |
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| 62 | #ifdef CPU_U32_FIX |
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| 63 | extern void ipalign(struct mbuf *m); |
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| 64 | #endif |
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| 65 | |
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| 66 | /* message descriptor entry */ |
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| 67 | struct MDTX |
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| 68 | { |
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| 69 | char *buf; |
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| 70 | }; |
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| 71 | |
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| 72 | struct MDRX |
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| 73 | { |
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| 74 | struct mbuf *m; |
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| 75 | }; |
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| 76 | |
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| 77 | /* |
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| 78 | * Number of OCs supported by this driver |
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| 79 | */ |
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| 80 | #define NOCDRIVER 1 |
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| 81 | |
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| 82 | /* |
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| 83 | * Receive buffer size -- Allow for a full ethernet packet including CRC |
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| 84 | */ |
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| 85 | #define RBUF_SIZE 1536 |
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| 86 | |
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| 87 | #define ET_MINLEN 64 /* minimum message length */ |
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| 88 | |
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| 89 | /* |
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| 90 | * RTEMS event used by interrupt handler to signal driver tasks. |
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| 91 | * This must not be any of the events used by the network task synchronization. |
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| 92 | */ |
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| 93 | #define INTERRUPT_EVENT RTEMS_EVENT_1 |
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| 94 | |
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| 95 | /* |
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| 96 | * RTEMS event used to start transmit daemon. |
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| 97 | * This must not be the same as INTERRUPT_EVENT. |
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| 98 | */ |
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| 99 | #define START_TRANSMIT_EVENT RTEMS_EVENT_2 |
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| 100 | |
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| 101 | /* event to send when tx buffers become available */ |
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| 102 | #define OPEN_ETH_TX_WAIT_EVENT RTEMS_EVENT_3 |
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| 103 | |
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| 104 | /* suspend when all TX descriptors exhausted */ |
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| 105 | /* |
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| 106 | #define OETH_SUSPEND_NOTXBUF |
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| 107 | */ |
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| 108 | |
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| 109 | #if (MCLBYTES < RBUF_SIZE) |
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| 110 | # error "Driver must have MCLBYTES > RBUF_SIZE" |
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| 111 | #endif |
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| 112 | |
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| 113 | /* |
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| 114 | * Per-device data |
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| 115 | */ |
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| 116 | struct open_eth_softc |
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| 117 | { |
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| 118 | |
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| 119 | struct arpcom arpcom; |
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| 120 | |
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| 121 | oeth_regs *regs; |
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| 122 | |
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| 123 | int acceptBroadcast; |
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| 124 | rtems_id rxDaemonTid; |
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| 125 | rtems_id txDaemonTid; |
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| 126 | |
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| 127 | unsigned int tx_ptr; |
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| 128 | unsigned int rx_ptr; |
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| 129 | unsigned int txbufs; |
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| 130 | unsigned int rxbufs; |
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| 131 | struct MDTX *txdesc; |
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| 132 | struct MDRX *rxdesc; |
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| 133 | rtems_vector_number vector; |
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[104df63] | 134 | unsigned int en100MHz; |
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[398ed76] | 135 | |
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| 136 | /* |
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| 137 | * Statistics |
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| 138 | */ |
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| 139 | unsigned long rxInterrupts; |
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| 140 | unsigned long rxPackets; |
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| 141 | unsigned long rxLengthError; |
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| 142 | unsigned long rxNonOctet; |
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| 143 | unsigned long rxBadCRC; |
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| 144 | unsigned long rxOverrun; |
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| 145 | unsigned long rxMiss; |
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| 146 | unsigned long rxCollision; |
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| 147 | |
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| 148 | unsigned long txInterrupts; |
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| 149 | unsigned long txDeferred; |
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| 150 | unsigned long txHeartbeat; |
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| 151 | unsigned long txLateCollision; |
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| 152 | unsigned long txRetryLimit; |
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| 153 | unsigned long txUnderrun; |
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| 154 | unsigned long txLostCarrier; |
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| 155 | unsigned long txRawWait; |
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| 156 | }; |
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| 157 | |
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| 158 | static struct open_eth_softc oc; |
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| 159 | |
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| 160 | /* OPEN_ETH interrupt handler */ |
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| 161 | |
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| 162 | static rtems_isr |
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| 163 | open_eth_interrupt_handler (rtems_vector_number v) |
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| 164 | { |
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[104df63] | 165 | uint32_t status; |
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[398ed76] | 166 | |
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| 167 | /* read and clear interrupt cause */ |
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| 168 | |
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| 169 | status = oc.regs->int_src; |
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| 170 | oc.regs->int_src = status; |
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| 171 | |
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| 172 | /* Frame received? */ |
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| 173 | |
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| 174 | if (status & (OETH_INT_RXF | OETH_INT_RXE)) |
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| 175 | { |
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| 176 | oc.rxInterrupts++; |
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| 177 | rtems_event_send (oc.rxDaemonTid, INTERRUPT_EVENT); |
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| 178 | } |
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| 179 | #ifdef OETH_SUSPEND_NOTXBUF |
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| 180 | if (status & (OETH_INT_MASK_TXB | OETH_INT_MASK_TXC | OETH_INT_MASK_TXE)) |
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| 181 | { |
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| 182 | oc.txInterrupts++; |
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| 183 | rtems_event_send (oc.txDaemonTid, OPEN_ETH_TX_WAIT_EVENT); |
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| 184 | } |
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| 185 | #endif |
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| 186 | /* |
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| 187 | #ifdef __leon__ |
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| 188 | LEON_Clear_interrupt(v-0x10); |
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| 189 | #endif |
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| 190 | */ |
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| 191 | } |
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| 192 | |
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[104df63] | 193 | static uint32_t read_mii(uint32_t addr) |
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[398ed76] | 194 | { |
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| 195 | while (oc.regs->miistatus & OETH_MIISTATUS_BUSY) {} |
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| 196 | oc.regs->miiaddress = addr << 8; |
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| 197 | oc.regs->miicommand = OETH_MIICOMMAND_RSTAT; |
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| 198 | while (oc.regs->miistatus & OETH_MIISTATUS_BUSY) {} |
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| 199 | if (!(oc.regs->miistatus & OETH_MIISTATUS_NVALID)) |
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| 200 | return(oc.regs->miirx_data); |
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| 201 | else { |
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| 202 | printf("open_eth: failed to read mii\n"); |
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| 203 | return (0); |
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| 204 | } |
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| 205 | } |
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| 206 | |
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[104df63] | 207 | static void write_mii(uint32_t addr, uint32_t data) |
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[398ed76] | 208 | { |
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| 209 | while (oc.regs->miistatus & OETH_MIISTATUS_BUSY) {} |
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| 210 | oc.regs->miiaddress = addr << 8; |
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| 211 | oc.regs->miitx_data = data; |
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| 212 | oc.regs->miicommand = OETH_MIICOMMAND_WCTRLDATA; |
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| 213 | while (oc.regs->miistatus & OETH_MIISTATUS_BUSY) {} |
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| 214 | } |
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| 215 | /* |
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| 216 | * Initialize the ethernet hardware |
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| 217 | */ |
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| 218 | static void |
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| 219 | open_eth_initialize_hardware (struct open_eth_softc *sc) |
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| 220 | { |
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| 221 | struct mbuf *m; |
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| 222 | int i; |
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| 223 | int mii_cr = 0; |
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| 224 | |
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| 225 | oeth_regs *regs; |
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| 226 | |
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| 227 | regs = sc->regs; |
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| 228 | |
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| 229 | /* Reset the controller. */ |
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| 230 | |
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| 231 | regs->ctrlmoder = 0; |
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| 232 | regs->moder = OETH_MODER_RST; /* Reset ON */ |
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| 233 | regs->moder = 0; /* Reset OFF */ |
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| 234 | |
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| 235 | /* reset PHY and wait for complettion */ |
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[104df63] | 236 | mii_cr = 0x3300; |
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| 237 | if (!sc->en100MHz) mii_cr = 0; |
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[a3d3d9a] | 238 | write_mii(0, mii_cr | 0x8000); |
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[398ed76] | 239 | while (read_mii(0) & 0x8000) {} |
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[104df63] | 240 | if (!sc->en100MHz) write_mii(0, 0); |
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| 241 | mii_cr = read_mii(0); |
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| 242 | printf("open_eth: driver attached, PHY config : 0x%04" PRIx32 "\n", read_mii(0)); |
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[398ed76] | 243 | |
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| 244 | #ifdef OPEN_ETH_DEBUG |
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| 245 | printf("mii_cr: %04x\n", mii_cr); |
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| 246 | for (i=0;i<21;i++) |
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| 247 | printf("mii_reg %2d : 0x%04x\n", i, read_mii(i)); |
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| 248 | #endif |
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| 249 | |
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| 250 | /* Setting TXBD base to sc->txbufs */ |
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| 251 | |
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| 252 | regs->tx_bd_num = sc->txbufs; |
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| 253 | |
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| 254 | /* Initialize rx/tx pointers. */ |
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| 255 | |
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| 256 | sc->rx_ptr = 0; |
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| 257 | sc->tx_ptr = 0; |
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| 258 | |
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| 259 | /* Set min/max packet length */ |
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| 260 | regs->packet_len = 0x00400600; |
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| 261 | |
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| 262 | /* Set IPGT register to recomended value */ |
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| 263 | regs->ipgt = 0x00000015; |
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| 264 | |
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| 265 | /* Set IPGR1 register to recomended value */ |
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| 266 | regs->ipgr1 = 0x0000000c; |
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| 267 | |
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| 268 | /* Set IPGR2 register to recomended value */ |
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| 269 | regs->ipgr2 = 0x00000012; |
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| 270 | |
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| 271 | /* Set COLLCONF register to recomended value */ |
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| 272 | regs->collconf = 0x000f003f; |
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| 273 | |
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| 274 | /* initialize TX descriptors */ |
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| 275 | |
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| 276 | sc->txdesc = calloc(sc->txbufs, sizeof(*sc->txdesc)); |
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| 277 | for (i = 0; i < sc->txbufs; i++) |
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| 278 | { |
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| 279 | sc->regs->xd[i].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC; |
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| 280 | sc->txdesc[i].buf = calloc(1, OETH_MAXBUF_LEN); |
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| 281 | #ifdef OPEN_ETH_DEBUG |
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| 282 | printf("TXBUF: %08x\n", (int) sc->txdesc[i].buf); |
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| 283 | #endif |
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| 284 | } |
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| 285 | sc->regs->xd[sc->txbufs - 1].len_status |= OETH_TX_BD_WRAP; |
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| 286 | |
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| 287 | /* allocate RX buffers */ |
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| 288 | |
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| 289 | sc->rxdesc = calloc(sc->rxbufs, sizeof(*sc->rxdesc)); |
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| 290 | for (i = 0; i < sc->rxbufs; i++) |
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| 291 | { |
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| 292 | |
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| 293 | MGETHDR (m, M_WAIT, MT_DATA); |
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| 294 | MCLGET (m, M_WAIT); |
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| 295 | m->m_pkthdr.rcvif = &sc->arpcom.ac_if; |
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| 296 | sc->rxdesc[i].m = m; |
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[509fec9c] | 297 | sc->regs->xd[i + sc->txbufs].addr = mtod (m, uint32_t*); |
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[398ed76] | 298 | sc->regs->xd[i + sc->txbufs].len_status = |
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| 299 | OETH_RX_BD_EMPTY | OETH_RX_BD_IRQ; |
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| 300 | #ifdef OPEN_ETH_DEBUG |
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| 301 | printf("RXBUF: %08x\n", (int) sc->rxdesc[i].m); |
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| 302 | #endif |
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| 303 | } |
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| 304 | sc->regs->xd[sc->rxbufs + sc->txbufs - 1].len_status |= OETH_RX_BD_WRAP; |
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| 305 | |
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| 306 | |
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| 307 | /* set ethernet address. */ |
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| 308 | |
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| 309 | regs->mac_addr1 = sc->arpcom.ac_enaddr[0] << 8 | sc->arpcom.ac_enaddr[1]; |
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| 310 | regs->mac_addr0 = sc->arpcom.ac_enaddr[2] << 24 | sc->arpcom.ac_enaddr[3] << 16 | |
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| 311 | sc->arpcom.ac_enaddr[4] << 8 | sc->arpcom.ac_enaddr[5]; |
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| 312 | |
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| 313 | /* install interrupt vector */ |
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| 314 | set_vector (open_eth_interrupt_handler, sc->vector, 1); |
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| 315 | |
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| 316 | /* clear all pending interrupts */ |
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| 317 | |
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| 318 | regs->int_src = 0xffffffff; |
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| 319 | |
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| 320 | /* MAC mode register: PAD, IFG, CRCEN */ |
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| 321 | |
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| 322 | regs->moder = OETH_MODER_PAD | OETH_MODER_CRCEN | ((mii_cr & 0x100) << 2); |
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| 323 | |
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| 324 | /* enable interrupts */ |
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| 325 | |
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| 326 | regs->int_mask = OETH_INT_MASK_RXF | OETH_INT_MASK_RXE | OETH_INT_MASK_RXC; |
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| 327 | |
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| 328 | #ifdef OETH_SUSPEND_NOTXBUF |
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| 329 | regs->int_mask |= OETH_INT_MASK_TXB | OETH_INT_MASK_TXC | OETH_INT_MASK_TXE | OETH_INT_BUSY;*/ |
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| 330 | sc->regs->xd[(sc->txbufs - 1)/2].len_status |= OETH_TX_BD_IRQ; |
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| 331 | sc->regs->xd[sc->txbufs - 1].len_status |= OETH_TX_BD_IRQ; |
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| 332 | #endif |
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| 333 | |
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| 334 | regs->moder |= OETH_MODER_RXEN | OETH_MODER_TXEN; |
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| 335 | } |
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| 336 | |
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| 337 | static void |
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| 338 | open_eth_rxDaemon (void *arg) |
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| 339 | { |
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| 340 | struct ether_header *eh; |
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| 341 | struct open_eth_softc *dp = (struct open_eth_softc *) &oc; |
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| 342 | struct ifnet *ifp = &dp->arpcom.ac_if; |
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| 343 | struct mbuf *m; |
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| 344 | unsigned int len, len_status, bad; |
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| 345 | rtems_event_set events; |
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| 346 | |
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| 347 | |
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| 348 | for (;;) |
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| 349 | { |
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| 350 | |
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| 351 | rtems_bsdnet_event_receive (INTERRUPT_EVENT, |
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| 352 | RTEMS_WAIT | RTEMS_EVENT_ANY, |
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| 353 | RTEMS_NO_TIMEOUT, &events); |
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| 354 | #ifdef OPEN_ETH_DEBUG |
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| 355 | printf ("r\n"); |
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| 356 | #endif |
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| 357 | |
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| 358 | while (! |
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| 359 | ((len_status = |
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| 360 | dp->regs->xd[dp->rx_ptr+dp->txbufs].len_status) & OETH_RX_BD_EMPTY)) |
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| 361 | { |
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| 362 | bad = 0; |
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| 363 | if (len_status & (OETH_RX_BD_TOOLONG | OETH_RX_BD_SHORT)) |
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| 364 | { |
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| 365 | dp->rxLengthError++; |
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| 366 | bad = 1; |
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| 367 | } |
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| 368 | if (len_status & OETH_RX_BD_DRIBBLE) |
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| 369 | { |
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| 370 | dp->rxNonOctet++; |
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| 371 | bad = 1; |
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| 372 | } |
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| 373 | if (len_status & OETH_RX_BD_CRCERR) |
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| 374 | { |
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| 375 | dp->rxBadCRC++; |
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| 376 | bad = 1; |
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| 377 | } |
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| 378 | if (len_status & OETH_RX_BD_OVERRUN) |
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| 379 | { |
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| 380 | dp->rxOverrun++; |
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| 381 | bad = 1; |
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| 382 | } |
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| 383 | if (len_status & OETH_RX_BD_MISS) |
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| 384 | { |
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| 385 | dp->rxMiss++; |
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| 386 | bad = 1; |
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| 387 | } |
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| 388 | if (len_status & OETH_RX_BD_LATECOL) |
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| 389 | { |
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| 390 | dp->rxCollision++; |
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| 391 | bad = 1; |
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| 392 | } |
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| 393 | |
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| 394 | if (!bad) |
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| 395 | { |
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| 396 | /* pass on the packet in the receive buffer */ |
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| 397 | len = len_status >> 16; |
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| 398 | m = (struct mbuf *) (dp->rxdesc[dp->rx_ptr].m); |
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| 399 | m->m_len = m->m_pkthdr.len = |
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| 400 | len - sizeof (struct ether_header); |
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| 401 | eh = mtod (m, struct ether_header *); |
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| 402 | m->m_data += sizeof (struct ether_header); |
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| 403 | #ifdef CPU_U32_FIX |
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| 404 | ipalign(m); /* Align packet on 32-bit boundary */ |
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| 405 | #endif |
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| 406 | |
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| 407 | ether_input (ifp, eh, m); |
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| 408 | |
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| 409 | /* get a new mbuf */ |
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| 410 | MGETHDR (m, M_WAIT, MT_DATA); |
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| 411 | MCLGET (m, M_WAIT); |
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| 412 | m->m_pkthdr.rcvif = ifp; |
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| 413 | dp->rxdesc[dp->rx_ptr].m = m; |
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| 414 | dp->regs->xd[dp->rx_ptr + dp->txbufs].addr = |
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[509fec9c] | 415 | (uint32_t*) mtod (m, void *); |
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[398ed76] | 416 | dp->rxPackets++; |
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| 417 | } |
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| 418 | |
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| 419 | dp->regs->xd[dp->rx_ptr+dp->txbufs].len_status = |
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| 420 | (dp->regs->xd[dp->rx_ptr+dp->txbufs].len_status & |
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| 421 | ~OETH_TX_BD_STATS) | OETH_TX_BD_READY; |
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| 422 | dp->rx_ptr = (dp->rx_ptr + 1) % dp->rxbufs; |
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| 423 | } |
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| 424 | } |
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| 425 | } |
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| 426 | |
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| 427 | static int inside = 0; |
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| 428 | static void |
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| 429 | sendpacket (struct ifnet *ifp, struct mbuf *m) |
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| 430 | { |
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| 431 | struct open_eth_softc *dp = ifp->if_softc; |
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| 432 | unsigned char *temp; |
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| 433 | struct mbuf *n; |
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| 434 | unsigned int len, len_status; |
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| 435 | |
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| 436 | if (inside) printf ("error: sendpacket re-entered!!\n"); |
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| 437 | inside = 1; |
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| 438 | /* |
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| 439 | * Waiting for Transmitter ready |
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| 440 | */ |
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| 441 | n = m; |
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| 442 | |
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| 443 | while (dp->regs->xd[dp->tx_ptr].len_status & OETH_TX_BD_READY) |
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| 444 | { |
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| 445 | #ifdef OETH_SUSPEND_NOTXBUF |
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| 446 | rtems_event_set events; |
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| 447 | rtems_bsdnet_event_receive (OPEN_ETH_TX_WAIT_EVENT, |
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| 448 | RTEMS_WAIT | RTEMS_EVENT_ANY, |
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| 449 | TOD_MILLISECONDS_TO_TICKS(500), &events); |
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| 450 | #endif |
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| 451 | } |
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| 452 | |
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| 453 | len = 0; |
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| 454 | temp = (unsigned char *) dp->txdesc[dp->tx_ptr].buf; |
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[509fec9c] | 455 | dp->regs->xd[dp->tx_ptr].addr = (uint32_t*) temp; |
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[398ed76] | 456 | |
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| 457 | #ifdef OPEN_ETH_DEBUG |
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| 458 | printf("TXD: 0x%08x\n", (int) m->m_data); |
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| 459 | #endif |
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| 460 | for (;;) |
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| 461 | { |
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| 462 | #ifdef OPEN_ETH_DEBUG |
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| 463 | int i; |
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| 464 | printf("MBUF: 0x%08x : ", (int) m->m_data); |
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| 465 | for (i=0;i<m->m_len;i++) |
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| 466 | printf("%x%x", (m->m_data[i] >> 4) & 0x0ff, m->m_data[i] & 0x0ff); |
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| 467 | printf("\n"); |
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| 468 | #endif |
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| 469 | len += m->m_len; |
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| 470 | if (len <= RBUF_SIZE) |
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| 471 | memcpy ((void *) temp, (char *) m->m_data, m->m_len); |
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| 472 | temp += m->m_len; |
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| 473 | if ((m = m->m_next) == NULL) |
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| 474 | break; |
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| 475 | } |
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| 476 | |
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| 477 | m_freem (n); |
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| 478 | |
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| 479 | /* don't send long packets */ |
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| 480 | |
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| 481 | if (len <= RBUF_SIZE) { |
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| 482 | |
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| 483 | /* Clear all of the status flags. */ |
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| 484 | len_status = dp->regs->xd[dp->tx_ptr].len_status & ~OETH_TX_BD_STATS; |
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| 485 | |
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| 486 | /* If the frame is short, tell CPM to pad it. */ |
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| 487 | if (len < ET_MINLEN) { |
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| 488 | len_status |= OETH_TX_BD_PAD; |
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| 489 | len = ET_MINLEN; |
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| 490 | } |
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| 491 | else |
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| 492 | len_status &= ~OETH_TX_BD_PAD; |
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| 493 | |
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| 494 | /* write buffer descriptor length and status */ |
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[104df63] | 495 | len_status &= 0x0000ffff; |
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[398ed76] | 496 | len_status |= (len << 16) | (OETH_TX_BD_READY | OETH_TX_BD_CRC); |
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| 497 | dp->regs->xd[dp->tx_ptr].len_status = len_status; |
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| 498 | dp->tx_ptr = (dp->tx_ptr + 1) % dp->txbufs; |
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| 499 | |
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| 500 | } |
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| 501 | inside = 0; |
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| 502 | } |
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| 503 | |
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| 504 | /* |
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| 505 | * Driver transmit daemon |
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| 506 | */ |
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| 507 | void |
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| 508 | open_eth_txDaemon (void *arg) |
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| 509 | { |
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| 510 | struct open_eth_softc *sc = (struct open_eth_softc *) arg; |
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| 511 | struct ifnet *ifp = &sc->arpcom.ac_if; |
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| 512 | struct mbuf *m; |
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| 513 | rtems_event_set events; |
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| 514 | |
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| 515 | for (;;) |
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| 516 | { |
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| 517 | /* |
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| 518 | * Wait for packet |
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| 519 | */ |
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| 520 | |
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| 521 | rtems_bsdnet_event_receive (START_TRANSMIT_EVENT, |
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| 522 | RTEMS_EVENT_ANY | RTEMS_WAIT, |
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| 523 | RTEMS_NO_TIMEOUT, &events); |
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| 524 | #ifdef OPEN_ETH_DEBUG |
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| 525 | printf ("t\n"); |
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| 526 | #endif |
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| 527 | |
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| 528 | /* |
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| 529 | * Send packets till queue is empty |
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| 530 | */ |
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| 531 | for (;;) |
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| 532 | { |
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| 533 | /* |
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| 534 | * Get the next mbuf chain to transmit. |
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| 535 | */ |
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| 536 | IF_DEQUEUE (&ifp->if_snd, m); |
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| 537 | if (!m) |
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| 538 | break; |
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| 539 | sendpacket (ifp, m); |
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| 540 | } |
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| 541 | ifp->if_flags &= ~IFF_OACTIVE; |
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| 542 | } |
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| 543 | } |
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| 544 | |
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| 545 | |
---|
| 546 | static void |
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| 547 | open_eth_start (struct ifnet *ifp) |
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| 548 | { |
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| 549 | struct open_eth_softc *sc = ifp->if_softc; |
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| 550 | |
---|
| 551 | rtems_event_send (sc->txDaemonTid, START_TRANSMIT_EVENT); |
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| 552 | ifp->if_flags |= IFF_OACTIVE; |
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| 553 | } |
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| 554 | |
---|
| 555 | /* |
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| 556 | * Initialize and start the device |
---|
| 557 | */ |
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| 558 | static void |
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| 559 | open_eth_init (void *arg) |
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| 560 | { |
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| 561 | struct open_eth_softc *sc = arg; |
---|
| 562 | struct ifnet *ifp = &sc->arpcom.ac_if; |
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| 563 | |
---|
| 564 | if (sc->txDaemonTid == 0) |
---|
| 565 | { |
---|
| 566 | |
---|
| 567 | /* |
---|
| 568 | * Set up OPEN_ETH hardware |
---|
| 569 | */ |
---|
| 570 | open_eth_initialize_hardware (sc); |
---|
| 571 | |
---|
| 572 | /* |
---|
| 573 | * Start driver tasks |
---|
| 574 | */ |
---|
| 575 | sc->rxDaemonTid = rtems_bsdnet_newproc ("DCrx", 4096, |
---|
| 576 | open_eth_rxDaemon, sc); |
---|
| 577 | sc->txDaemonTid = rtems_bsdnet_newproc ("DCtx", 4096, |
---|
| 578 | open_eth_txDaemon, sc); |
---|
| 579 | } |
---|
| 580 | |
---|
| 581 | /* |
---|
| 582 | * Tell the world that we're running. |
---|
| 583 | */ |
---|
| 584 | ifp->if_flags |= IFF_RUNNING; |
---|
| 585 | |
---|
| 586 | } |
---|
| 587 | |
---|
| 588 | /* |
---|
| 589 | * Stop the device |
---|
| 590 | */ |
---|
| 591 | static void |
---|
| 592 | open_eth_stop (struct open_eth_softc *sc) |
---|
| 593 | { |
---|
| 594 | struct ifnet *ifp = &sc->arpcom.ac_if; |
---|
| 595 | |
---|
| 596 | ifp->if_flags &= ~IFF_RUNNING; |
---|
| 597 | |
---|
| 598 | sc->regs->moder = 0; /* RX/TX OFF */ |
---|
| 599 | sc->regs->moder = OETH_MODER_RST; /* Reset ON */ |
---|
| 600 | sc->regs->moder = 0; /* Reset OFF */ |
---|
| 601 | } |
---|
| 602 | |
---|
| 603 | |
---|
| 604 | /* |
---|
| 605 | * Show interface statistics |
---|
| 606 | */ |
---|
| 607 | static void |
---|
| 608 | open_eth_stats (struct open_eth_softc *sc) |
---|
| 609 | { |
---|
| 610 | printf (" Rx Packets:%-8lu", sc->rxPackets); |
---|
| 611 | printf (" Rx Interrupts:%-8lu", sc->rxInterrupts); |
---|
| 612 | printf (" Length:%-8lu", sc->rxLengthError); |
---|
| 613 | printf (" Non-octet:%-8lu\n", sc->rxNonOctet); |
---|
| 614 | printf (" Bad CRC:%-8lu", sc->rxBadCRC); |
---|
| 615 | printf (" Overrun:%-8lu", sc->rxOverrun); |
---|
| 616 | printf (" Miss:%-8lu", sc->rxMiss); |
---|
| 617 | printf (" Collision:%-8lu\n", sc->rxCollision); |
---|
| 618 | |
---|
| 619 | printf (" Tx Interrupts:%-8lu", sc->txInterrupts); |
---|
| 620 | printf (" Deferred:%-8lu", sc->txDeferred); |
---|
| 621 | printf (" Missed Hearbeat:%-8lu\n", sc->txHeartbeat); |
---|
| 622 | printf (" No Carrier:%-8lu", sc->txLostCarrier); |
---|
| 623 | printf ("Retransmit Limit:%-8lu", sc->txRetryLimit); |
---|
| 624 | printf (" Late Collision:%-8lu\n", sc->txLateCollision); |
---|
| 625 | printf (" Underrun:%-8lu", sc->txUnderrun); |
---|
| 626 | printf (" Raw output wait:%-8lu\n", sc->txRawWait); |
---|
| 627 | } |
---|
| 628 | |
---|
| 629 | /* |
---|
| 630 | * Driver ioctl handler |
---|
| 631 | */ |
---|
| 632 | static int |
---|
[b7acc4ad] | 633 | open_eth_ioctl (struct ifnet *ifp, u_long command, caddr_t data) |
---|
[398ed76] | 634 | { |
---|
| 635 | struct open_eth_softc *sc = ifp->if_softc; |
---|
| 636 | int error = 0; |
---|
| 637 | |
---|
| 638 | switch (command) |
---|
| 639 | { |
---|
| 640 | case SIOCGIFADDR: |
---|
| 641 | case SIOCSIFADDR: |
---|
| 642 | ether_ioctl (ifp, command, data); |
---|
| 643 | break; |
---|
| 644 | |
---|
| 645 | case SIOCSIFFLAGS: |
---|
| 646 | switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) |
---|
| 647 | { |
---|
| 648 | case IFF_RUNNING: |
---|
| 649 | open_eth_stop (sc); |
---|
| 650 | break; |
---|
| 651 | |
---|
| 652 | case IFF_UP: |
---|
| 653 | open_eth_init (sc); |
---|
| 654 | break; |
---|
| 655 | |
---|
| 656 | case IFF_UP | IFF_RUNNING: |
---|
| 657 | open_eth_stop (sc); |
---|
| 658 | open_eth_init (sc); |
---|
| 659 | break; |
---|
| 660 | |
---|
| 661 | default: |
---|
| 662 | break; |
---|
| 663 | } |
---|
| 664 | break; |
---|
| 665 | |
---|
| 666 | case SIO_RTEMS_SHOW_STATS: |
---|
| 667 | open_eth_stats (sc); |
---|
| 668 | break; |
---|
| 669 | |
---|
| 670 | /* |
---|
| 671 | * FIXME: All sorts of multicast commands need to be added here! |
---|
| 672 | */ |
---|
| 673 | default: |
---|
| 674 | error = EINVAL; |
---|
| 675 | break; |
---|
| 676 | } |
---|
| 677 | |
---|
| 678 | return error; |
---|
| 679 | } |
---|
| 680 | |
---|
| 681 | /* |
---|
| 682 | * Attach an OPEN_ETH driver to the system |
---|
| 683 | */ |
---|
| 684 | int |
---|
| 685 | rtems_open_eth_driver_attach (struct rtems_bsdnet_ifconfig *config, |
---|
| 686 | open_eth_configuration_t * chip) |
---|
| 687 | { |
---|
| 688 | struct open_eth_softc *sc; |
---|
| 689 | struct ifnet *ifp; |
---|
| 690 | int mtu; |
---|
| 691 | int unitNumber; |
---|
| 692 | char *unitName; |
---|
| 693 | |
---|
| 694 | /* parse driver name */ |
---|
| 695 | if ((unitNumber = rtems_bsdnet_parse_driver_name (config, &unitName)) < 0) |
---|
| 696 | return 0; |
---|
| 697 | |
---|
| 698 | sc = &oc; |
---|
| 699 | ifp = &sc->arpcom.ac_if; |
---|
| 700 | memset (sc, 0, sizeof (*sc)); |
---|
| 701 | |
---|
| 702 | if (config->hardware_address) |
---|
| 703 | { |
---|
| 704 | memcpy (sc->arpcom.ac_enaddr, config->hardware_address, |
---|
| 705 | ETHER_ADDR_LEN); |
---|
| 706 | } |
---|
| 707 | else |
---|
| 708 | { |
---|
| 709 | memset (sc->arpcom.ac_enaddr, 0x08, ETHER_ADDR_LEN); |
---|
| 710 | } |
---|
| 711 | |
---|
| 712 | if (config->mtu) |
---|
| 713 | mtu = config->mtu; |
---|
| 714 | else |
---|
| 715 | mtu = ETHERMTU; |
---|
| 716 | |
---|
| 717 | sc->acceptBroadcast = !config->ignore_broadcast; |
---|
| 718 | sc->regs = (void *) chip->base_address; |
---|
| 719 | sc->vector = chip->vector; |
---|
| 720 | sc->txbufs = chip->txd_count; |
---|
| 721 | sc->rxbufs = chip->rxd_count; |
---|
[104df63] | 722 | sc->en100MHz = chip->en100MHz; |
---|
[398ed76] | 723 | |
---|
| 724 | |
---|
| 725 | /* |
---|
| 726 | * Set up network interface values |
---|
| 727 | */ |
---|
| 728 | ifp->if_softc = sc; |
---|
| 729 | ifp->if_unit = unitNumber; |
---|
| 730 | ifp->if_name = unitName; |
---|
| 731 | ifp->if_mtu = mtu; |
---|
| 732 | ifp->if_init = open_eth_init; |
---|
| 733 | ifp->if_ioctl = open_eth_ioctl; |
---|
| 734 | ifp->if_start = open_eth_start; |
---|
| 735 | ifp->if_output = ether_output; |
---|
| 736 | ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX; |
---|
| 737 | if (ifp->if_snd.ifq_maxlen == 0) |
---|
| 738 | ifp->if_snd.ifq_maxlen = ifqmaxlen; |
---|
| 739 | |
---|
| 740 | /* |
---|
| 741 | * Attach the interface |
---|
| 742 | */ |
---|
| 743 | if_attach (ifp); |
---|
| 744 | ether_ifattach (ifp); |
---|
| 745 | |
---|
| 746 | #ifdef OPEN_ETH_DEBUG |
---|
| 747 | printf ("OPEN_ETH : driver has been attached\n"); |
---|
| 748 | #endif |
---|
| 749 | return 1; |
---|
| 750 | }; |
---|
[845e4f3] | 751 | |
---|
| 752 | #endif /* OPENETH_NOT_SUPPORTED */ |
---|