source: rtems/c/src/libchip/network/if_fxpvar.h @ 8730f45

4.104.114.84.95
Last change on this file since 8730f45 was 2b947a4, checked in by Joel Sherrill <joel.sherrill@…>, on 07/16/02 at 22:37:13

2002-07-16 Eric Norum <eric.norum@…>

  • New driver for the Intel EtherExpressPro? (82559ER) chip.
  • network/if_fxp.c, network/if_fxpreg.h, network/if_fxpvar.h, network/pci.h: New file.
  • network/Makefile.am: Modified to reflect above.
  • Property mode set to 100644
File size: 7.7 KB
Line 
1/*                 
2 * Copyright (c) 1995, David Greenman
3 * All rights reserved.
4 *             
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:             
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice unmodified, this list of conditions, and the following
10 *    disclaimer. 
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: src/sys/dev/fxp/if_fxpvar.h,v 1.17.2.3 2001/06/08 20:36:58 jlemon Exp $
28 */
29
30/*
31 * Misc. defintions for the Intel EtherExpress Pro/100B PCI Fast
32 * Ethernet driver
33 */
34
35/*
36 * Number of transmit control blocks. This determines the number
37 * of transmit buffers that can be chained in the CB list.
38 * This must be a power of two.
39 */
40#define FXP_NTXCB       128
41
42/*
43 * Number of completed TX commands at which point an interrupt
44 * will be generated to garbage collect the attached buffers.
45 * Must be at least one less than FXP_NTXCB, and should be
46 * enough less so that the transmitter doesn't becomes idle
47 * during the buffer rundown (which would reduce performance).
48 */
49#define FXP_CXINT_THRESH 120
50
51/*
52 * TxCB list index mask. This is used to do list wrap-around.
53 */
54#define FXP_TXCB_MASK   (FXP_NTXCB - 1)
55
56/*
57 * Number of receive frame area buffers. These are large so chose
58 * wisely.
59 */
60#if 0
61#define FXP_NRFABUFS    64
62#else
63#define FXP_NRFABUFS    16
64#endif
65/*
66 * Maximum number of seconds that the receiver can be idle before we
67 * assume it's dead and attempt to reset it by reprogramming the
68 * multicast filter. This is part of a work-around for a bug in the
69 * NIC. See fxp_stats_update().
70 */
71#define FXP_MAX_RX_IDLE 15
72
73#if __FreeBSD_version < 500000
74#define FXP_LOCK(_sc)
75#define FXP_UNLOCK(_sc)
76#define mtx_init(a, b, c)
77#define mtx_destroy(a)
78struct mtx { int dummy; };
79#else
80#define FXP_LOCK(_sc)           mtx_lock(&(_sc)->sc_mtx)
81#define FXP_UNLOCK(_sc)         mtx_unlock(&(_sc)->sc_mtx)
82#endif
83
84#ifdef __alpha__
85#undef vtophys
86#define vtophys(va)     alpha_XXX_dmamap((vm_offset_t)(va))
87#endif /* __alpha__ */
88
89/*
90 * NOTE: Elements are ordered for optimal cacheline behavior, and NOT
91 *       for functional grouping.
92 */
93struct fxp_softc {
94        struct arpcom arpcom;           /* per-interface network data */
95#ifdef NOTUSED
96        struct resource *mem;           /* resource descriptor for registers */
97        int rtp;                        /* register resource type */
98        int rgd;                        /* register descriptor in use */
99        struct resource *irq;           /* resource descriptor for interrupt */
100#endif
101        void *ih;                       /* interrupt handler cookie */
102        struct mtx sc_mtx;
103#ifdef NOTUSED /* change for RTEMS */
104        bus_space_tag_t sc_st;          /* bus space tag */
105        bus_space_handle_t sc_sh;       /* bus space handle */
106#else
107        int pci_signature;              /* RTEMS i386 PCI signature */
108        boolean pci_regs_are_io;        /* RTEMS dev regs are I/O mapped */
109        u_int32_t pci_regs_base;        /* RTEMS i386 register base */
110        rtems_id daemonTid;             /* Task ID of deamon        */
111        rtems_irq_connect_data  irqInfo;
112
113#endif
114        struct mbuf *rfa_headm;         /* first mbuf in receive frame area */
115        struct mbuf *rfa_tailm;         /* last mbuf in receive frame area */
116        struct fxp_cb_tx *cbl_first;    /* first active TxCB in list */
117        int tx_queued;                  /* # of active TxCB's */
118        int need_mcsetup;               /* multicast filter needs programming */
119        struct fxp_cb_tx *cbl_last;     /* last active TxCB in list */
120        struct fxp_stats *fxp_stats;    /* Pointer to interface stats */
121        int rx_idle_secs;               /* # of seconds RX has been idle */
122        enum {fxp_timeout_stopped,fxp_timeout_running,fxp_timeout_stop_rq}
123          stat_ch;                     /* status of status updater */
124        struct fxp_cb_tx *cbl_base;     /* base of TxCB list */
125        struct fxp_cb_mcs *mcsp;        /* Pointer to mcast setup descriptor */
126#ifdef NOTUSED
127        struct ifmedia sc_media;        /* media information */
128        device_t miibus;
129        device_t dev;
130#endif
131        int eeprom_size;                /* size of serial EEPROM */
132        int suspended;                  /* 0 = normal  1 = suspended (APM) */
133        int cu_resume_bug;
134        int chip;
135        int flags;
136        u_int32_t saved_maps[5];        /* pci data */
137        u_int32_t saved_biosaddr;
138        u_int8_t saved_intline;
139        u_int8_t saved_cachelnsz;
140        u_int8_t saved_lattimer;
141};
142
143#define FXP_CHIP_82557          1       /* 82557 chip type */
144
145#define FXP_FLAG_MWI_ENABLE     0x0001  /* MWI enable */
146#define FXP_FLAG_READ_ALIGN     0x0002  /* align read access with cacheline */
147#define FXP_FLAG_WRITE_ALIGN    0x0004  /* end write on cacheline */
148#define FXP_FLAG_EXT_TXCB       0x0008  /* enable use of extended TXCB */
149#define FXP_FLAG_SERIAL_MEDIA   0x0010  /* 10Mbps serial interface */
150#define FXP_FLAG_LONG_PKT_EN    0x0020  /* enable long packet reception */
151#define FXP_FLAG_ALL_MCAST      0x0040  /* accept all multicast frames */
152#define FXP_FLAG_CU_RESUME_BUG  0x0080  /* requires workaround for CU_RESUME */
153
154/* Macros to ease CSR access. */
155#if 0
156#define CSR_READ_1(sc, reg)                                             \
157        bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
158#define CSR_READ_2(sc, reg)                                             \
159        bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
160#define CSR_READ_4(sc, reg)                                             \
161        bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
162#define CSR_WRITE_1(sc, reg, val)                                       \
163        bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
164#define CSR_WRITE_2(sc, reg, val)                                       \
165        bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
166#define CSR_WRITE_4(sc, reg, val)                                       \
167        bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
168#else
169#define CSR_READ_1(sc, reg) fxp_csr_read_1(sc,reg)
170#define CSR_READ_2(sc, reg) fxp_csr_read_2(sc,reg)
171#define CSR_READ_4(sc, reg) fxp_csr_read_4(sc,reg)
172
173#define CSR_WRITE_1(sc, reg, val)                                       \
174  do {                                                                  \
175     if ((sc)->pci_regs_are_io)                                         \
176       outport_byte((sc)->pci_regs_base+(reg),val);                     \
177     else                                                               \
178       *((u_int8_t *)((sc)->pci_regs_base)+(reg)) = val;                \
179  }while (0)
180
181#define CSR_WRITE_2(sc, reg, val)                                       \
182  do {                                                                  \
183     if ((sc)->pci_regs_are_io)                                         \
184       outport_word((sc)->pci_regs_base+(reg),val);                     \
185     else                                                               \
186       *((u_int16_t *)((u_int8_t *)((sc)->pci_regs_base)+(reg))) = val; \
187  }while (0)
188
189#define CSR_WRITE_4(sc, reg, val)                                       \
190  do {                                                                  \
191     if ((sc)->pci_regs_are_io)                                         \
192       outport_long((sc)->pci_regs_base+(reg),val);                     \
193     else                                                               \
194       *((u_int32_t *)((u_int8_t *)((sc)->pci_regs_base)+(reg))) = val; \
195  }while (0)
196
197#endif
198
199#define sc_if                   arpcom.ac_if
200
201#define FXP_UNIT(_sc)           (_sc)->arpcom.ac_if.if_unit
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