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source: rtems/c/src/libchip/network/if_fxp.c @ dbc7c79

4.104.114.84.95

Last change on this file since dbc7c79 was c140041b, checked in by Ralf Corsepius <ralf.corsepius@…>, on 09/19/05 at 03:46:17
Include <errno.h> instead of <sys/errno.h>.
Property mode set to `100644`
File size: 61.4 KB

Line
1	/*-
2	* Copyright (c) 1995, David Greenman
3	* Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
4	* All rights reserved.
5	*
6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions
8	* are met:
9	* 1. Redistributions of source code must retain the above copyright
10	* notice unmodified, this list of conditions, and the following
11	* disclaimer.
12	* 2. Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	*
16	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26	* SUCH DAMAGE.
27	*
28	* $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.118 2001/09/05 23:33:58 brooks Exp $
29	*/
30
31	/*
32	* Intel EtherExpress Pro/100B PCI Fast Ethernet driver
33	*/
34
35	/*
36	* RTEMS Revision Preliminary History
37	*
38	* July XXX, 2002 W. Eric Norum <eric.norum@usask.ca>
39	* Placed in RTEMS CVS repository. All further modifications will be
40	* noted in the CVS log and not in this comment.
41	*
42	* July 11, 2002 W. Eric Norum <eric.norum@usask.ca>
43	* Minor modifications to get driver working with NIC on VersaLogic
44	* Bobcat PC-104 single-board computer. The Bobcat has no video
45	* driver so printf/printk calls are directed to COM2:. This
46	* arrangement seems to require delays after the printk calls or
47	* else things lock up. Perhaps the RTEMS pc386 console code
48	* should be modified to insert these delays itself.
49	*
50	* June 27, 2002 W. Eric Norum <eric.norum@usask.ca>
51	* Obtained from Thomas Doerfler <Thomas.Doerfler@imd-systems.de>.
52	* A big thank-you to Thomas for making this available.
53	*
54	* October 01, 2001 Thomas Doerfler <Thomas.Doerfler@imd-systems.de>
55	* Original RTEMS modifications.
56	*/
57
58	#if defined(__i386__)
59
60	/#define DEBUG_OUT 0/
61
62	#include <rtems.h>
63	#include <rtems/error.h>
64	#include <rtems/rtems_bsdnet.h>
65	#include <bsp.h>
66
67	#include <errno.h>
68	#include <sys/param.h>
69	#include <sys/mbuf.h>
70	#include <sys/socket.h>
71	#include <sys/sockio.h>
72	#include <net/if.h>
73	#include <netinet/in.h>
74	#include <netinet/if_ether.h>
75	#include <sys/malloc.h>
76	#include <sys/systm.h>
77	#include <bsp.h>
78	#include <pcibios.h>
79	#include <bsp/irq.h>
80	#include <rtems/pci.h>
81
82	#ifdef NS
83	#include <netns/ns.h>
84	#include <netns/ns_if.h>
85	#endif
86
87	#include <net/bpf.h>
88
89	#include <vm/vm.h> /* for vtophys */
90
91	#include <net/if_types.h>
92
93	#include "if_fxpreg.h"
94	#include "if_fxpvar.h"
95
96	/*
97	* some adaptation replacements for RTEMS
98	*/
99	static rtems_interval fxp_ticksPerSecond;
100	#define device_printf(device,format,args...) printk(format,## args)
101	#define DELAY(n) rtems_task_wake_after(((n)*fxp_ticksPerSecond/1000000)+1)
102	#ifdef DEBUG_OUT
103	#define DBGLVL_PRINTK(LVL,format, args...) \
104	if (DEBUG_OUT >= (LVL)) { \
105	printk(format, ## args); \
106	}
107	#else
108	#define DBGLVL_PRINTK(LVL,format, args...)
109	#endif
110
111	/*
112	* RTEMS event used by interrupt handler to signal driver tasks.
113	* This must not be any of the events used by the network task synchronization.
114	*/
115	#define INTERRUPT_EVENT RTEMS_EVENT_1
116
117	/*
118	* remapping between PCI device and CPU memmory address view...
119	*/
120	#if defined(__i386)
121	#define vtophys(p) (u_int32_t)(p)
122	#else
123	#define vtophys(p) vtophys(p)
124	#endif
125
126	#define NFXPDRIVER 1
127	static struct fxp_softc fxp_softc[NFXPDRIVER];
128	static int fxp_is_verbose = TRUE;
129	/*
130	* NOTE! On the Alpha, we have an alignment constraint. The
131	* card DMAs the packet immediately following the RFA. However,
132	* the first thing in the packet is a 14-byte Ethernet header.
133	* This means that the packet is misaligned. To compensate,
134	* we actually offset the RFA 2 bytes into the cluster. This
135	* alignes the packet after the Ethernet header at a 32-bit
136	* boundary. HOWEVER! This means that the RFA is misaligned!
137	*/
138	#define RFA_ALIGNMENT_FUDGE 2
139
140	/*
141	* Set initial transmit threshold at 64 (512 bytes). This is
142	* increased by 64 (512 bytes) at a time, to maximum of 192
143	* (1536 bytes), if an underrun occurs.
144	*/
145	static int tx_threshold = 64;
146
147	/*
148	* The configuration byte map has several undefined fields which
149	* must be one or must be zero. Set up a template for these bits
150	* only, (assuming a 82557 chip) leaving the actual configuration
151	* to fxp_init.
152	*
153	* See struct fxp_cb_config for the bit definitions.
154	*/
155	static u_char fxp_cb_config_template[] = {
156	0x0, 0x0, /* cb_status */
157	0x0, 0x0, /* cb_command */
158	0x0, 0x0, 0x0, 0x0, /* link_addr */
159	0x0, /* 0 */
160	0x0, /* 1 */
161	0x0, /* 2 */
162	0x0, /* 3 */
163	0x0, /* 4 */
164	0x0, /* 5 */
165	0x32, /* 6 */
166	0x0, /* 7 */
167	0x0, /* 8 */
168	0x0, /* 9 */
169	0x6, /* 10 */
170	0x0, /* 11 */
171	0x0, /* 12 */
172	0x0, /* 13 */
173	0xf2, /* 14 */
174	0x48, /* 15 */
175	0x0, /* 16 */
176	0x40, /* 17 */
177	0xf0, /* 18 */
178	0x0, /* 19 */
179	0x3f, /* 20 */
180	0x5 /* 21 */
181	};
182
183	struct fxp_ident {
184	u_int16_t devid;
185	char *name;
186	int warn;
187	};
188
189	#define UNTESTED 1
190
191	/*
192	* Claim various Intel PCI device identifiers for this driver. The
193	* sub-vendor and sub-device field are extensively used to identify
194	* particular variants, but we don't currently differentiate between
195	* them.
196	*/
197	static struct fxp_ident fxp_ident_table[] = {
198	{ 0x1229, "Intel Pro 10/100B/100+ Ethernet", 0 },
199	{ 0x2449, "Intel Pro/100 Ethernet", UNTESTED },
200	{ 0x1209, "Intel Embedded 10/100 Ethernet", 0 },
201	{ 0x1029, "Intel Pro/100 Ethernet", UNTESTED },
202	{ 0x1030, "Intel Pro/100 Ethernet", 0 },
203	{ 0x1031, "Intel Pro/100 Ethernet", UNTESTED },
204	{ 0x1032, "Intel Pro/100 Ethernet", UNTESTED },
205	{ 0x1033, "Intel Pro/100 Ethernet", UNTESTED },
206	{ 0x1034, "Intel Pro/100 Ethernet", UNTESTED },
207	{ 0x1035, "Intel Pro/100 Ethernet", UNTESTED },
208	{ 0x1036, "Intel Pro/100 Ethernet", UNTESTED },
209	{ 0x1037, "Intel Pro/100 Ethernet", UNTESTED },
210	{ 0x1038, "Intel Pro/100 Ethernet", UNTESTED },
211	{ 0x103B, "Intel Pro/100 Ethernet (82801BD PRO/100 VM (LOM))", 0 },
212	{ 0, NULL },
213	};
214
215	#if 0
216	static int fxp_probe(device_t dev);
217	static int fxp_attach(device_t dev);
218	static int fxp_detach(device_t dev);
219	static int fxp_shutdown(device_t dev);
220	#endif
221	int fxp_output (struct ifnet *,
222	struct mbuf , struct sockaddr , struct rtentry *);
223
224
225	static rtems_isr fxp_intr(rtems_vector_number v);
226	static void fxp_init(void *xsc);
227	static void fxp_tick(void *xsc);
228	static void fxp_start(struct ifnet *ifp);
229	static void fxp_stop(struct fxp_softc *sc);
230	static void fxp_release(struct fxp_softc *sc);
231	static int fxp_ioctl(struct ifnet *ifp, u_long command,
232	caddr_t data);
233	static void fxp_watchdog(struct ifnet *ifp);
234	static int fxp_add_rfabuf(struct fxp_softc sc, struct mbuf oldm);
235	static void fxp_mc_setup(struct fxp_softc *sc);
236	static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
237	int autosize);
238	static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
239	u_int16_t data);
240	static void fxp_autosize_eeprom(struct fxp_softc *sc);
241	static void fxp_read_eeprom(struct fxp_softc sc, u_short data,
242	int offset, int words);
243	static void fxp_write_eeprom(struct fxp_softc sc, u_short data,
244	int offset, int words);
245	#ifdef NOTUSED
246	static int fxp_ifmedia_upd(struct ifnet *ifp);
247	static void fxp_ifmedia_sts(struct ifnet *ifp,
248	struct ifmediareq *ifmr);
249	static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
250	static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
251	struct ifmediareq *ifmr);
252	static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg);
253	static void fxp_miibus_writereg(device_t dev, int phy, int reg,
254	int value);
255	#endif
256	static __inline void fxp_lwcopy(volatile u_int32_t *src,
257	volatile u_int32_t *dst);
258	static __inline void fxp_scb_wait(struct fxp_softc *sc);
259	static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
260	static __inline void fxp_dma_wait(volatile u_int16_t *status,
261	struct fxp_softc *sc);
262
263	/*
264	* Inline function to copy a 16-bit aligned 32-bit quantity.
265	*/
266	static __inline void
267	fxp_lwcopy(volatile u_int32_t src, volatile u_int32_t dst)
268	{
269	#ifdef __i386__
270	dst = src;
271	#else
272	volatile u_int16_t a = (volatile u_int16_t)src;
273	volatile u_int16_t b = (volatile u_int16_t)dst;
274
275	b[0] = a[0];
276	b[1] = a[1];
277	#endif
278	}
279
280	/*
281	* inline access functions to pci space registers
282	*/
283	static __inline u_int8_t fxp_csr_read_1(struct fxp_softc *sc,int reg) {
284	u_int8_t val;
285	if (sc->pci_regs_are_io) {
286	inport_byte(sc->pci_regs_base + reg,val);
287	}
288	else {
289	val = (u_int8_t)(sc->pci_regs_base+reg);
290	}
291	return val;
292	}
293	static __inline u_int32_t fxp_csr_read_2(struct fxp_softc *sc,int reg) {
294	u_int16_t val;
295	if (sc->pci_regs_are_io) {
296	inport_word(sc->pci_regs_base + reg,val);
297	}
298	else {
299	val = (u_int16_t)(sc->pci_regs_base+reg);
300	}
301	return val;
302	}
303	static __inline u_int32_t fxp_csr_read_4(struct fxp_softc *sc,int reg) {
304	u_int32_t val;
305	if (sc->pci_regs_are_io) {
306	inport_long(sc->pci_regs_base + reg,val);
307	}
308	else {
309	val = (u_int32_t)(sc->pci_regs_base+reg);
310	}
311	return val;
312	}
313
314	/*
315	* Wait for the previous command to be accepted (but not necessarily
316	* completed).
317	*/
318	static __inline void
319	fxp_scb_wait(struct fxp_softc *sc)
320	{
321	int i = 10000;
322
323	while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
324	DELAY(2);
325	if (i == 0)
326	device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
327	CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
328	CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
329	CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS),
330	CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
331	}
332
333	static __inline void
334	fxp_scb_cmd(struct fxp_softc *sc, int cmd)
335	{
336
337	if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
338	CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
339	fxp_scb_wait(sc);
340	}
341	CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
342	}
343
344	static __inline void
345	fxp_dma_wait(volatile u_int16_t status, struct fxp_softc sc)
346	{
347	int i = 10000;
348
349	while (!(*status & FXP_CB_STATUS_C) && --i)
350	DELAY(2);
351	if (i == 0)
352	device_printf(sc->dev, "DMA timeout\n");
353	}
354
355	static __inline unsigned int pci_get_vendor(struct fxp_softc *sc) {
356	u_int16_t vendor;
357	pcib_conf_read16(sc->pci_signature,0,&vendor);
358	return vendor;
359	}
360
361	static __inline unsigned int pci_get_device(struct fxp_softc *sc) {
362	u_int16_t device;
363	pcib_conf_read16(sc->pci_signature,2,&device);
364	return device;
365	}
366
367	static __inline unsigned int pci_get_subvendor(struct fxp_softc *sc) {
368	u_int16_t subvendor;
369	pcib_conf_read16(sc->pci_signature,0x2c,&subvendor);
370	return subvendor;
371	}
372
373	static __inline unsigned int pci_get_subdevice(struct fxp_softc *sc) {
374	u_int16_t subdevice;
375	pcib_conf_read16(sc->pci_signature,0x2e,&subdevice);
376	return subdevice;
377	}
378
379	static __inline unsigned int pci_get_revid(struct fxp_softc *sc) {
380	u_int8_t revid;
381	pcib_conf_read8(sc->pci_signature,0x08,&revid);
382	return revid;
383	}
384
385	static void nopOn(const rtems_irq_connect_data* notUsed)
386	{
387	/*
388	* code should be moved from fxp_Enet_initialize_hardware
389	* to this location
390	*/
391	}
392
393	static int fxpIsOn(const rtems_irq_connect_data* irq)
394	{
395	return BSP_irq_enabled_at_i8259s (irq->name);
396	}
397
398	int
399	rtems_fxp_attach(struct rtems_bsdnet_ifconfig *config, int attaching)
400	{
401	int error = 0;
402	struct fxp_softc *sc;
403	struct ifnet *ifp;
404	u_int16_t val16;
405	u_int32_t val32;
406	u_int16_t data;
407	int i;
408	int s;
409	int unitNumber;
410	char *unitName;
411	u_int16_t dev_id;
412	u_int8_t interrupt;
413	int mtu;
414
415	/*
416	* Set up some timing values
417	*/
418	rtems_clock_get(RTEMS_CLOCK_GET_TICKS_PER_SECOND, &fxp_ticksPerSecond);
419	DBGLVL_PRINTK(1,"fxp_attach called\n");
420
421	/*
422	* Parse driver name
423	*/
424	if ((unitNumber = rtems_bsdnet_parse_driver_name (config, &unitName)) < 0)
425	return 0;
426
427	/*
428	* Is driver free?
429	*/
430	if ((unitNumber <= 0) \|\| (unitNumber > NFXPDRIVER)) {
431	device_printf(dev,"Bad FXP unit number.\n");
432	return 0;
433	}
434	sc = &fxp_softc[unitNumber - 1];
435	ifp = &sc->arpcom.ac_if;
436	if (ifp->if_softc != NULL) {
437	device_printf(dev,"FXP Driver already in use.\n");
438	return 0;
439	}
440
441	memset(sc, 0, sizeof(*sc));
442	#ifdef NOTUSED
443	sc->dev = dev;
444	callout_handle_init(&sc->stat_ch);
445	mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF \| MTX_RECURSE);
446	#endif
447	s = splimp();
448
449	/*
450	* find device on pci bus
451	*/
452	{ int j; int pbus, pdev, pfun;
453
454	for (j=0; fxp_ident_table[j].devid; j++ ) {
455	i = pci_find_device( 0x8086, fxp_ident_table[j].devid,
456	unitNumber-1, &pbus, &pdev, &pfun );
457	sc->pci_signature = PCIB_DEVSIG_MAKE( pbus, pdev, pfun );
458	DBGLVL_PRINTK(2,"fxp_attach: find_devid returned %d "
459	"and pci signature 0x%x\n",
460	i,sc->pci_signature);
461	if (PCIB_ERR_SUCCESS == i) {
462	if ( UNTESTED == fxp_ident_table[j].warn ) {
463	device_printf(dev,
464	"WARNING: this chip version has NOT been reported to work under RTEMS yet.\n");
465	device_printf(dev,
466	" If it works OK, report it as tested in 'c/src/libchip/network/if_fxp.c'\n");
467	}
468	break;
469	}
470	}
471	}
472
473	/*
474	* FIXME: add search for more device types...
475	*/
476	if (i != PCIB_ERR_SUCCESS) {
477	device_printf(dev, "could not find 82559ER device\n");
478	return 0;
479	}
480
481
482	/*
483	* Enable bus mastering. Enable memory space too, in case
484	* BIOS/Prom forgot about it.
485	*/
486	pcib_conf_read16(sc->pci_signature, PCI_COMMAND,&val16);
487	val16 \|= (PCI_COMMAND_MEMORY\|PCI_COMMAND_MASTER);
488	pcib_conf_write16(sc->pci_signature, PCI_COMMAND, val16);
489	DBGLVL_PRINTK(3,"fxp_attach: PCI_COMMAND_write = 0x%x\n",val16);
490	pcib_conf_read16(sc->pci_signature, PCI_COMMAND,&val16);
491	DBGLVL_PRINTK(4,"fxp_attach: PCI_COMMAND_read = 0x%x\n",val16);
492
493	/*
494	* Figure out which we should try first - memory mapping or i/o mapping?
495	* We default to memory mapping. Then we accept an override from the
496	* command line. Then we check to see which one is enabled.
497	*/
498	#ifdef NOTUSED
499	m1 = PCI_COMMAND_MEMORY;
500	m2 = PCI_COMMAND_IO;
501	prefer_iomap = 0;
502	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
503	"prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) {
504	m1 = PCI_COMMAND_IO;
505	m2 = PCI_COMMAND_MEMORY;
506	}
507
508	if (val & m1) {
509	sc->rtp = ((m1 == PCI_COMMAND_MEMORY)
510	? SYS_RES_MEMORY : SYS_RES_IOPORT);
511	sc->rgd = ((m1 == PCI_COMMAND_MEMORY)
512	? FXP_PCI_MMBA : FXP_PCI_IOBA);
513	sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
514	0, ~0, 1, RF_ACTIVE);
515	}
516	if (sc->mem == NULL && (val & m2)) {
517	sc->rtp = ((m2 == PCI_COMMAND_MEMORY)
518	? SYS_RES_MEMORY : SYS_RES_IOPORT);
519	sc->rgd = ((m2 == PCI_COMMAND_MEMORY)
520	? FXP_PCI_MMBA : FXP_PCI_IOBA);
521	sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
522	0, ~0, 1, RF_ACTIVE);
523	}
524
525	if (!sc->mem) {
526	device_printf(dev, "could not map device registers\n");
527	error = ENXIO;
528	goto fail;
529	}
530	if (fxp_is_verbose) {
531	device_printf(dev, "using %s space register mapping\n",
532	sc->rtp == SYS_RES_MEMORY? "memory" : "I/O");
533	}
534
535	sc->sc_st = rman_get_bustag(sc->mem);
536	sc->sc_sh = rman_get_bushandle(sc->mem);
537
538	/*
539	* Allocate our interrupt.
540	*/
541	rid = 0;
542	sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
543	RF_SHAREABLE \| RF_ACTIVE);
544	if (sc->irq == NULL) {
545	device_printf(dev, "could not map interrupt\n");
546	error = ENXIO;
547	goto fail;
548	}
549
550	error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
551	fxp_intr, sc, &sc->ih);
552	if (error) {
553	device_printf(dev, "could not setup irq\n");
554	goto fail;
555	}
556	#endif
557
558	/*
559	* get mapping and base address of registers
560	*/
561	pcib_conf_read16(sc->pci_signature, PCI_COMMAND,&val16);
562	DBGLVL_PRINTK(4,"fxp_attach: PCI_COMMAND_read = 0x%x\n",val16);
563	if((val16 & PCI_COMMAND_IO) != 0) {
564	sc->pci_regs_are_io = TRUE;
565	pcib_conf_read32(sc->pci_signature,
566	PCI_BASE_ADDRESS_1,
567	&val32);
568	sc->pci_regs_base = val32 & PCI_BASE_ADDRESS_IO_MASK;
569	}
570	else {
571	sc->pci_regs_are_io = FALSE;
572	pcib_conf_read32(sc->pci_signature,
573	PCI_BASE_ADDRESS_0,
574	&val32);
575	sc->pci_regs_base = val32 & PCI_BASE_ADDRESS_MEM_MASK;
576	}
577	DBGLVL_PRINTK(3,"fxp_attach: CSR registers are mapped in %s space"
578	" at address 0x%x\n",
579	sc->pci_regs_are_io ? "I/O" : "MEM",
580	sc->pci_regs_base);
581
582	/*
583	* get interrupt level to be used
584	*/
585	pcib_conf_read8(sc->pci_signature, 60, &interrupt);
586	DBGLVL_PRINTK(3,"fxp_attach: interrupt = 0x%x\n",interrupt);
587	sc->irqInfo.name = (rtems_irq_number)interrupt;
588	/*
589	* Set up interrupts
590	*/
591	sc->irqInfo.hdl = (rtems_irq_hdl)fxp_intr;
592	sc->irqInfo.on = nopOn;
593	sc->irqInfo.off = nopOn;
594	sc->irqInfo.isOn = fxpIsOn;
595	s = BSP_install_rtems_irq_handler (&sc->irqInfo);
596	if (!s)
597	rtems_panic ("Can't attach fxp interrupt handler for irq %d\n",
598	sc->irqInfo.name);
599	/*
600	* Reset to a stable state.
601	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
602	*/
603	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
604	DELAY(10);
605
606	sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB,
607	M_DEVBUF, M_NOWAIT);
608	DBGLVL_PRINTK(3,"fxp_attach: sc->cbl_base = 0x%x\n",sc->cbl_base);
609	if (sc->cbl_base == NULL)
610	goto failmem;
611	else
612	memset(sc->cbl_base, 0, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
613
614	sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF,
615	M_NOWAIT);
616	DBGLVL_PRINTK(3,"fxp_attach: sc->fxp_stats = 0x%x\n",sc->fxp_stats);
617	if (sc->fxp_stats == NULL)
618	goto failmem;
619	else
620	memset(sc->fxp_stats, 0, sizeof(struct fxp_stats));
621
622	sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT);
623	DBGLVL_PRINTK(3,"fxp_attach: sc->mcsp = 0x%x\n",sc->mcsp);
624	if (sc->mcsp == NULL)
625	goto failmem;
626
627	/*
628	* Pre-allocate our receive buffers.
629	*/
630	for (i = 0; i < FXP_NRFABUFS; i++) {
631	if (fxp_add_rfabuf(sc, NULL) != 0) {
632	goto failmem;
633	}
634	}
635
636	/*
637	* Find out how large of an SEEPROM we have.
638	*/
639	DBGLVL_PRINTK(3,"fxp_attach: calling fxp_autosize_eeprom\n");
640	fxp_autosize_eeprom(sc);
641
642	/*
643	* Determine whether we must use the 503 serial interface.
644	*/
645	fxp_read_eeprom(sc, &data, 6, 1);
646	if ((data & FXP_PHY_DEVICE_MASK) != 0 &&
647	(data & FXP_PHY_SERIAL_ONLY))
648	sc->flags \|= FXP_FLAG_SERIAL_MEDIA;
649
650	/*
651	* Find out the basic controller type; we currently only
652	* differentiate between a 82557 and greater.
653	*/
654	fxp_read_eeprom(sc, &data, 5, 1);
655	if ((data >> 8) == 1)
656	sc->chip = FXP_CHIP_82557;
657	DBGLVL_PRINTK(3,"fxp_attach: sc->chip = %d\n",sc->chip);
658
659	/*
660	* Enable workarounds for certain chip revision deficiencies.
661	*
662	* Systems based on the ICH2/ICH2-M chip from Intel have a defect
663	* where the chip can cause a PCI protocol violation if it receives
664	* a CU_RESUME command when it is entering the IDLE state. The
665	* workaround is to disable Dynamic Standby Mode, so the chip never
666	* deasserts CLKRUN#, and always remains in an active state.
667	*
668	* See Intel 82801BA/82801BAM Specification Update, Errata #30.
669	*/
670	#ifdef NOTUSED
671	i = pci_get_device(dev);
672	#else
673	pcib_conf_read16(sc->pci_signature,2,&dev_id);
674	DBGLVL_PRINTK(3,"fxp_attach: device id = 0x%x\n",dev_id);
675	#endif
676	if (dev_id == 0x2449 \|\| (dev_id > 0x1030 && dev_id < 0x1039)) {
677	device_printf(dev, "* See Intel 82801BA/82801BAM Specification Update, Errata #30. *\n");
678	fxp_read_eeprom(sc, &data, 10, 1);
679	if (data & 0x02) { /* STB enable */
680	u_int16_t cksum;
681	int i;
682
683	device_printf(dev,
684	"* DISABLING DYNAMIC STANDBY MODE IN EEPROM *\n");
685	data &= ~0x02;
686	fxp_write_eeprom(sc, &data, 10, 1);
687	device_printf(dev, "New EEPROM ID: 0x%x\n", data);
688	cksum = 0;
689	for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
690	fxp_read_eeprom(sc, &data, i, 1);
691	cksum += data;
692	}
693	i = (1 << sc->eeprom_size) - 1;
694	cksum = 0xBABA - cksum;
695	fxp_read_eeprom(sc, &data, i, 1);
696	fxp_write_eeprom(sc, &cksum, i, 1);
697	device_printf(dev,
698	"EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
699	i, data, cksum);
700	/*
701	* We need to do a full PCI reset here. A software
702	* reset to the port doesn't cut it, but let's try
703	* anyway.
704	*/
705	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
706	DELAY(50);
707	device_printf(dev,
708	"* PLEASE REBOOT THE SYSTEM NOW FOR CORRECT OPERATION *\n");
709	#if 1
710	/*
711	* If the user elects to continue, try the software
712	* workaround, as it is better than nothing.
713	*/
714	sc->flags \|= FXP_FLAG_CU_RESUME_BUG;
715	#endif
716	}
717	}
718
719	/*
720	* If we are not a 82557 chip, we can enable extended features.
721	*/
722	if (sc->chip != FXP_CHIP_82557) {
723	u_int8_t tmp_val;
724	/*
725	* If MWI is enabled in the PCI configuration, and there
726	* is a valid cacheline size (8 or 16 dwords), then tell
727	* the board to turn on MWI.
728	*/
729	pcib_conf_read8(sc->pci_signature,
730	PCI_CACHE_LINE_SIZE,&tmp_val);
731	DBGLVL_PRINTK(3,"fxp_attach: CACHE_LINE_SIZE = %d\n",tmp_val);
732	if (val16 & PCI_COMMAND_MEMORY &&
733	tmp_val != 0)
734	sc->flags \|= FXP_FLAG_MWI_ENABLE;
735
736	/* turn on the extended TxCB feature */
737	sc->flags \|= FXP_FLAG_EXT_TXCB;
738
739	/* enable reception of long frames for VLAN */
740	sc->flags \|= FXP_FLAG_LONG_PKT_EN;
741	DBGLVL_PRINTK(3,"fxp_attach: sc->flags = 0x%x\n",
742	sc->flags);
743	}
744
745	/*
746	* Read MAC address.
747	*/
748	fxp_read_eeprom(sc, (u_int16_t*)sc->arpcom.ac_enaddr, 0, 3);
749	if (fxp_is_verbose) {
750	device_printf(dev, "Ethernet address %x:%x:%x:%x:%x:%x %s \n",
751	((u_int8_t*)sc->arpcom.ac_enaddr)[0],
752	((u_int8_t*)sc->arpcom.ac_enaddr)[1],
753	((u_int8_t*)sc->arpcom.ac_enaddr)[2],
754	((u_int8_t*)sc->arpcom.ac_enaddr)[3],
755	((u_int8_t*)sc->arpcom.ac_enaddr)[4],
756	((u_int8_t*)sc->arpcom.ac_enaddr)[5],
757	sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : "");
758	device_printf(dev, "PCI IDs: 0x%x 0x%x 0x%x 0x%x 0x%x\n",
759	pci_get_vendor(sc), pci_get_device(sc),
760	pci_get_subvendor(sc), pci_get_subdevice(sc),
761	pci_get_revid(sc));
762	device_printf(dev, "Chip Type: %d\n", sc->chip);
763	}
764
765	#ifdef NOTUSED /* do not set up interface at all... */
766	/*
767	* If this is only a 10Mbps device, then there is no MII, and
768	* the PHY will use a serial interface instead.
769	*
770	* The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
771	* doesn't have a programming interface of any sort. The
772	* media is sensed automatically based on how the link partner
773	* is configured. This is, in essence, manual configuration.
774	*/
775	if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
776	ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
777	fxp_serial_ifmedia_sts);
778	ifmedia_add(&sc->sc_media, IFM_ETHER\|IFM_MANUAL, 0, NULL);
779	ifmedia_set(&sc->sc_media, IFM_ETHER\|IFM_MANUAL);
780	} else {
781	if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
782	fxp_ifmedia_sts)) {
783	device_printf(dev, "MII without any PHY!\n");
784	error = ENXIO;
785	goto fail;
786	}
787	}
788	#endif
789	if (config->mtu)
790	mtu = config->mtu;
791	else
792	mtu = ETHERMTU;
793
794	ifp->if_softc = sc;
795	ifp->if_unit = unitNumber;
796	ifp->if_name = unitName;
797	ifp->if_mtu = mtu;
798	ifp->if_baudrate = 100000000;
799	ifp->if_init = fxp_init;
800	ifp->if_ioctl = fxp_ioctl;
801	ifp->if_start = fxp_start;
802	ifp->if_output = ether_output;
803	ifp->if_watchdog = fxp_watchdog;
804	ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX /\| IFF_MULTICAST/;
805	if (ifp->if_snd.ifq_maxlen == 0)
806	ifp->if_snd.ifq_maxlen = ifqmaxlen;
807
808	/*
809	* Attach the interface.
810	*/
811	DBGLVL_PRINTK(3,"fxp_attach: calling if_attach\n");
812	if_attach (ifp);
813	DBGLVL_PRINTK(3,"fxp_attach: calling ether_if_attach\n");
814	ether_ifattach(ifp);
815	DBGLVL_PRINTK(3,"fxp_attach: return from ether_if_attach\n");
816
817	#ifdef NOTUSED
818	/*
819	* Tell the upper layer(s) we support long frames.
820	*/
821	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
822	#endif
823	/*
824	* Let the system queue as many packets as we have available
825	* TX descriptors.
826	*/
827	ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1;
828
829	splx(s);
830	return (0);
831
832	failmem:
833	device_printf(dev, "Failed to malloc memory\n");
834	error = ENOMEM;
835	#ifdef NOTUSED
836	fail:
837	#endif
838	splx(s);
839	fxp_release(sc);
840	return (error);
841	}
842
843	/*
844	* release all resources
845	*/
846	static void
847	fxp_release(struct fxp_softc *sc)
848	{
849
850	#ifdef NOTUSED
851	bus_generic_detach(sc->dev);
852	if (sc->miibus)
853	device_delete_child(sc->dev, sc->miibus);
854	#endif
855	if (sc->cbl_base)
856	free(sc->cbl_base, M_DEVBUF);
857	if (sc->fxp_stats)
858	free(sc->fxp_stats, M_DEVBUF);
859	if (sc->mcsp)
860	free(sc->mcsp, M_DEVBUF);
861	if (sc->rfa_headm)
862	m_freem(sc->rfa_headm);
863
864	#ifdef NOTUSED
865	if (sc->ih)
866	bus_teardown_intr(sc->dev, sc->irq, sc->ih);
867	if (sc->irq)
868	bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
869	if (sc->mem)
870	bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem);
871	mtx_destroy(&sc->sc_mtx);
872	#endif
873	}
874
875	#if NOTUSED
876	/*
877	* Detach interface.
878	*/
879	static int
880	fxp_detach(device_t dev)
881	{
882	struct fxp_softc *sc = device_get_softc(dev);
883	int s;
884
885	/* disable interrupts */
886	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
887
888	s = splimp();
889
890	/*
891	* Stop DMA and drop transmit queue.
892	*/
893	fxp_stop(sc);
894
895	/*
896	* Close down routes etc.
897	*/
898	ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED);
899
900	/*
901	* Free all media structures.
902	*/
903	ifmedia_removeall(&sc->sc_media);
904
905	splx(s);
906
907	/* Release our allocated resources. */
908	fxp_release(sc);
909
910	return (0);
911	}
912
913	/*
914	* Device shutdown routine. Called at system shutdown after sync. The
915	* main purpose of this routine is to shut off receiver DMA so that
916	* kernel memory doesn't get clobbered during warmboot.
917	*/
918	static int
919	fxp_shutdown(device_t dev)
920	{
921	/*
922	* Make sure that DMA is disabled prior to reboot. Not doing
923	* do could allow DMA to corrupt kernel memory during the
924	* reboot before the driver initializes.
925	*/
926	fxp_stop((struct fxp_softc *) device_get_softc(dev));
927	return (0);
928	}
929	#endif
930
931	/*
932	* Show interface statistics
933	*/
934	static void
935	fxp_stats(struct fxp_softc *sc)
936	{
937	struct ifnet *ifp = &sc->sc_if;
938
939	printf (" Output packets:%-8lu", ifp->if_opackets);
940	printf (" Collisions:%-8lu", ifp->if_collisions);
941	printf (" Output errors:%-8lu\n", ifp->if_oerrors);
942	printf (" Input packets:%-8lu", ifp->if_ipackets);
943	printf (" Input errors:%-8lu\n", ifp->if_ierrors);
944	}
945
946	static void
947	fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
948	{
949	u_int16_t reg;
950	int x;
951
952	/*
953	* Shift in data.
954	*/
955	for (x = 1 << (length - 1); x; x >>= 1) {
956	if (data & x)
957	reg = FXP_EEPROM_EECS \| FXP_EEPROM_EEDI;
958	else
959	reg = FXP_EEPROM_EECS;
960	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
961	DELAY(1);
962	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg \| FXP_EEPROM_EESK);
963	DELAY(1);
964	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
965	DELAY(1);
966	}
967	}
968
969	/*
970	* Read from the serial EEPROM. Basically, you manually shift in
971	* the read opcode (one bit at a time) and then shift in the address,
972	* and then you shift out the data (all of this one bit at a time).
973	* The word size is 16 bits, so you have to provide the address for
974	* every 16 bits of data.
975	*/
976	static u_int16_t
977	fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
978	{
979	u_int16_t reg, data;
980	int x;
981
982	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
983	/*
984	* Shift in read opcode.
985	*/
986	fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
987	/*
988	* Shift in address.
989	*/
990	data = 0;
991	for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
992	if (offset & x)
993	reg = FXP_EEPROM_EECS \| FXP_EEPROM_EEDI;
994	else
995	reg = FXP_EEPROM_EECS;
996	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
997	DELAY(1);
998	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg \| FXP_EEPROM_EESK);
999	DELAY(1);
1000	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1001	DELAY(1);
1002	reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
1003	data++;
1004	if (autosize && reg == 0) {
1005	sc->eeprom_size = data;
1006	break;
1007	}
1008	}
1009	/*
1010	* Shift out data.
1011	*/
1012	data = 0;
1013	reg = FXP_EEPROM_EECS;
1014	for (x = 1 << 15; x; x >>= 1) {
1015	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg \| FXP_EEPROM_EESK);
1016	DELAY(1);
1017	if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1018	data \|= x;
1019	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1020	DELAY(1);
1021	}
1022	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1023	DELAY(1);
1024
1025	return (data);
1026	}
1027
1028	static void
1029	fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data)
1030	{
1031	int i;
1032
1033	/*
1034	* Erase/write enable.
1035	*/
1036	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1037	fxp_eeprom_shiftin(sc, 0x4, 3);
1038	fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1039	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1040	DELAY(1);
1041	/*
1042	* Shift in write opcode, address, data.
1043	*/
1044	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1045	fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1046	fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1047	fxp_eeprom_shiftin(sc, data, 16);
1048	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1049	DELAY(1);
1050	/*
1051	* Wait for EEPROM to finish up.
1052	*/
1053	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1054	DELAY(1);
1055	for (i = 0; i < 1000; i++) {
1056	if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1057	break;
1058	DELAY(50);
1059	}
1060	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1061	DELAY(1);
1062	/*
1063	* Erase/write disable.
1064	*/
1065	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1066	fxp_eeprom_shiftin(sc, 0x4, 3);
1067	fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1068	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1069	DELAY(1);
1070	}
1071
1072	/*
1073	* From NetBSD:
1074	*
1075	* Figure out EEPROM size.
1076	*
1077	* 559's can have either 64-word or 256-word EEPROMs, the 558
1078	* datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1079	* talks about the existance of 16 to 256 word EEPROMs.
1080	*
1081	* The only known sizes are 64 and 256, where the 256 version is used
1082	* by CardBus cards to store CIS information.
1083	*
1084	* The address is shifted in msb-to-lsb, and after the last
1085	* address-bit the EEPROM is supposed to output a `dummy zero' bit,
1086	* after which follows the actual data. We try to detect this zero, by
1087	* probing the data-out bit in the EEPROM control register just after
1088	* having shifted in a bit. If the bit is zero, we assume we've
1089	* shifted enough address bits. The data-out should be tri-state,
1090	* before this, which should translate to a logical one.
1091	*/
1092	static void
1093	fxp_autosize_eeprom(struct fxp_softc *sc)
1094	{
1095
1096	/* guess maximum size of 256 words */
1097	sc->eeprom_size = 8;
1098
1099	/* autosize */
1100	(void) fxp_eeprom_getword(sc, 0, 1);
1101	}
1102
1103	static void
1104	fxp_read_eeprom(struct fxp_softc sc, u_short data, int offset, int words)
1105	{
1106	int i;
1107
1108	for (i = 0; i < words; i++) {
1109	data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1110	DBGLVL_PRINTK(4,"fxp_eeprom_read(off=0x%x)=0x%x\n",
1111	offset+i,data[i]);
1112	}
1113	}
1114
1115	static void
1116	fxp_write_eeprom(struct fxp_softc sc, u_short data, int offset, int words)
1117	{
1118	int i;
1119
1120	for (i = 0; i < words; i++)
1121	fxp_eeprom_putword(sc, offset + i, data[i]);
1122	DBGLVL_PRINTK(4,"fxp_eeprom_write(off=0x%x,0x%x)\n",
1123	offset+i,data[i]);
1124	}
1125
1126	/*
1127	* Start packet transmission on the interface.
1128	*/
1129	static void
1130	fxp_start(struct ifnet *ifp)
1131	{
1132	struct fxp_softc *sc = ifp->if_softc;
1133	struct fxp_cb_tx *txp;
1134
1135	DBGLVL_PRINTK(3,"fxp_start called\n");
1136
1137	/*
1138	* See if we need to suspend xmit until the multicast filter
1139	* has been reprogrammed (which can only be done at the head
1140	* of the command chain).
1141	*/
1142	if (sc->need_mcsetup) {
1143	return;
1144	}
1145
1146	txp = NULL;
1147
1148	/*
1149	* We're finished if there is nothing more to add to the list or if
1150	* we're all filled up with buffers to transmit.
1151	* NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1152	* a NOP command when needed.
1153	*/
1154	while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) {
1155	struct mbuf m, mb_head;
1156	int segment;
1157
1158	/*
1159	* Grab a packet to transmit.
1160	*/
1161	IF_DEQUEUE(&ifp->if_snd, mb_head);
1162
1163	/*
1164	* Get pointer to next available tx desc.
1165	*/
1166	txp = sc->cbl_last->next;
1167
1168	/*
1169	* Go through each of the mbufs in the chain and initialize
1170	* the transmit buffer descriptors with the physical address
1171	* and size of the mbuf.
1172	*/
1173	tbdinit:
1174	for (m = mb_head, segment = 0; m != NULL; m = m->m_next) {
1175	if (m->m_len != 0) {
1176	if (segment == FXP_NTXSEG)
1177	break;
1178	txp->tbd[segment].tb_addr =
1179	vtophys(mtod(m, vm_offset_t));
1180	txp->tbd[segment].tb_size = m->m_len;
1181	segment++;
1182	}
1183	}
1184	if (m != NULL) {
1185	struct mbuf *mn;
1186
1187	/*
1188	* We ran out of segments. We have to recopy this
1189	* mbuf chain first. Bail out if we can't get the
1190	* new buffers.
1191	*/
1192	MGETHDR(mn, M_DONTWAIT, MT_DATA);
1193	if (mn == NULL) {
1194	m_freem(mb_head);
1195	break;
1196	}
1197	if (mb_head->m_pkthdr.len > MHLEN) {
1198	MCLGET(mn, M_DONTWAIT);
1199	if ((mn->m_flags & M_EXT) == 0) {
1200	m_freem(mn);
1201	m_freem(mb_head);
1202	break;
1203	}
1204	}
1205	m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
1206	mtod(mn, caddr_t));
1207	mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len;
1208	m_freem(mb_head);
1209	mb_head = mn;
1210	goto tbdinit;
1211	}
1212
1213	txp->tbd_number = segment;
1214	txp->mb_head = mb_head;
1215	txp->cb_status = 0;
1216	if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1217	txp->cb_command =
1218	FXP_CB_COMMAND_XMIT \| FXP_CB_COMMAND_SF \|
1219	FXP_CB_COMMAND_S;
1220	} else {
1221	txp->cb_command =
1222	FXP_CB_COMMAND_XMIT \| FXP_CB_COMMAND_SF \|
1223	FXP_CB_COMMAND_S \| FXP_CB_COMMAND_I;
1224	/*
1225	* Set a 5 second timer just in case we don't hear
1226	* from the card again.
1227	*/
1228	ifp->if_timer = 5;
1229	}
1230	txp->tx_threshold = tx_threshold;
1231
1232	/*
1233	* Advance the end of list forward.
1234	*/
1235
1236	#ifdef __alpha__
1237	/*
1238	* On platforms which can't access memory in 16-bit
1239	* granularities, we must prevent the card from DMA'ing
1240	* up the status while we update the command field.
1241	* This could cause us to overwrite the completion status.
1242	*/
1243	atomic_clear_short(&sc->cbl_last->cb_command,
1244	FXP_CB_COMMAND_S);
1245	#else
1246	sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
1247	#endif /__alpha__/
1248	sc->cbl_last = txp;
1249
1250	/*
1251	* Advance the beginning of the list forward if there are
1252	* no other packets queued (when nothing is queued, cbl_first
1253	* sits on the last TxCB that was sent out).
1254	*/
1255	if (sc->tx_queued == 0)
1256	sc->cbl_first = txp;
1257
1258	sc->tx_queued++;
1259
1260	#ifdef NOTUSED
1261	/*
1262	* Pass packet to bpf if there is a listener.
1263	*/
1264	if (ifp->if_bpf)
1265	bpf_mtap(ifp, mb_head);
1266	#endif
1267	}
1268
1269	/*
1270	* We're finished. If we added to the list, issue a RESUME to get DMA
1271	* going again if suspended.
1272	*/
1273	if (txp != NULL) {
1274	fxp_scb_wait(sc);
1275	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1276	}
1277	}
1278
1279	/*
1280	* Process interface interrupts.
1281	*/
1282	static rtems_isr fxp_intr(rtems_vector_number v)
1283	{
1284	/*
1285	* FIXME: currently only works with one interface...
1286	*/
1287	struct fxp_softc *sc = &(fxp_softc[0]);
1288
1289	/*
1290	* disable interrupts
1291	*/
1292	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1293	/*
1294	* send event to deamon
1295	*/
1296	rtems_event_send (sc->daemonTid, INTERRUPT_EVENT);
1297	}
1298
1299	static void fxp_daemon(void *xsc)
1300	{
1301	struct fxp_softc *sc = xsc;
1302	struct ifnet *ifp = &sc->sc_if;
1303	u_int8_t statack;
1304	rtems_event_set events;
1305	rtems_interrupt_level level;
1306
1307	#ifdef NOTUSED
1308	if (sc->suspended) {
1309	return;
1310	}
1311	#endif
1312	for (;;) {
1313
1314	DBGLVL_PRINTK(4,"fxp_daemon waiting for event\n");
1315	/*
1316	* wait for event to receive from interrupt function
1317	*/
1318	rtems_bsdnet_event_receive (INTERRUPT_EVENT,
1319	RTEMS_WAIT\|RTEMS_EVENT_ANY,
1320	RTEMS_NO_TIMEOUT,
1321	&events);
1322	while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1323	DBGLVL_PRINTK(4,"fxp_daemon: processing event, statack = 0x%x\n",
1324	statack);
1325	#ifdef NOTUSED
1326	/*
1327	* It should not be possible to have all bits set; the
1328	* FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1329	* all bits are set, this may indicate that the card has
1330	* been physically ejected, so ignore it.
1331	*/
1332	if (statack == 0xff)
1333	return;
1334	#endif
1335
1336	/*
1337	* First ACK all the interrupts in this pass.
1338	*/
1339	CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1340
1341	/*
1342	* Free any finished transmit mbuf chains.
1343	*
1344	* Handle the CNA event likt a CXTNO event. It used to
1345	* be that this event (control unit not ready) was not
1346	* encountered, but it is now with the SMPng modifications.
1347	* The exact sequence of events that occur when the interface
1348	* is brought up are different now, and if this event
1349	* goes unhandled, the configuration/rxfilter setup sequence
1350	* can stall for several seconds. The result is that no
1351	* packets go out onto the wire for about 5 to 10 seconds
1352	* after the interface is ifconfig'ed for the first time.
1353	*/
1354	if (statack & (FXP_SCB_STATACK_CXTNO \| FXP_SCB_STATACK_CNA)) {
1355	struct fxp_cb_tx *txp;
1356
1357	for (txp = sc->cbl_first; sc->tx_queued &&
1358	(txp->cb_status & FXP_CB_STATUS_C) != 0;
1359	txp = txp->next) {
1360	if (txp->mb_head != NULL) {
1361	m_freem(txp->mb_head);
1362	txp->mb_head = NULL;
1363	}
1364	sc->tx_queued--;
1365	}
1366	sc->cbl_first = txp;
1367	ifp->if_timer = 0;
1368	if (sc->tx_queued == 0) {
1369	if (sc->need_mcsetup)
1370	fxp_mc_setup(sc);
1371	}
1372	/*
1373	* Try to start more packets transmitting.
1374	*/
1375	if (ifp->if_snd.ifq_head != NULL)
1376	fxp_start(ifp);
1377	}
1378	/*
1379	* Process receiver interrupts. If a no-resource (RNR)
1380	* condition exists, get whatever packets we can and
1381	* re-start the receiver.
1382	*/
1383	if (statack & (FXP_SCB_STATACK_FR \| FXP_SCB_STATACK_RNR)) {
1384	struct mbuf *m;
1385	struct fxp_rfa *rfa;
1386	rcvloop:
1387	m = sc->rfa_headm;
1388	rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1389	RFA_ALIGNMENT_FUDGE);
1390
1391	if (rfa->rfa_status & FXP_RFA_STATUS_C) {
1392	/*
1393	* Remove first packet from the chain.
1394	*/
1395	sc->rfa_headm = m->m_next;
1396	m->m_next = NULL;
1397
1398	/*
1399	* Add a new buffer to the receive chain.
1400	* If this fails, the old buffer is recycled
1401	* instead.
1402	*/
1403	if (fxp_add_rfabuf(sc, m) == 0) {
1404	struct ether_header *eh;
1405	int total_len;
1406
1407	total_len = rfa->actual_size &
1408	(MCLBYTES - 1);
1409	if (total_len <
1410	sizeof(struct ether_header)) {
1411	m_freem(m);
1412	goto rcvloop;
1413	}
1414
1415	/*
1416	* Drop the packet if it has CRC
1417	* errors. This test is only needed
1418	* when doing 802.1q VLAN on the 82557
1419	* chip.
1420	*/
1421	if (rfa->rfa_status &
1422	FXP_RFA_STATUS_CRC) {
1423	m_freem(m);
1424	goto rcvloop;
1425	}
1426
1427	m->m_pkthdr.rcvif = ifp;
1428	m->m_pkthdr.len = m->m_len = total_len;
1429	eh = mtod(m, struct ether_header *);
1430	m->m_data +=
1431	sizeof(struct ether_header);
1432	m->m_len -=
1433	sizeof(struct ether_header);
1434	m->m_pkthdr.len = m->m_len;
1435	ether_input(ifp, eh, m);
1436	}
1437	goto rcvloop;
1438	}
1439	if (statack & FXP_SCB_STATACK_RNR) {
1440	fxp_scb_wait(sc);
1441	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1442	vtophys(sc->rfa_headm->m_ext.ext_buf) +
1443	RFA_ALIGNMENT_FUDGE);
1444	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1445	}
1446	}
1447	}
1448	/*
1449	* reenable interrupts
1450	*/
1451	rtems_interrupt_disable (level);
1452	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,0);
1453	rtems_interrupt_enable (level);
1454	}
1455	}
1456
1457	/*
1458	* Update packet in/out/collision statistics. The i82557 doesn't
1459	* allow you to access these counters without doing a fairly
1460	* expensive DMA to get _all_ of the statistics it maintains, so
1461	* we do this operation here only once per second. The statistics
1462	* counters in the kernel are updated from the previous dump-stats
1463	* DMA and then a new dump-stats DMA is started. The on-chip
1464	* counters are zeroed when the DMA completes. If we can't start
1465	* the DMA immediately, we don't wait - we just prepare to read
1466	* them again next time.
1467	*/
1468	static void
1469	fxp_tick(void *xsc)
1470	{
1471	struct fxp_softc *sc = xsc;
1472	struct ifnet *ifp = &sc->sc_if;
1473	struct fxp_stats *sp = sc->fxp_stats;
1474	struct fxp_cb_tx *txp;
1475	int s;
1476
1477	DBGLVL_PRINTK(4,"fxp_tick called\n");
1478
1479	ifp->if_opackets += sp->tx_good;
1480	ifp->if_collisions += sp->tx_total_collisions;
1481	if (sp->rx_good) {
1482	ifp->if_ipackets += sp->rx_good;
1483	sc->rx_idle_secs = 0;
1484	} else {
1485	/*
1486	* Receiver's been idle for another second.
1487	*/
1488	sc->rx_idle_secs++;
1489	}
1490	ifp->if_ierrors +=
1491	sp->rx_crc_errors +
1492	sp->rx_alignment_errors +
1493	sp->rx_rnr_errors +
1494	sp->rx_overrun_errors;
1495	/*
1496	* If any transmit underruns occured, bump up the transmit
1497	* threshold by another 512 bytes (64 * 8).
1498	*/
1499	if (sp->tx_underruns) {
1500	ifp->if_oerrors += sp->tx_underruns;
1501	if (tx_threshold < 192)
1502	tx_threshold += 64;
1503	}
1504	s = splimp();
1505	/*
1506	* Release any xmit buffers that have completed DMA. This isn't
1507	* strictly necessary to do here, but it's advantagous for mbufs
1508	* with external storage to be released in a timely manner rather
1509	* than being defered for a potentially long time. This limits
1510	* the delay to a maximum of one second.
1511	*/
1512	for (txp = sc->cbl_first; sc->tx_queued &&
1513	(txp->cb_status & FXP_CB_STATUS_C) != 0;
1514	txp = txp->next) {
1515	if (txp->mb_head != NULL) {
1516	m_freem(txp->mb_head);
1517	txp->mb_head = NULL;
1518	}
1519	sc->tx_queued--;
1520	}
1521	sc->cbl_first = txp;
1522	/*
1523	* If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1524	* then assume the receiver has locked up and attempt to clear
1525	* the condition by reprogramming the multicast filter. This is
1526	* a work-around for a bug in the 82557 where the receiver locks
1527	* up if it gets certain types of garbage in the syncronization
1528	* bits prior to the packet header. This bug is supposed to only
1529	* occur in 10Mbps mode, but has been seen to occur in 100Mbps
1530	* mode as well (perhaps due to a 10/100 speed transition).
1531	*/
1532	if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1533	sc->rx_idle_secs = 0;
1534	fxp_mc_setup(sc);
1535	}
1536	/*
1537	* If there is no pending command, start another stats
1538	* dump. Otherwise punt for now.
1539	*/
1540	if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1541	/*
1542	* Start another stats dump.
1543	*/
1544	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1545	} else {
1546	/*
1547	* A previous command is still waiting to be accepted.
1548	* Just zero our copy of the stats and wait for the
1549	* next timer event to update them.
1550	*/
1551	sp->tx_good = 0;
1552	sp->tx_underruns = 0;
1553	sp->tx_total_collisions = 0;
1554
1555	sp->rx_good = 0;
1556	sp->rx_crc_errors = 0;
1557	sp->rx_alignment_errors = 0;
1558	sp->rx_rnr_errors = 0;
1559	sp->rx_overrun_errors = 0;
1560	}
1561	#ifdef NOTUSED
1562	if (sc->miibus != NULL)
1563	mii_tick(device_get_softc(sc->miibus));
1564	#endif
1565	splx(s);
1566	/*
1567	* Schedule another timeout one second from now.
1568	*/
1569	if (sc->stat_ch == fxp_timeout_running) {
1570	timeout(fxp_tick, sc, hz);
1571	}
1572	else if (sc->stat_ch == fxp_timeout_stop_rq) {
1573	sc->stat_ch = fxp_timeout_stopped;
1574	}
1575	}
1576
1577	/*
1578	* Stop the interface. Cancels the statistics updater and resets
1579	* the interface.
1580	*/
1581	static void
1582	fxp_stop(struct fxp_softc *sc)
1583	{
1584	struct ifnet *ifp = &sc->sc_if;
1585	struct fxp_cb_tx *txp;
1586	int i;
1587
1588	DBGLVL_PRINTK(2,"fxp_stop called\n");
1589
1590	ifp->if_flags &= ~(IFF_RUNNING \| IFF_OACTIVE);
1591	ifp->if_timer = 0;
1592
1593	/*
1594	* stop stats updater.
1595	*/
1596	if (sc->stat_ch == fxp_timeout_running) {
1597	DBGLVL_PRINTK(3,"fxp_stop: trying to stop stat update tick\n");
1598	sc->stat_ch = fxp_timeout_stop_rq;
1599	while(sc->stat_ch != fxp_timeout_stopped) {
1600	rtems_bsdnet_semaphore_release();
1601	rtems_task_wake_after(fxp_ticksPerSecond);
1602	rtems_bsdnet_semaphore_obtain();
1603	}
1604	DBGLVL_PRINTK(3,"fxp_stop: stat update tick stopped\n");
1605	}
1606	/*
1607	* Issue software reset
1608	*/
1609	DBGLVL_PRINTK(3,"fxp_stop: issue software reset\n");
1610	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1611	DELAY(10);
1612
1613	/*
1614	* Release any xmit buffers.
1615	*/
1616	DBGLVL_PRINTK(3,"fxp_stop: releasing xmit buffers\n");
1617	txp = sc->cbl_base;
1618	if (txp != NULL) {
1619	for (i = 0; i < FXP_NTXCB; i++) {
1620	if (txp[i].mb_head != NULL) {
1621	m_freem(txp[i].mb_head);
1622	txp[i].mb_head = NULL;
1623	}
1624	}
1625	}
1626	sc->tx_queued = 0;
1627
1628	/*
1629	* Free all the receive buffers then reallocate/reinitialize
1630	*/
1631	DBGLVL_PRINTK(3,"fxp_stop: free and reinit all receive buffers\n");
1632	if (sc->rfa_headm != NULL)
1633	m_freem(sc->rfa_headm);
1634	sc->rfa_headm = NULL;
1635	sc->rfa_tailm = NULL;
1636	for (i = 0; i < FXP_NRFABUFS; i++) {
1637	if (fxp_add_rfabuf(sc, NULL) != 0) {
1638	/*
1639	* This "can't happen" - we're at splimp()
1640	* and we just freed all the buffers we need
1641	* above.
1642	*/
1643	panic("fxp_stop: no buffers!");
1644	}
1645	}
1646	DBGLVL_PRINTK(2,"fxp_stop: finished\n");
1647	}
1648
1649	/*
1650	* Watchdog/transmission transmit timeout handler. Called when a
1651	* transmission is started on the interface, but no interrupt is
1652	* received before the timeout. This usually indicates that the
1653	* card has wedged for some reason.
1654	*/
1655	static void
1656	fxp_watchdog(struct ifnet *ifp)
1657	{
1658	struct fxp_softc *sc = ifp->if_softc;
1659
1660	device_printf(sc->dev, "device timeout\n");
1661	ifp->if_oerrors++;
1662
1663	fxp_init(sc);
1664	}
1665
1666	static void
1667	fxp_init(void *xsc)
1668	{
1669	struct fxp_softc *sc = xsc;
1670	struct ifnet *ifp = &sc->sc_if;
1671	struct fxp_cb_config *cbp;
1672	struct fxp_cb_ias *cb_ias;
1673	struct fxp_cb_tx *txp;
1674	int i, prm, s;
1675
1676	rtems_task_wake_after(100);
1677	DBGLVL_PRINTK(2,"fxp_init called\n");
1678
1679	s = splimp();
1680	/*
1681	* Cancel any pending I/O
1682	*/
1683	/*
1684	* E. Norum 2004-10-11
1685	* Add line suggested by "Eugene Denisov" <dea@sendmail.ru>.
1686	* Prevents lockup at initialization.
1687	*/
1688	sc->stat_ch = fxp_timeout_stopped;
1689	fxp_stop(sc);
1690
1691	prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1692
1693	DBGLVL_PRINTK(5,"fxp_init: Initializing base of CBL and RFA memory\n");
1694	/*
1695	* Initialize base of CBL and RFA memory. Loading with zero
1696	* sets it up for regular linear addressing.
1697	*/
1698	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1699	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
1700
1701	fxp_scb_wait(sc);
1702	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
1703
1704	/*
1705	* Initialize base of dump-stats buffer.
1706	*/
1707	DBGLVL_PRINTK(5,"fxp_init: Initializing base of dump-stats buffer\n");
1708	fxp_scb_wait(sc);
1709	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats));
1710	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
1711
1712	/*
1713	* We temporarily use memory that contains the TxCB list to
1714	* construct the config CB. The TxCB list memory is rebuilt
1715	* later.
1716	*/
1717	cbp = (struct fxp_cb_config *) sc->cbl_base;
1718	DBGLVL_PRINTK(5,"fxp_init: cbp = 0x%x\n",cbp);
1719
1720	/*
1721	* This memcpy is kind of disgusting, but there are a bunch of must be
1722	* zero and must be one bits in this structure and this is the easiest
1723	* way to initialize them all to proper values.
1724	*/
1725	memcpy( (void )(u_int32_t)(volatile void *)&cbp->cb_status,
1726	fxp_cb_config_template,
1727	sizeof(fxp_cb_config_template));
1728
1729	cbp->cb_status = 0;
1730	cbp->cb_command = FXP_CB_COMMAND_CONFIG \| FXP_CB_COMMAND_EL;
1731	cbp->link_addr = -1; /* (no) next command */
1732	cbp->byte_count = 22; /* (22) bytes to config */
1733	cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
1734	cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
1735	cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
1736	cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
1737	cbp->type_enable = 0; /* actually reserved */
1738	cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
1739	cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
1740	cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
1741	cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
1742	cbp->dma_mbce = 0; /* (disable) dma max counters */
1743	cbp->late_scb = 0; /* (don't) defer SCB update */
1744	cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
1745	cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
1746	cbp->ci_int = 1; /* interrupt on CU idle */
1747	cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
1748	cbp->ext_stats_dis = 1; /* disable extended counters */
1749	cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
1750	cbp->save_bf = sc->chip == FXP_CHIP_82557 ? 1 : prm;
1751	cbp->disc_short_rx = !prm; /* discard short packets */
1752	cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
1753	cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
1754	cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */
1755	cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
1756	cbp->csma_dis = 0; /* (don't) disable link */
1757	cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */
1758	cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
1759	cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
1760	cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
1761	cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
1762	cbp->nsai = 1; /* (don't) disable source addr insert */
1763	cbp->preamble_length = 2; /* (7 byte) preamble */
1764	cbp->loopback = 0; /* (don't) loopback */
1765	cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
1766	cbp->linear_pri_mode = 0; /* (wait after xmit only) */
1767	cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
1768	cbp->promiscuous = prm; /* promiscuous mode */
1769	cbp->bcast_disable = 0; /* (don't) disable broadcasts */
1770	cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
1771	cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
1772	cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
1773	cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
1774
1775	cbp->stripping = !prm; /* truncate rx packet to byte count */
1776	cbp->padding = 1; /* (do) pad short tx packets */
1777	cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
1778	cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
1779	cbp->ia_wake_en = 0; /* (don't) wake up on address match */
1780	cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */
1781	/* must set wake_en in PMCSR also */
1782	cbp->force_fdx = 0; /* (don't) force full duplex */
1783	cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
1784	cbp->multi_ia = 0; /* (don't) accept multiple IAs */
1785	cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
1786
1787	DBGLVL_PRINTK(5,"fxp_init: cbp initialized\n");
1788	if (sc->chip == FXP_CHIP_82557) {
1789	/*
1790	* The 82557 has no hardware flow control, the values
1791	* below are the defaults for the chip.
1792	*/
1793	cbp->fc_delay_lsb = 0;
1794	cbp->fc_delay_msb = 0x40;
1795	cbp->pri_fc_thresh = 3;
1796	cbp->tx_fc_dis = 0;
1797	cbp->rx_fc_restop = 0;
1798	cbp->rx_fc_restart = 0;
1799	cbp->fc_filter = 0;
1800	cbp->pri_fc_loc = 1;
1801	} else {
1802	cbp->fc_delay_lsb = 0x1f;
1803	cbp->fc_delay_msb = 0x01;
1804	cbp->pri_fc_thresh = 3;
1805	cbp->tx_fc_dis = 0; /* enable transmit FC */
1806	cbp->rx_fc_restop = 1; /* enable FC restop frames */
1807	cbp->rx_fc_restart = 1; /* enable FC restart frames */
1808	cbp->fc_filter = !prm; /* drop FC frames to host */
1809	cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
1810	}
1811
1812	/*
1813	* Start the config command/DMA.
1814	*/
1815	DBGLVL_PRINTK(5,"fxp_init: starting config command/DMA\n");
1816	fxp_scb_wait(sc);
1817	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
1818	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1819	/* ...and wait for it to complete. */
1820	fxp_dma_wait(&cbp->cb_status, sc);
1821
1822	/*
1823	* Now initialize the station address. Temporarily use the TxCB
1824	* memory area like we did above for the config CB.
1825	*/
1826	DBGLVL_PRINTK(5,"fxp_init: initialize station address\n");
1827	cb_ias = (struct fxp_cb_ias *) sc->cbl_base;
1828	cb_ias->cb_status = 0;
1829	cb_ias->cb_command = FXP_CB_COMMAND_IAS \| FXP_CB_COMMAND_EL;
1830	cb_ias->link_addr = -1;
1831	memcpy((void )(u_int32_t)(volatile void *)cb_ias->macaddr,
1832	sc->arpcom.ac_enaddr,
1833	sizeof(sc->arpcom.ac_enaddr));
1834
1835	/*
1836	* Start the IAS (Individual Address Setup) command/DMA.
1837	*/
1838	DBGLVL_PRINTK(5,"fxp_init: start IAS command/DMA\n");
1839	fxp_scb_wait(sc);
1840	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1841	/* ...and wait for it to complete. */
1842	fxp_dma_wait(&cb_ias->cb_status, sc);
1843
1844	/*
1845	* Initialize transmit control block (TxCB) list.
1846	*/
1847
1848	DBGLVL_PRINTK(5,"fxp_init: initialize TxCB list\n");
1849	txp = sc->cbl_base;
1850	memset(txp, 0, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
1851	for (i = 0; i < FXP_NTXCB; i++) {
1852	txp[i].cb_status = FXP_CB_STATUS_C \| FXP_CB_STATUS_OK;
1853	txp[i].cb_command = FXP_CB_COMMAND_NOP;
1854	txp[i].link_addr =
1855	vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status);
1856	if (sc->flags & FXP_FLAG_EXT_TXCB)
1857	txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]);
1858	else
1859	txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]);
1860	txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK];
1861	}
1862	/*
1863	* Set the suspend flag on the first TxCB and start the control
1864	* unit. It will execute the NOP and then suspend.
1865	*/
1866	DBGLVL_PRINTK(5,"fxp_init: setup suspend flag\n");
1867	txp->cb_command = FXP_CB_COMMAND_NOP \| FXP_CB_COMMAND_S;
1868	sc->cbl_first = sc->cbl_last = txp;
1869	sc->tx_queued = 1;
1870
1871	fxp_scb_wait(sc);
1872	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1873
1874	/*
1875	* Initialize receiver buffer area - RFA.
1876	*/
1877	DBGLVL_PRINTK(5,"fxp_init: initialize RFA\n");
1878	fxp_scb_wait(sc);
1879	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1880	vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE);
1881	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1882
1883	#ifdef NOTUSED
1884	/*
1885	* Set current media.
1886	*/
1887	if (sc->miibus != NULL)
1888	mii_mediachg(device_get_softc(sc->miibus));
1889	#endif
1890
1891	ifp->if_flags \|= IFF_RUNNING;
1892	ifp->if_flags &= ~IFF_OACTIVE;
1893
1894	if (sc->daemonTid == 0) {
1895	/*
1896	* Start driver task
1897	*/
1898	sc->daemonTid = rtems_bsdnet_newproc ("FXPd", 4096, fxp_daemon, sc);
1899
1900	}
1901	/*
1902	* Enable interrupts.
1903	*/
1904	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1905	splx(s);
1906
1907	/*
1908	* Start stats updater.
1909	*/
1910	sc->stat_ch = fxp_timeout_running;
1911	DBGLVL_PRINTK(2,"fxp_init: stats updater timeout called with hz=%d\n", hz);
1912	timeout(fxp_tick, sc, hz);
1913	DBGLVL_PRINTK(2,"fxp_init finished\n");
1914	}
1915
1916	#ifdef NOTUSED
1917	static int
1918	fxp_serial_ifmedia_upd(struct ifnet *ifp)
1919	{
1920
1921	return (0);
1922	}
1923
1924	static void
1925	fxp_serial_ifmedia_sts(struct ifnet ifp, struct ifmediareq ifmr)
1926	{
1927
1928	ifmr->ifm_active = IFM_ETHER\|IFM_MANUAL;
1929	}
1930
1931	/*
1932	* Change media according to request.
1933	*/
1934	static int
1935	fxp_ifmedia_upd(struct ifnet *ifp)
1936	{
1937	struct fxp_softc *sc = ifp->if_softc;
1938	struct mii_data *mii;
1939
1940	mii = device_get_softc(sc->miibus);
1941	mii_mediachg(mii);
1942	return (0);
1943	}
1944
1945	/*
1946	* Notify the world which media we're using.
1947	*/
1948	static void
1949	fxp_ifmedia_sts(struct ifnet ifp, struct ifmediareq ifmr)
1950	{
1951	struct fxp_softc *sc = ifp->if_softc;
1952	struct mii_data *mii;
1953
1954	mii = device_get_softc(sc->miibus);
1955	mii_pollstat(mii);
1956	ifmr->ifm_active = mii->mii_media_active;
1957	ifmr->ifm_status = mii->mii_media_status;
1958
1959	if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG)
1960	sc->cu_resume_bug = 1;
1961	else
1962	sc->cu_resume_bug = 0;
1963	}
1964	#endif
1965
1966	/*
1967	* Add a buffer to the end of the RFA buffer list.
1968	* Return 0 if successful, 1 for failure. A failure results in
1969	* adding the 'oldm' (if non-NULL) on to the end of the list -
1970	* tossing out its old contents and recycling it.
1971	* The RFA struct is stuck at the beginning of mbuf cluster and the
1972	* data pointer is fixed up to point just past it.
1973	*/
1974	static int
1975	fxp_add_rfabuf(struct fxp_softc sc, struct mbuf oldm)
1976	{
1977	u_int32_t v;
1978	struct mbuf *m;
1979	struct fxp_rfa rfa, p_rfa;
1980
1981	DBGLVL_PRINTK(4,"fxp_add_rfabuf called\n");
1982
1983	MGETHDR(m, M_DONTWAIT, MT_DATA);
1984	if (m != NULL) {
1985	MCLGET(m, M_DONTWAIT);
1986	if ((m->m_flags & M_EXT) == 0) {
1987	m_freem(m);
1988	if (oldm == NULL)
1989	return 1;
1990	m = oldm;
1991	m->m_data = m->m_ext.ext_buf;
1992	}
1993	} else {
1994	if (oldm == NULL)
1995	return 1;
1996	m = oldm;
1997	m->m_data = m->m_ext.ext_buf;
1998	}
1999
2000	/*
2001	* Move the data pointer up so that the incoming data packet
2002	* will be 32-bit aligned.
2003	*/
2004	m->m_data += RFA_ALIGNMENT_FUDGE;
2005
2006	/*
2007	* Get a pointer to the base of the mbuf cluster and move
2008	* data start past it.
2009	*/
2010	rfa = mtod(m, struct fxp_rfa *);
2011	m->m_data += sizeof(struct fxp_rfa);
2012	rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE);
2013
2014	/*
2015	* Initialize the rest of the RFA. Note that since the RFA
2016	* is misaligned, we cannot store values directly. Instead,
2017	* we use an optimized, inline copy.
2018	*/
2019
2020	rfa->rfa_status = 0;
2021	rfa->rfa_control = FXP_RFA_CONTROL_EL;
2022	rfa->actual_size = 0;
2023
2024	v = -1;
2025	fxp_lwcopy(&v, (volatile u_int32_t*) rfa->link_addr);
2026	fxp_lwcopy(&v, (volatile u_int32_t*) rfa->rbd_addr);
2027
2028	/*
2029	* If there are other buffers already on the list, attach this
2030	* one to the end by fixing up the tail to point to this one.
2031	*/
2032	if (sc->rfa_headm != NULL) {
2033	p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf +
2034	RFA_ALIGNMENT_FUDGE);
2035	sc->rfa_tailm->m_next = m;
2036	v = vtophys(rfa);
2037	fxp_lwcopy(&v, (volatile u_int32_t*) p_rfa->link_addr);
2038	p_rfa->rfa_control = 0;
2039	} else {
2040	sc->rfa_headm = m;
2041	}
2042	sc->rfa_tailm = m;
2043
2044	return (m == oldm);
2045	}
2046
2047	#ifdef NOTUSED
2048	static volatile int
2049	fxp_miibus_readreg(device_t dev, int phy, int reg)
2050	{
2051	struct fxp_softc *sc = device_get_softc(dev);
2052	int count = 10000;
2053	int value;
2054
2055	CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2056	(FXP_MDI_READ << 26) \| (reg << 16) \| (phy << 21));
2057
2058	while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2059	&& count--)
2060	DELAY(10);
2061
2062	if (count <= 0)
2063	device_printf(dev, "fxp_miibus_readreg: timed out\n");
2064
2065	return (value & 0xffff);
2066	}
2067
2068	static void
2069	fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2070	{
2071	struct fxp_softc *sc = device_get_softc(dev);
2072	int count = 10000;
2073
2074	CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2075	(FXP_MDI_WRITE << 26) \| (reg << 16) \| (phy << 21) \|
2076	(value & 0xffff));
2077
2078	while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2079	count--)
2080	DELAY(10);
2081
2082	if (count <= 0)
2083	device_printf(dev, "fxp_miibus_writereg: timed out\n");
2084	}
2085	#endif
2086
2087	static int
2088	fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2089	{
2090	struct fxp_softc *sc = ifp->if_softc;
2091	#ifdef NOTUSED
2092	struct ifreq ifr = (struct ifreq )data;
2093	struct mii_data *mii;
2094	#endif
2095	int s, error = 0;
2096
2097	DBGLVL_PRINTK(2,"fxp_ioctl called\n");
2098
2099	s = splimp();
2100
2101	switch (command) {
2102	case SIOCSIFADDR:
2103	case SIOCGIFADDR:
2104	case SIOCSIFMTU:
2105	error = ether_ioctl(ifp, command, data);
2106	break;
2107
2108	case SIOCSIFFLAGS:
2109	if (ifp->if_flags & IFF_ALLMULTI)
2110	sc->flags \|= FXP_FLAG_ALL_MCAST;
2111	else
2112	sc->flags &= ~FXP_FLAG_ALL_MCAST;
2113
2114	/*
2115	* If interface is marked up and not running, then start it.
2116	* If it is marked down and running, stop it.
2117	* XXX If it's up then re-initialize it. This is so flags
2118	* such as IFF_PROMISC are handled.
2119	*/
2120	if (ifp->if_flags & IFF_UP) {
2121	fxp_init(sc);
2122	} else {
2123	if (ifp->if_flags & IFF_RUNNING)
2124	fxp_stop(sc);
2125	}
2126	break;
2127
2128	case SIOCADDMULTI:
2129	case SIOCDELMULTI:
2130	if (ifp->if_flags & IFF_ALLMULTI)
2131	sc->flags \|= FXP_FLAG_ALL_MCAST;
2132	else
2133	sc->flags &= ~FXP_FLAG_ALL_MCAST;
2134	/*
2135	* Multicast list has changed; set the hardware filter
2136	* accordingly.
2137	*/
2138	if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
2139	fxp_mc_setup(sc);
2140	/*
2141	* fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
2142	* again rather than else {}.
2143	*/
2144	if (sc->flags & FXP_FLAG_ALL_MCAST)
2145	fxp_init(sc);
2146	error = 0;
2147	break;
2148
2149	#ifdef NOTUSED
2150	case SIOCSIFMEDIA:
2151	case SIOCGIFMEDIA:
2152	if (sc->miibus != NULL) {
2153	mii = device_get_softc(sc->miibus);
2154	error = ifmedia_ioctl(ifp, ifr,
2155	&mii->mii_media, command);
2156	} else {
2157	error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2158	}
2159	break;
2160	#endif
2161
2162	case SIO_RTEMS_SHOW_STATS:
2163	fxp_stats(sc);
2164	break;
2165
2166	default:
2167	error = EINVAL;
2168	}
2169	splx(s);
2170	return (error);
2171	}
2172
2173	/*
2174	* Program the multicast filter.
2175	*
2176	* We have an artificial restriction that the multicast setup command
2177	* must be the first command in the chain, so we take steps to ensure
2178	* this. By requiring this, it allows us to keep up the performance of
2179	* the pre-initialized command ring (esp. link pointers) by not actually
2180	* inserting the mcsetup command in the ring - i.e. its link pointer
2181	* points to the TxCB ring, but the mcsetup descriptor itself is not part
2182	* of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2183	* lead into the regular TxCB ring when it completes.
2184	*
2185	* This function must be called at splimp.
2186	*/
2187	static void
2188	fxp_mc_setup(struct fxp_softc *sc)
2189	{
2190	struct fxp_cb_mcs *mcsp = sc->mcsp;
2191	struct ifnet *ifp = &sc->sc_if;
2192	#ifdef NOTUSED
2193	struct ifmultiaddr *ifma;
2194	#endif
2195	int nmcasts;
2196	int count;
2197
2198	DBGLVL_PRINTK(2,"fxp_mc_setup called\n");
2199
2200	/*
2201	* If there are queued commands, we must wait until they are all
2202	* completed. If we are already waiting, then add a NOP command
2203	* with interrupt option so that we're notified when all commands
2204	* have been completed - fxp_start() ensures that no additional
2205	* TX commands will be added when need_mcsetup is true.
2206	*/
2207	if (sc->tx_queued) {
2208	struct fxp_cb_tx *txp;
2209
2210	/*
2211	* need_mcsetup will be true if we are already waiting for the
2212	* NOP command to be completed (see below). In this case, bail.
2213	*/
2214	if (sc->need_mcsetup)
2215	return;
2216	sc->need_mcsetup = 1;
2217
2218	/*
2219	* Add a NOP command with interrupt so that we are notified when all
2220	* TX commands have been processed.
2221	*/
2222	txp = sc->cbl_last->next;
2223	txp->mb_head = NULL;
2224	txp->cb_status = 0;
2225	txp->cb_command = FXP_CB_COMMAND_NOP \|
2226	FXP_CB_COMMAND_S \| FXP_CB_COMMAND_I;
2227	/*
2228	* Advance the end of list forward.
2229	*/
2230	sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
2231	sc->cbl_last = txp;
2232	sc->tx_queued++;
2233	/*
2234	* Issue a resume in case the CU has just suspended.
2235	*/
2236	fxp_scb_wait(sc);
2237	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2238	/*
2239	* Set a 5 second timer just in case we don't hear from the
2240	* card again.
2241	*/
2242	ifp->if_timer = 5;
2243
2244	return;
2245	}
2246	sc->need_mcsetup = 0;
2247
2248	/*
2249	* Initialize multicast setup descriptor.
2250	*/
2251	mcsp->next = sc->cbl_base;
2252	mcsp->mb_head = NULL;
2253	mcsp->cb_status = 0;
2254	mcsp->cb_command = FXP_CB_COMMAND_MCAS \|
2255	FXP_CB_COMMAND_S \| FXP_CB_COMMAND_I;
2256	mcsp->link_addr = vtophys(&sc->cbl_base->cb_status);
2257
2258	nmcasts = 0;
2259	#ifdef NOTUSED /* FIXME: Multicast not supported? */
2260	if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
2261	#if __FreeBSD_version < 500000
2262	LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2263	#else
2264	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2265	#endif
2266	if (ifma->ifma_addr->sa_family != AF_LINK)
2267	continue;
2268	if (nmcasts >= MAXMCADDR) {
2269	sc->flags \|= FXP_FLAG_ALL_MCAST;
2270	nmcasts = 0;
2271	break;
2272	}
2273	memcpy((void )(uintptr_t)(volatile void )
2274	&sc->mcsp->mc_addr[nmcasts][0],
2275	LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 6);
2276	nmcasts++;
2277	}
2278	}
2279	#endif
2280	mcsp->mc_cnt = nmcasts * 6;
2281	sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp;
2282	sc->tx_queued = 1;
2283
2284	/*
2285	* Wait until command unit is not active. This should never
2286	* be the case when nothing is queued, but make sure anyway.
2287	*/
2288	count = 100;
2289	while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2290	FXP_SCB_CUS_ACTIVE && --count)
2291	DELAY(10);
2292	if (count == 0) {
2293	device_printf(sc->dev, "command queue timeout\n");
2294	return;
2295	}
2296
2297	/*
2298	* Start the multicast setup command.
2299	*/
2300	fxp_scb_wait(sc);
2301	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
2302	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2303
2304	ifp->if_timer = 2;
2305	return;
2306	}
2307
2308	#endif /* defined(__i386__) */

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