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source: rtems/c/src/libchip/network/if_fxp.c @ a4ce29f

4.104.114.84.95

Last change on this file since a4ce29f was a4ce29f, checked in by Jennifer Averett <Jennifer.Averett@…>, on 05/17/05 at 15:15:07

2005-05-17 Jennifer Averett <jennifer.averett@…>

ChangeLog?, libchip/network/if_fxp.c, libchip/serial/ns16550.c: Modified to use rtems/irq.h.

Property mode set to 100644

File size: 61.7 KB

Line
1	/*-
2	* Copyright (c) 1995, David Greenman
3	* Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
4	* All rights reserved.
5	*
6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions
8	* are met:
9	* 1. Redistributions of source code must retain the above copyright
10	* notice unmodified, this list of conditions, and the following
11	* disclaimer.
12	* 2. Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	*
16	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26	* SUCH DAMAGE.
27	*
28	* $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.118 2001/09/05 23:33:58 brooks Exp $
29	*/
30
31	/*
32	* Intel EtherExpress Pro/100B PCI Fast Ethernet driver
33	*/
34
35	/*
36	* RTEMS Revision Preliminary History
37	*
38	* July XXX, 2002 W. Eric Norum <eric.norum@usask.ca>
39	* Placed in RTEMS CVS repository. All further modifications will be
40	* noted in the CVS log and not in this comment.
41	*
42	* July 11, 2002 W. Eric Norum <eric.norum@usask.ca>
43	* Minor modifications to get driver working with NIC on VersaLogic
44	* Bobcat PC-104 single-board computer. The Bobcat has no video
45	* driver so printf/printk calls are directed to COM2:. This
46	* arrangement seems to require delays after the printk calls or
47	* else things lock up. Perhaps the RTEMS pc386 console code
48	* should be modified to insert these delays itself.
49	*
50	* June 27, 2002 W. Eric Norum <eric.norum@usask.ca>
51	* Obtained from Thomas Doerfler <Thomas.Doerfler@imd-systems.de>.
52	* A big thank-you to Thomas for making this available.
53	*
54	* October 01, 2001 Thomas Doerfler <Thomas.Doerfler@imd-systems.de>
55	* Original RTEMS modifications.
56	*/
57
58	#if defined(__i386__)
59
60	/#define DEBUG_OUT 0/
61
62	#include <rtems.h>
63	#include <rtems/error.h>
64	#include <rtems/rtems_bsdnet.h>
65	#include <bsp.h>
66
67	#include <sys/errno.h>
68	#include <sys/param.h>
69	#include <sys/mbuf.h>
70	#include <sys/socket.h>
71	#include <sys/sockio.h>
72	#include <net/if.h>
73	#include <netinet/in.h>
74	#include <netinet/if_ether.h>
75	#include <sys/malloc.h>
76	#include <sys/systm.h>
77	#include <bsp.h>
78	#include <pcibios.h>
79	#include <bsp/irq.h>
80	#include <rtems/pci.h>
81
82	#ifdef NS
83	#include <netns/ns.h>
84	#include <netns/ns_if.h>
85	#endif
86
87	#include <net/bpf.h>
88
89	#include <vm/vm.h> /* for vtophys */
90
91	#include <net/if_types.h>
92
93	#include "if_fxpreg.h"
94	#include "if_fxpvar.h"
95
96	/*
97	* some adaptation replacements for RTEMS
98	*/
99	static rtems_interval fxp_ticksPerSecond;
100	#define device_printf(device,format,args...) printk(format,## args)
101	#define DELAY(n) rtems_task_wake_after(((n)*fxp_ticksPerSecond/1000000)+1)
102	#ifdef DEBUG_OUT
103	#define DBGLVL_PRINTK(LVL,format, args...) \
104	if (DEBUG_OUT >= (LVL)) { \
105	printk(format, ## args); \
106	}
107	#else
108	#define DBGLVL_PRINTK(LVL,format, args...)
109	#endif
110
111	/*
112	* RTEMS event used by interrupt handler to signal driver tasks.
113	* This must not be any of the events used by the network task synchronization.
114	*/
115	#define INTERRUPT_EVENT RTEMS_EVENT_1
116
117	/*
118	* remapping between PCI device and CPU memmory address view...
119	*/
120	#if defined(__i386)
121	#define vtophys(p) (u_int32_t)(p)
122	#else
123	#define vtophys(p) vtophys(p)
124	#endif
125
126	#define NFXPDRIVER 1
127	static struct fxp_softc fxp_softc[NFXPDRIVER];
128	static int fxp_is_verbose = TRUE;
129	/*
130	* NOTE! On the Alpha, we have an alignment constraint. The
131	* card DMAs the packet immediately following the RFA. However,
132	* the first thing in the packet is a 14-byte Ethernet header.
133	* This means that the packet is misaligned. To compensate,
134	* we actually offset the RFA 2 bytes into the cluster. This
135	* alignes the packet after the Ethernet header at a 32-bit
136	* boundary. HOWEVER! This means that the RFA is misaligned!
137	*/
138	#define RFA_ALIGNMENT_FUDGE 2
139
140	/*
141	* Set initial transmit threshold at 64 (512 bytes). This is
142	* increased by 64 (512 bytes) at a time, to maximum of 192
143	* (1536 bytes), if an underrun occurs.
144	*/
145	static int tx_threshold = 64;
146
147	/*
148	* The configuration byte map has several undefined fields which
149	* must be one or must be zero. Set up a template for these bits
150	* only, (assuming a 82557 chip) leaving the actual configuration
151	* to fxp_init.
152	*
153	* See struct fxp_cb_config for the bit definitions.
154	*/
155	static u_char fxp_cb_config_template[] = {
156	0x0, 0x0, /* cb_status */
157	0x0, 0x0, /* cb_command */
158	0x0, 0x0, 0x0, 0x0, /* link_addr */
159	0x0, /* 0 */
160	0x0, /* 1 */
161	0x0, /* 2 */
162	0x0, /* 3 */
163	0x0, /* 4 */
164	0x0, /* 5 */
165	0x32, /* 6 */
166	0x0, /* 7 */
167	0x0, /* 8 */
168	0x0, /* 9 */
169	0x6, /* 10 */
170	0x0, /* 11 */
171	0x0, /* 12 */
172	0x0, /* 13 */
173	0xf2, /* 14 */
174	0x48, /* 15 */
175	0x0, /* 16 */
176	0x40, /* 17 */
177	0xf0, /* 18 */
178	0x0, /* 19 */
179	0x3f, /* 20 */
180	0x5 /* 21 */
181	};
182
183	struct fxp_ident {
184	u_int16_t devid;
185	char *name;
186	int warn;
187	};
188
189	#define UNTESTED 1
190
191	/*
192	* Claim various Intel PCI device identifiers for this driver. The
193	* sub-vendor and sub-device field are extensively used to identify
194	* particular variants, but we don't currently differentiate between
195	* them.
196	*/
197	static struct fxp_ident fxp_ident_table[] = {
198	{ 0x1229, "Intel Pro 10/100B/100+ Ethernet", UNTESTED },
199	{ 0x2449, "Intel Pro/100 Ethernet", UNTESTED },
200	{ 0x1209, "Intel Embedded 10/100 Ethernet", 0 },
201	{ 0x1029, "Intel Pro/100 Ethernet", UNTESTED },
202	{ 0x1030, "Intel Pro/100 Ethernet", 0 },
203	{ 0x1031, "Intel Pro/100 Ethernet", UNTESTED },
204	{ 0x1032, "Intel Pro/100 Ethernet", UNTESTED },
205	{ 0x1033, "Intel Pro/100 Ethernet", UNTESTED },
206	{ 0x1034, "Intel Pro/100 Ethernet", UNTESTED },
207	{ 0x1035, "Intel Pro/100 Ethernet", UNTESTED },
208	{ 0x1036, "Intel Pro/100 Ethernet", UNTESTED },
209	{ 0x1037, "Intel Pro/100 Ethernet", UNTESTED },
210	{ 0x1038, "Intel Pro/100 Ethernet", UNTESTED },
211	{ 0x103B, "Intel Pro/100 Ethernet (82801BD PRO/100 VM (LOM))", 0 },
212	{ 0, NULL },
213	};
214
215	#if 0
216	static int fxp_probe(device_t dev);
217	static int fxp_attach(device_t dev);
218	static int fxp_detach(device_t dev);
219	static int fxp_shutdown(device_t dev);
220	#endif
221	int fxp_output (struct ifnet *,
222	struct mbuf , struct sockaddr , struct rtentry *);
223
224
225	static rtems_isr fxp_intr(rtems_vector_number v);
226	static void fxp_init(void *xsc);
227	static void fxp_tick(void *xsc);
228	static void fxp_start(struct ifnet *ifp);
229	static void fxp_stop(struct fxp_softc *sc);
230	static void fxp_release(struct fxp_softc *sc);
231	static int fxp_ioctl(struct ifnet *ifp, u_long command,
232	caddr_t data);
233	static void fxp_watchdog(struct ifnet *ifp);
234	static int fxp_add_rfabuf(struct fxp_softc sc, struct mbuf oldm);
235	static void fxp_mc_setup(struct fxp_softc *sc);
236	static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
237	int autosize);
238	static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
239	u_int16_t data);
240	static void fxp_autosize_eeprom(struct fxp_softc *sc);
241	static void fxp_read_eeprom(struct fxp_softc sc, u_short data,
242	int offset, int words);
243	static void fxp_write_eeprom(struct fxp_softc sc, u_short data,
244	int offset, int words);
245	#ifdef NOTUSED
246	static int fxp_ifmedia_upd(struct ifnet *ifp);
247	static void fxp_ifmedia_sts(struct ifnet *ifp,
248	struct ifmediareq *ifmr);
249	static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
250	static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
251	struct ifmediareq *ifmr);
252	static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg);
253	static void fxp_miibus_writereg(device_t dev, int phy, int reg,
254	int value);
255	#endif
256	static __inline void fxp_lwcopy(volatile u_int32_t *src,
257	volatile u_int32_t *dst);
258	static __inline void fxp_scb_wait(struct fxp_softc *sc);
259	static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
260	static __inline void fxp_dma_wait(volatile u_int16_t *status,
261	struct fxp_softc *sc);
262
263	/*
264	* Inline function to copy a 16-bit aligned 32-bit quantity.
265	*/
266	static __inline void
267	fxp_lwcopy(volatile u_int32_t src, volatile u_int32_t dst)
268	{
269	#ifdef __i386__
270	dst = src;
271	#else
272	volatile u_int16_t a = (volatile u_int16_t)src;
273	volatile u_int16_t b = (volatile u_int16_t)dst;
274
275	b[0] = a[0];
276	b[1] = a[1];
277	#endif
278	}
279
280	/*
281	* inline access functions to pci space registers
282	*/
283	static __inline u_int8_t fxp_csr_read_1(struct fxp_softc *sc,int reg) {
284	u_int8_t val;
285	if (sc->pci_regs_are_io) {
286	inport_byte(sc->pci_regs_base + reg,val);
287	}
288	else {
289	val = (u_int8_t)(sc->pci_regs_base+reg);
290	}
291	return val;
292	}
293	static __inline u_int32_t fxp_csr_read_2(struct fxp_softc *sc,int reg) {
294	u_int16_t val;
295	if (sc->pci_regs_are_io) {
296	inport_word(sc->pci_regs_base + reg,val);
297	}
298	else {
299	val = (u_int16_t)(sc->pci_regs_base+reg);
300	}
301	return val;
302	}
303	static __inline u_int32_t fxp_csr_read_4(struct fxp_softc *sc,int reg) {
304	u_int32_t val;
305	if (sc->pci_regs_are_io) {
306	inport_long(sc->pci_regs_base + reg,val);
307	}
308	else {
309	val = (u_int32_t)(sc->pci_regs_base+reg);
310	}
311	return val;
312	}
313
314	/*
315	* Wait for the previous command to be accepted (but not necessarily
316	* completed).
317	*/
318	static __inline void
319	fxp_scb_wait(struct fxp_softc *sc)
320	{
321	int i = 10000;
322
323	while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
324	DELAY(2);
325	if (i == 0)
326	device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
327	CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
328	CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
329	CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS),
330	CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
331	}
332
333	static __inline void
334	fxp_scb_cmd(struct fxp_softc *sc, int cmd)
335	{
336
337	if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
338	CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
339	fxp_scb_wait(sc);
340	}
341	CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
342	}
343
344	static __inline void
345	fxp_dma_wait(volatile u_int16_t status, struct fxp_softc sc)
346	{
347	int i = 10000;
348
349	while (!(*status & FXP_CB_STATUS_C) && --i)
350	DELAY(2);
351	if (i == 0)
352	device_printf(sc->dev, "DMA timeout\n");
353	}
354
355	static __inline unsigned int pci_get_vendor(struct fxp_softc *sc) {
356	u_int16_t vendor;
357	pcib_conf_read16(sc->pci_signature,0,&vendor);
358	return vendor;
359	}
360
361	static __inline unsigned int pci_get_device(struct fxp_softc *sc) {
362	u_int16_t device;
363	pcib_conf_read16(sc->pci_signature,2,&device);
364	return device;
365	}
366
367	static __inline unsigned int pci_get_subvendor(struct fxp_softc *sc) {
368	u_int16_t subvendor;
369	pcib_conf_read16(sc->pci_signature,0x2c,&subvendor);
370	return subvendor;
371	}
372
373	static __inline unsigned int pci_get_subdevice(struct fxp_softc *sc) {
374	u_int16_t subdevice;
375	pcib_conf_read16(sc->pci_signature,0x2e,&subdevice);
376	return subdevice;
377	}
378
379	static __inline unsigned int pci_get_revid(struct fxp_softc *sc) {
380	u_int8_t revid;
381	pcib_conf_read8(sc->pci_signature,0x08,&revid);
382	return revid;
383	}
384
385	static void nopOn(const rtems_irq_connect_data* notUsed)
386	{
387	/*
388	* code should be moved from fxp_Enet_initialize_hardware
389	* to this location
390	*/
391	}
392
393	static int fxpIsOn(const rtems_irq_connect_data* irq)
394	{
395	return BSP_irq_enabled_at_i8259s (irq->name);
396	}
397
398	int
399	rtems_fxp_attach(struct rtems_bsdnet_ifconfig *config, int attaching)
400	{
401	int error = 0;
402	struct fxp_softc *sc;
403	struct ifnet *ifp;
404	u_int16_t val16;
405	u_int32_t val32;
406	u_int16_t data;
407	int i;
408	int s;
409	int unitNumber;
410	char *unitName;
411	u_int16_t dev_id;
412	u_int8_t interrupt;
413	int mtu;
414
415	/*
416	* Set up some timing values
417	*/
418	rtems_clock_get(RTEMS_CLOCK_GET_TICKS_PER_SECOND, &fxp_ticksPerSecond);
419	DBGLVL_PRINTK(1,"fxp_attach called\n");
420
421	/*
422	* Parse driver name
423	*/
424	if ((unitNumber = rtems_bsdnet_parse_driver_name (config, &unitName)) < 0)
425	return 0;
426
427	/*
428	* Is driver free?
429	*/
430	if ((unitNumber <= 0) \|\| (unitNumber > NFXPDRIVER)) {
431	device_printf(dev,"Bad FXP unit number.\n");
432	return 0;
433	}
434	sc = &fxp_softc[unitNumber - 1];
435	ifp = &sc->arpcom.ac_if;
436	if (ifp->if_softc != NULL) {
437	device_printf(dev,"FXP Driver already in use.\n");
438	return 0;
439	}
440
441	memset(sc, 0, sizeof(*sc));
442	#ifdef NOTUSED
443	sc->dev = dev;
444	callout_handle_init(&sc->stat_ch);
445	mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF \| MTX_RECURSE);
446	#endif
447	s = splimp();
448
449	/*
450	* init PCI Bios interface...
451	*/
452	i = pci_initialize();
453	DBGLVL_PRINTK(2,"fxp_attach: pcib_init returned %d\n",i);
454	if (i != PCIB_ERR_SUCCESS) {
455	device_printf(dev, "could not initialize pci bios interface\n");
456	return 0;
457	}
458
459	/*
460	* find device on pci bus
461	*/
462	{ int j; int pbus, pdev, pfun;
463
464	for (j=0; fxp_ident_table[j].devid; j++ ) {
465	i = pci_find_device( 0x8086, fxp_ident_table[j].devid,
466	unitNumber-1, &pbus, &pdev, &pfun );
467	sc->pci_signature = PCIB_DEVSIG_MAKE( pbus, pdev, pfun );
468	DBGLVL_PRINTK(2,"fxp_attach: find_devid returned %d "
469	"and pci signature 0x%x\n",
470	i,sc->pci_signature);
471	if (PCIB_ERR_SUCCESS == i) {
472	if ( UNTESTED == fxp_ident_table[j].warn ) {
473	device_printf(dev,
474	"WARNING: this chip version has NOT been reported to work under RTEMS yet.\n");
475	device_printf(dev,
476	" If it works OK, report it as tested in 'c/src/libchip/network/if_fxp.c'\n");
477	}
478	break;
479	}
480	}
481	}
482
483	/*
484	* FIXME: add search for more device types...
485	*/
486	if (i != PCIB_ERR_SUCCESS) {
487	device_printf(dev, "could not find 82559ER device\n");
488	return 0;
489	}
490
491
492	/*
493	* Enable bus mastering. Enable memory space too, in case
494	* BIOS/Prom forgot about it.
495	*/
496	pcib_conf_read16(sc->pci_signature, PCI_COMMAND,&val16);
497	val16 \|= (PCI_COMMAND_MEMORY\|PCI_COMMAND_MASTER);
498	pcib_conf_write16(sc->pci_signature, PCI_COMMAND, val16);
499	DBGLVL_PRINTK(3,"fxp_attach: PCI_COMMAND_write = 0x%x\n",val16);
500	pcib_conf_read16(sc->pci_signature, PCI_COMMAND,&val16);
501	DBGLVL_PRINTK(4,"fxp_attach: PCI_COMMAND_read = 0x%x\n",val16);
502
503	/*
504	* Figure out which we should try first - memory mapping or i/o mapping?
505	* We default to memory mapping. Then we accept an override from the
506	* command line. Then we check to see which one is enabled.
507	*/
508	#ifdef NOTUSED
509	m1 = PCI_COMMAND_MEMORY;
510	m2 = PCI_COMMAND_IO;
511	prefer_iomap = 0;
512	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
513	"prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) {
514	m1 = PCI_COMMAND_IO;
515	m2 = PCI_COMMAND_MEMORY;
516	}
517
518	if (val & m1) {
519	sc->rtp = ((m1 == PCI_COMMAND_MEMORY)
520	? SYS_RES_MEMORY : SYS_RES_IOPORT);
521	sc->rgd = ((m1 == PCI_COMMAND_MEMORY)
522	? FXP_PCI_MMBA : FXP_PCI_IOBA);
523	sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
524	0, ~0, 1, RF_ACTIVE);
525	}
526	if (sc->mem == NULL && (val & m2)) {
527	sc->rtp = ((m2 == PCI_COMMAND_MEMORY)
528	? SYS_RES_MEMORY : SYS_RES_IOPORT);
529	sc->rgd = ((m2 == PCI_COMMAND_MEMORY)
530	? FXP_PCI_MMBA : FXP_PCI_IOBA);
531	sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
532	0, ~0, 1, RF_ACTIVE);
533	}
534
535	if (!sc->mem) {
536	device_printf(dev, "could not map device registers\n");
537	error = ENXIO;
538	goto fail;
539	}
540	if (fxp_is_verbose) {
541	device_printf(dev, "using %s space register mapping\n",
542	sc->rtp == SYS_RES_MEMORY? "memory" : "I/O");
543	}
544
545	sc->sc_st = rman_get_bustag(sc->mem);
546	sc->sc_sh = rman_get_bushandle(sc->mem);
547
548	/*
549	* Allocate our interrupt.
550	*/
551	rid = 0;
552	sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
553	RF_SHAREABLE \| RF_ACTIVE);
554	if (sc->irq == NULL) {
555	device_printf(dev, "could not map interrupt\n");
556	error = ENXIO;
557	goto fail;
558	}
559
560	error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
561	fxp_intr, sc, &sc->ih);
562	if (error) {
563	device_printf(dev, "could not setup irq\n");
564	goto fail;
565	}
566	#endif
567
568	/*
569	* get mapping and base address of registers
570	*/
571	pcib_conf_read16(sc->pci_signature, PCI_COMMAND,&val16);
572	DBGLVL_PRINTK(4,"fxp_attach: PCI_COMMAND_read = 0x%x\n",val16);
573	if((val16 & PCI_COMMAND_IO) != 0) {
574	sc->pci_regs_are_io = TRUE;
575	pcib_conf_read32(sc->pci_signature,
576	PCI_BASE_ADDRESS_1,
577	&val32);
578	sc->pci_regs_base = val32 & PCI_BASE_ADDRESS_IO_MASK;
579	}
580	else {
581	sc->pci_regs_are_io = FALSE;
582	pcib_conf_read32(sc->pci_signature,
583	PCI_BASE_ADDRESS_0,
584	&val32);
585	sc->pci_regs_base = val32 & PCI_BASE_ADDRESS_MEM_MASK;
586	}
587	DBGLVL_PRINTK(3,"fxp_attach: CSR registers are mapped in %s space"
588	" at address 0x%x\n",
589	sc->pci_regs_are_io ? "I/O" : "MEM",
590	sc->pci_regs_base);
591
592	/*
593	* get interrupt level to be used
594	*/
595	pcib_conf_read8(sc->pci_signature, 60, &interrupt);
596	DBGLVL_PRINTK(3,"fxp_attach: interrupt = 0x%x\n",interrupt);
597	sc->irqInfo.name = (rtems_irq_number)interrupt;
598	/*
599	* Set up interrupts
600	*/
601	sc->irqInfo.hdl = (rtems_irq_hdl)fxp_intr;
602	sc->irqInfo.on = nopOn;
603	sc->irqInfo.off = nopOn;
604	sc->irqInfo.isOn = fxpIsOn;
605	s = BSP_install_rtems_irq_handler (&sc->irqInfo);
606	if (!s)
607	rtems_panic ("Can't attach fxp interrupt handler for irq %d\n",
608	sc->irqInfo.name);
609	/*
610	* Reset to a stable state.
611	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
612	*/
613	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
614	DELAY(10);
615
616	sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB,
617	M_DEVBUF, M_NOWAIT);
618	DBGLVL_PRINTK(3,"fxp_attach: sc->cbl_base = 0x%x\n",sc->cbl_base);
619	if (sc->cbl_base == NULL)
620	goto failmem;
621	else
622	memset(sc->cbl_base, 0, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
623
624	sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF,
625	M_NOWAIT);
626	DBGLVL_PRINTK(3,"fxp_attach: sc->fxp_stats = 0x%x\n",sc->fxp_stats);
627	if (sc->fxp_stats == NULL)
628	goto failmem;
629	else
630	memset(sc->fxp_stats, 0, sizeof(struct fxp_stats));
631
632	sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT);
633	DBGLVL_PRINTK(3,"fxp_attach: sc->mcsp = 0x%x\n",sc->mcsp);
634	if (sc->mcsp == NULL)
635	goto failmem;
636
637	/*
638	* Pre-allocate our receive buffers.
639	*/
640	for (i = 0; i < FXP_NRFABUFS; i++) {
641	if (fxp_add_rfabuf(sc, NULL) != 0) {
642	goto failmem;
643	}
644	}
645
646	/*
647	* Find out how large of an SEEPROM we have.
648	*/
649	DBGLVL_PRINTK(3,"fxp_attach: calling fxp_autosize_eeprom\n");
650	fxp_autosize_eeprom(sc);
651
652	/*
653	* Determine whether we must use the 503 serial interface.
654	*/
655	fxp_read_eeprom(sc, &data, 6, 1);
656	if ((data & FXP_PHY_DEVICE_MASK) != 0 &&
657	(data & FXP_PHY_SERIAL_ONLY))
658	sc->flags \|= FXP_FLAG_SERIAL_MEDIA;
659
660	/*
661	* Find out the basic controller type; we currently only
662	* differentiate between a 82557 and greater.
663	*/
664	fxp_read_eeprom(sc, &data, 5, 1);
665	if ((data >> 8) == 1)
666	sc->chip = FXP_CHIP_82557;
667	DBGLVL_PRINTK(3,"fxp_attach: sc->chip = %d\n",sc->chip);
668
669	/*
670	* Enable workarounds for certain chip revision deficiencies.
671	*
672	* Systems based on the ICH2/ICH2-M chip from Intel have a defect
673	* where the chip can cause a PCI protocol violation if it receives
674	* a CU_RESUME command when it is entering the IDLE state. The
675	* workaround is to disable Dynamic Standby Mode, so the chip never
676	* deasserts CLKRUN#, and always remains in an active state.
677	*
678	* See Intel 82801BA/82801BAM Specification Update, Errata #30.
679	*/
680	#ifdef NOTUSED
681	i = pci_get_device(dev);
682	#else
683	pcib_conf_read16(sc->pci_signature,2,&dev_id);
684	DBGLVL_PRINTK(3,"fxp_attach: device id = 0x%x\n",dev_id);
685	#endif
686	if (dev_id == 0x2449 \|\| (dev_id > 0x1030 && dev_id < 0x1039)) {
687	device_printf(dev, "* See Intel 82801BA/82801BAM Specification Update, Errata #30. *\n");
688	fxp_read_eeprom(sc, &data, 10, 1);
689	if (data & 0x02) { /* STB enable */
690	u_int16_t cksum;
691	int i;
692
693	device_printf(dev,
694	"* DISABLING DYNAMIC STANDBY MODE IN EEPROM *\n");
695	data &= ~0x02;
696	fxp_write_eeprom(sc, &data, 10, 1);
697	device_printf(dev, "New EEPROM ID: 0x%x\n", data);
698	cksum = 0;
699	for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
700	fxp_read_eeprom(sc, &data, i, 1);
701	cksum += data;
702	}
703	i = (1 << sc->eeprom_size) - 1;
704	cksum = 0xBABA - cksum;
705	fxp_read_eeprom(sc, &data, i, 1);
706	fxp_write_eeprom(sc, &cksum, i, 1);
707	device_printf(dev,
708	"EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
709	i, data, cksum);
710	/*
711	* We need to do a full PCI reset here. A software
712	* reset to the port doesn't cut it, but let's try
713	* anyway.
714	*/
715	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
716	DELAY(50);
717	device_printf(dev,
718	"* PLEASE REBOOT THE SYSTEM NOW FOR CORRECT OPERATION *\n");
719	#if 1
720	/*
721	* If the user elects to continue, try the software
722	* workaround, as it is better than nothing.
723	*/
724	sc->flags \|= FXP_FLAG_CU_RESUME_BUG;
725	#endif
726	}
727	}
728
729	/*
730	* If we are not a 82557 chip, we can enable extended features.
731	*/
732	if (sc->chip != FXP_CHIP_82557) {
733	u_int8_t tmp_val;
734	/*
735	* If MWI is enabled in the PCI configuration, and there
736	* is a valid cacheline size (8 or 16 dwords), then tell
737	* the board to turn on MWI.
738	*/
739	pcib_conf_read8(sc->pci_signature,
740	PCI_CACHE_LINE_SIZE,&tmp_val);
741	DBGLVL_PRINTK(3,"fxp_attach: CACHE_LINE_SIZE = %d\n",tmp_val);
742	if (val16 & PCI_COMMAND_MEMORY &&
743	tmp_val != 0)
744	sc->flags \|= FXP_FLAG_MWI_ENABLE;
745
746	/* turn on the extended TxCB feature */
747	sc->flags \|= FXP_FLAG_EXT_TXCB;
748
749	/* enable reception of long frames for VLAN */
750	sc->flags \|= FXP_FLAG_LONG_PKT_EN;
751	DBGLVL_PRINTK(3,"fxp_attach: sc->flags = 0x%x\n",
752	sc->flags);
753	}
754
755	/*
756	* Read MAC address.
757	*/
758	fxp_read_eeprom(sc, (u_int16_t*)sc->arpcom.ac_enaddr, 0, 3);
759	if (fxp_is_verbose) {
760	device_printf(dev, "Ethernet address %x:%x:%x:%x:%x:%x %s \n",
761	((u_int8_t*)sc->arpcom.ac_enaddr)[0],
762	((u_int8_t*)sc->arpcom.ac_enaddr)[1],
763	((u_int8_t*)sc->arpcom.ac_enaddr)[2],
764	((u_int8_t*)sc->arpcom.ac_enaddr)[3],
765	((u_int8_t*)sc->arpcom.ac_enaddr)[4],
766	((u_int8_t*)sc->arpcom.ac_enaddr)[5],
767	sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : "");
768	device_printf(dev, "PCI IDs: 0x%x 0x%x 0x%x 0x%x 0x%x\n",
769	pci_get_vendor(sc), pci_get_device(sc),
770	pci_get_subvendor(sc), pci_get_subdevice(sc),
771	pci_get_revid(sc));
772	device_printf(dev, "Chip Type: %d\n", sc->chip);
773	}
774
775	#ifdef NOTUSED /* do not set up interface at all... */
776	/*
777	* If this is only a 10Mbps device, then there is no MII, and
778	* the PHY will use a serial interface instead.
779	*
780	* The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
781	* doesn't have a programming interface of any sort. The
782	* media is sensed automatically based on how the link partner
783	* is configured. This is, in essence, manual configuration.
784	*/
785	if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
786	ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
787	fxp_serial_ifmedia_sts);
788	ifmedia_add(&sc->sc_media, IFM_ETHER\|IFM_MANUAL, 0, NULL);
789	ifmedia_set(&sc->sc_media, IFM_ETHER\|IFM_MANUAL);
790	} else {
791	if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
792	fxp_ifmedia_sts)) {
793	device_printf(dev, "MII without any PHY!\n");
794	error = ENXIO;
795	goto fail;
796	}
797	}
798	#endif
799	if (config->mtu)
800	mtu = config->mtu;
801	else
802	mtu = ETHERMTU;
803
804	ifp->if_softc = sc;
805	ifp->if_unit = unitNumber;
806	ifp->if_name = unitName;
807	ifp->if_mtu = mtu;
808	ifp->if_baudrate = 100000000;
809	ifp->if_init = fxp_init;
810	ifp->if_ioctl = fxp_ioctl;
811	ifp->if_start = fxp_start;
812	ifp->if_output = ether_output;
813	ifp->if_watchdog = fxp_watchdog;
814	ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX /\| IFF_MULTICAST/;
815	if (ifp->if_snd.ifq_maxlen == 0)
816	ifp->if_snd.ifq_maxlen = ifqmaxlen;
817
818	/*
819	* Attach the interface.
820	*/
821	DBGLVL_PRINTK(3,"fxp_attach: calling if_attach\n");
822	if_attach (ifp);
823	DBGLVL_PRINTK(3,"fxp_attach: calling ether_if_attach\n");
824	ether_ifattach(ifp);
825	DBGLVL_PRINTK(3,"fxp_attach: return from ether_if_attach\n");
826
827	#ifdef NOTUSED
828	/*
829	* Tell the upper layer(s) we support long frames.
830	*/
831	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
832	#endif
833	/*
834	* Let the system queue as many packets as we have available
835	* TX descriptors.
836	*/
837	ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1;
838
839	splx(s);
840	return (0);
841
842	failmem:
843	device_printf(dev, "Failed to malloc memory\n");
844	error = ENOMEM;
845	#ifdef NOTUSED
846	fail:
847	#endif
848	splx(s);
849	fxp_release(sc);
850	return (error);
851	}
852
853	/*
854	* release all resources
855	*/
856	static void
857	fxp_release(struct fxp_softc *sc)
858	{
859
860	#ifdef NOTUSED
861	bus_generic_detach(sc->dev);
862	if (sc->miibus)
863	device_delete_child(sc->dev, sc->miibus);
864	#endif
865	if (sc->cbl_base)
866	free(sc->cbl_base, M_DEVBUF);
867	if (sc->fxp_stats)
868	free(sc->fxp_stats, M_DEVBUF);
869	if (sc->mcsp)
870	free(sc->mcsp, M_DEVBUF);
871	if (sc->rfa_headm)
872	m_freem(sc->rfa_headm);
873
874	#ifdef NOTUSED
875	if (sc->ih)
876	bus_teardown_intr(sc->dev, sc->irq, sc->ih);
877	if (sc->irq)
878	bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
879	if (sc->mem)
880	bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem);
881	mtx_destroy(&sc->sc_mtx);
882	#endif
883	}
884
885	#if NOTUSED
886	/*
887	* Detach interface.
888	*/
889	static int
890	fxp_detach(device_t dev)
891	{
892	struct fxp_softc *sc = device_get_softc(dev);
893	int s;
894
895	/* disable interrupts */
896	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
897
898	s = splimp();
899
900	/*
901	* Stop DMA and drop transmit queue.
902	*/
903	fxp_stop(sc);
904
905	/*
906	* Close down routes etc.
907	*/
908	ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED);
909
910	/*
911	* Free all media structures.
912	*/
913	ifmedia_removeall(&sc->sc_media);
914
915	splx(s);
916
917	/* Release our allocated resources. */
918	fxp_release(sc);
919
920	return (0);
921	}
922
923	/*
924	* Device shutdown routine. Called at system shutdown after sync. The
925	* main purpose of this routine is to shut off receiver DMA so that
926	* kernel memory doesn't get clobbered during warmboot.
927	*/
928	static int
929	fxp_shutdown(device_t dev)
930	{
931	/*
932	* Make sure that DMA is disabled prior to reboot. Not doing
933	* do could allow DMA to corrupt kernel memory during the
934	* reboot before the driver initializes.
935	*/
936	fxp_stop((struct fxp_softc *) device_get_softc(dev));
937	return (0);
938	}
939	#endif
940
941	/*
942	* Show interface statistics
943	*/
944	static void
945	fxp_stats(struct fxp_softc *sc)
946	{
947	struct ifnet *ifp = &sc->sc_if;
948
949	printf (" Output packets:%-8lu", ifp->if_opackets);
950	printf (" Collisions:%-8lu", ifp->if_collisions);
951	printf (" Output errors:%-8lu\n", ifp->if_oerrors);
952	printf (" Input packets:%-8lu", ifp->if_ipackets);
953	printf (" Input errors:%-8lu\n", ifp->if_ierrors);
954	}
955
956	static void
957	fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
958	{
959	u_int16_t reg;
960	int x;
961
962	/*
963	* Shift in data.
964	*/
965	for (x = 1 << (length - 1); x; x >>= 1) {
966	if (data & x)
967	reg = FXP_EEPROM_EECS \| FXP_EEPROM_EEDI;
968	else
969	reg = FXP_EEPROM_EECS;
970	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
971	DELAY(1);
972	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg \| FXP_EEPROM_EESK);
973	DELAY(1);
974	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
975	DELAY(1);
976	}
977	}
978
979	/*
980	* Read from the serial EEPROM. Basically, you manually shift in
981	* the read opcode (one bit at a time) and then shift in the address,
982	* and then you shift out the data (all of this one bit at a time).
983	* The word size is 16 bits, so you have to provide the address for
984	* every 16 bits of data.
985	*/
986	static u_int16_t
987	fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
988	{
989	u_int16_t reg, data;
990	int x;
991
992	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
993	/*
994	* Shift in read opcode.
995	*/
996	fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
997	/*
998	* Shift in address.
999	*/
1000	data = 0;
1001	for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
1002	if (offset & x)
1003	reg = FXP_EEPROM_EECS \| FXP_EEPROM_EEDI;
1004	else
1005	reg = FXP_EEPROM_EECS;
1006	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1007	DELAY(1);
1008	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg \| FXP_EEPROM_EESK);
1009	DELAY(1);
1010	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1011	DELAY(1);
1012	reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
1013	data++;
1014	if (autosize && reg == 0) {
1015	sc->eeprom_size = data;
1016	break;
1017	}
1018	}
1019	/*
1020	* Shift out data.
1021	*/
1022	data = 0;
1023	reg = FXP_EEPROM_EECS;
1024	for (x = 1 << 15; x; x >>= 1) {
1025	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg \| FXP_EEPROM_EESK);
1026	DELAY(1);
1027	if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1028	data \|= x;
1029	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1030	DELAY(1);
1031	}
1032	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1033	DELAY(1);
1034
1035	return (data);
1036	}
1037
1038	static void
1039	fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data)
1040	{
1041	int i;
1042
1043	/*
1044	* Erase/write enable.
1045	*/
1046	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1047	fxp_eeprom_shiftin(sc, 0x4, 3);
1048	fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1049	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1050	DELAY(1);
1051	/*
1052	* Shift in write opcode, address, data.
1053	*/
1054	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1055	fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1056	fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1057	fxp_eeprom_shiftin(sc, data, 16);
1058	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1059	DELAY(1);
1060	/*
1061	* Wait for EEPROM to finish up.
1062	*/
1063	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1064	DELAY(1);
1065	for (i = 0; i < 1000; i++) {
1066	if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1067	break;
1068	DELAY(50);
1069	}
1070	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1071	DELAY(1);
1072	/*
1073	* Erase/write disable.
1074	*/
1075	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1076	fxp_eeprom_shiftin(sc, 0x4, 3);
1077	fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1078	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1079	DELAY(1);
1080	}
1081
1082	/*
1083	* From NetBSD:
1084	*
1085	* Figure out EEPROM size.
1086	*
1087	* 559's can have either 64-word or 256-word EEPROMs, the 558
1088	* datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1089	* talks about the existance of 16 to 256 word EEPROMs.
1090	*
1091	* The only known sizes are 64 and 256, where the 256 version is used
1092	* by CardBus cards to store CIS information.
1093	*
1094	* The address is shifted in msb-to-lsb, and after the last
1095	* address-bit the EEPROM is supposed to output a `dummy zero' bit,
1096	* after which follows the actual data. We try to detect this zero, by
1097	* probing the data-out bit in the EEPROM control register just after
1098	* having shifted in a bit. If the bit is zero, we assume we've
1099	* shifted enough address bits. The data-out should be tri-state,
1100	* before this, which should translate to a logical one.
1101	*/
1102	static void
1103	fxp_autosize_eeprom(struct fxp_softc *sc)
1104	{
1105
1106	/* guess maximum size of 256 words */
1107	sc->eeprom_size = 8;
1108
1109	/* autosize */
1110	(void) fxp_eeprom_getword(sc, 0, 1);
1111	}
1112
1113	static void
1114	fxp_read_eeprom(struct fxp_softc sc, u_short data, int offset, int words)
1115	{
1116	int i;
1117
1118	for (i = 0; i < words; i++) {
1119	data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1120	DBGLVL_PRINTK(4,"fxp_eeprom_read(off=0x%x)=0x%x\n",
1121	offset+i,data[i]);
1122	}
1123	}
1124
1125	static void
1126	fxp_write_eeprom(struct fxp_softc sc, u_short data, int offset, int words)
1127	{
1128	int i;
1129
1130	for (i = 0; i < words; i++)
1131	fxp_eeprom_putword(sc, offset + i, data[i]);
1132	DBGLVL_PRINTK(4,"fxp_eeprom_write(off=0x%x,0x%x)\n",
1133	offset+i,data[i]);
1134	}
1135
1136	/*
1137	* Start packet transmission on the interface.
1138	*/
1139	static void
1140	fxp_start(struct ifnet *ifp)
1141	{
1142	struct fxp_softc *sc = ifp->if_softc;
1143	struct fxp_cb_tx *txp;
1144
1145	DBGLVL_PRINTK(3,"fxp_start called\n");
1146
1147	/*
1148	* See if we need to suspend xmit until the multicast filter
1149	* has been reprogrammed (which can only be done at the head
1150	* of the command chain).
1151	*/
1152	if (sc->need_mcsetup) {
1153	return;
1154	}
1155
1156	txp = NULL;
1157
1158	/*
1159	* We're finished if there is nothing more to add to the list or if
1160	* we're all filled up with buffers to transmit.
1161	* NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1162	* a NOP command when needed.
1163	*/
1164	while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) {
1165	struct mbuf m, mb_head;
1166	int segment;
1167
1168	/*
1169	* Grab a packet to transmit.
1170	*/
1171	IF_DEQUEUE(&ifp->if_snd, mb_head);
1172
1173	/*
1174	* Get pointer to next available tx desc.
1175	*/
1176	txp = sc->cbl_last->next;
1177
1178	/*
1179	* Go through each of the mbufs in the chain and initialize
1180	* the transmit buffer descriptors with the physical address
1181	* and size of the mbuf.
1182	*/
1183	tbdinit:
1184	for (m = mb_head, segment = 0; m != NULL; m = m->m_next) {
1185	if (m->m_len != 0) {
1186	if (segment == FXP_NTXSEG)
1187	break;
1188	txp->tbd[segment].tb_addr =
1189	vtophys(mtod(m, vm_offset_t));
1190	txp->tbd[segment].tb_size = m->m_len;
1191	segment++;
1192	}
1193	}
1194	if (m != NULL) {
1195	struct mbuf *mn;
1196
1197	/*
1198	* We ran out of segments. We have to recopy this
1199	* mbuf chain first. Bail out if we can't get the
1200	* new buffers.
1201	*/
1202	MGETHDR(mn, M_DONTWAIT, MT_DATA);
1203	if (mn == NULL) {
1204	m_freem(mb_head);
1205	break;
1206	}
1207	if (mb_head->m_pkthdr.len > MHLEN) {
1208	MCLGET(mn, M_DONTWAIT);
1209	if ((mn->m_flags & M_EXT) == 0) {
1210	m_freem(mn);
1211	m_freem(mb_head);
1212	break;
1213	}
1214	}
1215	m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
1216	mtod(mn, caddr_t));
1217	mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len;
1218	m_freem(mb_head);
1219	mb_head = mn;
1220	goto tbdinit;
1221	}
1222
1223	txp->tbd_number = segment;
1224	txp->mb_head = mb_head;
1225	txp->cb_status = 0;
1226	if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1227	txp->cb_command =
1228	FXP_CB_COMMAND_XMIT \| FXP_CB_COMMAND_SF \|
1229	FXP_CB_COMMAND_S;
1230	} else {
1231	txp->cb_command =
1232	FXP_CB_COMMAND_XMIT \| FXP_CB_COMMAND_SF \|
1233	FXP_CB_COMMAND_S \| FXP_CB_COMMAND_I;
1234	/*
1235	* Set a 5 second timer just in case we don't hear
1236	* from the card again.
1237	*/
1238	ifp->if_timer = 5;
1239	}
1240	txp->tx_threshold = tx_threshold;
1241
1242	/*
1243	* Advance the end of list forward.
1244	*/
1245
1246	#ifdef __alpha__
1247	/*
1248	* On platforms which can't access memory in 16-bit
1249	* granularities, we must prevent the card from DMA'ing
1250	* up the status while we update the command field.
1251	* This could cause us to overwrite the completion status.
1252	*/
1253	atomic_clear_short(&sc->cbl_last->cb_command,
1254	FXP_CB_COMMAND_S);
1255	#else
1256	sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
1257	#endif /__alpha__/
1258	sc->cbl_last = txp;
1259
1260	/*
1261	* Advance the beginning of the list forward if there are
1262	* no other packets queued (when nothing is queued, cbl_first
1263	* sits on the last TxCB that was sent out).
1264	*/
1265	if (sc->tx_queued == 0)
1266	sc->cbl_first = txp;
1267
1268	sc->tx_queued++;
1269
1270	#ifdef NOTUSED
1271	/*
1272	* Pass packet to bpf if there is a listener.
1273	*/
1274	if (ifp->if_bpf)
1275	bpf_mtap(ifp, mb_head);
1276	#endif
1277	}
1278
1279	/*
1280	* We're finished. If we added to the list, issue a RESUME to get DMA
1281	* going again if suspended.
1282	*/
1283	if (txp != NULL) {
1284	fxp_scb_wait(sc);
1285	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1286	}
1287	}
1288
1289	/*
1290	* Process interface interrupts.
1291	*/
1292	static rtems_isr fxp_intr(rtems_vector_number v)
1293	{
1294	/*
1295	* FIXME: currently only works with one interface...
1296	*/
1297	struct fxp_softc *sc = &(fxp_softc[0]);
1298
1299	/*
1300	* disable interrupts
1301	*/
1302	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1303	/*
1304	* send event to deamon
1305	*/
1306	rtems_event_send (sc->daemonTid, INTERRUPT_EVENT);
1307	}
1308
1309	static void fxp_daemon(void *xsc)
1310	{
1311	struct fxp_softc *sc = xsc;
1312	struct ifnet *ifp = &sc->sc_if;
1313	u_int8_t statack;
1314	rtems_event_set events;
1315	rtems_interrupt_level level;
1316
1317	#ifdef NOTUSED
1318	if (sc->suspended) {
1319	return;
1320	}
1321	#endif
1322	for (;;) {
1323
1324	DBGLVL_PRINTK(4,"fxp_daemon waiting for event\n");
1325	/*
1326	* wait for event to receive from interrupt function
1327	*/
1328	rtems_bsdnet_event_receive (INTERRUPT_EVENT,
1329	RTEMS_WAIT\|RTEMS_EVENT_ANY,
1330	RTEMS_NO_TIMEOUT,
1331	&events);
1332	while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1333	DBGLVL_PRINTK(4,"fxp_daemon: processing event, statack = 0x%x\n",
1334	statack);
1335	#ifdef NOTUSED
1336	/*
1337	* It should not be possible to have all bits set; the
1338	* FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1339	* all bits are set, this may indicate that the card has
1340	* been physically ejected, so ignore it.
1341	*/
1342	if (statack == 0xff)
1343	return;
1344	#endif
1345
1346	/*
1347	* First ACK all the interrupts in this pass.
1348	*/
1349	CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1350
1351	/*
1352	* Free any finished transmit mbuf chains.
1353	*
1354	* Handle the CNA event likt a CXTNO event. It used to
1355	* be that this event (control unit not ready) was not
1356	* encountered, but it is now with the SMPng modifications.
1357	* The exact sequence of events that occur when the interface
1358	* is brought up are different now, and if this event
1359	* goes unhandled, the configuration/rxfilter setup sequence
1360	* can stall for several seconds. The result is that no
1361	* packets go out onto the wire for about 5 to 10 seconds
1362	* after the interface is ifconfig'ed for the first time.
1363	*/
1364	if (statack & (FXP_SCB_STATACK_CXTNO \| FXP_SCB_STATACK_CNA)) {
1365	struct fxp_cb_tx *txp;
1366
1367	for (txp = sc->cbl_first; sc->tx_queued &&
1368	(txp->cb_status & FXP_CB_STATUS_C) != 0;
1369	txp = txp->next) {
1370	if (txp->mb_head != NULL) {
1371	m_freem(txp->mb_head);
1372	txp->mb_head = NULL;
1373	}
1374	sc->tx_queued--;
1375	}
1376	sc->cbl_first = txp;
1377	ifp->if_timer = 0;
1378	if (sc->tx_queued == 0) {
1379	if (sc->need_mcsetup)
1380	fxp_mc_setup(sc);
1381	}
1382	/*
1383	* Try to start more packets transmitting.
1384	*/
1385	if (ifp->if_snd.ifq_head != NULL)
1386	fxp_start(ifp);
1387	}
1388	/*
1389	* Process receiver interrupts. If a no-resource (RNR)
1390	* condition exists, get whatever packets we can and
1391	* re-start the receiver.
1392	*/
1393	if (statack & (FXP_SCB_STATACK_FR \| FXP_SCB_STATACK_RNR)) {
1394	struct mbuf *m;
1395	struct fxp_rfa *rfa;
1396	rcvloop:
1397	m = sc->rfa_headm;
1398	rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1399	RFA_ALIGNMENT_FUDGE);
1400
1401	if (rfa->rfa_status & FXP_RFA_STATUS_C) {
1402	/*
1403	* Remove first packet from the chain.
1404	*/
1405	sc->rfa_headm = m->m_next;
1406	m->m_next = NULL;
1407
1408	/*
1409	* Add a new buffer to the receive chain.
1410	* If this fails, the old buffer is recycled
1411	* instead.
1412	*/
1413	if (fxp_add_rfabuf(sc, m) == 0) {
1414	struct ether_header *eh;
1415	int total_len;
1416
1417	total_len = rfa->actual_size &
1418	(MCLBYTES - 1);
1419	if (total_len <
1420	sizeof(struct ether_header)) {
1421	m_freem(m);
1422	goto rcvloop;
1423	}
1424
1425	/*
1426	* Drop the packet if it has CRC
1427	* errors. This test is only needed
1428	* when doing 802.1q VLAN on the 82557
1429	* chip.
1430	*/
1431	if (rfa->rfa_status &
1432	FXP_RFA_STATUS_CRC) {
1433	m_freem(m);
1434	goto rcvloop;
1435	}
1436
1437	m->m_pkthdr.rcvif = ifp;
1438	m->m_pkthdr.len = m->m_len = total_len;
1439	eh = mtod(m, struct ether_header *);
1440	m->m_data +=
1441	sizeof(struct ether_header);
1442	m->m_len -=
1443	sizeof(struct ether_header);
1444	m->m_pkthdr.len = m->m_len;
1445	ether_input(ifp, eh, m);
1446	}
1447	goto rcvloop;
1448	}
1449	if (statack & FXP_SCB_STATACK_RNR) {
1450	fxp_scb_wait(sc);
1451	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1452	vtophys(sc->rfa_headm->m_ext.ext_buf) +
1453	RFA_ALIGNMENT_FUDGE);
1454	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1455	}
1456	}
1457	}
1458	/*
1459	* reenable interrupts
1460	*/
1461	rtems_interrupt_disable (level);
1462	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,0);
1463	rtems_interrupt_enable (level);
1464	}
1465	}
1466
1467	/*
1468	* Update packet in/out/collision statistics. The i82557 doesn't
1469	* allow you to access these counters without doing a fairly
1470	* expensive DMA to get _all_ of the statistics it maintains, so
1471	* we do this operation here only once per second. The statistics
1472	* counters in the kernel are updated from the previous dump-stats
1473	* DMA and then a new dump-stats DMA is started. The on-chip
1474	* counters are zeroed when the DMA completes. If we can't start
1475	* the DMA immediately, we don't wait - we just prepare to read
1476	* them again next time.
1477	*/
1478	static void
1479	fxp_tick(void *xsc)
1480	{
1481	struct fxp_softc *sc = xsc;
1482	struct ifnet *ifp = &sc->sc_if;
1483	struct fxp_stats *sp = sc->fxp_stats;
1484	struct fxp_cb_tx *txp;
1485	int s;
1486
1487	DBGLVL_PRINTK(4,"fxp_tick called\n");
1488
1489	ifp->if_opackets += sp->tx_good;
1490	ifp->if_collisions += sp->tx_total_collisions;
1491	if (sp->rx_good) {
1492	ifp->if_ipackets += sp->rx_good;
1493	sc->rx_idle_secs = 0;
1494	} else {
1495	/*
1496	* Receiver's been idle for another second.
1497	*/
1498	sc->rx_idle_secs++;
1499	}
1500	ifp->if_ierrors +=
1501	sp->rx_crc_errors +
1502	sp->rx_alignment_errors +
1503	sp->rx_rnr_errors +
1504	sp->rx_overrun_errors;
1505	/*
1506	* If any transmit underruns occured, bump up the transmit
1507	* threshold by another 512 bytes (64 * 8).
1508	*/
1509	if (sp->tx_underruns) {
1510	ifp->if_oerrors += sp->tx_underruns;
1511	if (tx_threshold < 192)
1512	tx_threshold += 64;
1513	}
1514	s = splimp();
1515	/*
1516	* Release any xmit buffers that have completed DMA. This isn't
1517	* strictly necessary to do here, but it's advantagous for mbufs
1518	* with external storage to be released in a timely manner rather
1519	* than being defered for a potentially long time. This limits
1520	* the delay to a maximum of one second.
1521	*/
1522	for (txp = sc->cbl_first; sc->tx_queued &&
1523	(txp->cb_status & FXP_CB_STATUS_C) != 0;
1524	txp = txp->next) {
1525	if (txp->mb_head != NULL) {
1526	m_freem(txp->mb_head);
1527	txp->mb_head = NULL;
1528	}
1529	sc->tx_queued--;
1530	}
1531	sc->cbl_first = txp;
1532	/*
1533	* If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1534	* then assume the receiver has locked up and attempt to clear
1535	* the condition by reprogramming the multicast filter. This is
1536	* a work-around for a bug in the 82557 where the receiver locks
1537	* up if it gets certain types of garbage in the syncronization
1538	* bits prior to the packet header. This bug is supposed to only
1539	* occur in 10Mbps mode, but has been seen to occur in 100Mbps
1540	* mode as well (perhaps due to a 10/100 speed transition).
1541	*/
1542	if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1543	sc->rx_idle_secs = 0;
1544	fxp_mc_setup(sc);
1545	}
1546	/*
1547	* If there is no pending command, start another stats
1548	* dump. Otherwise punt for now.
1549	*/
1550	if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1551	/*
1552	* Start another stats dump.
1553	*/
1554	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1555	} else {
1556	/*
1557	* A previous command is still waiting to be accepted.
1558	* Just zero our copy of the stats and wait for the
1559	* next timer event to update them.
1560	*/
1561	sp->tx_good = 0;
1562	sp->tx_underruns = 0;
1563	sp->tx_total_collisions = 0;
1564
1565	sp->rx_good = 0;
1566	sp->rx_crc_errors = 0;
1567	sp->rx_alignment_errors = 0;
1568	sp->rx_rnr_errors = 0;
1569	sp->rx_overrun_errors = 0;
1570	}
1571	#ifdef NOTUSED
1572	if (sc->miibus != NULL)
1573	mii_tick(device_get_softc(sc->miibus));
1574	#endif
1575	splx(s);
1576	/*
1577	* Schedule another timeout one second from now.
1578	*/
1579	if (sc->stat_ch == fxp_timeout_running) {
1580	timeout(fxp_tick, sc, hz);
1581	}
1582	else if (sc->stat_ch == fxp_timeout_stop_rq) {
1583	sc->stat_ch = fxp_timeout_stopped;
1584	}
1585	}
1586
1587	/*
1588	* Stop the interface. Cancels the statistics updater and resets
1589	* the interface.
1590	*/
1591	static void
1592	fxp_stop(struct fxp_softc *sc)
1593	{
1594	struct ifnet *ifp = &sc->sc_if;
1595	struct fxp_cb_tx *txp;
1596	int i;
1597
1598	DBGLVL_PRINTK(2,"fxp_stop called\n");
1599
1600	ifp->if_flags &= ~(IFF_RUNNING \| IFF_OACTIVE);
1601	ifp->if_timer = 0;
1602
1603	/*
1604	* stop stats updater.
1605	*/
1606	if (sc->stat_ch == fxp_timeout_running) {
1607	DBGLVL_PRINTK(3,"fxp_stop: trying to stop stat update tick\n");
1608	sc->stat_ch = fxp_timeout_stop_rq;
1609	while(sc->stat_ch != fxp_timeout_stopped) {
1610	rtems_bsdnet_semaphore_release();
1611	rtems_task_wake_after(fxp_ticksPerSecond);
1612	rtems_bsdnet_semaphore_obtain();
1613	}
1614	DBGLVL_PRINTK(3,"fxp_stop: stat update tick stopped\n");
1615	}
1616	/*
1617	* Issue software reset
1618	*/
1619	DBGLVL_PRINTK(3,"fxp_stop: issue software reset\n");
1620	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1621	DELAY(10);
1622
1623	/*
1624	* Release any xmit buffers.
1625	*/
1626	DBGLVL_PRINTK(3,"fxp_stop: releasing xmit buffers\n");
1627	txp = sc->cbl_base;
1628	if (txp != NULL) {
1629	for (i = 0; i < FXP_NTXCB; i++) {
1630	if (txp[i].mb_head != NULL) {
1631	m_freem(txp[i].mb_head);
1632	txp[i].mb_head = NULL;
1633	}
1634	}
1635	}
1636	sc->tx_queued = 0;
1637
1638	/*
1639	* Free all the receive buffers then reallocate/reinitialize
1640	*/
1641	DBGLVL_PRINTK(3,"fxp_stop: free and reinit all receive buffers\n");
1642	if (sc->rfa_headm != NULL)
1643	m_freem(sc->rfa_headm);
1644	sc->rfa_headm = NULL;
1645	sc->rfa_tailm = NULL;
1646	for (i = 0; i < FXP_NRFABUFS; i++) {
1647	if (fxp_add_rfabuf(sc, NULL) != 0) {
1648	/*
1649	* This "can't happen" - we're at splimp()
1650	* and we just freed all the buffers we need
1651	* above.
1652	*/
1653	panic("fxp_stop: no buffers!");
1654	}
1655	}
1656	DBGLVL_PRINTK(2,"fxp_stop: finished\n");
1657	}
1658
1659	/*
1660	* Watchdog/transmission transmit timeout handler. Called when a
1661	* transmission is started on the interface, but no interrupt is
1662	* received before the timeout. This usually indicates that the
1663	* card has wedged for some reason.
1664	*/
1665	static void
1666	fxp_watchdog(struct ifnet *ifp)
1667	{
1668	struct fxp_softc *sc = ifp->if_softc;
1669
1670	device_printf(sc->dev, "device timeout\n");
1671	ifp->if_oerrors++;
1672
1673	fxp_init(sc);
1674	}
1675
1676	static void
1677	fxp_init(void *xsc)
1678	{
1679	struct fxp_softc *sc = xsc;
1680	struct ifnet *ifp = &sc->sc_if;
1681	struct fxp_cb_config *cbp;
1682	struct fxp_cb_ias *cb_ias;
1683	struct fxp_cb_tx *txp;
1684	int i, prm, s;
1685
1686	rtems_task_wake_after(100);
1687	DBGLVL_PRINTK(2,"fxp_init called\n");
1688
1689	s = splimp();
1690	/*
1691	* Cancel any pending I/O
1692	*/
1693	/*
1694	* E. Norum 2004-10-11
1695	* Add line suggested by "Eugene Denisov" <dea@sendmail.ru>.
1696	* Prevents lockup at initialization.
1697	*/
1698	sc->stat_ch = fxp_timeout_stopped;
1699	fxp_stop(sc);
1700
1701	prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1702
1703	DBGLVL_PRINTK(5,"fxp_init: Initializing base of CBL and RFA memory\n");
1704	/*
1705	* Initialize base of CBL and RFA memory. Loading with zero
1706	* sets it up for regular linear addressing.
1707	*/
1708	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1709	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
1710
1711	fxp_scb_wait(sc);
1712	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
1713
1714	/*
1715	* Initialize base of dump-stats buffer.
1716	*/
1717	DBGLVL_PRINTK(5,"fxp_init: Initializing base of dump-stats buffer\n");
1718	fxp_scb_wait(sc);
1719	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats));
1720	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
1721
1722	/*
1723	* We temporarily use memory that contains the TxCB list to
1724	* construct the config CB. The TxCB list memory is rebuilt
1725	* later.
1726	*/
1727	cbp = (struct fxp_cb_config *) sc->cbl_base;
1728	DBGLVL_PRINTK(5,"fxp_init: cbp = 0x%x\n",cbp);
1729
1730	/*
1731	* This memcpy is kind of disgusting, but there are a bunch of must be
1732	* zero and must be one bits in this structure and this is the easiest
1733	* way to initialize them all to proper values.
1734	*/
1735	memcpy( (void )(u_int32_t)(volatile void *)&cbp->cb_status,
1736	fxp_cb_config_template,
1737	sizeof(fxp_cb_config_template));
1738
1739	cbp->cb_status = 0;
1740	cbp->cb_command = FXP_CB_COMMAND_CONFIG \| FXP_CB_COMMAND_EL;
1741	cbp->link_addr = -1; /* (no) next command */
1742	cbp->byte_count = 22; /* (22) bytes to config */
1743	cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
1744	cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
1745	cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
1746	cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
1747	cbp->type_enable = 0; /* actually reserved */
1748	cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
1749	cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
1750	cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
1751	cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
1752	cbp->dma_mbce = 0; /* (disable) dma max counters */
1753	cbp->late_scb = 0; /* (don't) defer SCB update */
1754	cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
1755	cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
1756	cbp->ci_int = 1; /* interrupt on CU idle */
1757	cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
1758	cbp->ext_stats_dis = 1; /* disable extended counters */
1759	cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
1760	cbp->save_bf = sc->chip == FXP_CHIP_82557 ? 1 : prm;
1761	cbp->disc_short_rx = !prm; /* discard short packets */
1762	cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
1763	cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
1764	cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */
1765	cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
1766	cbp->csma_dis = 0; /* (don't) disable link */
1767	cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */
1768	cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
1769	cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
1770	cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
1771	cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
1772	cbp->nsai = 1; /* (don't) disable source addr insert */
1773	cbp->preamble_length = 2; /* (7 byte) preamble */
1774	cbp->loopback = 0; /* (don't) loopback */
1775	cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
1776	cbp->linear_pri_mode = 0; /* (wait after xmit only) */
1777	cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
1778	cbp->promiscuous = prm; /* promiscuous mode */
1779	cbp->bcast_disable = 0; /* (don't) disable broadcasts */
1780	cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
1781	cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
1782	cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
1783	cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
1784
1785	cbp->stripping = !prm; /* truncate rx packet to byte count */
1786	cbp->padding = 1; /* (do) pad short tx packets */
1787	cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
1788	cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
1789	cbp->ia_wake_en = 0; /* (don't) wake up on address match */
1790	cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */
1791	/* must set wake_en in PMCSR also */
1792	cbp->force_fdx = 0; /* (don't) force full duplex */
1793	cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
1794	cbp->multi_ia = 0; /* (don't) accept multiple IAs */
1795	cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
1796
1797	DBGLVL_PRINTK(5,"fxp_init: cbp initialized\n");
1798	if (sc->chip == FXP_CHIP_82557) {
1799	/*
1800	* The 82557 has no hardware flow control, the values
1801	* below are the defaults for the chip.
1802	*/
1803	cbp->fc_delay_lsb = 0;
1804	cbp->fc_delay_msb = 0x40;
1805	cbp->pri_fc_thresh = 3;
1806	cbp->tx_fc_dis = 0;
1807	cbp->rx_fc_restop = 0;
1808	cbp->rx_fc_restart = 0;
1809	cbp->fc_filter = 0;
1810	cbp->pri_fc_loc = 1;
1811	} else {
1812	cbp->fc_delay_lsb = 0x1f;
1813	cbp->fc_delay_msb = 0x01;
1814	cbp->pri_fc_thresh = 3;
1815	cbp->tx_fc_dis = 0; /* enable transmit FC */
1816	cbp->rx_fc_restop = 1; /* enable FC restop frames */
1817	cbp->rx_fc_restart = 1; /* enable FC restart frames */
1818	cbp->fc_filter = !prm; /* drop FC frames to host */
1819	cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
1820	}
1821
1822	/*
1823	* Start the config command/DMA.
1824	*/
1825	DBGLVL_PRINTK(5,"fxp_init: starting config command/DMA\n");
1826	fxp_scb_wait(sc);
1827	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
1828	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1829	/* ...and wait for it to complete. */
1830	fxp_dma_wait(&cbp->cb_status, sc);
1831
1832	/*
1833	* Now initialize the station address. Temporarily use the TxCB
1834	* memory area like we did above for the config CB.
1835	*/
1836	DBGLVL_PRINTK(5,"fxp_init: initialize station address\n");
1837	cb_ias = (struct fxp_cb_ias *) sc->cbl_base;
1838	cb_ias->cb_status = 0;
1839	cb_ias->cb_command = FXP_CB_COMMAND_IAS \| FXP_CB_COMMAND_EL;
1840	cb_ias->link_addr = -1;
1841	memcpy((void )(u_int32_t)(volatile void *)cb_ias->macaddr,
1842	sc->arpcom.ac_enaddr,
1843	sizeof(sc->arpcom.ac_enaddr));
1844
1845	/*
1846	* Start the IAS (Individual Address Setup) command/DMA.
1847	*/
1848	DBGLVL_PRINTK(5,"fxp_init: start IAS command/DMA\n");
1849	fxp_scb_wait(sc);
1850	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1851	/* ...and wait for it to complete. */
1852	fxp_dma_wait(&cb_ias->cb_status, sc);
1853
1854	/*
1855	* Initialize transmit control block (TxCB) list.
1856	*/
1857
1858	DBGLVL_PRINTK(5,"fxp_init: initialize TxCB list\n");
1859	txp = sc->cbl_base;
1860	memset(txp, 0, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
1861	for (i = 0; i < FXP_NTXCB; i++) {
1862	txp[i].cb_status = FXP_CB_STATUS_C \| FXP_CB_STATUS_OK;
1863	txp[i].cb_command = FXP_CB_COMMAND_NOP;
1864	txp[i].link_addr =
1865	vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status);
1866	if (sc->flags & FXP_FLAG_EXT_TXCB)
1867	txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]);
1868	else
1869	txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]);
1870	txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK];
1871	}
1872	/*
1873	* Set the suspend flag on the first TxCB and start the control
1874	* unit. It will execute the NOP and then suspend.
1875	*/
1876	DBGLVL_PRINTK(5,"fxp_init: setup suspend flag\n");
1877	txp->cb_command = FXP_CB_COMMAND_NOP \| FXP_CB_COMMAND_S;
1878	sc->cbl_first = sc->cbl_last = txp;
1879	sc->tx_queued = 1;
1880
1881	fxp_scb_wait(sc);
1882	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1883
1884	/*
1885	* Initialize receiver buffer area - RFA.
1886	*/
1887	DBGLVL_PRINTK(5,"fxp_init: initialize RFA\n");
1888	fxp_scb_wait(sc);
1889	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1890	vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE);
1891	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1892
1893	#ifdef NOTUSED
1894	/*
1895	* Set current media.
1896	*/
1897	if (sc->miibus != NULL)
1898	mii_mediachg(device_get_softc(sc->miibus));
1899	#endif
1900
1901	ifp->if_flags \|= IFF_RUNNING;
1902	ifp->if_flags &= ~IFF_OACTIVE;
1903
1904	if (sc->daemonTid == 0) {
1905	/*
1906	* Start driver task
1907	*/
1908	sc->daemonTid = rtems_bsdnet_newproc ("FXPd", 4096, fxp_daemon, sc);
1909
1910	}
1911	/*
1912	* Enable interrupts.
1913	*/
1914	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1915	splx(s);
1916
1917	/*
1918	* Start stats updater.
1919	*/
1920	sc->stat_ch = fxp_timeout_running;
1921	DBGLVL_PRINTK(2,"fxp_init: stats updater timeout called with hz=%d\n", hz);
1922	timeout(fxp_tick, sc, hz);
1923	DBGLVL_PRINTK(2,"fxp_init finished\n");
1924	}
1925
1926	#ifdef NOTUSED
1927	static int
1928	fxp_serial_ifmedia_upd(struct ifnet *ifp)
1929	{
1930
1931	return (0);
1932	}
1933
1934	static void
1935	fxp_serial_ifmedia_sts(struct ifnet ifp, struct ifmediareq ifmr)
1936	{
1937
1938	ifmr->ifm_active = IFM_ETHER\|IFM_MANUAL;
1939	}
1940
1941	/*
1942	* Change media according to request.
1943	*/
1944	static int
1945	fxp_ifmedia_upd(struct ifnet *ifp)
1946	{
1947	struct fxp_softc *sc = ifp->if_softc;
1948	struct mii_data *mii;
1949
1950	mii = device_get_softc(sc->miibus);
1951	mii_mediachg(mii);
1952	return (0);
1953	}
1954
1955	/*
1956	* Notify the world which media we're using.
1957	*/
1958	static void
1959	fxp_ifmedia_sts(struct ifnet ifp, struct ifmediareq ifmr)
1960	{
1961	struct fxp_softc *sc = ifp->if_softc;
1962	struct mii_data *mii;
1963
1964	mii = device_get_softc(sc->miibus);
1965	mii_pollstat(mii);
1966	ifmr->ifm_active = mii->mii_media_active;
1967	ifmr->ifm_status = mii->mii_media_status;
1968
1969	if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG)
1970	sc->cu_resume_bug = 1;
1971	else
1972	sc->cu_resume_bug = 0;
1973	}
1974	#endif
1975
1976	/*
1977	* Add a buffer to the end of the RFA buffer list.
1978	* Return 0 if successful, 1 for failure. A failure results in
1979	* adding the 'oldm' (if non-NULL) on to the end of the list -
1980	* tossing out its old contents and recycling it.
1981	* The RFA struct is stuck at the beginning of mbuf cluster and the
1982	* data pointer is fixed up to point just past it.
1983	*/
1984	static int
1985	fxp_add_rfabuf(struct fxp_softc sc, struct mbuf oldm)
1986	{
1987	u_int32_t v;
1988	struct mbuf *m;
1989	struct fxp_rfa rfa, p_rfa;
1990
1991	DBGLVL_PRINTK(4,"fxp_add_rfabuf called\n");
1992
1993	MGETHDR(m, M_DONTWAIT, MT_DATA);
1994	if (m != NULL) {
1995	MCLGET(m, M_DONTWAIT);
1996	if ((m->m_flags & M_EXT) == 0) {
1997	m_freem(m);
1998	if (oldm == NULL)
1999	return 1;
2000	m = oldm;
2001	m->m_data = m->m_ext.ext_buf;
2002	}
2003	} else {
2004	if (oldm == NULL)
2005	return 1;
2006	m = oldm;
2007	m->m_data = m->m_ext.ext_buf;
2008	}
2009
2010	/*
2011	* Move the data pointer up so that the incoming data packet
2012	* will be 32-bit aligned.
2013	*/
2014	m->m_data += RFA_ALIGNMENT_FUDGE;
2015
2016	/*
2017	* Get a pointer to the base of the mbuf cluster and move
2018	* data start past it.
2019	*/
2020	rfa = mtod(m, struct fxp_rfa *);
2021	m->m_data += sizeof(struct fxp_rfa);
2022	rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE);
2023
2024	/*
2025	* Initialize the rest of the RFA. Note that since the RFA
2026	* is misaligned, we cannot store values directly. Instead,
2027	* we use an optimized, inline copy.
2028	*/
2029
2030	rfa->rfa_status = 0;
2031	rfa->rfa_control = FXP_RFA_CONTROL_EL;
2032	rfa->actual_size = 0;
2033
2034	v = -1;
2035	fxp_lwcopy(&v, (volatile u_int32_t*) rfa->link_addr);
2036	fxp_lwcopy(&v, (volatile u_int32_t*) rfa->rbd_addr);
2037
2038	/*
2039	* If there are other buffers already on the list, attach this
2040	* one to the end by fixing up the tail to point to this one.
2041	*/
2042	if (sc->rfa_headm != NULL) {
2043	p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf +
2044	RFA_ALIGNMENT_FUDGE);
2045	sc->rfa_tailm->m_next = m;
2046	v = vtophys(rfa);
2047	fxp_lwcopy(&v, (volatile u_int32_t*) p_rfa->link_addr);
2048	p_rfa->rfa_control = 0;
2049	} else {
2050	sc->rfa_headm = m;
2051	}
2052	sc->rfa_tailm = m;
2053
2054	return (m == oldm);
2055	}
2056
2057	#ifdef NOTUSED
2058	static volatile int
2059	fxp_miibus_readreg(device_t dev, int phy, int reg)
2060	{
2061	struct fxp_softc *sc = device_get_softc(dev);
2062	int count = 10000;
2063	int value;
2064
2065	CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2066	(FXP_MDI_READ << 26) \| (reg << 16) \| (phy << 21));
2067
2068	while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2069	&& count--)
2070	DELAY(10);
2071
2072	if (count <= 0)
2073	device_printf(dev, "fxp_miibus_readreg: timed out\n");
2074
2075	return (value & 0xffff);
2076	}
2077
2078	static void
2079	fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2080	{
2081	struct fxp_softc *sc = device_get_softc(dev);
2082	int count = 10000;
2083
2084	CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2085	(FXP_MDI_WRITE << 26) \| (reg << 16) \| (phy << 21) \|
2086	(value & 0xffff));
2087
2088	while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2089	count--)
2090	DELAY(10);
2091
2092	if (count <= 0)
2093	device_printf(dev, "fxp_miibus_writereg: timed out\n");
2094	}
2095	#endif
2096
2097	static int
2098	fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2099	{
2100	struct fxp_softc *sc = ifp->if_softc;
2101	#ifdef NOTUSED
2102	struct ifreq ifr = (struct ifreq )data;
2103	struct mii_data *mii;
2104	#endif
2105	int s, error = 0;
2106
2107	DBGLVL_PRINTK(2,"fxp_ioctl called\n");
2108
2109	s = splimp();
2110
2111	switch (command) {
2112	case SIOCSIFADDR:
2113	case SIOCGIFADDR:
2114	case SIOCSIFMTU:
2115	error = ether_ioctl(ifp, command, data);
2116	break;
2117
2118	case SIOCSIFFLAGS:
2119	if (ifp->if_flags & IFF_ALLMULTI)
2120	sc->flags \|= FXP_FLAG_ALL_MCAST;
2121	else
2122	sc->flags &= ~FXP_FLAG_ALL_MCAST;
2123
2124	/*
2125	* If interface is marked up and not running, then start it.
2126	* If it is marked down and running, stop it.
2127	* XXX If it's up then re-initialize it. This is so flags
2128	* such as IFF_PROMISC are handled.
2129	*/
2130	if (ifp->if_flags & IFF_UP) {
2131	fxp_init(sc);
2132	} else {
2133	if (ifp->if_flags & IFF_RUNNING)
2134	fxp_stop(sc);
2135	}
2136	break;
2137
2138	case SIOCADDMULTI:
2139	case SIOCDELMULTI:
2140	if (ifp->if_flags & IFF_ALLMULTI)
2141	sc->flags \|= FXP_FLAG_ALL_MCAST;
2142	else
2143	sc->flags &= ~FXP_FLAG_ALL_MCAST;
2144	/*
2145	* Multicast list has changed; set the hardware filter
2146	* accordingly.
2147	*/
2148	if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
2149	fxp_mc_setup(sc);
2150	/*
2151	* fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
2152	* again rather than else {}.
2153	*/
2154	if (sc->flags & FXP_FLAG_ALL_MCAST)
2155	fxp_init(sc);
2156	error = 0;
2157	break;
2158
2159	#ifdef NOTUSED
2160	case SIOCSIFMEDIA:
2161	case SIOCGIFMEDIA:
2162	if (sc->miibus != NULL) {
2163	mii = device_get_softc(sc->miibus);
2164	error = ifmedia_ioctl(ifp, ifr,
2165	&mii->mii_media, command);
2166	} else {
2167	error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2168	}
2169	break;
2170	#endif
2171
2172	case SIO_RTEMS_SHOW_STATS:
2173	fxp_stats(sc);
2174	break;
2175
2176	default:
2177	error = EINVAL;
2178	}
2179	splx(s);
2180	return (error);
2181	}
2182
2183	/*
2184	* Program the multicast filter.
2185	*
2186	* We have an artificial restriction that the multicast setup command
2187	* must be the first command in the chain, so we take steps to ensure
2188	* this. By requiring this, it allows us to keep up the performance of
2189	* the pre-initialized command ring (esp. link pointers) by not actually
2190	* inserting the mcsetup command in the ring - i.e. its link pointer
2191	* points to the TxCB ring, but the mcsetup descriptor itself is not part
2192	* of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2193	* lead into the regular TxCB ring when it completes.
2194	*
2195	* This function must be called at splimp.
2196	*/
2197	static void
2198	fxp_mc_setup(struct fxp_softc *sc)
2199	{
2200	struct fxp_cb_mcs *mcsp = sc->mcsp;
2201	struct ifnet *ifp = &sc->sc_if;
2202	#ifdef NOTUSED
2203	struct ifmultiaddr *ifma;
2204	#endif
2205	int nmcasts;
2206	int count;
2207
2208	DBGLVL_PRINTK(2,"fxp_mc_setup called\n");
2209
2210	/*
2211	* If there are queued commands, we must wait until they are all
2212	* completed. If we are already waiting, then add a NOP command
2213	* with interrupt option so that we're notified when all commands
2214	* have been completed - fxp_start() ensures that no additional
2215	* TX commands will be added when need_mcsetup is true.
2216	*/
2217	if (sc->tx_queued) {
2218	struct fxp_cb_tx *txp;
2219
2220	/*
2221	* need_mcsetup will be true if we are already waiting for the
2222	* NOP command to be completed (see below). In this case, bail.
2223	*/
2224	if (sc->need_mcsetup)
2225	return;
2226	sc->need_mcsetup = 1;
2227
2228	/*
2229	* Add a NOP command with interrupt so that we are notified when all
2230	* TX commands have been processed.
2231	*/
2232	txp = sc->cbl_last->next;
2233	txp->mb_head = NULL;
2234	txp->cb_status = 0;
2235	txp->cb_command = FXP_CB_COMMAND_NOP \|
2236	FXP_CB_COMMAND_S \| FXP_CB_COMMAND_I;
2237	/*
2238	* Advance the end of list forward.
2239	*/
2240	sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
2241	sc->cbl_last = txp;
2242	sc->tx_queued++;
2243	/*
2244	* Issue a resume in case the CU has just suspended.
2245	*/
2246	fxp_scb_wait(sc);
2247	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2248	/*
2249	* Set a 5 second timer just in case we don't hear from the
2250	* card again.
2251	*/
2252	ifp->if_timer = 5;
2253
2254	return;
2255	}
2256	sc->need_mcsetup = 0;
2257
2258	/*
2259	* Initialize multicast setup descriptor.
2260	*/
2261	mcsp->next = sc->cbl_base;
2262	mcsp->mb_head = NULL;
2263	mcsp->cb_status = 0;
2264	mcsp->cb_command = FXP_CB_COMMAND_MCAS \|
2265	FXP_CB_COMMAND_S \| FXP_CB_COMMAND_I;
2266	mcsp->link_addr = vtophys(&sc->cbl_base->cb_status);
2267
2268	nmcasts = 0;
2269	#ifdef NOTUSED /* FIXME: Multicast not supported? */
2270	if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
2271	#if __FreeBSD_version < 500000
2272	LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2273	#else
2274	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2275	#endif
2276	if (ifma->ifma_addr->sa_family != AF_LINK)
2277	continue;
2278	if (nmcasts >= MAXMCADDR) {
2279	sc->flags \|= FXP_FLAG_ALL_MCAST;
2280	nmcasts = 0;
2281	break;
2282	}
2283	memcpy((void )(uintptr_t)(volatile void )
2284	&sc->mcsp->mc_addr[nmcasts][0],
2285	LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 6);
2286	nmcasts++;
2287	}
2288	}
2289	#endif
2290	mcsp->mc_cnt = nmcasts * 6;
2291	sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp;
2292	sc->tx_queued = 1;
2293
2294	/*
2295	* Wait until command unit is not active. This should never
2296	* be the case when nothing is queued, but make sure anyway.
2297	*/
2298	count = 100;
2299	while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2300	FXP_SCB_CUS_ACTIVE && --count)
2301	DELAY(10);
2302	if (count == 0) {
2303	device_printf(sc->dev, "command queue timeout\n");
2304	return;
2305	}
2306
2307	/*
2308	* Start the multicast setup command.
2309	*/
2310	fxp_scb_wait(sc);
2311	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
2312	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2313
2314	ifp->if_timer = 2;
2315	return;
2316	}
2317
2318	#endif /* defined(__i386__) */

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