source: rtems/c/src/libchip/network/if_fxp.c @ 8730f45

4.104.114.84.95
Last change on this file since 8730f45 was 2b947a4, checked in by Joel Sherrill <joel.sherrill@…>, on 07/16/02 at 22:37:13

2002-07-16 Eric Norum <eric.norum@…>

  • New driver for the Intel EtherExpressPro? (82559ER) chip.
  • network/if_fxp.c, network/if_fxpreg.h, network/if_fxpvar.h, network/pci.h: New file.
  • network/Makefile.am: Modified to reflect above.
  • Property mode set to 100644
File size: 60.8 KB
Line 
1/*-
2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice unmodified, this list of conditions, and the following
11 *    disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.118 2001/09/05 23:33:58 brooks Exp $
29 */
30
31/*
32 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
33 */
34
35/*
36 * RTEMS Revision Preliminary History
37 *
38 * July XXX, 2002     W. Eric Norum <eric.norum@usask.ca>
39 *     Placed in RTEMS CVS repository.  All further modifications will be
40 *     noted in the CVS log and not in this comment.
41 *
42 * July 11, 2002     W. Eric Norum <eric.norum@usask.ca>
43 *     Minor modifications to get driver working with NIC on VersaLogic
44 *     Bobcat PC-104 single-board computer.  The Bobcat has no video
45 *     driver so printf/printk calls are directed to COM2:.  This
46 *     arrangement seems to require delays after the printk calls or
47 *     else things lock up.  Perhaps the RTEMS pc386 console code
48 *     should be modified to insert these delays itself.
49 *
50 * June 27, 2002     W. Eric Norum <eric.norum@usask.ca>
51 *     Obtained from Thomas Doerfler <Thomas.Doerfler@imd-systems.de>.
52 *     A big thank-you to Thomas for making this available.
53 *
54 * October 01, 2001  Thomas Doerfler <Thomas.Doerfler@imd-systems.de>
55 *     Original RTEMS modifications.
56 */
57
58#if defined(__i386__)
59
60/*#define DEBUG_OUT 0*/
61
62#include <rtems.h>
63#include <rtems/error.h>
64#include <rtems/rtems_bsdnet.h>
65#include <bsp.h>
66
67#include <sys/param.h>
68#include <sys/mbuf.h>
69#include <sys/socket.h>
70#include <sys/sockio.h>
71#include <net/if.h>
72#include <netinet/in.h>
73#include <netinet/if_ether.h>
74#include <sys/malloc.h>
75#include <sys/systm.h>
76#include <bsp.h>
77#include <pcibios.h>
78#include <irq.h>
79#include "pci.h"
80
81#ifdef NS
82#include <netns/ns.h>
83#include <netns/ns_if.h>
84#endif
85
86#include <net/bpf.h>
87
88#include <vm/vm.h>              /* for vtophys */
89
90#include <net/if_types.h>
91
92#include "if_fxpreg.h"
93#include "if_fxpvar.h"
94
95/*
96 * some adaptation replacements for RTEMS
97 */
98static rtems_interval fxp_ticksPerSecond;
99#define device_printf(device,format,args...) printk(format,## args)
100#define DELAY(n) rtems_task_wake_after(((n)*fxp_ticksPerSecond/1000000)+1)
101#ifdef DEBUG_OUT
102#define DBGLVL_PRINTK(LVL,format, args...)                   \
103if (DEBUG_OUT >= (LVL)) {                                    \
104  printk(format, ## args);                                   \
105}
106#else
107#define DBGLVL_PRINTK(LVL,format, args...)
108#endif
109
110/*
111 * RTEMS event used by interrupt handler to signal driver tasks.
112 * This must not be any of the events used by the network task synchronization.
113 */
114#define INTERRUPT_EVENT RTEMS_EVENT_1
115
116/*
117 * remapping between PCI device and CPU memmory address view...
118 */
119#if defined(__i386)
120#define vtophys(p) (u_int32_t)(p)
121#else
122#define vtophys(p) vtophys(p)
123#endif
124
125#define NFXPDRIVER 1
126static struct fxp_softc fxp_softc[NFXPDRIVER];
127static int fxp_is_verbose = TRUE;
128/*
129 * NOTE!  On the Alpha, we have an alignment constraint.  The
130 * card DMAs the packet immediately following the RFA.  However,
131 * the first thing in the packet is a 14-byte Ethernet header.
132 * This means that the packet is misaligned.  To compensate,
133 * we actually offset the RFA 2 bytes into the cluster.  This
134 * alignes the packet after the Ethernet header at a 32-bit
135 * boundary.  HOWEVER!  This means that the RFA is misaligned!
136 */
137#define RFA_ALIGNMENT_FUDGE     2
138
139/*
140 * Set initial transmit threshold at 64 (512 bytes). This is
141 * increased by 64 (512 bytes) at a time, to maximum of 192
142 * (1536 bytes), if an underrun occurs.
143 */
144static int tx_threshold = 64;
145
146/*
147 * The configuration byte map has several undefined fields which
148 * must be one or must be zero.  Set up a template for these bits
149 * only, (assuming a 82557 chip) leaving the actual configuration
150 * to fxp_init.
151 *
152 * See struct fxp_cb_config for the bit definitions.
153 */
154static u_char fxp_cb_config_template[] = {
155        0x0, 0x0,               /* cb_status */
156        0x0, 0x0,               /* cb_command */
157        0x0, 0x0, 0x0, 0x0,     /* link_addr */
158        0x0,    /*  0 */
159        0x0,    /*  1 */
160        0x0,    /*  2 */
161        0x0,    /*  3 */
162        0x0,    /*  4 */
163        0x0,    /*  5 */
164        0x32,   /*  6 */
165        0x0,    /*  7 */
166        0x0,    /*  8 */
167        0x0,    /*  9 */
168        0x6,    /* 10 */
169        0x0,    /* 11 */
170        0x0,    /* 12 */
171        0x0,    /* 13 */
172        0xf2,   /* 14 */
173        0x48,   /* 15 */
174        0x0,    /* 16 */
175        0x40,   /* 17 */
176        0xf0,   /* 18 */
177        0x0,    /* 19 */
178        0x3f,   /* 20 */
179        0x5     /* 21 */
180};
181
182struct fxp_ident {
183        u_int16_t       devid;
184        char            *name;
185};
186
187/*
188 * Claim various Intel PCI device identifiers for this driver.  The
189 * sub-vendor and sub-device field are extensively used to identify
190 * particular variants, but we don't currently differentiate between
191 * them.
192 */
193#ifdef NOTUSED
194static struct fxp_ident fxp_ident_table[] = {
195    { 0x1229,           "Intel Pro 10/100B/100+ Ethernet" },
196    { 0x2449,           "Intel Pro/100 Ethernet" },
197    { 0x1209,           "Intel Embedded 10/100 Ethernet" },
198    { 0x1029,           "Intel Pro/100 Ethernet" },
199    { 0x1030,           "Intel Pro/100 Ethernet" },
200    { 0x1031,           "Intel Pro/100 Ethernet" },
201    { 0x1032,           "Intel Pro/100 Ethernet" },
202    { 0x1033,           "Intel Pro/100 Ethernet" },
203    { 0x1034,           "Intel Pro/100 Ethernet" },
204    { 0x1035,           "Intel Pro/100 Ethernet" },
205    { 0x1036,           "Intel Pro/100 Ethernet" },
206    { 0x1037,           "Intel Pro/100 Ethernet" },
207    { 0x1038,           "Intel Pro/100 Ethernet" },
208    { 0,                NULL },
209};
210#endif
211
212#if 0
213static int              fxp_probe(device_t dev);
214static int              fxp_attach(device_t dev);
215static int              fxp_detach(device_t dev);
216static int              fxp_shutdown(device_t dev);
217#endif
218int     fxp_output (struct ifnet *,
219           struct mbuf *, struct sockaddr *, struct rtentry *);
220
221
222static rtems_isr        fxp_intr(rtems_vector_number v);
223static void             fxp_init(void *xsc);
224static void             fxp_tick(void *xsc);
225static void             fxp_start(struct ifnet *ifp);
226static void             fxp_stop(struct fxp_softc *sc);
227static void             fxp_release(struct fxp_softc *sc);
228static int              fxp_ioctl(struct ifnet *ifp, int command,
229                            caddr_t data);
230static void             fxp_watchdog(struct ifnet *ifp);
231static int              fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm);
232static void             fxp_mc_setup(struct fxp_softc *sc);
233static u_int16_t        fxp_eeprom_getword(struct fxp_softc *sc, int offset,
234                            int autosize);
235static void             fxp_eeprom_putword(struct fxp_softc *sc, int offset,
236                            u_int16_t data);
237static void             fxp_autosize_eeprom(struct fxp_softc *sc);
238static void             fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
239                            int offset, int words);
240static void             fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
241                            int offset, int words);
242#ifdef NOTUSED
243static int              fxp_ifmedia_upd(struct ifnet *ifp);
244static void             fxp_ifmedia_sts(struct ifnet *ifp,
245                            struct ifmediareq *ifmr);
246static int              fxp_serial_ifmedia_upd(struct ifnet *ifp);
247static void             fxp_serial_ifmedia_sts(struct ifnet *ifp,
248                            struct ifmediareq *ifmr);
249static volatile int     fxp_miibus_readreg(device_t dev, int phy, int reg);
250static void             fxp_miibus_writereg(device_t dev, int phy, int reg,
251                            int value);
252#endif
253static __inline void    fxp_lwcopy(volatile u_int32_t *src,
254                            volatile u_int32_t *dst);
255static __inline void    fxp_scb_wait(struct fxp_softc *sc);
256static __inline void    fxp_scb_cmd(struct fxp_softc *sc, int cmd);
257static __inline void    fxp_dma_wait(volatile u_int16_t *status,
258                            struct fxp_softc *sc);
259
260/*
261 * Inline function to copy a 16-bit aligned 32-bit quantity.
262 */
263static __inline void
264fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst)
265{
266#ifdef __i386__
267        *dst = *src;
268#else
269        volatile u_int16_t *a = (volatile u_int16_t *)src;
270        volatile u_int16_t *b = (volatile u_int16_t *)dst;
271
272        b[0] = a[0];
273        b[1] = a[1];
274#endif
275}
276
277/*
278 * inline access functions to pci space registers
279 */
280static __inline u_int8_t fxp_csr_read_1(struct fxp_softc *sc,int  reg) {
281  u_int8_t val;
282  if (sc->pci_regs_are_io) {
283    inport_byte(sc->pci_regs_base + reg,val);
284  }
285  else {
286    val = *(u_int8_t *)(sc->pci_regs_base+reg);
287  }
288  return val;
289}
290static __inline u_int32_t fxp_csr_read_2(struct fxp_softc *sc,int  reg) {
291  u_int16_t val;
292  if (sc->pci_regs_are_io) {
293    inport_word(sc->pci_regs_base + reg,val);
294  }
295  else {
296    val = *(u_int16_t *)(sc->pci_regs_base+reg);
297  }
298  return val;
299}
300static __inline u_int32_t fxp_csr_read_4(struct fxp_softc *sc,int  reg) {
301  u_int32_t val;
302  if (sc->pci_regs_are_io) {
303    inport_long(sc->pci_regs_base + reg,val);
304  }
305  else {
306    val = *(u_int32_t *)(sc->pci_regs_base+reg);
307  }
308  return val;
309}
310
311/*
312 * Wait for the previous command to be accepted (but not necessarily
313 * completed).
314 */
315static __inline void
316fxp_scb_wait(struct fxp_softc *sc)
317{
318        int i = 10000;
319
320        while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
321                DELAY(2);
322        if (i == 0)
323                device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
324                    CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
325                    CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
326                    CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS),
327                    CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
328}
329
330static __inline void
331fxp_scb_cmd(struct fxp_softc *sc, int cmd)
332{
333
334        if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
335                CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
336                fxp_scb_wait(sc);
337        }
338        CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
339}
340
341static __inline void
342fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc)
343{
344        int i = 10000;
345
346        while (!(*status & FXP_CB_STATUS_C) && --i)
347                DELAY(2);
348        if (i == 0)
349                device_printf(sc->dev, "DMA timeout\n");
350}
351
352static __inline unsigned int pci_get_vendor(struct fxp_softc *sc) {
353  u_int16_t vendor;
354  pcib_conf_read16(sc->pci_signature,0,&vendor);
355  return vendor;
356}
357
358static __inline unsigned int pci_get_device(struct fxp_softc *sc) {
359  u_int16_t device;
360  pcib_conf_read16(sc->pci_signature,2,&device);
361  return device;
362}
363
364static __inline unsigned int pci_get_subvendor(struct fxp_softc *sc) {
365  u_int16_t subvendor;
366  pcib_conf_read16(sc->pci_signature,0x2c,&subvendor);
367  return subvendor;
368}
369
370static __inline unsigned int pci_get_subdevice(struct fxp_softc *sc) {
371  u_int16_t subdevice;
372  pcib_conf_read16(sc->pci_signature,0x2e,&subdevice);
373  return subdevice;
374}
375
376static __inline unsigned int pci_get_revid(struct fxp_softc *sc) {
377  u_int8_t revid;
378  pcib_conf_read8(sc->pci_signature,0x08,&revid);
379  return revid;
380}
381
382static void nopOn(const rtems_irq_connect_data* notUsed)
383{
384  /*
385   * code should be moved from fxp_Enet_initialize_hardware
386   * to this location
387   */
388}
389
390static int fxpIsOn(const rtems_irq_connect_data* irq)
391{
392  return BSP_irq_enabled_at_i8259s (irq->name);
393}
394
395int
396rtems_fxp_attach(struct rtems_bsdnet_ifconfig *config, int attaching)
397{
398        int error = 0;
399        struct fxp_softc *sc;
400        struct ifnet *ifp;
401        u_int16_t val16;
402        u_int32_t val32;
403        u_int16_t data;
404        int i;
405        int s;
406        int unitNumber;
407        char *unitName;
408        u_int16_t dev_id;
409        u_int8_t interrupt;
410        int mtu;
411
412    /*
413     * Set up some timing values
414     */
415    rtems_clock_get(RTEMS_CLOCK_GET_TICKS_PER_SECOND, &fxp_ticksPerSecond);
416        DBGLVL_PRINTK(1,"fxp_attach called\n");
417
418        /*
419         * Parse driver name
420         */
421        if ((unitNumber = rtems_bsdnet_parse_driver_name (config, &unitName)) < 0)
422                return 0;
423       
424        /*
425         * Is driver free?
426         */
427        if ((unitNumber <= 0) || (unitNumber > NFXPDRIVER)) {
428                device_printf(dev,"Bad FXP unit number.\n");
429                return 0;
430        }
431        sc = &fxp_softc[unitNumber - 1];
432        ifp = &sc->arpcom.ac_if;
433        if (ifp->if_softc != NULL) {
434                device_printf(dev,"FXP Driver already in use.\n");
435                return 0;
436        }
437
438        bzero(sc, sizeof(*sc));
439#ifdef NOTUSED
440        sc->dev = dev;
441        callout_handle_init(&sc->stat_ch);
442        mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
443#endif
444        s = splimp();
445
446        /*
447         * init PCI Bios interface...
448         */
449        i = pcib_init();
450        DBGLVL_PRINTK(2,"fxp_attach: pcib_init returned %d\n",i);
451        if (i != PCIB_ERR_SUCCESS) {
452          device_printf(dev, "could not initialize pci bios interface\n");
453          return 0;
454        }
455       
456        /*
457         * find device on pci bus
458         */     
459        i = pcib_find_by_devid(0x8086,0x1209,unitNumber-1,
460                               &(sc->pci_signature));
461        DBGLVL_PRINTK(2,"fxp_attach: find_devid returned %d "
462                      "and pci signature 0x%x\n",
463                      i,sc->pci_signature);
464
465        /*
466         * FIXME: add search for more device types...
467         */
468        if (i != PCIB_ERR_SUCCESS) {
469          device_printf(dev, "could not find 82559ER device\n");
470          return 0;
471        }
472         
473
474        /*
475         * Enable bus mastering. Enable memory space too, in case
476         * BIOS/Prom forgot about it.
477         */
478        pcib_conf_read16(sc->pci_signature, PCI_COMMAND,&val16);
479        val16 |= (PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER);
480        pcib_conf_write16(sc->pci_signature, PCI_COMMAND, val16);
481        DBGLVL_PRINTK(3,"fxp_attach: PCI_COMMAND_write = 0x%x\n",val16);
482        pcib_conf_read16(sc->pci_signature, PCI_COMMAND,&val16);
483        DBGLVL_PRINTK(4,"fxp_attach: PCI_COMMAND_read  = 0x%x\n",val16);
484
485        /*
486         * Figure out which we should try first - memory mapping or i/o mapping?
487         * We default to memory mapping. Then we accept an override from the
488         * command line. Then we check to see which one is enabled.
489         */
490#ifdef NOTUSED
491        m1 = PCI_COMMAND_MEMORY;
492        m2 = PCI_COMMAND_IO;
493        prefer_iomap = 0;
494        if (resource_int_value(device_get_name(dev), device_get_unit(dev),
495            "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) {
496                m1 = PCI_COMMAND_IO;
497                m2 = PCI_COMMAND_MEMORY;
498        }
499
500        if (val & m1) {
501                sc->rtp = ((m1 == PCI_COMMAND_MEMORY)
502                           ? SYS_RES_MEMORY : SYS_RES_IOPORT);
503                sc->rgd = ((m1 == PCI_COMMAND_MEMORY)
504                           ? FXP_PCI_MMBA   : FXP_PCI_IOBA);
505                sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
506                                             0, ~0, 1, RF_ACTIVE);
507        }
508        if (sc->mem == NULL && (val & m2)) {
509                sc->rtp = ((m2 == PCI_COMMAND_MEMORY)
510                           ? SYS_RES_MEMORY : SYS_RES_IOPORT);
511                sc->rgd = ((m2 == PCI_COMMAND_MEMORY)
512                           ? FXP_PCI_MMBA : FXP_PCI_IOBA);
513                sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
514                                            0, ~0, 1, RF_ACTIVE);
515        }
516
517        if (!sc->mem) {
518                device_printf(dev, "could not map device registers\n");
519                error = ENXIO;
520                goto fail;
521        }
522        if (fxp_is_verbose) {
523                device_printf(dev, "using %s space register mapping\n",
524                   sc->rtp == SYS_RES_MEMORY? "memory" : "I/O");
525        }
526
527        sc->sc_st = rman_get_bustag(sc->mem);
528        sc->sc_sh = rman_get_bushandle(sc->mem);
529
530        /*
531         * Allocate our interrupt.
532         */
533        rid = 0;
534        sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
535                                 RF_SHAREABLE | RF_ACTIVE);
536        if (sc->irq == NULL) {
537                device_printf(dev, "could not map interrupt\n");
538                error = ENXIO;
539                goto fail;
540        }
541
542        error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
543                               fxp_intr, sc, &sc->ih);
544        if (error) {
545                device_printf(dev, "could not setup irq\n");
546                goto fail;
547        }
548#endif
549
550        /*
551         * get mapping and base address of registers
552         */
553        pcib_conf_read16(sc->pci_signature, PCI_COMMAND,&val16);
554        DBGLVL_PRINTK(4,"fxp_attach: PCI_COMMAND_read  = 0x%x\n",val16);
555        if((val16 & PCI_COMMAND_IO) != 0) {
556          sc->pci_regs_are_io = TRUE;
557          pcib_conf_read32(sc->pci_signature,
558                           PCI_BASE_ADDRESS_1,
559                           &val32);       
560          sc->pci_regs_base = val32 & PCI_BASE_ADDRESS_IO_MASK;
561        }
562        else {
563          sc->pci_regs_are_io = FALSE;
564          pcib_conf_read32(sc->pci_signature,
565                           PCI_BASE_ADDRESS_0,
566                           &val32);
567          sc->pci_regs_base = val32 & PCI_BASE_ADDRESS_MEM_MASK;
568        }
569        DBGLVL_PRINTK(3,"fxp_attach: CSR registers are mapped in %s space"
570                      " at address 0x%x\n",
571                      sc->pci_regs_are_io ? "I/O" : "MEM",
572                      sc->pci_regs_base);
573
574        /*
575         * get interrupt level to be used
576         */
577        pcib_conf_read8(sc->pci_signature, 60, &interrupt);
578        DBGLVL_PRINTK(3,"fxp_attach: interrupt = 0x%x\n",interrupt);
579        sc->irqInfo.name = (rtems_irq_symbolic_name)interrupt;
580        /*
581         * Set up interrupts
582         */
583        sc->irqInfo.hdl = (rtems_irq_hdl)fxp_intr;
584        sc->irqInfo.on  = nopOn;
585        sc->irqInfo.off = nopOn;
586        sc->irqInfo.isOn = fxpIsOn; 
587        s = BSP_install_rtems_irq_handler (&sc->irqInfo);
588        if (!s)
589          rtems_panic ("Can't attach fxp interrupt handler for irq %d\n",
590                       sc->irqInfo.name);
591        /*
592         * Reset to a stable state.
593        CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
594         */
595        CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
596        DELAY(10);
597
598        sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB,
599            M_DEVBUF, M_NOWAIT);
600        DBGLVL_PRINTK(3,"fxp_attach: sc->cbl_base = 0x%x\n",sc->cbl_base);
601        if (sc->cbl_base == NULL)
602                goto failmem;
603        else
604                bzero(sc->cbl_base,sizeof(struct fxp_cb_tx) * FXP_NTXCB);
605
606        sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF,
607            M_NOWAIT);
608        DBGLVL_PRINTK(3,"fxp_attach: sc->fxp_stats = 0x%x\n",sc->fxp_stats);
609        if (sc->fxp_stats == NULL)
610                goto failmem;
611        else
612                bzero(sc->fxp_stats,sizeof(struct fxp_stats));
613
614        sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT);
615        DBGLVL_PRINTK(3,"fxp_attach: sc->mcsp = 0x%x\n",sc->mcsp);
616        if (sc->mcsp == NULL)
617                goto failmem;
618
619        /*
620         * Pre-allocate our receive buffers.
621         */
622        for (i = 0; i < FXP_NRFABUFS; i++) {
623                if (fxp_add_rfabuf(sc, NULL) != 0) {
624                        goto failmem;
625                }
626        }
627
628        /*
629         * Find out how large of an SEEPROM we have.
630         */
631        DBGLVL_PRINTK(3,"fxp_attach: calling fxp_autosize_eeprom\n");
632        fxp_autosize_eeprom(sc);
633
634        /*
635         * Determine whether we must use the 503 serial interface.
636         */
637        fxp_read_eeprom(sc, &data, 6, 1);
638        if ((data & FXP_PHY_DEVICE_MASK) != 0 &&
639            (data & FXP_PHY_SERIAL_ONLY))
640                sc->flags |= FXP_FLAG_SERIAL_MEDIA;
641
642        /*
643         * Find out the basic controller type; we currently only
644         * differentiate between a 82557 and greater.
645         */
646        fxp_read_eeprom(sc, &data, 5, 1);
647        if ((data >> 8) == 1)
648                sc->chip = FXP_CHIP_82557;
649        DBGLVL_PRINTK(3,"fxp_attach: sc->chip = %d\n",sc->chip);
650
651        /*
652         * Enable workarounds for certain chip revision deficiencies.
653         *
654         * Systems based on the ICH2/ICH2-M chip from Intel have a defect
655         * where the chip can cause a PCI protocol violation if it receives
656         * a CU_RESUME command when it is entering the IDLE state.  The
657         * workaround is to disable Dynamic Standby Mode, so the chip never
658         * deasserts CLKRUN#, and always remains in an active state.
659         *
660         * See Intel 82801BA/82801BAM Specification Update, Errata #30.
661         */
662#ifdef NOTUSED
663        i = pci_get_device(dev);
664#else
665        pcib_conf_read16(sc->pci_signature,2,&dev_id);
666        DBGLVL_PRINTK(3,"fxp_attach: device id = 0x%x\n",dev_id);
667#endif
668        if (dev_id == 0x2449 || (dev_id > 0x1030 && dev_id < 0x1039)) {
669        device_printf(dev, "*** See Intel 82801BA/82801BAM Specification Update, Errata #30. ***\n");
670                fxp_read_eeprom(sc, &data, 10, 1);
671                if (data & 0x02) {                      /* STB enable */
672                        u_int16_t cksum;
673                        int i;
674
675                        device_printf(dev,
676                    "*** DISABLING DYNAMIC STANDBY MODE IN EEPROM ***\n");
677                        data &= ~0x02;
678                        fxp_write_eeprom(sc, &data, 10, 1);
679                        device_printf(dev, "New EEPROM ID: 0x%x\n", data);
680                        cksum = 0;
681                        for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
682                                fxp_read_eeprom(sc, &data, i, 1);
683                                cksum += data;
684                        }
685                        i = (1 << sc->eeprom_size) - 1;
686                        cksum = 0xBABA - cksum;
687                        fxp_read_eeprom(sc, &data, i, 1);
688                        fxp_write_eeprom(sc, &cksum, i, 1);
689                        device_printf(dev,
690                            "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
691                            i, data, cksum);
692                        /*
693                         * We need to do a full PCI reset here.  A software
694                         * reset to the port doesn't cut it, but let's try
695                         * anyway.
696                         */
697                        CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
698                        DELAY(50);
699                        device_printf(dev,
700            "*** PLEASE REBOOT THE SYSTEM NOW FOR CORRECT OPERATION ***\n");
701#if 1
702                        /*
703                         * If the user elects to continue, try the software
704                         * workaround, as it is better than nothing.
705                         */
706                        sc->flags |= FXP_FLAG_CU_RESUME_BUG;
707#endif
708                }
709        }
710
711        /*
712         * If we are not a 82557 chip, we can enable extended features.
713         */
714        if (sc->chip != FXP_CHIP_82557) {
715          u_int8_t tmp_val;
716                /*
717                 * If MWI is enabled in the PCI configuration, and there
718                 * is a valid cacheline size (8 or 16 dwords), then tell
719                 * the board to turn on MWI.
720                 */
721                pcib_conf_read8(sc->pci_signature,
722                                PCI_CACHE_LINE_SIZE,&tmp_val);
723                DBGLVL_PRINTK(3,"fxp_attach: CACHE_LINE_SIZE = %d\n",tmp_val);
724                if (val16 & PCI_COMMAND_MEMORY &&
725                    tmp_val != 0)
726                        sc->flags |= FXP_FLAG_MWI_ENABLE;
727
728                /* turn on the extended TxCB feature */
729                sc->flags |= FXP_FLAG_EXT_TXCB;
730
731                /* enable reception of long frames for VLAN */
732                sc->flags |= FXP_FLAG_LONG_PKT_EN;
733                DBGLVL_PRINTK(3,"fxp_attach: sc->flags = 0x%x\n",
734                              sc->flags);
735        }
736
737        /*
738         * Read MAC address.
739         */
740        fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3);
741        if (fxp_is_verbose) {
742            device_printf(dev, "Ethernet address %x:%x:%x:%x:%x:%x %s \n",
743                ((u_int8_t *)sc->arpcom.ac_enaddr)[0],
744                ((u_int8_t *)sc->arpcom.ac_enaddr)[1],
745            ((u_int8_t *)sc->arpcom.ac_enaddr)[2],
746            ((u_int8_t *)sc->arpcom.ac_enaddr)[3],
747            ((u_int8_t *)sc->arpcom.ac_enaddr)[4],
748            ((u_int8_t *)sc->arpcom.ac_enaddr)[5],
749            sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : "");
750                device_printf(dev, "PCI IDs: 0x%x 0x%x 0x%x 0x%x 0x%x\n",
751                    pci_get_vendor(sc), pci_get_device(sc),
752                    pci_get_subvendor(sc), pci_get_subdevice(sc),
753                    pci_get_revid(sc));
754                device_printf(dev, "Chip Type: %d\n", sc->chip);
755        }
756
757#ifdef NOTUSED /* do not set up interface at all... */
758        /*
759         * If this is only a 10Mbps device, then there is no MII, and
760         * the PHY will use a serial interface instead.
761         *
762         * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
763         * doesn't have a programming interface of any sort.  The
764         * media is sensed automatically based on how the link partner
765         * is configured.  This is, in essence, manual configuration.
766         */
767        if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
768                ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
769                    fxp_serial_ifmedia_sts);
770                ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
771                ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
772        } else {
773                if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
774                    fxp_ifmedia_sts)) {
775                        device_printf(dev, "MII without any PHY!\n");
776                        error = ENXIO;
777                        goto fail;
778                }
779        }
780#endif
781        if (config->mtu)
782                mtu = config->mtu;
783        else
784                mtu = ETHERMTU;
785
786        ifp->if_softc = sc;
787        ifp->if_unit = unitNumber;
788        ifp->if_name = unitName;
789        ifp->if_mtu  = mtu;
790        ifp->if_baudrate = 100000000;
791        ifp->if_init = fxp_init;
792        ifp->if_ioctl = fxp_ioctl;
793        ifp->if_start = fxp_start;
794        ifp->if_output = ether_output;
795        ifp->if_watchdog = fxp_watchdog;
796        ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX /*| IFF_MULTICAST*/;
797        if (ifp->if_snd.ifq_maxlen == 0)
798                ifp->if_snd.ifq_maxlen = ifqmaxlen;
799
800        /*
801         * Attach the interface.
802         */
803        DBGLVL_PRINTK(3,"fxp_attach: calling if_attach\n");
804        if_attach (ifp);
805        DBGLVL_PRINTK(3,"fxp_attach: calling ether_if_attach\n");
806        ether_ifattach(ifp);
807        DBGLVL_PRINTK(3,"fxp_attach: return from ether_if_attach\n");
808
809#ifdef NOTUSED
810        /*
811         * Tell the upper layer(s) we support long frames.
812         */
813        ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
814#endif
815        /*
816         * Let the system queue as many packets as we have available
817         * TX descriptors.
818         */
819        ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1;
820
821        splx(s);
822        return (0);
823
824failmem:
825        device_printf(dev, "Failed to malloc memory\n");
826        error = ENOMEM;
827#ifdef NOTUSED
828fail:
829#endif
830        splx(s);
831        fxp_release(sc);
832        return (error);
833}
834
835/*
836 * release all resources
837 */
838static void
839fxp_release(struct fxp_softc *sc)
840{
841
842#ifdef NOTUSED
843        bus_generic_detach(sc->dev);
844        if (sc->miibus)
845                device_delete_child(sc->dev, sc->miibus);
846#endif
847        if (sc->cbl_base)
848                free(sc->cbl_base, M_DEVBUF);
849        if (sc->fxp_stats)
850                free(sc->fxp_stats, M_DEVBUF);
851        if (sc->mcsp)
852                free(sc->mcsp, M_DEVBUF);
853        if (sc->rfa_headm)
854                m_freem(sc->rfa_headm);
855
856#ifdef NOTUSED
857        if (sc->ih)
858                bus_teardown_intr(sc->dev, sc->irq, sc->ih);
859        if (sc->irq)
860                bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
861        if (sc->mem)
862                bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem);
863        mtx_destroy(&sc->sc_mtx);
864#endif
865}
866
867#if NOTUSED
868/*
869 * Detach interface.
870 */
871static int
872fxp_detach(device_t dev)
873{
874        struct fxp_softc *sc = device_get_softc(dev);
875        int s;
876
877        /* disable interrupts */
878        CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
879
880        s = splimp();
881
882        /*
883         * Stop DMA and drop transmit queue.
884         */
885        fxp_stop(sc);
886
887        /*
888         * Close down routes etc.
889         */
890        ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED);
891
892        /*
893         * Free all media structures.
894         */
895        ifmedia_removeall(&sc->sc_media);
896
897        splx(s);
898
899        /* Release our allocated resources. */
900        fxp_release(sc);
901
902        return (0);
903}
904
905/*
906 * Device shutdown routine. Called at system shutdown after sync. The
907 * main purpose of this routine is to shut off receiver DMA so that
908 * kernel memory doesn't get clobbered during warmboot.
909 */
910static int
911fxp_shutdown(device_t dev)
912{
913        /*
914         * Make sure that DMA is disabled prior to reboot. Not doing
915         * do could allow DMA to corrupt kernel memory during the
916         * reboot before the driver initializes.
917         */
918        fxp_stop((struct fxp_softc *) device_get_softc(dev));
919        return (0);
920}
921#endif
922
923/*
924 * Show interface statistics
925 */
926static void
927fxp_stats(struct fxp_softc *sc)
928{
929        struct ifnet *ifp = &sc->sc_if;
930
931        printf ("   Output packets:%-8lu", ifp->if_opackets);
932        printf ("    Collisions:%-8lu", ifp->if_collisions);
933        printf (" Output errors:%-8lu\n", ifp->if_oerrors);
934        printf ("    Input packets:%-8lu", ifp->if_ipackets);
935        printf ("  Input errors:%-8lu\n", ifp->if_ierrors);
936}
937
938static void
939fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
940{
941        u_int16_t reg;
942        int x;
943
944        /*
945         * Shift in data.
946         */
947        for (x = 1 << (length - 1); x; x >>= 1) {
948                if (data & x)
949                        reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
950                else
951                        reg = FXP_EEPROM_EECS;
952                CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
953                DELAY(1);
954                CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
955                DELAY(1);
956                CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
957                DELAY(1);
958        }
959}
960
961/*
962 * Read from the serial EEPROM. Basically, you manually shift in
963 * the read opcode (one bit at a time) and then shift in the address,
964 * and then you shift out the data (all of this one bit at a time).
965 * The word size is 16 bits, so you have to provide the address for
966 * every 16 bits of data.
967 */
968static u_int16_t
969fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
970{
971        u_int16_t reg, data;
972        int x;
973
974        CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
975        /*
976         * Shift in read opcode.
977         */
978        fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
979        /*
980         * Shift in address.
981         */
982        data = 0;
983        for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
984                if (offset & x)
985                        reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
986                else
987                        reg = FXP_EEPROM_EECS;
988                CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
989                DELAY(1);
990                CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
991                DELAY(1);
992                CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
993                DELAY(1);
994                reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
995                data++;
996                if (autosize && reg == 0) {
997                        sc->eeprom_size = data;
998                        break;
999                }
1000        }
1001        /*
1002         * Shift out data.
1003         */
1004        data = 0;
1005        reg = FXP_EEPROM_EECS;
1006        for (x = 1 << 15; x; x >>= 1) {
1007                CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1008                DELAY(1);
1009                if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1010                        data |= x;
1011                CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1012                DELAY(1);
1013        }
1014        CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1015        DELAY(1);
1016
1017        return (data);
1018}
1019
1020static void
1021fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data)
1022{
1023        int i;
1024
1025        /*
1026         * Erase/write enable.
1027         */
1028        CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1029        fxp_eeprom_shiftin(sc, 0x4, 3);
1030        fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1031        CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1032        DELAY(1);
1033        /*
1034         * Shift in write opcode, address, data.
1035         */
1036        CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1037        fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1038        fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1039        fxp_eeprom_shiftin(sc, data, 16);
1040        CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1041        DELAY(1);
1042        /*
1043         * Wait for EEPROM to finish up.
1044         */
1045        CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1046        DELAY(1);
1047        for (i = 0; i < 1000; i++) {
1048                if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1049                        break;
1050                DELAY(50);
1051        }
1052        CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1053        DELAY(1);
1054        /*
1055         * Erase/write disable.
1056         */
1057        CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1058        fxp_eeprom_shiftin(sc, 0x4, 3);
1059        fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1060        CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1061        DELAY(1);
1062}
1063
1064/*
1065 * From NetBSD:
1066 *
1067 * Figure out EEPROM size.
1068 *
1069 * 559's can have either 64-word or 256-word EEPROMs, the 558
1070 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1071 * talks about the existance of 16 to 256 word EEPROMs.
1072 *
1073 * The only known sizes are 64 and 256, where the 256 version is used
1074 * by CardBus cards to store CIS information.
1075 *
1076 * The address is shifted in msb-to-lsb, and after the last
1077 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1078 * after which follows the actual data. We try to detect this zero, by
1079 * probing the data-out bit in the EEPROM control register just after
1080 * having shifted in a bit. If the bit is zero, we assume we've
1081 * shifted enough address bits. The data-out should be tri-state,
1082 * before this, which should translate to a logical one.
1083 */
1084static void
1085fxp_autosize_eeprom(struct fxp_softc *sc)
1086{
1087
1088        /* guess maximum size of 256 words */
1089        sc->eeprom_size = 8;
1090
1091        /* autosize */
1092        (void) fxp_eeprom_getword(sc, 0, 1);
1093}
1094
1095static void
1096fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1097{
1098        int i;
1099
1100        for (i = 0; i < words; i++) {
1101                data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1102                DBGLVL_PRINTK(4,"fxp_eeprom_read(off=0x%x)=0x%x\n",
1103                              offset+i,data[i]);
1104        }
1105}
1106
1107static void
1108fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1109{
1110        int i;
1111
1112        for (i = 0; i < words; i++)
1113                fxp_eeprom_putword(sc, offset + i, data[i]);
1114                DBGLVL_PRINTK(4,"fxp_eeprom_write(off=0x%x,0x%x)\n",
1115                              offset+i,data[i]);
1116}
1117
1118/*
1119 * Start packet transmission on the interface.
1120 */
1121static void
1122fxp_start(struct ifnet *ifp)
1123{
1124        struct fxp_softc *sc = ifp->if_softc;
1125        struct fxp_cb_tx *txp;
1126
1127        DBGLVL_PRINTK(3,"fxp_start called\n");
1128
1129        /*
1130         * See if we need to suspend xmit until the multicast filter
1131         * has been reprogrammed (which can only be done at the head
1132         * of the command chain).
1133         */
1134        if (sc->need_mcsetup) {
1135                return;
1136        }
1137
1138        txp = NULL;
1139
1140        /*
1141         * We're finished if there is nothing more to add to the list or if
1142         * we're all filled up with buffers to transmit.
1143         * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1144         *       a NOP command when needed.
1145         */
1146        while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) {
1147                struct mbuf *m, *mb_head;
1148                int segment;
1149
1150                /*
1151                 * Grab a packet to transmit.
1152                 */
1153                IF_DEQUEUE(&ifp->if_snd, mb_head);
1154
1155                /*
1156                 * Get pointer to next available tx desc.
1157                 */
1158                txp = sc->cbl_last->next;
1159
1160                /*
1161                 * Go through each of the mbufs in the chain and initialize
1162                 * the transmit buffer descriptors with the physical address
1163                 * and size of the mbuf.
1164                 */
1165tbdinit:
1166                for (m = mb_head, segment = 0; m != NULL; m = m->m_next) {
1167                        if (m->m_len != 0) {
1168                                if (segment == FXP_NTXSEG)
1169                                        break;
1170                                txp->tbd[segment].tb_addr =
1171                                    vtophys(mtod(m, vm_offset_t));
1172                                txp->tbd[segment].tb_size = m->m_len;
1173                                segment++;
1174                        }
1175                }
1176                if (m != NULL) {
1177                        struct mbuf *mn;
1178
1179                        /*
1180                         * We ran out of segments. We have to recopy this
1181                         * mbuf chain first. Bail out if we can't get the
1182                         * new buffers.
1183                         */
1184                        MGETHDR(mn, M_DONTWAIT, MT_DATA);
1185                        if (mn == NULL) {
1186                                m_freem(mb_head);
1187                                break;
1188                        }
1189                        if (mb_head->m_pkthdr.len > MHLEN) {
1190                                MCLGET(mn, M_DONTWAIT);
1191                                if ((mn->m_flags & M_EXT) == 0) {
1192                                        m_freem(mn);
1193                                        m_freem(mb_head);
1194                                        break;
1195                                }
1196                        }
1197                        m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
1198                            mtod(mn, caddr_t));
1199                        mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len;
1200                        m_freem(mb_head);
1201                        mb_head = mn;
1202                        goto tbdinit;
1203                }
1204
1205                txp->tbd_number = segment;
1206                txp->mb_head = mb_head;
1207                txp->cb_status = 0;
1208                if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1209                        txp->cb_command =
1210                            FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1211                            FXP_CB_COMMAND_S;
1212                } else {
1213                        txp->cb_command =
1214                            FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1215                            FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
1216                        /*
1217                         * Set a 5 second timer just in case we don't hear
1218                         * from the card again.
1219                         */
1220                        ifp->if_timer = 5;
1221                }
1222                txp->tx_threshold = tx_threshold;
1223       
1224                /*
1225                 * Advance the end of list forward.
1226                 */
1227
1228#ifdef __alpha__
1229                /*
1230                 * On platforms which can't access memory in 16-bit
1231                 * granularities, we must prevent the card from DMA'ing
1232                 * up the status while we update the command field.
1233                 * This could cause us to overwrite the completion status.
1234                 */
1235                atomic_clear_short(&sc->cbl_last->cb_command,
1236                    FXP_CB_COMMAND_S);
1237#else
1238                sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
1239#endif /*__alpha__*/
1240                sc->cbl_last = txp;
1241
1242                /*
1243                 * Advance the beginning of the list forward if there are
1244                 * no other packets queued (when nothing is queued, cbl_first
1245                 * sits on the last TxCB that was sent out).
1246                 */
1247                if (sc->tx_queued == 0)
1248                        sc->cbl_first = txp;
1249
1250                sc->tx_queued++;
1251
1252#ifdef NOTUSED
1253                /*
1254                 * Pass packet to bpf if there is a listener.
1255                 */
1256                if (ifp->if_bpf)
1257                        bpf_mtap(ifp, mb_head);
1258#endif
1259        }
1260
1261        /*
1262         * We're finished. If we added to the list, issue a RESUME to get DMA
1263         * going again if suspended.
1264         */
1265        if (txp != NULL) {
1266                fxp_scb_wait(sc);
1267                fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1268        }
1269}
1270
1271/*
1272 * Process interface interrupts.
1273 */
1274static rtems_isr fxp_intr(rtems_vector_number v)
1275{
1276  /*
1277   * FIXME: currently only works with one interface...
1278   */
1279  struct fxp_softc *sc = &(fxp_softc[0]);
1280
1281  /*
1282   * disable interrupts
1283   */
1284  CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1285  /*
1286   * send event to deamon
1287   */
1288  rtems_event_send (sc->daemonTid, INTERRUPT_EVENT);
1289}
1290
1291static void fxp_daemon(void *xsc)
1292{
1293        struct fxp_softc *sc = xsc;
1294        struct ifnet *ifp = &sc->sc_if;
1295        u_int8_t statack;
1296        rtems_event_set events;
1297        rtems_interrupt_level level;
1298
1299#ifdef NOTUSED
1300        if (sc->suspended) {
1301                return;
1302        }
1303#endif
1304        for (;;) {
1305
1306        DBGLVL_PRINTK(4,"fxp_daemon waiting for event\n");
1307          /*
1308           * wait for event to receive from interrupt function
1309           */
1310          rtems_bsdnet_event_receive (INTERRUPT_EVENT,
1311                                      RTEMS_WAIT|RTEMS_EVENT_ANY,
1312                                      RTEMS_NO_TIMEOUT,
1313                                      &events);
1314          while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1315            DBGLVL_PRINTK(4,"fxp_daemon: processing event, statack = 0x%x\n",
1316                          statack);
1317#ifdef NOTUSED
1318                /*
1319                 * It should not be possible to have all bits set; the
1320                 * FXP_SCB_INTR_SWI bit always returns 0 on a read.  If
1321                 * all bits are set, this may indicate that the card has
1322                 * been physically ejected, so ignore it.
1323                 */ 
1324                if (statack == 0xff)
1325                        return;
1326#endif
1327
1328                /*
1329                 * First ACK all the interrupts in this pass.
1330                 */
1331                CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1332
1333                /*
1334                 * Free any finished transmit mbuf chains.
1335                 *
1336                 * Handle the CNA event likt a CXTNO event. It used to
1337                 * be that this event (control unit not ready) was not
1338                 * encountered, but it is now with the SMPng modifications.
1339                 * The exact sequence of events that occur when the interface
1340                 * is brought up are different now, and if this event
1341                 * goes unhandled, the configuration/rxfilter setup sequence
1342                 * can stall for several seconds. The result is that no
1343                 * packets go out onto the wire for about 5 to 10 seconds
1344                 * after the interface is ifconfig'ed for the first time.
1345                 */
1346                if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) {
1347                        struct fxp_cb_tx *txp;
1348
1349                        for (txp = sc->cbl_first; sc->tx_queued &&
1350                            (txp->cb_status & FXP_CB_STATUS_C) != 0;
1351                            txp = txp->next) {
1352                                if (txp->mb_head != NULL) {
1353                                        m_freem(txp->mb_head);
1354                                        txp->mb_head = NULL;
1355                                }
1356                                sc->tx_queued--;
1357                        }
1358                        sc->cbl_first = txp;
1359                        ifp->if_timer = 0;
1360                        if (sc->tx_queued == 0) {
1361                                if (sc->need_mcsetup)
1362                                        fxp_mc_setup(sc);
1363                        }
1364                        /*
1365                         * Try to start more packets transmitting.
1366                         */
1367                        if (ifp->if_snd.ifq_head != NULL)
1368                                fxp_start(ifp);
1369                }
1370                /*
1371                 * Process receiver interrupts. If a no-resource (RNR)
1372                 * condition exists, get whatever packets we can and
1373                 * re-start the receiver.
1374                 */
1375                if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) {
1376                        struct mbuf *m;
1377                        struct fxp_rfa *rfa;
1378rcvloop:
1379                        m = sc->rfa_headm;
1380                        rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1381                            RFA_ALIGNMENT_FUDGE);
1382
1383                        if (rfa->rfa_status & FXP_RFA_STATUS_C) {
1384                                /*
1385                                 * Remove first packet from the chain.
1386                                 */
1387                                sc->rfa_headm = m->m_next;
1388                                m->m_next = NULL;
1389
1390                                /*
1391                                 * Add a new buffer to the receive chain.
1392                                 * If this fails, the old buffer is recycled
1393                                 * instead.
1394                                 */
1395                                if (fxp_add_rfabuf(sc, m) == 0) {
1396                                        struct ether_header *eh;
1397                                        int total_len;
1398
1399                                        total_len = rfa->actual_size &
1400                                            (MCLBYTES - 1);
1401                                        if (total_len <
1402                                            sizeof(struct ether_header)) {
1403                                                m_freem(m);
1404                                                goto rcvloop;
1405                                        }
1406
1407                                        /*
1408                                         * Drop the packet if it has CRC
1409                                         * errors.  This test is only needed
1410                                         * when doing 802.1q VLAN on the 82557
1411                                         * chip.
1412                                         */
1413                                        if (rfa->rfa_status &
1414                                            FXP_RFA_STATUS_CRC) {
1415                                                m_freem(m);
1416                                                goto rcvloop;
1417                                        }
1418
1419                                        m->m_pkthdr.rcvif = ifp;
1420                                        m->m_pkthdr.len = m->m_len = total_len;
1421                                        eh = mtod(m, struct ether_header *);
1422                                        m->m_data +=
1423                                            sizeof(struct ether_header);
1424                                        m->m_len -=
1425                                            sizeof(struct ether_header);
1426                                        m->m_pkthdr.len = m->m_len;
1427                                        ether_input(ifp, eh, m);
1428                                }
1429                                goto rcvloop;
1430                        }
1431                        if (statack & FXP_SCB_STATACK_RNR) {
1432                                fxp_scb_wait(sc);
1433                                CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1434                                    vtophys(sc->rfa_headm->m_ext.ext_buf) +
1435                                        RFA_ALIGNMENT_FUDGE);
1436                                fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1437                        }
1438                }
1439          }
1440          /*
1441           * reenable interrupts
1442           */
1443          rtems_interrupt_disable (level);
1444          CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,0);
1445          rtems_interrupt_enable (level);
1446        }
1447}
1448
1449/*
1450 * Update packet in/out/collision statistics. The i82557 doesn't
1451 * allow you to access these counters without doing a fairly
1452 * expensive DMA to get _all_ of the statistics it maintains, so
1453 * we do this operation here only once per second. The statistics
1454 * counters in the kernel are updated from the previous dump-stats
1455 * DMA and then a new dump-stats DMA is started. The on-chip
1456 * counters are zeroed when the DMA completes. If we can't start
1457 * the DMA immediately, we don't wait - we just prepare to read
1458 * them again next time.
1459 */
1460static void
1461fxp_tick(void *xsc)
1462{
1463        struct fxp_softc *sc = xsc;
1464        struct ifnet *ifp = &sc->sc_if;
1465        struct fxp_stats *sp = sc->fxp_stats;
1466        struct fxp_cb_tx *txp;
1467        int s;
1468
1469        DBGLVL_PRINTK(4,"fxp_tick called\n");
1470
1471        ifp->if_opackets += sp->tx_good;
1472        ifp->if_collisions += sp->tx_total_collisions;
1473        if (sp->rx_good) {
1474                ifp->if_ipackets += sp->rx_good;
1475                sc->rx_idle_secs = 0;
1476        } else {
1477                /*
1478                 * Receiver's been idle for another second.
1479                 */
1480                sc->rx_idle_secs++;
1481        }
1482        ifp->if_ierrors +=
1483            sp->rx_crc_errors +
1484            sp->rx_alignment_errors +
1485            sp->rx_rnr_errors +
1486            sp->rx_overrun_errors;
1487        /*
1488         * If any transmit underruns occured, bump up the transmit
1489         * threshold by another 512 bytes (64 * 8).
1490         */
1491        if (sp->tx_underruns) {
1492                ifp->if_oerrors += sp->tx_underruns;
1493                if (tx_threshold < 192)
1494                        tx_threshold += 64;
1495        }
1496        s = splimp();
1497        /*
1498         * Release any xmit buffers that have completed DMA. This isn't
1499         * strictly necessary to do here, but it's advantagous for mbufs
1500         * with external storage to be released in a timely manner rather
1501         * than being defered for a potentially long time. This limits
1502         * the delay to a maximum of one second.
1503         */
1504        for (txp = sc->cbl_first; sc->tx_queued &&
1505            (txp->cb_status & FXP_CB_STATUS_C) != 0;
1506            txp = txp->next) {
1507                if (txp->mb_head != NULL) {
1508                        m_freem(txp->mb_head);
1509                        txp->mb_head = NULL;
1510                }
1511                sc->tx_queued--;
1512        }
1513        sc->cbl_first = txp;
1514        /*
1515         * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1516         * then assume the receiver has locked up and attempt to clear
1517         * the condition by reprogramming the multicast filter. This is
1518         * a work-around for a bug in the 82557 where the receiver locks
1519         * up if it gets certain types of garbage in the syncronization
1520         * bits prior to the packet header. This bug is supposed to only
1521         * occur in 10Mbps mode, but has been seen to occur in 100Mbps
1522         * mode as well (perhaps due to a 10/100 speed transition).
1523         */
1524        if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1525                sc->rx_idle_secs = 0;
1526                fxp_mc_setup(sc);
1527        }
1528        /*
1529         * If there is no pending command, start another stats
1530         * dump. Otherwise punt for now.
1531         */
1532        if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1533                /*
1534                 * Start another stats dump.
1535                 */
1536                fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1537        } else {
1538                /*
1539                 * A previous command is still waiting to be accepted.
1540                 * Just zero our copy of the stats and wait for the
1541                 * next timer event to update them.
1542                 */
1543                sp->tx_good = 0;
1544                sp->tx_underruns = 0;
1545                sp->tx_total_collisions = 0;
1546
1547                sp->rx_good = 0;
1548                sp->rx_crc_errors = 0;
1549                sp->rx_alignment_errors = 0;
1550                sp->rx_rnr_errors = 0;
1551                sp->rx_overrun_errors = 0;
1552        }
1553#ifdef NOTUSED
1554        if (sc->miibus != NULL)
1555                mii_tick(device_get_softc(sc->miibus));
1556#endif
1557        splx(s);
1558        /*
1559         * Schedule another timeout one second from now.
1560         */
1561        if (sc->stat_ch == fxp_timeout_running) {
1562          timeout(fxp_tick, sc, hz);
1563        }
1564        else if (sc->stat_ch == fxp_timeout_stop_rq) {
1565          sc->stat_ch = fxp_timeout_stopped;
1566        }         
1567}
1568
1569/*
1570 * Stop the interface. Cancels the statistics updater and resets
1571 * the interface.
1572 */
1573static void
1574fxp_stop(struct fxp_softc *sc)
1575{
1576        struct ifnet *ifp = &sc->sc_if;
1577        struct fxp_cb_tx *txp;
1578        int i;
1579
1580        DBGLVL_PRINTK(2,"fxp_stop called\n");
1581
1582        ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1583        ifp->if_timer = 0;
1584
1585        /*
1586         * stop stats updater.
1587         */
1588        if (sc->stat_ch == fxp_timeout_running) {
1589          DBGLVL_PRINTK(3,"fxp_stop: trying to stop stat update tick\n");
1590          sc->stat_ch = fxp_timeout_stop_rq;
1591          while(sc->stat_ch != fxp_timeout_stopped) {
1592            rtems_bsdnet_semaphore_release();
1593            rtems_task_wake_after(fxp_ticksPerSecond);
1594            rtems_bsdnet_semaphore_obtain();
1595          }
1596          DBGLVL_PRINTK(3,"fxp_stop: stat update tick stopped\n");
1597        }
1598        /*
1599         * Issue software reset
1600         */
1601        DBGLVL_PRINTK(3,"fxp_stop: issue software reset\n");
1602        CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1603        DELAY(10);
1604
1605        /*
1606         * Release any xmit buffers.
1607         */
1608        DBGLVL_PRINTK(3,"fxp_stop: releasing xmit buffers\n");
1609        txp = sc->cbl_base;
1610        if (txp != NULL) {
1611                for (i = 0; i < FXP_NTXCB; i++) {
1612                        if (txp[i].mb_head != NULL) {
1613                                m_freem(txp[i].mb_head);
1614                                txp[i].mb_head = NULL;
1615                        }
1616                }
1617        }
1618        sc->tx_queued = 0;
1619
1620        /*
1621         * Free all the receive buffers then reallocate/reinitialize
1622         */
1623        DBGLVL_PRINTK(3,"fxp_stop: free and reinit all receive buffers\n");
1624        if (sc->rfa_headm != NULL)
1625                m_freem(sc->rfa_headm);
1626        sc->rfa_headm = NULL;
1627        sc->rfa_tailm = NULL;
1628        for (i = 0; i < FXP_NRFABUFS; i++) {
1629                if (fxp_add_rfabuf(sc, NULL) != 0) {
1630                        /*
1631                         * This "can't happen" - we're at splimp()
1632                         * and we just freed all the buffers we need
1633                         * above.
1634                         */
1635                        panic("fxp_stop: no buffers!");
1636                }
1637        }
1638        DBGLVL_PRINTK(2,"fxp_stop: finished\n");
1639}
1640
1641/*
1642 * Watchdog/transmission transmit timeout handler. Called when a
1643 * transmission is started on the interface, but no interrupt is
1644 * received before the timeout. This usually indicates that the
1645 * card has wedged for some reason.
1646 */
1647static void
1648fxp_watchdog(struct ifnet *ifp)
1649{
1650        struct fxp_softc *sc = ifp->if_softc;
1651
1652        device_printf(sc->dev, "device timeout\n");
1653        ifp->if_oerrors++;
1654
1655        fxp_init(sc);
1656}
1657
1658static void
1659fxp_init(void *xsc)
1660{
1661        struct fxp_softc *sc = xsc;
1662        struct ifnet *ifp = &sc->sc_if;
1663        struct fxp_cb_config *cbp;
1664        struct fxp_cb_ias *cb_ias;
1665        struct fxp_cb_tx *txp;
1666        int i, prm, s;
1667
1668rtems_task_wake_after(100);
1669        DBGLVL_PRINTK(2,"fxp_init called\n");
1670
1671        s = splimp();
1672        /*
1673         * Cancel any pending I/O
1674         */
1675        fxp_stop(sc);
1676
1677        prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1678
1679        DBGLVL_PRINTK(5,"fxp_init: Initializing base of CBL and RFA memory\n");
1680        /*
1681         * Initialize base of CBL and RFA memory. Loading with zero
1682         * sets it up for regular linear addressing.
1683         */
1684        CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1685        fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
1686
1687        fxp_scb_wait(sc);
1688        fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
1689
1690        /*
1691         * Initialize base of dump-stats buffer.
1692         */
1693        DBGLVL_PRINTK(5,"fxp_init: Initializing base of dump-stats buffer\n");
1694        fxp_scb_wait(sc);
1695        CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats));
1696        fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
1697
1698        /*
1699         * We temporarily use memory that contains the TxCB list to
1700         * construct the config CB. The TxCB list memory is rebuilt
1701         * later.
1702         */
1703        cbp = (struct fxp_cb_config *) sc->cbl_base;
1704        DBGLVL_PRINTK(5,"fxp_init: cbp = 0x%x\n",cbp);
1705
1706        /*
1707         * This bcopy is kind of disgusting, but there are a bunch of must be
1708         * zero and must be one bits in this structure and this is the easiest
1709         * way to initialize them all to proper values.
1710         */
1711        bcopy(fxp_cb_config_template,
1712                (void *)(u_int32_t *)(volatile void *)&cbp->cb_status,
1713                sizeof(fxp_cb_config_template));
1714
1715        cbp->cb_status =        0;
1716        cbp->cb_command =       FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL;
1717        cbp->link_addr =        -1;     /* (no) next command */
1718        cbp->byte_count =       22;     /* (22) bytes to config */
1719        cbp->rx_fifo_limit =    8;      /* rx fifo threshold (32 bytes) */
1720        cbp->tx_fifo_limit =    0;      /* tx fifo threshold (0 bytes) */
1721        cbp->adaptive_ifs =     0;      /* (no) adaptive interframe spacing */
1722        cbp->mwi_enable =       sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
1723        cbp->type_enable =      0;      /* actually reserved */
1724        cbp->read_align_en =    sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
1725        cbp->end_wr_on_cl =     sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
1726        cbp->rx_dma_bytecount = 0;      /* (no) rx DMA max */
1727        cbp->tx_dma_bytecount = 0;      /* (no) tx DMA max */
1728        cbp->dma_mbce =         0;      /* (disable) dma max counters */
1729        cbp->late_scb =         0;      /* (don't) defer SCB update */
1730        cbp->direct_dma_dis =   1;      /* disable direct rcv dma mode */
1731        cbp->tno_int_or_tco_en =0;      /* (disable) tx not okay interrupt */
1732        cbp->ci_int =           1;      /* interrupt on CU idle */
1733        cbp->ext_txcb_dis =     sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
1734        cbp->ext_stats_dis =    1;      /* disable extended counters */
1735        cbp->keep_overrun_rx =  0;      /* don't pass overrun frames to host */
1736        cbp->save_bf =          sc->chip == FXP_CHIP_82557 ? 1 : prm;
1737        cbp->disc_short_rx =    !prm;   /* discard short packets */
1738        cbp->underrun_retry =   1;      /* retry mode (once) on DMA underrun */
1739        cbp->two_frames =       0;      /* do not limit FIFO to 2 frames */
1740        cbp->dyn_tbd =          0;      /* (no) dynamic TBD mode */
1741        cbp->mediatype =        sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
1742        cbp->csma_dis =         0;      /* (don't) disable link */
1743        cbp->tcp_udp_cksum =    0;      /* (don't) enable checksum */
1744        cbp->vlan_tco =         0;      /* (don't) enable vlan wakeup */
1745        cbp->link_wake_en =     0;      /* (don't) assert PME# on link change */
1746        cbp->arp_wake_en =      0;      /* (don't) assert PME# on arp */
1747        cbp->mc_wake_en =       0;      /* (don't) enable PME# on mcmatch */
1748        cbp->nsai =             1;      /* (don't) disable source addr insert */
1749        cbp->preamble_length =  2;      /* (7 byte) preamble */
1750        cbp->loopback =         0;      /* (don't) loopback */
1751        cbp->linear_priority =  0;      /* (normal CSMA/CD operation) */
1752        cbp->linear_pri_mode =  0;      /* (wait after xmit only) */
1753        cbp->interfrm_spacing = 6;      /* (96 bits of) interframe spacing */
1754        cbp->promiscuous =      prm;    /* promiscuous mode */
1755        cbp->bcast_disable =    0;      /* (don't) disable broadcasts */
1756        cbp->wait_after_win =   0;      /* (don't) enable modified backoff alg*/
1757        cbp->ignore_ul =        0;      /* consider U/L bit in IA matching */
1758        cbp->crc16_en =         0;      /* (don't) enable crc-16 algorithm */
1759        cbp->crscdt =           sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
1760
1761        cbp->stripping =        !prm;   /* truncate rx packet to byte count */
1762        cbp->padding =          1;      /* (do) pad short tx packets */
1763        cbp->rcv_crc_xfer =     0;      /* (don't) xfer CRC to host */
1764        cbp->long_rx_en =       sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
1765        cbp->ia_wake_en =       0;      /* (don't) wake up on address match */
1766        cbp->magic_pkt_dis =    0;      /* (don't) disable magic packet */
1767                                        /* must set wake_en in PMCSR also */
1768        cbp->force_fdx =        0;      /* (don't) force full duplex */
1769        cbp->fdx_pin_en =       1;      /* (enable) FDX# pin */
1770        cbp->multi_ia =         0;      /* (don't) accept multiple IAs */
1771        cbp->mc_all =           sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
1772
1773        DBGLVL_PRINTK(5,"fxp_init: cbp initialized\n");
1774        if (sc->chip == FXP_CHIP_82557) {
1775                /*
1776                 * The 82557 has no hardware flow control, the values
1777                 * below are the defaults for the chip.
1778                 */
1779                cbp->fc_delay_lsb =     0;
1780                cbp->fc_delay_msb =     0x40;
1781                cbp->pri_fc_thresh =    3;
1782                cbp->tx_fc_dis =        0;
1783                cbp->rx_fc_restop =     0;
1784                cbp->rx_fc_restart =    0;
1785                cbp->fc_filter =        0;
1786                cbp->pri_fc_loc =       1;
1787        } else {
1788                cbp->fc_delay_lsb =     0x1f;
1789                cbp->fc_delay_msb =     0x01;
1790                cbp->pri_fc_thresh =    3;
1791                cbp->tx_fc_dis =        0;      /* enable transmit FC */
1792                cbp->rx_fc_restop =     1;      /* enable FC restop frames */
1793                cbp->rx_fc_restart =    1;      /* enable FC restart frames */
1794                cbp->fc_filter =        !prm;   /* drop FC frames to host */
1795                cbp->pri_fc_loc =       1;      /* FC pri location (byte31) */
1796        }
1797
1798        /*
1799         * Start the config command/DMA.
1800         */
1801        DBGLVL_PRINTK(5,"fxp_init: starting config command/DMA\n");
1802        fxp_scb_wait(sc);
1803        CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
1804        fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1805        /* ...and wait for it to complete. */
1806        fxp_dma_wait(&cbp->cb_status, sc);
1807
1808        /*
1809         * Now initialize the station address. Temporarily use the TxCB
1810         * memory area like we did above for the config CB.
1811         */
1812        DBGLVL_PRINTK(5,"fxp_init: initialize station address\n");
1813        cb_ias = (struct fxp_cb_ias *) sc->cbl_base;
1814        cb_ias->cb_status = 0;
1815        cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL;
1816        cb_ias->link_addr = -1;
1817        bcopy(sc->arpcom.ac_enaddr,
1818            (void *)(u_int32_t *)(volatile void *)cb_ias->macaddr,
1819            sizeof(sc->arpcom.ac_enaddr));
1820
1821        /*
1822         * Start the IAS (Individual Address Setup) command/DMA.
1823         */
1824        DBGLVL_PRINTK(5,"fxp_init: start IAS command/DMA\n");
1825        fxp_scb_wait(sc);
1826        fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1827        /* ...and wait for it to complete. */
1828        fxp_dma_wait(&cb_ias->cb_status, sc);
1829
1830        /*
1831         * Initialize transmit control block (TxCB) list.
1832         */
1833
1834        DBGLVL_PRINTK(5,"fxp_init: initialize TxCB list\n");
1835        txp = sc->cbl_base;
1836        bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
1837        for (i = 0; i < FXP_NTXCB; i++) {
1838                txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK;
1839                txp[i].cb_command = FXP_CB_COMMAND_NOP;
1840                txp[i].link_addr =
1841                    vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status);
1842                if (sc->flags & FXP_FLAG_EXT_TXCB)
1843                        txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]);
1844                else
1845                        txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]);
1846                txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK];
1847        }
1848        /*
1849         * Set the suspend flag on the first TxCB and start the control
1850         * unit. It will execute the NOP and then suspend.
1851         */
1852        DBGLVL_PRINTK(5,"fxp_init: setup suspend flag\n");
1853        txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S;
1854        sc->cbl_first = sc->cbl_last = txp;
1855        sc->tx_queued = 1;
1856
1857        fxp_scb_wait(sc);
1858        fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1859
1860        /*
1861         * Initialize receiver buffer area - RFA.
1862         */
1863        DBGLVL_PRINTK(5,"fxp_init: initialize RFA\n");
1864        fxp_scb_wait(sc);
1865        CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1866            vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE);
1867        fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1868
1869#ifdef NOTUSED
1870        /*
1871         * Set current media.
1872         */
1873        if (sc->miibus != NULL)
1874                mii_mediachg(device_get_softc(sc->miibus));
1875#endif
1876
1877        ifp->if_flags |= IFF_RUNNING;
1878        ifp->if_flags &= ~IFF_OACTIVE;
1879
1880        if (sc->daemonTid == 0) {
1881                /*
1882                 * Start driver task
1883                 */
1884                sc->daemonTid = rtems_bsdnet_newproc ("FXPd", 4096, fxp_daemon, sc);
1885
1886        }
1887        /*
1888         * Enable interrupts.
1889         */
1890        CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1891        splx(s);
1892
1893        /*
1894         * Start stats updater.
1895         */
1896        sc->stat_ch = fxp_timeout_running;
1897        DBGLVL_PRINTK(2,"fxp_init: stats updater timeout called with hz=%d\n", hz);
1898        timeout(fxp_tick, sc, hz);
1899        DBGLVL_PRINTK(2,"fxp_init finished\n");
1900}
1901
1902#ifdef NOTUSED
1903static int
1904fxp_serial_ifmedia_upd(struct ifnet *ifp)
1905{
1906
1907        return (0);
1908}
1909
1910static void
1911fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1912{
1913
1914        ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
1915}
1916
1917/*
1918 * Change media according to request.
1919 */
1920static int
1921fxp_ifmedia_upd(struct ifnet *ifp)
1922{
1923        struct fxp_softc *sc = ifp->if_softc;
1924        struct mii_data *mii;
1925
1926        mii = device_get_softc(sc->miibus);
1927        mii_mediachg(mii);
1928        return (0);
1929}
1930
1931/*
1932 * Notify the world which media we're using.
1933 */
1934static void
1935fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1936{
1937        struct fxp_softc *sc = ifp->if_softc;
1938        struct mii_data *mii;
1939
1940        mii = device_get_softc(sc->miibus);
1941        mii_pollstat(mii);
1942        ifmr->ifm_active = mii->mii_media_active;
1943        ifmr->ifm_status = mii->mii_media_status;
1944
1945        if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG)
1946                sc->cu_resume_bug = 1;
1947        else
1948                sc->cu_resume_bug = 0;
1949}
1950#endif
1951
1952/*
1953 * Add a buffer to the end of the RFA buffer list.
1954 * Return 0 if successful, 1 for failure. A failure results in
1955 * adding the 'oldm' (if non-NULL) on to the end of the list -
1956 * tossing out its old contents and recycling it.
1957 * The RFA struct is stuck at the beginning of mbuf cluster and the
1958 * data pointer is fixed up to point just past it.
1959 */
1960static int
1961fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm)
1962{
1963        u_int32_t v;
1964        struct mbuf *m;
1965        struct fxp_rfa *rfa, *p_rfa;
1966
1967        DBGLVL_PRINTK(4,"fxp_add_rfabuf called\n");
1968
1969        MGETHDR(m, M_DONTWAIT, MT_DATA);
1970        if (m != NULL) {
1971                MCLGET(m, M_DONTWAIT);
1972                if ((m->m_flags & M_EXT) == 0) {
1973                        m_freem(m);
1974                        if (oldm == NULL)
1975                                return 1;
1976                        m = oldm;
1977                        m->m_data = m->m_ext.ext_buf;
1978                }
1979        } else {
1980                if (oldm == NULL)
1981                        return 1;
1982                m = oldm;
1983                m->m_data = m->m_ext.ext_buf;
1984        }
1985
1986        /*
1987         * Move the data pointer up so that the incoming data packet
1988         * will be 32-bit aligned.
1989         */
1990        m->m_data += RFA_ALIGNMENT_FUDGE;
1991
1992        /*
1993         * Get a pointer to the base of the mbuf cluster and move
1994         * data start past it.
1995         */
1996        rfa = mtod(m, struct fxp_rfa *);
1997        m->m_data += sizeof(struct fxp_rfa);
1998        rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE);
1999
2000        /*
2001         * Initialize the rest of the RFA.  Note that since the RFA
2002         * is misaligned, we cannot store values directly.  Instead,
2003         * we use an optimized, inline copy.
2004         */
2005
2006        rfa->rfa_status = 0;
2007        rfa->rfa_control = FXP_RFA_CONTROL_EL;
2008        rfa->actual_size = 0;
2009
2010        v = -1;
2011        fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr);
2012        fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr);
2013
2014        /*
2015         * If there are other buffers already on the list, attach this
2016         * one to the end by fixing up the tail to point to this one.
2017         */
2018        if (sc->rfa_headm != NULL) {
2019                p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf +
2020                    RFA_ALIGNMENT_FUDGE);
2021                sc->rfa_tailm->m_next = m;
2022                v = vtophys(rfa);
2023                fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr);
2024                p_rfa->rfa_control = 0;
2025        } else {
2026                sc->rfa_headm = m;
2027        }
2028        sc->rfa_tailm = m;
2029
2030        return (m == oldm);
2031}
2032
2033#ifdef NOTUSED
2034static volatile int
2035fxp_miibus_readreg(device_t dev, int phy, int reg)
2036{
2037        struct fxp_softc *sc = device_get_softc(dev);
2038        int count = 10000;
2039        int value;
2040
2041        CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2042            (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2043
2044        while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2045            && count--)
2046                DELAY(10);
2047
2048        if (count <= 0)
2049                device_printf(dev, "fxp_miibus_readreg: timed out\n");
2050
2051        return (value & 0xffff);
2052}
2053
2054static void
2055fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2056{
2057        struct fxp_softc *sc = device_get_softc(dev);
2058        int count = 10000;
2059
2060        CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2061            (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2062            (value & 0xffff));
2063
2064        while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2065            count--)
2066                DELAY(10);
2067
2068        if (count <= 0)
2069                device_printf(dev, "fxp_miibus_writereg: timed out\n");
2070}
2071#endif
2072
2073static int
2074fxp_ioctl(struct ifnet *ifp, int command, caddr_t data)
2075{
2076        struct fxp_softc *sc = ifp->if_softc;
2077#ifdef NOTUSED
2078        struct ifreq *ifr = (struct ifreq *)data;
2079        struct mii_data *mii;
2080#endif
2081        int s, error = 0;
2082
2083        DBGLVL_PRINTK(2,"fxp_ioctl called\n");
2084
2085        s = splimp();
2086
2087        switch (command) {
2088        case SIOCSIFADDR:
2089        case SIOCGIFADDR:
2090        case SIOCSIFMTU:
2091                error = ether_ioctl(ifp, command, data);
2092                break;
2093
2094        case SIOCSIFFLAGS:
2095                if (ifp->if_flags & IFF_ALLMULTI)
2096                        sc->flags |= FXP_FLAG_ALL_MCAST;
2097                else
2098                        sc->flags &= ~FXP_FLAG_ALL_MCAST;
2099
2100                /*
2101                 * If interface is marked up and not running, then start it.
2102                 * If it is marked down and running, stop it.
2103                 * XXX If it's up then re-initialize it. This is so flags
2104                 * such as IFF_PROMISC are handled.
2105                 */
2106                if (ifp->if_flags & IFF_UP) {
2107                        fxp_init(sc);
2108                } else {
2109                        if (ifp->if_flags & IFF_RUNNING)
2110                                fxp_stop(sc);
2111                }
2112                break;
2113
2114        case SIOCADDMULTI:
2115        case SIOCDELMULTI:
2116                if (ifp->if_flags & IFF_ALLMULTI)
2117                        sc->flags |= FXP_FLAG_ALL_MCAST;
2118                else
2119                        sc->flags &= ~FXP_FLAG_ALL_MCAST;
2120                /*
2121                 * Multicast list has changed; set the hardware filter
2122                 * accordingly.
2123                 */
2124                if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
2125                        fxp_mc_setup(sc);
2126                /*
2127                 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
2128                 * again rather than else {}.
2129                 */
2130                if (sc->flags & FXP_FLAG_ALL_MCAST)
2131                        fxp_init(sc);
2132                error = 0;
2133                break;
2134
2135#ifdef NOTUSED
2136        case SIOCSIFMEDIA:
2137        case SIOCGIFMEDIA:
2138                if (sc->miibus != NULL) {
2139                        mii = device_get_softc(sc->miibus);
2140                        error = ifmedia_ioctl(ifp, ifr,
2141                            &mii->mii_media, command);
2142                } else {
2143                        error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2144                }
2145                break;
2146#endif
2147
2148    case SIO_RTEMS_SHOW_STATS:
2149        fxp_stats(sc);
2150        break;
2151
2152        default:
2153                error = EINVAL;
2154        }
2155        splx(s);
2156        return (error);
2157}
2158
2159/*
2160 * Program the multicast filter.
2161 *
2162 * We have an artificial restriction that the multicast setup command
2163 * must be the first command in the chain, so we take steps to ensure
2164 * this. By requiring this, it allows us to keep up the performance of
2165 * the pre-initialized command ring (esp. link pointers) by not actually
2166 * inserting the mcsetup command in the ring - i.e. its link pointer
2167 * points to the TxCB ring, but the mcsetup descriptor itself is not part
2168 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2169 * lead into the regular TxCB ring when it completes.
2170 *
2171 * This function must be called at splimp.
2172 */
2173static void
2174fxp_mc_setup(struct fxp_softc *sc)
2175{
2176        struct fxp_cb_mcs *mcsp = sc->mcsp;
2177        struct ifnet *ifp = &sc->sc_if;
2178#ifdef NOTUSED
2179        struct ifmultiaddr *ifma;
2180#endif
2181        int nmcasts;
2182        int count;
2183
2184        DBGLVL_PRINTK(2,"fxp_mc_setup called\n");
2185
2186        /*
2187         * If there are queued commands, we must wait until they are all
2188         * completed. If we are already waiting, then add a NOP command
2189         * with interrupt option so that we're notified when all commands
2190         * have been completed - fxp_start() ensures that no additional
2191         * TX commands will be added when need_mcsetup is true.
2192         */
2193        if (sc->tx_queued) {
2194                struct fxp_cb_tx *txp;
2195
2196                /*
2197                 * need_mcsetup will be true if we are already waiting for the
2198                 * NOP command to be completed (see below). In this case, bail.
2199                 */
2200                if (sc->need_mcsetup)
2201                        return;
2202                sc->need_mcsetup = 1;
2203
2204                /*
2205                 * Add a NOP command with interrupt so that we are notified when all
2206                 * TX commands have been processed.
2207                 */
2208                txp = sc->cbl_last->next;
2209                txp->mb_head = NULL;
2210                txp->cb_status = 0;
2211                txp->cb_command = FXP_CB_COMMAND_NOP |
2212                    FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2213                /*
2214                 * Advance the end of list forward.
2215                 */
2216                sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
2217                sc->cbl_last = txp;
2218                sc->tx_queued++;
2219                /*
2220                 * Issue a resume in case the CU has just suspended.
2221                 */
2222                fxp_scb_wait(sc);
2223                fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2224                /*
2225                 * Set a 5 second timer just in case we don't hear from the
2226                 * card again.
2227                 */
2228                ifp->if_timer = 5;
2229
2230                return;
2231        }
2232        sc->need_mcsetup = 0;
2233
2234        /*
2235         * Initialize multicast setup descriptor.
2236         */
2237        mcsp->next = sc->cbl_base;
2238        mcsp->mb_head = NULL;
2239        mcsp->cb_status = 0;
2240        mcsp->cb_command = FXP_CB_COMMAND_MCAS |
2241            FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2242        mcsp->link_addr = vtophys(&sc->cbl_base->cb_status);
2243
2244        nmcasts = 0;
2245#ifdef NOTUSED /* FIXME: Multicast not supported? */
2246        if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
2247#if __FreeBSD_version < 500000
2248                LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2249#else
2250                TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2251#endif
2252                        if (ifma->ifma_addr->sa_family != AF_LINK)
2253                                continue;
2254                        if (nmcasts >= MAXMCADDR) {
2255                                sc->flags |= FXP_FLAG_ALL_MCAST;
2256                                nmcasts = 0;
2257                                break;
2258                        }
2259                        bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2260                            (void *)(uintptr_t)(volatile void *)
2261                                &sc->mcsp->mc_addr[nmcasts][0], 6);
2262                        nmcasts++;
2263                }
2264        }
2265#endif
2266        mcsp->mc_cnt = nmcasts * 6;
2267        sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp;
2268        sc->tx_queued = 1;
2269
2270        /*
2271         * Wait until command unit is not active. This should never
2272         * be the case when nothing is queued, but make sure anyway.
2273         */
2274        count = 100;
2275        while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2276            FXP_SCB_CUS_ACTIVE && --count)
2277                DELAY(10);
2278        if (count == 0) {
2279                device_printf(sc->dev, "command queue timeout\n");
2280                return;
2281        }
2282
2283        /*
2284         * Start the multicast setup command.
2285         */
2286        fxp_scb_wait(sc);
2287        CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
2288        fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2289
2290        ifp->if_timer = 2;
2291        return;
2292        }
2293
2294#endif /* defined(__i386__) */
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