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if_fxp.c @ 6279149

4.115

Last change on this file since 6279149 was 26e90fb1, checked in by Sebastian Huber <sebastian.huber@…>, on 10/30/12 at 16:42:17

libnetworking: Use system events

Add reserved system events RTEMS_EVENT_SYSTEM_NETWORK_SBWAIT and
RTEMS_EVENT_SYSTEM_NETWORK_SOSLEEP.

Add and use rtems_bsdnet_event_send().

Property mode set to 100644

File size: 61.5 KB

Line
1	/*-
2	* Copyright (c) 1995, David Greenman
3	* Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
4	* All rights reserved.
5	*
6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions
8	* are met:
9	* 1. Redistributions of source code must retain the above copyright
10	* notice unmodified, this list of conditions, and the following
11	* disclaimer.
12	* 2. Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	*
16	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26	* SUCH DAMAGE.
27	*
28	* $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.118 2001/09/05 23:33:58 brooks Exp $
29	*/
30
31	/*
32	* Intel EtherExpress Pro/100B PCI Fast Ethernet driver
33	*/
34
35	/*
36	* RTEMS Revision Preliminary History
37	*
38	* July XXX, 2002 W. Eric Norum <eric.norum@usask.ca>
39	* Placed in RTEMS CVS repository. All further modifications will be
40	* noted in the CVS log and not in this comment.
41	*
42	* July 11, 2002 W. Eric Norum <eric.norum@usask.ca>
43	* Minor modifications to get driver working with NIC on VersaLogic
44	* Bobcat PC-104 single-board computer. The Bobcat has no video
45	* driver so printf/printk calls are directed to COM2:. This
46	* arrangement seems to require delays after the printk calls or
47	* else things lock up. Perhaps the RTEMS pc386 console code
48	* should be modified to insert these delays itself.
49	*
50	* June 27, 2002 W. Eric Norum <eric.norum@usask.ca>
51	* Obtained from Thomas Doerfler <Thomas.Doerfler@imd-systems.de>.
52	* A big thank-you to Thomas for making this available.
53	*
54	* October 01, 2001 Thomas Doerfler <Thomas.Doerfler@imd-systems.de>
55	* Original RTEMS modifications.
56	*/
57
58	#if defined(__i386__)
59
60	/#define DEBUG_OUT 0/
61
62	#include <rtems.h>
63	#include <rtems/error.h>
64	#include <rtems/rtems_bsdnet.h>
65	#include <bsp.h>
66
67	#include <errno.h>
68	#include <sys/param.h>
69	#include <sys/mbuf.h>
70	#include <sys/socket.h>
71	#include <sys/sockio.h>
72	#include <net/if.h>
73	#include <netinet/in.h>
74	#include <netinet/if_ether.h>
75	#include <sys/malloc.h>
76	#include <sys/systm.h>
77	#include <bsp.h>
78	#include <pcibios.h>
79	#include <bsp/irq.h>
80	#include <rtems/pci.h>
81
82	#ifdef NS
83	#include <netns/ns.h>
84	#include <netns/ns_if.h>
85	#endif
86
87	#include <net/bpf.h>
88
89	#include <vm/vm.h> /* for vtophys */
90
91	#include <net/if_types.h>
92
93	#include "if_fxpreg.h"
94	#include "if_fxpvar.h"
95
96	/*
97	* some adaptation replacements for RTEMS
98	*/
99	static rtems_interval fxp_ticksPerSecond;
100	#define device_printf(device,format,args...) printk(format,## args)
101	#define DELAY(n) rtems_task_wake_after(((n)*fxp_ticksPerSecond/1000000)+1)
102	#ifdef DEBUG_OUT
103	#define DBGLVL_PRINTK(LVL,format, args...) \
104	if (DEBUG_OUT >= (LVL)) { \
105	printk(format, ## args); \
106	}
107	#else
108	#define DBGLVL_PRINTK(LVL,format, args...)
109	#endif
110
111	/*
112	* RTEMS event used by interrupt handler to signal driver tasks.
113	* This must not be any of the events used by the network task synchronization.
114	*/
115	#define INTERRUPT_EVENT RTEMS_EVENT_1
116
117	/*
118	* remapping between PCI device and CPU memmory address view...
119	*/
120	#if defined(__i386)
121	#define vtophys(p) (u_int32_t)(p)
122	#else
123	#define vtophys(p) vtophys(p)
124	#endif
125
126	#define NFXPDRIVER 1
127	static struct fxp_softc fxp_softc[NFXPDRIVER];
128	static bool fxp_is_verbose = true;
129	/*
130	* NOTE! On the Alpha, we have an alignment constraint. The
131	* card DMAs the packet immediately following the RFA. However,
132	* the first thing in the packet is a 14-byte Ethernet header.
133	* This means that the packet is misaligned. To compensate,
134	* we actually offset the RFA 2 bytes into the cluster. This
135	* alignes the packet after the Ethernet header at a 32-bit
136	* boundary. HOWEVER! This means that the RFA is misaligned!
137	*/
138	#define RFA_ALIGNMENT_FUDGE 2
139
140	/*
141	* Set initial transmit threshold at 64 (512 bytes). This is
142	* increased by 64 (512 bytes) at a time, to maximum of 192
143	* (1536 bytes), if an underrun occurs.
144	*/
145	static int tx_threshold = 64;
146
147	/*
148	* The configuration byte map has several undefined fields which
149	* must be one or must be zero. Set up a template for these bits
150	* only, (assuming a 82557 chip) leaving the actual configuration
151	* to fxp_init.
152	*
153	* See struct fxp_cb_config for the bit definitions.
154	*/
155	static u_char fxp_cb_config_template[] = {
156	0x0, 0x0, /* cb_status */
157	0x0, 0x0, /* cb_command */
158	0x0, 0x0, 0x0, 0x0, /* link_addr */
159	0x0, /* 0 */
160	0x0, /* 1 */
161	0x0, /* 2 */
162	0x0, /* 3 */
163	0x0, /* 4 */
164	0x0, /* 5 */
165	0x32, /* 6 */
166	0x0, /* 7 */
167	0x0, /* 8 */
168	0x0, /* 9 */
169	0x6, /* 10 */
170	0x0, /* 11 */
171	0x0, /* 12 */
172	0x0, /* 13 */
173	0xf2, /* 14 */
174	0x48, /* 15 */
175	0x0, /* 16 */
176	0x40, /* 17 */
177	0xf0, /* 18 */
178	0x0, /* 19 */
179	0x3f, /* 20 */
180	0x5 /* 21 */
181	};
182
183	struct fxp_ident {
184	u_int16_t devid;
185	char *name;
186	int warn;
187	};
188
189	#define UNTESTED 1
190
191	/*
192	* Claim various Intel PCI device identifiers for this driver. The
193	* sub-vendor and sub-device field are extensively used to identify
194	* particular variants, but we don't currently differentiate between
195	* them.
196	*/
197	static struct fxp_ident fxp_ident_table[] = {
198	{ 0x1229, "Intel Pro 10/100B/100+ Ethernet", 0 },
199	{ 0x2449, "Intel Pro/100 Ethernet", UNTESTED },
200	{ 0x1209, "Intel Embedded 10/100 Ethernet", 0 },
201	{ 0x1029, "Intel Pro/100 Ethernet", UNTESTED },
202	{ 0x1030, "Intel Pro/100 Ethernet", 0 },
203	{ 0x1031, "Intel Pro/100 Ethernet", UNTESTED },
204	{ 0x1032, "Intel Pro/100 Ethernet", UNTESTED },
205	{ 0x1033, "Intel Pro/100 Ethernet", UNTESTED },
206	{ 0x1034, "Intel Pro/100 Ethernet", UNTESTED },
207	{ 0x1035, "Intel Pro/100 Ethernet", UNTESTED },
208	{ 0x1036, "Intel Pro/100 Ethernet", UNTESTED },
209	{ 0x1037, "Intel Pro/100 Ethernet", UNTESTED },
210	{ 0x1038, "Intel Pro/100 Ethernet", UNTESTED },
211	{ 0x103B, "Intel Pro/100 Ethernet (82801BD PRO/100 VM (LOM))", 0 },
212	{ 0, NULL, 0 }
213	};
214
215	#if 0
216	static int fxp_probe(device_t dev);
217	static int fxp_attach(device_t dev);
218	static int fxp_detach(device_t dev);
219	static int fxp_shutdown(device_t dev);
220	#endif
221	int fxp_output (struct ifnet *,
222	struct mbuf , struct sockaddr , struct rtentry *);
223
224
225	static rtems_isr fxp_intr(rtems_vector_number v);
226	static void fxp_init(void *xsc);
227	static void fxp_tick(void *xsc);
228	static void fxp_start(struct ifnet *ifp);
229	static void fxp_stop(struct fxp_softc *sc);
230	static void fxp_release(struct fxp_softc *sc);
231	static int fxp_ioctl(struct ifnet *ifp, ioctl_command_t command,
232	caddr_t data);
233	static void fxp_watchdog(struct ifnet *ifp);
234	static int fxp_add_rfabuf(struct fxp_softc sc, struct mbuf oldm);
235	static void fxp_mc_setup(struct fxp_softc *sc);
236	static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
237	int autosize);
238	static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
239	u_int16_t data);
240	static void fxp_autosize_eeprom(struct fxp_softc *sc);
241	static void fxp_read_eeprom(struct fxp_softc sc, u_short data,
242	int offset, int words);
243	static void fxp_write_eeprom(struct fxp_softc sc, u_short data,
244	int offset, int words);
245	#ifdef NOTUSED
246	static int fxp_ifmedia_upd(struct ifnet *ifp);
247	static void fxp_ifmedia_sts(struct ifnet *ifp,
248	struct ifmediareq *ifmr);
249	static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
250	static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
251	struct ifmediareq *ifmr);
252	static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg);
253	static void fxp_miibus_writereg(device_t dev, int phy, int reg,
254	int value);
255	#endif
256	static __inline void fxp_lwcopy(volatile u_int32_t *src,
257	volatile u_int32_t *dst);
258	static __inline void fxp_scb_wait(struct fxp_softc *sc);
259	static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
260	static __inline void fxp_dma_wait(volatile u_int16_t *status,
261	struct fxp_softc *sc);
262
263	/*
264	* Inline function to copy a 16-bit aligned 32-bit quantity.
265	*/
266	static __inline void
267	fxp_lwcopy(volatile u_int32_t src, volatile u_int32_t dst)
268	{
269	#ifdef __i386__
270	dst = src;
271	#else
272	volatile u_int16_t a = (volatile u_int16_t)src;
273	volatile u_int16_t b = (volatile u_int16_t)dst;
274
275	b[0] = a[0];
276	b[1] = a[1];
277	#endif
278	}
279
280	/*
281	* inline access functions to pci space registers
282	*/
283	static __inline u_int8_t fxp_csr_read_1(struct fxp_softc *sc,int reg) {
284	u_int8_t val;
285	if (sc->pci_regs_are_io) {
286	inport_byte(sc->pci_regs_base + reg,val);
287	}
288	else {
289	val = (u_int8_t)(sc->pci_regs_base+reg);
290	}
291	return val;
292	}
293	static __inline u_int32_t fxp_csr_read_2(struct fxp_softc *sc,int reg) {
294	u_int16_t val;
295	if (sc->pci_regs_are_io) {
296	inport_word(sc->pci_regs_base + reg,val);
297	}
298	else {
299	val = (u_int16_t)(sc->pci_regs_base+reg);
300	}
301	return val;
302	}
303	static __inline u_int32_t fxp_csr_read_4(struct fxp_softc *sc,int reg) {
304	u_int32_t val;
305	if (sc->pci_regs_are_io) {
306	inport_long(sc->pci_regs_base + reg,val);
307	}
308	else {
309	val = (u_int32_t)(sc->pci_regs_base+reg);
310	}
311	return val;
312	}
313
314	/*
315	* Wait for the previous command to be accepted (but not necessarily
316	* completed).
317	*/
318	static __inline void
319	fxp_scb_wait(struct fxp_softc *sc)
320	{
321	int i = 10000;
322
323	while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
324	DELAY(2);
325	if (i == 0)
326	device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
327	CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
328	CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
329	CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS),
330	CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
331	}
332
333	static __inline void
334	fxp_scb_cmd(struct fxp_softc *sc, int cmd)
335	{
336
337	if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
338	CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
339	fxp_scb_wait(sc);
340	}
341	CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
342	}
343
344	static __inline void
345	fxp_dma_wait(volatile u_int16_t status, struct fxp_softc sc)
346	{
347	int i = 10000;
348
349	while (!(*status & FXP_CB_STATUS_C) && --i)
350	DELAY(2);
351	if (i == 0)
352	device_printf(sc->dev, "DMA timeout\n");
353	}
354
355	static __inline unsigned int pci_get_vendor(struct fxp_softc *sc) {
356	u_int16_t vendor;
357	pcib_conf_read16(sc->pci_signature,0,&vendor);
358	return vendor;
359	}
360
361	static __inline unsigned int pci_get_device(struct fxp_softc *sc) {
362	u_int16_t device;
363	pcib_conf_read16(sc->pci_signature,2,&device);
364	return device;
365	}
366
367	static __inline unsigned int pci_get_subvendor(struct fxp_softc *sc) {
368	u_int16_t subvendor;
369	pcib_conf_read16(sc->pci_signature,0x2c,&subvendor);
370	return subvendor;
371	}
372
373	static __inline unsigned int pci_get_subdevice(struct fxp_softc *sc) {
374	u_int16_t subdevice;
375	pcib_conf_read16(sc->pci_signature,0x2e,&subdevice);
376	return subdevice;
377	}
378
379	static __inline unsigned int pci_get_revid(struct fxp_softc *sc) {
380	u_int8_t revid;
381	pcib_conf_read8(sc->pci_signature,0x08,&revid);
382	return revid;
383	}
384
385	static void nopOn(const rtems_irq_connect_data* notUsed)
386	{
387	/*
388	* code should be moved from fxp_Enet_initialize_hardware
389	* to this location
390	*/
391	}
392
393	static int fxpIsOn(const rtems_irq_connect_data* irq)
394	{
395	return BSP_irq_enabled_at_i8259s (irq->name);
396	}
397
398	int
399	rtems_fxp_attach(struct rtems_bsdnet_ifconfig *config, int attaching)
400	{
401	int error = 0;
402	struct fxp_softc *sc;
403	struct ifnet *ifp;
404	uint16_t val16;
405	uint32_t val32;
406	uint16_t data;
407	int i;
408	int s;
409	int unitNumber;
410	char *unitName;
411	u_int16_t dev_id;
412	u_int8_t interrupt;
413	int mtu;
414
415	/*
416	* Set up some timing values
417	*/
418	rtems_clock_get(RTEMS_CLOCK_GET_TICKS_PER_SECOND, &fxp_ticksPerSecond);
419	DBGLVL_PRINTK(1,"fxp_attach called\n");
420
421	/*
422	* Parse driver name
423	*/
424	if ((unitNumber = rtems_bsdnet_parse_driver_name (config, &unitName)) < 0)
425	return 0;
426
427	/*
428	* Is driver free?
429	*/
430	if ((unitNumber <= 0) \|\| (unitNumber > NFXPDRIVER)) {
431	device_printf(dev,"Bad FXP unit number.\n");
432	return 0;
433	}
434	sc = &fxp_softc[unitNumber - 1];
435	ifp = &sc->arpcom.ac_if;
436	if (ifp->if_softc != NULL) {
437	device_printf(dev,"FXP Driver already in use.\n");
438	return 0;
439	}
440
441	memset(sc, 0, sizeof(*sc));
442	#ifdef NOTUSED
443	sc->dev = dev;
444	callout_handle_init(&sc->stat_ch);
445	mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF \| MTX_RECURSE);
446	#endif
447	s = splimp();
448
449	/*
450	* find device on pci bus
451	*/
452	{ int j; int pbus, pdev, pfun;
453
454	for (j=0; fxp_ident_table[j].devid; j++ ) {
455	i = pci_find_device( 0x8086, fxp_ident_table[j].devid,
456	unitNumber-1, &pbus, &pdev, &pfun );
457	sc->pci_signature = PCIB_DEVSIG_MAKE( pbus, pdev, pfun );
458	DBGLVL_PRINTK(2,"fxp_attach: find_devid returned %d "
459	"and pci signature 0x%x\n",
460	i,sc->pci_signature);
461	if (PCIB_ERR_SUCCESS == i) {
462	if ( UNTESTED == fxp_ident_table[j].warn ) {
463	device_printf(dev,
464	"WARNING: this chip version has NOT been reported to work under RTEMS yet.\n");
465	device_printf(dev,
466	" If it works OK, report it as tested in 'c/src/libchip/network/if_fxp.c'\n");
467	}
468	break;
469	}
470	}
471	}
472
473	/*
474	* FIXME: add search for more device types...
475	*/
476	if (i != PCIB_ERR_SUCCESS) {
477	device_printf(dev, "could not find 82559ER device\n");
478	return 0;
479	}
480
481
482	/*
483	* Enable bus mastering. Enable memory space too, in case
484	* BIOS/Prom forgot about it.
485	*/
486	pcib_conf_read16(sc->pci_signature, PCI_COMMAND,&val16);
487	val16 \|= (PCI_COMMAND_MEMORY\|PCI_COMMAND_MASTER);
488	pcib_conf_write16(sc->pci_signature, PCI_COMMAND, val16);
489	DBGLVL_PRINTK(3,"fxp_attach: PCI_COMMAND_write = 0x%x\n",val16);
490	pcib_conf_read16(sc->pci_signature, PCI_COMMAND,&val16);
491	DBGLVL_PRINTK(4,"fxp_attach: PCI_COMMAND_read = 0x%x\n",val16);
492
493	/*
494	* Figure out which we should try first - memory mapping or i/o mapping?
495	* We default to memory mapping. Then we accept an override from the
496	* command line. Then we check to see which one is enabled.
497	*/
498	#ifdef NOTUSED
499	m1 = PCI_COMMAND_MEMORY;
500	m2 = PCI_COMMAND_IO;
501	prefer_iomap = 0;
502	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
503	"prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) {
504	m1 = PCI_COMMAND_IO;
505	m2 = PCI_COMMAND_MEMORY;
506	}
507
508	if (val & m1) {
509	sc->rtp = ((m1 == PCI_COMMAND_MEMORY)
510	? SYS_RES_MEMORY : SYS_RES_IOPORT);
511	sc->rgd = ((m1 == PCI_COMMAND_MEMORY)
512	? FXP_PCI_MMBA : FXP_PCI_IOBA);
513	sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
514	0, ~0, 1, RF_ACTIVE);
515	}
516	if (sc->mem == NULL && (val & m2)) {
517	sc->rtp = ((m2 == PCI_COMMAND_MEMORY)
518	? SYS_RES_MEMORY : SYS_RES_IOPORT);
519	sc->rgd = ((m2 == PCI_COMMAND_MEMORY)
520	? FXP_PCI_MMBA : FXP_PCI_IOBA);
521	sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
522	0, ~0, 1, RF_ACTIVE);
523	}
524
525	if (!sc->mem) {
526	device_printf(dev, "could not map device registers\n");
527	error = ENXIO;
528	goto fail;
529	}
530	if (fxp_is_verbose) {
531	device_printf(dev, "using %s space register mapping\n",
532	sc->rtp == SYS_RES_MEMORY? "memory" : "I/O");
533	}
534
535	sc->sc_st = rman_get_bustag(sc->mem);
536	sc->sc_sh = rman_get_bushandle(sc->mem);
537
538	/*
539	* Allocate our interrupt.
540	*/
541	rid = 0;
542	sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
543	RF_SHAREABLE \| RF_ACTIVE);
544	if (sc->irq == NULL) {
545	device_printf(dev, "could not map interrupt\n");
546	error = ENXIO;
547	goto fail;
548	}
549
550	error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
551	fxp_intr, sc, &sc->ih);
552	if (error) {
553	device_printf(dev, "could not setup irq\n");
554	goto fail;
555	}
556	#endif
557
558	/*
559	* get mapping and base address of registers
560	*/
561	pcib_conf_read16(sc->pci_signature, PCI_COMMAND,&val16);
562	DBGLVL_PRINTK(4,"fxp_attach: PCI_COMMAND_read = 0x%x\n",val16);
563	if((val16 & PCI_COMMAND_IO) != 0) {
564	sc->pci_regs_are_io = true;
565	pcib_conf_read32(sc->pci_signature,
566	PCI_BASE_ADDRESS_1,
567	&val32);
568	sc->pci_regs_base = val32 & PCI_BASE_ADDRESS_IO_MASK;
569	}
570	else {
571	sc->pci_regs_are_io = false;
572	pcib_conf_read32(sc->pci_signature,
573	PCI_BASE_ADDRESS_0,
574	&val32);
575	sc->pci_regs_base = val32 & PCI_BASE_ADDRESS_MEM_MASK;
576	}
577	DBGLVL_PRINTK(3,"fxp_attach: CSR registers are mapped in %s space"
578	" at address 0x%x\n",
579	sc->pci_regs_are_io ? "I/O" : "MEM",
580	sc->pci_regs_base);
581
582	/*
583	* get interrupt level to be used
584	*/
585	pcib_conf_read8(sc->pci_signature, 60, &interrupt);
586	DBGLVL_PRINTK(3,"fxp_attach: interrupt = 0x%x\n",interrupt);
587	sc->irqInfo.name = (rtems_irq_number)interrupt;
588	/*
589	* Reset to a stable state.
590	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
591	*/
592	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
593	DELAY(10);
594
595	sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB,
596	M_DEVBUF, M_NOWAIT);
597	DBGLVL_PRINTK(3,"fxp_attach: sc->cbl_base = 0x%x\n",sc->cbl_base);
598	if (sc->cbl_base == NULL)
599	goto failmem;
600	else
601	memset(sc->cbl_base, 0, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
602
603	sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF,
604	M_NOWAIT);
605	DBGLVL_PRINTK(3,"fxp_attach: sc->fxp_stats = 0x%x\n",sc->fxp_stats);
606	if (sc->fxp_stats == NULL)
607	goto failmem;
608	else
609	memset(sc->fxp_stats, 0, sizeof(struct fxp_stats));
610
611	sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT);
612	DBGLVL_PRINTK(3,"fxp_attach: sc->mcsp = 0x%x\n",sc->mcsp);
613	if (sc->mcsp == NULL)
614	goto failmem;
615
616	/*
617	* Pre-allocate our receive buffers.
618	*/
619	for (i = 0; i < FXP_NRFABUFS; i++) {
620	if (fxp_add_rfabuf(sc, NULL) != 0) {
621	goto failmem;
622	}
623	}
624
625	/*
626	* Find out how large of an SEEPROM we have.
627	*/
628	DBGLVL_PRINTK(3,"fxp_attach: calling fxp_autosize_eeprom\n");
629	fxp_autosize_eeprom(sc);
630
631	/*
632	* Determine whether we must use the 503 serial interface.
633	*/
634	fxp_read_eeprom(sc, &data, 6, 1);
635	if ((data & FXP_PHY_DEVICE_MASK) != 0 &&
636	(data & FXP_PHY_SERIAL_ONLY))
637	sc->flags \|= FXP_FLAG_SERIAL_MEDIA;
638
639	/*
640	* Find out the basic controller type; we currently only
641	* differentiate between a 82557 and greater.
642	*/
643	fxp_read_eeprom(sc, &data, 5, 1);
644	if ((data >> 8) == 1)
645	sc->chip = FXP_CHIP_82557;
646	DBGLVL_PRINTK(3,"fxp_attach: sc->chip = %d\n",sc->chip);
647
648	/*
649	* Enable workarounds for certain chip revision deficiencies.
650	*
651	* Systems based on the ICH2/ICH2-M chip from Intel have a defect
652	* where the chip can cause a PCI protocol violation if it receives
653	* a CU_RESUME command when it is entering the IDLE state. The
654	* workaround is to disable Dynamic Standby Mode, so the chip never
655	* deasserts CLKRUN#, and always remains in an active state.
656	*
657	* See Intel 82801BA/82801BAM Specification Update, Errata #30.
658	*/
659	#ifdef NOTUSED
660	i = pci_get_device(dev);
661	#else
662	pcib_conf_read16(sc->pci_signature,2,&dev_id);
663	DBGLVL_PRINTK(3,"fxp_attach: device id = 0x%x\n",dev_id);
664	#endif
665	if (dev_id == 0x2449 \|\| (dev_id > 0x1030 && dev_id < 0x1039)) {
666	device_printf(dev, "* See Intel 82801BA/82801BAM Specification Update, Errata #30. *\n");
667	fxp_read_eeprom(sc, &data, 10, 1);
668	if (data & 0x02) { /* STB enable */
669	u_int16_t cksum;
670	int i;
671
672	device_printf(dev,
673	"* DISABLING DYNAMIC STANDBY MODE IN EEPROM *\n");
674	data &= ~0x02;
675	fxp_write_eeprom(sc, &data, 10, 1);
676	device_printf(dev, "New EEPROM ID: 0x%x\n", data);
677	cksum = 0;
678	for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
679	fxp_read_eeprom(sc, &data, i, 1);
680	cksum += data;
681	}
682	i = (1 << sc->eeprom_size) - 1;
683	cksum = 0xBABA - cksum;
684	fxp_read_eeprom(sc, &data, i, 1);
685	fxp_write_eeprom(sc, &cksum, i, 1);
686	device_printf(dev,
687	"EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
688	i, data, cksum);
689	/*
690	* We need to do a full PCI reset here. A software
691	* reset to the port doesn't cut it, but let's try
692	* anyway.
693	*/
694	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
695	DELAY(50);
696	device_printf(dev,
697	"* PLEASE REBOOT THE SYSTEM NOW FOR CORRECT OPERATION *\n");
698	#if 1
699	/*
700	* If the user elects to continue, try the software
701	* workaround, as it is better than nothing.
702	*/
703	sc->flags \|= FXP_FLAG_CU_RESUME_BUG;
704	#endif
705	}
706	}
707
708	/*
709	* If we are not a 82557 chip, we can enable extended features.
710	*/
711	if (sc->chip != FXP_CHIP_82557) {
712	u_int8_t tmp_val;
713	/*
714	* If MWI is enabled in the PCI configuration, and there
715	* is a valid cacheline size (8 or 16 dwords), then tell
716	* the board to turn on MWI.
717	*/
718	pcib_conf_read8(sc->pci_signature,
719	PCI_CACHE_LINE_SIZE,&tmp_val);
720	DBGLVL_PRINTK(3,"fxp_attach: CACHE_LINE_SIZE = %d\n",tmp_val);
721	if (val16 & PCI_COMMAND_MEMORY &&
722	tmp_val != 0)
723	sc->flags \|= FXP_FLAG_MWI_ENABLE;
724
725	/* turn on the extended TxCB feature */
726	sc->flags \|= FXP_FLAG_EXT_TXCB;
727
728	/* enable reception of long frames for VLAN */
729	sc->flags \|= FXP_FLAG_LONG_PKT_EN;
730	DBGLVL_PRINTK(3,"fxp_attach: sc->flags = 0x%x\n",
731	sc->flags);
732	}
733
734	/*
735	* Read MAC address.
736	*/
737	fxp_read_eeprom(sc, (u_int16_t*)sc->arpcom.ac_enaddr, 0, 3);
738	if (fxp_is_verbose) {
739	device_printf(dev, "Ethernet address %x:%x:%x:%x:%x:%x %s \n",
740	((u_int8_t*)sc->arpcom.ac_enaddr)[0],
741	((u_int8_t*)sc->arpcom.ac_enaddr)[1],
742	((u_int8_t*)sc->arpcom.ac_enaddr)[2],
743	((u_int8_t*)sc->arpcom.ac_enaddr)[3],
744	((u_int8_t*)sc->arpcom.ac_enaddr)[4],
745	((u_int8_t*)sc->arpcom.ac_enaddr)[5],
746	sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : "");
747	device_printf(dev, "PCI IDs: 0x%x 0x%x 0x%x 0x%x 0x%x\n",
748	pci_get_vendor(sc), pci_get_device(sc),
749	pci_get_subvendor(sc), pci_get_subdevice(sc),
750	pci_get_revid(sc));
751	device_printf(dev, "Chip Type: %d\n", sc->chip);
752	}
753
754	#ifdef NOTUSED /* do not set up interface at all... */
755	/*
756	* If this is only a 10Mbps device, then there is no MII, and
757	* the PHY will use a serial interface instead.
758	*
759	* The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
760	* doesn't have a programming interface of any sort. The
761	* media is sensed automatically based on how the link partner
762	* is configured. This is, in essence, manual configuration.
763	*/
764	if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
765	ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
766	fxp_serial_ifmedia_sts);
767	ifmedia_add(&sc->sc_media, IFM_ETHER\|IFM_MANUAL, 0, NULL);
768	ifmedia_set(&sc->sc_media, IFM_ETHER\|IFM_MANUAL);
769	} else {
770	if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
771	fxp_ifmedia_sts)) {
772	device_printf(dev, "MII without any PHY!\n");
773	error = ENXIO;
774	goto fail;
775	}
776	}
777	#endif
778	if (config->mtu)
779	mtu = config->mtu;
780	else
781	mtu = ETHERMTU;
782
783	ifp->if_softc = sc;
784	ifp->if_unit = unitNumber;
785	ifp->if_name = unitName;
786	ifp->if_mtu = mtu;
787	ifp->if_baudrate = 100000000;
788	ifp->if_init = fxp_init;
789	ifp->if_ioctl = fxp_ioctl;
790	ifp->if_start = fxp_start;
791	ifp->if_output = ether_output;
792	ifp->if_watchdog = fxp_watchdog;
793	ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX /\| IFF_MULTICAST/;
794	if (ifp->if_snd.ifq_maxlen == 0)
795	ifp->if_snd.ifq_maxlen = ifqmaxlen;
796
797	/*
798	* Attach the interface.
799	*/
800	DBGLVL_PRINTK(3,"fxp_attach: calling if_attach\n");
801	if_attach (ifp);
802	DBGLVL_PRINTK(3,"fxp_attach: calling ether_if_attach\n");
803	ether_ifattach(ifp);
804	DBGLVL_PRINTK(3,"fxp_attach: return from ether_if_attach\n");
805
806	#ifdef NOTUSED
807	/*
808	* Tell the upper layer(s) we support long frames.
809	*/
810	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
811	#endif
812	/*
813	* Let the system queue as many packets as we have available
814	* TX descriptors.
815	*/
816	ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1;
817
818	splx(s);
819	return (0);
820
821	failmem:
822	device_printf(dev, "Failed to malloc memory\n");
823	error = ENOMEM;
824	#ifdef NOTUSED
825	fail:
826	#endif
827	splx(s);
828	fxp_release(sc);
829	return (error);
830	}
831
832	/*
833	* release all resources
834	*/
835	static void
836	fxp_release(struct fxp_softc *sc)
837	{
838
839	#ifdef NOTUSED
840	bus_generic_detach(sc->dev);
841	if (sc->miibus)
842	device_delete_child(sc->dev, sc->miibus);
843	#endif
844	if (sc->cbl_base)
845	free(sc->cbl_base, M_DEVBUF);
846	if (sc->fxp_stats)
847	free(sc->fxp_stats, M_DEVBUF);
848	if (sc->mcsp)
849	free(sc->mcsp, M_DEVBUF);
850	if (sc->rfa_headm)
851	m_freem(sc->rfa_headm);
852
853	#ifdef NOTUSED
854	if (sc->ih)
855	bus_teardown_intr(sc->dev, sc->irq, sc->ih);
856	if (sc->irq)
857	bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
858	if (sc->mem)
859	bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem);
860	mtx_destroy(&sc->sc_mtx);
861	#endif
862	}
863
864	#if NOTUSED
865	/*
866	* Detach interface.
867	*/
868	static int
869	fxp_detach(device_t dev)
870	{
871	struct fxp_softc *sc = device_get_softc(dev);
872	int s;
873
874	/* disable interrupts */
875	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
876
877	s = splimp();
878
879	/*
880	* Stop DMA and drop transmit queue.
881	*/
882	fxp_stop(sc);
883
884	/*
885	* Close down routes etc.
886	*/
887	ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED);
888
889	/*
890	* Free all media structures.
891	*/
892	ifmedia_removeall(&sc->sc_media);
893
894	splx(s);
895
896	/* Release our allocated resources. */
897	fxp_release(sc);
898
899	return (0);
900	}
901
902	/*
903	* Device shutdown routine. Called at system shutdown after sync. The
904	* main purpose of this routine is to shut off receiver DMA so that
905	* kernel memory doesn't get clobbered during warmboot.
906	*/
907	static int
908	fxp_shutdown(device_t dev)
909	{
910	/*
911	* Make sure that DMA is disabled prior to reboot. Not doing
912	* do could allow DMA to corrupt kernel memory during the
913	* reboot before the driver initializes.
914	*/
915	fxp_stop((struct fxp_softc *) device_get_softc(dev));
916	return (0);
917	}
918	#endif
919
920	/*
921	* Show interface statistics
922	*/
923	static void
924	fxp_stats(struct fxp_softc *sc)
925	{
926	struct ifnet *ifp = &sc->sc_if;
927
928	printf (" Output packets:%-8lu", ifp->if_opackets);
929	printf (" Collisions:%-8lu", ifp->if_collisions);
930	printf (" Output errors:%-8lu\n", ifp->if_oerrors);
931	printf (" Input packets:%-8lu", ifp->if_ipackets);
932	printf (" Input errors:%-8lu\n", ifp->if_ierrors);
933	}
934
935	static void
936	fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
937	{
938	u_int16_t reg;
939	int x;
940
941	/*
942	* Shift in data.
943	*/
944	for (x = 1 << (length - 1); x; x >>= 1) {
945	if (data & x)
946	reg = FXP_EEPROM_EECS \| FXP_EEPROM_EEDI;
947	else
948	reg = FXP_EEPROM_EECS;
949	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
950	DELAY(1);
951	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg \| FXP_EEPROM_EESK);
952	DELAY(1);
953	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
954	DELAY(1);
955	}
956	}
957
958	/*
959	* Read from the serial EEPROM. Basically, you manually shift in
960	* the read opcode (one bit at a time) and then shift in the address,
961	* and then you shift out the data (all of this one bit at a time).
962	* The word size is 16 bits, so you have to provide the address for
963	* every 16 bits of data.
964	*/
965	static u_int16_t
966	fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
967	{
968	u_int16_t reg, data;
969	int x;
970
971	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
972	/*
973	* Shift in read opcode.
974	*/
975	fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
976	/*
977	* Shift in address.
978	*/
979	data = 0;
980	for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
981	if (offset & x)
982	reg = FXP_EEPROM_EECS \| FXP_EEPROM_EEDI;
983	else
984	reg = FXP_EEPROM_EECS;
985	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
986	DELAY(1);
987	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg \| FXP_EEPROM_EESK);
988	DELAY(1);
989	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
990	DELAY(1);
991	reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
992	data++;
993	if (autosize && reg == 0) {
994	sc->eeprom_size = data;
995	break;
996	}
997	}
998	/*
999	* Shift out data.
1000	*/
1001	data = 0;
1002	reg = FXP_EEPROM_EECS;
1003	for (x = 1 << 15; x; x >>= 1) {
1004	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg \| FXP_EEPROM_EESK);
1005	DELAY(1);
1006	if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1007	data \|= x;
1008	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1009	DELAY(1);
1010	}
1011	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1012	DELAY(1);
1013
1014	return (data);
1015	}
1016
1017	static void
1018	fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data)
1019	{
1020	int i;
1021
1022	/*
1023	* Erase/write enable.
1024	*/
1025	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1026	fxp_eeprom_shiftin(sc, 0x4, 3);
1027	fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1028	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1029	DELAY(1);
1030	/*
1031	* Shift in write opcode, address, data.
1032	*/
1033	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1034	fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1035	fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1036	fxp_eeprom_shiftin(sc, data, 16);
1037	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1038	DELAY(1);
1039	/*
1040	* Wait for EEPROM to finish up.
1041	*/
1042	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1043	DELAY(1);
1044	for (i = 0; i < 1000; i++) {
1045	if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1046	break;
1047	DELAY(50);
1048	}
1049	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1050	DELAY(1);
1051	/*
1052	* Erase/write disable.
1053	*/
1054	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1055	fxp_eeprom_shiftin(sc, 0x4, 3);
1056	fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1057	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1058	DELAY(1);
1059	}
1060
1061	/*
1062	* From NetBSD:
1063	*
1064	* Figure out EEPROM size.
1065	*
1066	* 559's can have either 64-word or 256-word EEPROMs, the 558
1067	* datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1068	* talks about the existance of 16 to 256 word EEPROMs.
1069	*
1070	* The only known sizes are 64 and 256, where the 256 version is used
1071	* by CardBus cards to store CIS information.
1072	*
1073	* The address is shifted in msb-to-lsb, and after the last
1074	* address-bit the EEPROM is supposed to output a `dummy zero' bit,
1075	* after which follows the actual data. We try to detect this zero, by
1076	* probing the data-out bit in the EEPROM control register just after
1077	* having shifted in a bit. If the bit is zero, we assume we've
1078	* shifted enough address bits. The data-out should be tri-state,
1079	* before this, which should translate to a logical one.
1080	*/
1081	static void
1082	fxp_autosize_eeprom(struct fxp_softc *sc)
1083	{
1084
1085	/* guess maximum size of 256 words */
1086	sc->eeprom_size = 8;
1087
1088	/* autosize */
1089	(void) fxp_eeprom_getword(sc, 0, 1);
1090	}
1091
1092	static void
1093	fxp_read_eeprom(struct fxp_softc sc, u_short data, int offset, int words)
1094	{
1095	int i;
1096
1097	for (i = 0; i < words; i++) {
1098	data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1099	DBGLVL_PRINTK(4,"fxp_eeprom_read(off=0x%x)=0x%x\n",
1100	offset+i,data[i]);
1101	}
1102	}
1103
1104	static void
1105	fxp_write_eeprom(struct fxp_softc sc, u_short data, int offset, int words)
1106	{
1107	int i;
1108
1109	for (i = 0; i < words; i++)
1110	fxp_eeprom_putword(sc, offset + i, data[i]);
1111	DBGLVL_PRINTK(4,"fxp_eeprom_write(off=0x%x,0x%x)\n",
1112	offset+i,data[i]);
1113	}
1114
1115	/*
1116	* Start packet transmission on the interface.
1117	*/
1118	static void
1119	fxp_start(struct ifnet *ifp)
1120	{
1121	struct fxp_softc *sc = ifp->if_softc;
1122	struct fxp_cb_tx *txp;
1123
1124	DBGLVL_PRINTK(3,"fxp_start called\n");
1125
1126	/*
1127	* See if we need to suspend xmit until the multicast filter
1128	* has been reprogrammed (which can only be done at the head
1129	* of the command chain).
1130	*/
1131	if (sc->need_mcsetup) {
1132	return;
1133	}
1134
1135	txp = NULL;
1136
1137	/*
1138	* We're finished if there is nothing more to add to the list or if
1139	* we're all filled up with buffers to transmit.
1140	* NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1141	* a NOP command when needed.
1142	*/
1143	while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) {
1144	struct mbuf m, mb_head;
1145	int segment;
1146
1147	/*
1148	* Grab a packet to transmit.
1149	*/
1150	IF_DEQUEUE(&ifp->if_snd, mb_head);
1151
1152	/*
1153	* Get pointer to next available tx desc.
1154	*/
1155	txp = sc->cbl_last->next;
1156
1157	/*
1158	* Go through each of the mbufs in the chain and initialize
1159	* the transmit buffer descriptors with the physical address
1160	* and size of the mbuf.
1161	*/
1162	tbdinit:
1163	for (m = mb_head, segment = 0; m != NULL; m = m->m_next) {
1164	if (m->m_len != 0) {
1165	if (segment == FXP_NTXSEG)
1166	break;
1167	txp->tbd[segment].tb_addr =
1168	vtophys(mtod(m, vm_offset_t));
1169	txp->tbd[segment].tb_size = m->m_len;
1170	segment++;
1171	}
1172	}
1173	if (m != NULL) {
1174	struct mbuf *mn;
1175
1176	/*
1177	* We ran out of segments. We have to recopy this
1178	* mbuf chain first. Bail out if we can't get the
1179	* new buffers.
1180	*/
1181	MGETHDR(mn, M_DONTWAIT, MT_DATA);
1182	if (mn == NULL) {
1183	m_freem(mb_head);
1184	break;
1185	}
1186	if (mb_head->m_pkthdr.len > MHLEN) {
1187	MCLGET(mn, M_DONTWAIT);
1188	if ((mn->m_flags & M_EXT) == 0) {
1189	m_freem(mn);
1190	m_freem(mb_head);
1191	break;
1192	}
1193	}
1194	m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
1195	mtod(mn, caddr_t));
1196	mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len;
1197	m_freem(mb_head);
1198	mb_head = mn;
1199	goto tbdinit;
1200	}
1201
1202	txp->tbd_number = segment;
1203	txp->mb_head = mb_head;
1204	txp->cb_status = 0;
1205	if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1206	txp->cb_command =
1207	FXP_CB_COMMAND_XMIT \| FXP_CB_COMMAND_SF \|
1208	FXP_CB_COMMAND_S;
1209	} else {
1210	txp->cb_command =
1211	FXP_CB_COMMAND_XMIT \| FXP_CB_COMMAND_SF \|
1212	FXP_CB_COMMAND_S \| FXP_CB_COMMAND_I;
1213	/*
1214	* Set a 5 second timer just in case we don't hear
1215	* from the card again.
1216	*/
1217	ifp->if_timer = 5;
1218	}
1219	txp->tx_threshold = tx_threshold;
1220
1221	/*
1222	* Advance the end of list forward.
1223	*/
1224
1225	#ifdef __alpha__
1226	/*
1227	* On platforms which can't access memory in 16-bit
1228	* granularities, we must prevent the card from DMA'ing
1229	* up the status while we update the command field.
1230	* This could cause us to overwrite the completion status.
1231	*/
1232	atomic_clear_short(&sc->cbl_last->cb_command,
1233	FXP_CB_COMMAND_S);
1234	#else
1235	sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
1236	#endif /__alpha__/
1237	sc->cbl_last = txp;
1238
1239	/*
1240	* Advance the beginning of the list forward if there are
1241	* no other packets queued (when nothing is queued, cbl_first
1242	* sits on the last TxCB that was sent out).
1243	*/
1244	if (sc->tx_queued == 0)
1245	sc->cbl_first = txp;
1246
1247	sc->tx_queued++;
1248
1249	#ifdef NOTUSED
1250	/*
1251	* Pass packet to bpf if there is a listener.
1252	*/
1253	if (ifp->if_bpf)
1254	bpf_mtap(ifp, mb_head);
1255	#endif
1256	}
1257
1258	/*
1259	* We're finished. If we added to the list, issue a RESUME to get DMA
1260	* going again if suspended.
1261	*/
1262	if (txp != NULL) {
1263	fxp_scb_wait(sc);
1264	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1265	}
1266	}
1267
1268	/*
1269	* Process interface interrupts.
1270	*/
1271	static rtems_isr fxp_intr(rtems_vector_number v)
1272	{
1273	/*
1274	* FIXME: currently only works with one interface...
1275	*/
1276	struct fxp_softc *sc = &(fxp_softc[0]);
1277
1278	/*
1279	* disable interrupts
1280	*/
1281	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1282	/*
1283	* send event to deamon
1284	*/
1285	rtems_bsdnet_event_send (sc->daemonTid, INTERRUPT_EVENT);
1286	}
1287
1288	static void fxp_daemon(void *xsc)
1289	{
1290	struct fxp_softc *sc = xsc;
1291	struct ifnet *ifp = &sc->sc_if;
1292	u_int8_t statack;
1293	rtems_event_set events;
1294	rtems_interrupt_level level;
1295
1296	#ifdef NOTUSED
1297	if (sc->suspended) {
1298	return;
1299	}
1300	#endif
1301	for (;;) {
1302
1303	DBGLVL_PRINTK(4,"fxp_daemon waiting for event\n");
1304	/*
1305	* wait for event to receive from interrupt function
1306	*/
1307	rtems_bsdnet_event_receive (INTERRUPT_EVENT,
1308	RTEMS_WAIT\|RTEMS_EVENT_ANY,
1309	RTEMS_NO_TIMEOUT,
1310	&events);
1311	while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1312	DBGLVL_PRINTK(4,"fxp_daemon: processing event, statack = 0x%x\n",
1313	statack);
1314	#ifdef NOTUSED
1315	/*
1316	* It should not be possible to have all bits set; the
1317	* FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1318	* all bits are set, this may indicate that the card has
1319	* been physically ejected, so ignore it.
1320	*/
1321	if (statack == 0xff)
1322	return;
1323	#endif
1324
1325	/*
1326	* First ACK all the interrupts in this pass.
1327	*/
1328	CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1329
1330	/*
1331	* Free any finished transmit mbuf chains.
1332	*
1333	* Handle the CNA event likt a CXTNO event. It used to
1334	* be that this event (control unit not ready) was not
1335	* encountered, but it is now with the SMPng modifications.
1336	* The exact sequence of events that occur when the interface
1337	* is brought up are different now, and if this event
1338	* goes unhandled, the configuration/rxfilter setup sequence
1339	* can stall for several seconds. The result is that no
1340	* packets go out onto the wire for about 5 to 10 seconds
1341	* after the interface is ifconfig'ed for the first time.
1342	*/
1343	if (statack & (FXP_SCB_STATACK_CXTNO \| FXP_SCB_STATACK_CNA)) {
1344	struct fxp_cb_tx *txp;
1345
1346	for (txp = sc->cbl_first; sc->tx_queued &&
1347	(txp->cb_status & FXP_CB_STATUS_C) != 0;
1348	txp = txp->next) {
1349	if (txp->mb_head != NULL) {
1350	m_freem(txp->mb_head);
1351	txp->mb_head = NULL;
1352	}
1353	sc->tx_queued--;
1354	}
1355	sc->cbl_first = txp;
1356	ifp->if_timer = 0;
1357	if (sc->tx_queued == 0) {
1358	if (sc->need_mcsetup)
1359	fxp_mc_setup(sc);
1360	}
1361	/*
1362	* Try to start more packets transmitting.
1363	*/
1364	if (ifp->if_snd.ifq_head != NULL)
1365	fxp_start(ifp);
1366	}
1367	/*
1368	* Process receiver interrupts. If a no-resource (RNR)
1369	* condition exists, get whatever packets we can and
1370	* re-start the receiver.
1371	*/
1372	if (statack & (FXP_SCB_STATACK_FR \| FXP_SCB_STATACK_RNR)) {
1373	struct mbuf *m;
1374	struct fxp_rfa *rfa;
1375	rcvloop:
1376	m = sc->rfa_headm;
1377	rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1378	RFA_ALIGNMENT_FUDGE);
1379
1380	if (rfa->rfa_status & FXP_RFA_STATUS_C) {
1381	/*
1382	* Remove first packet from the chain.
1383	*/
1384	sc->rfa_headm = m->m_next;
1385	m->m_next = NULL;
1386
1387	/*
1388	* Add a new buffer to the receive chain.
1389	* If this fails, the old buffer is recycled
1390	* instead.
1391	*/
1392	if (fxp_add_rfabuf(sc, m) == 0) {
1393	struct ether_header *eh;
1394	int total_len;
1395
1396	total_len = rfa->actual_size &
1397	(MCLBYTES - 1);
1398	if (total_len <
1399	sizeof(struct ether_header)) {
1400	m_freem(m);
1401	goto rcvloop;
1402	}
1403
1404	/*
1405	* Drop the packet if it has CRC
1406	* errors. This test is only needed
1407	* when doing 802.1q VLAN on the 82557
1408	* chip.
1409	*/
1410	if (rfa->rfa_status &
1411	FXP_RFA_STATUS_CRC) {
1412	m_freem(m);
1413	goto rcvloop;
1414	}
1415
1416	m->m_pkthdr.rcvif = ifp;
1417	m->m_pkthdr.len = m->m_len = total_len;
1418	eh = mtod(m, struct ether_header *);
1419	m->m_data +=
1420	sizeof(struct ether_header);
1421	m->m_len -=
1422	sizeof(struct ether_header);
1423	m->m_pkthdr.len = m->m_len;
1424	ether_input(ifp, eh, m);
1425	}
1426	goto rcvloop;
1427	}
1428	if (statack & FXP_SCB_STATACK_RNR) {
1429	fxp_scb_wait(sc);
1430	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1431	vtophys(sc->rfa_headm->m_ext.ext_buf) +
1432	RFA_ALIGNMENT_FUDGE);
1433	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1434	}
1435	}
1436	}
1437	/*
1438	* reenable interrupts
1439	*/
1440	rtems_interrupt_disable (level);
1441	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,0);
1442	rtems_interrupt_enable (level);
1443	}
1444	}
1445
1446	/*
1447	* Update packet in/out/collision statistics. The i82557 doesn't
1448	* allow you to access these counters without doing a fairly
1449	* expensive DMA to get _all_ of the statistics it maintains, so
1450	* we do this operation here only once per second. The statistics
1451	* counters in the kernel are updated from the previous dump-stats
1452	* DMA and then a new dump-stats DMA is started. The on-chip
1453	* counters are zeroed when the DMA completes. If we can't start
1454	* the DMA immediately, we don't wait - we just prepare to read
1455	* them again next time.
1456	*/
1457	static void
1458	fxp_tick(void *xsc)
1459	{
1460	struct fxp_softc *sc = xsc;
1461	struct ifnet *ifp = &sc->sc_if;
1462	struct fxp_stats *sp = sc->fxp_stats;
1463	struct fxp_cb_tx *txp;
1464	int s;
1465
1466	DBGLVL_PRINTK(4,"fxp_tick called\n");
1467
1468	ifp->if_opackets += sp->tx_good;
1469	ifp->if_collisions += sp->tx_total_collisions;
1470	if (sp->rx_good) {
1471	ifp->if_ipackets += sp->rx_good;
1472	sc->rx_idle_secs = 0;
1473	} else {
1474	/*
1475	* Receiver's been idle for another second.
1476	*/
1477	sc->rx_idle_secs++;
1478	}
1479	ifp->if_ierrors +=
1480	sp->rx_crc_errors +
1481	sp->rx_alignment_errors +
1482	sp->rx_rnr_errors +
1483	sp->rx_overrun_errors;
1484	/*
1485	* If any transmit underruns occured, bump up the transmit
1486	* threshold by another 512 bytes (64 * 8).
1487	*/
1488	if (sp->tx_underruns) {
1489	ifp->if_oerrors += sp->tx_underruns;
1490	if (tx_threshold < 192)
1491	tx_threshold += 64;
1492	}
1493	s = splimp();
1494	/*
1495	* Release any xmit buffers that have completed DMA. This isn't
1496	* strictly necessary to do here, but it's advantagous for mbufs
1497	* with external storage to be released in a timely manner rather
1498	* than being defered for a potentially long time. This limits
1499	* the delay to a maximum of one second.
1500	*/
1501	for (txp = sc->cbl_first; sc->tx_queued &&
1502	(txp->cb_status & FXP_CB_STATUS_C) != 0;
1503	txp = txp->next) {
1504	if (txp->mb_head != NULL) {
1505	m_freem(txp->mb_head);
1506	txp->mb_head = NULL;
1507	}
1508	sc->tx_queued--;
1509	}
1510	sc->cbl_first = txp;
1511	/*
1512	* If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1513	* then assume the receiver has locked up and attempt to clear
1514	* the condition by reprogramming the multicast filter. This is
1515	* a work-around for a bug in the 82557 where the receiver locks
1516	* up if it gets certain types of garbage in the syncronization
1517	* bits prior to the packet header. This bug is supposed to only
1518	* occur in 10Mbps mode, but has been seen to occur in 100Mbps
1519	* mode as well (perhaps due to a 10/100 speed transition).
1520	*/
1521	if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1522	sc->rx_idle_secs = 0;
1523	fxp_mc_setup(sc);
1524	}
1525	/*
1526	* If there is no pending command, start another stats
1527	* dump. Otherwise punt for now.
1528	*/
1529	if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1530	/*
1531	* Start another stats dump.
1532	*/
1533	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1534	} else {
1535	/*
1536	* A previous command is still waiting to be accepted.
1537	* Just zero our copy of the stats and wait for the
1538	* next timer event to update them.
1539	*/
1540	sp->tx_good = 0;
1541	sp->tx_underruns = 0;
1542	sp->tx_total_collisions = 0;
1543
1544	sp->rx_good = 0;
1545	sp->rx_crc_errors = 0;
1546	sp->rx_alignment_errors = 0;
1547	sp->rx_rnr_errors = 0;
1548	sp->rx_overrun_errors = 0;
1549	}
1550	#ifdef NOTUSED
1551	if (sc->miibus != NULL)
1552	mii_tick(device_get_softc(sc->miibus));
1553	#endif
1554	splx(s);
1555	/*
1556	* Schedule another timeout one second from now.
1557	*/
1558	if (sc->stat_ch == fxp_timeout_running) {
1559	timeout(fxp_tick, sc, hz);
1560	}
1561	else if (sc->stat_ch == fxp_timeout_stop_rq) {
1562	sc->stat_ch = fxp_timeout_stopped;
1563	}
1564	}
1565
1566	/*
1567	* Stop the interface. Cancels the statistics updater and resets
1568	* the interface.
1569	*/
1570	static void
1571	fxp_stop(struct fxp_softc *sc)
1572	{
1573	struct ifnet *ifp = &sc->sc_if;
1574	struct fxp_cb_tx *txp;
1575	int i;
1576
1577	DBGLVL_PRINTK(2,"fxp_stop called\n");
1578
1579	ifp->if_flags &= ~(IFF_RUNNING \| IFF_OACTIVE);
1580	ifp->if_timer = 0;
1581
1582	/*
1583	* stop stats updater.
1584	*/
1585	if (sc->stat_ch == fxp_timeout_running) {
1586	DBGLVL_PRINTK(3,"fxp_stop: trying to stop stat update tick\n");
1587	sc->stat_ch = fxp_timeout_stop_rq;
1588	while(sc->stat_ch != fxp_timeout_stopped) {
1589	rtems_bsdnet_semaphore_release();
1590	rtems_task_wake_after(fxp_ticksPerSecond);
1591	rtems_bsdnet_semaphore_obtain();
1592	}
1593	DBGLVL_PRINTK(3,"fxp_stop: stat update tick stopped\n");
1594	}
1595	/*
1596	* Issue software reset
1597	*/
1598	DBGLVL_PRINTK(3,"fxp_stop: issue software reset\n");
1599	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1600	DELAY(10);
1601
1602	/*
1603	* Release any xmit buffers.
1604	*/
1605	DBGLVL_PRINTK(3,"fxp_stop: releasing xmit buffers\n");
1606	txp = sc->cbl_base;
1607	if (txp != NULL) {
1608	for (i = 0; i < FXP_NTXCB; i++) {
1609	if (txp[i].mb_head != NULL) {
1610	m_freem(txp[i].mb_head);
1611	txp[i].mb_head = NULL;
1612	}
1613	}
1614	}
1615	sc->tx_queued = 0;
1616
1617	/*
1618	* Free all the receive buffers then reallocate/reinitialize
1619	*/
1620	DBGLVL_PRINTK(3,"fxp_stop: free and reinit all receive buffers\n");
1621	if (sc->rfa_headm != NULL)
1622	m_freem(sc->rfa_headm);
1623	sc->rfa_headm = NULL;
1624	sc->rfa_tailm = NULL;
1625	for (i = 0; i < FXP_NRFABUFS; i++) {
1626	if (fxp_add_rfabuf(sc, NULL) != 0) {
1627	/*
1628	* This "can't happen" - we're at splimp()
1629	* and we just freed all the buffers we need
1630	* above.
1631	*/
1632	panic("fxp_stop: no buffers!");
1633	}
1634	}
1635	DBGLVL_PRINTK(2,"fxp_stop: finished\n");
1636	}
1637
1638	/*
1639	* Watchdog/transmission transmit timeout handler. Called when a
1640	* transmission is started on the interface, but no interrupt is
1641	* received before the timeout. This usually indicates that the
1642	* card has wedged for some reason.
1643	*/
1644	static void
1645	fxp_watchdog(struct ifnet *ifp)
1646	{
1647	struct fxp_softc *sc = ifp->if_softc;
1648
1649	device_printf(sc->dev, "device timeout\n");
1650	ifp->if_oerrors++;
1651
1652	fxp_init(sc);
1653	}
1654
1655	static void
1656	fxp_init(void *xsc)
1657	{
1658	struct fxp_softc *sc = xsc;
1659	struct ifnet *ifp = &sc->sc_if;
1660	struct fxp_cb_config *cbp;
1661	struct fxp_cb_ias *cb_ias;
1662	struct fxp_cb_tx *txp;
1663	int i, prm, s, rv;
1664
1665	rtems_task_wake_after(100);
1666	DBGLVL_PRINTK(2,"fxp_init called\n");
1667
1668	s = splimp();
1669	/*
1670	* Cancel any pending I/O
1671	*/
1672	/*
1673	* E. Norum 2004-10-11
1674	* Add line suggested by "Eugene Denisov" <dea@sendmail.ru>.
1675	* Prevents lockup at initialization.
1676	*/
1677	sc->stat_ch = fxp_timeout_stopped;
1678	fxp_stop(sc);
1679
1680	prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1681
1682	DBGLVL_PRINTK(5,"fxp_init: Initializing base of CBL and RFA memory\n");
1683	/*
1684	* Initialize base of CBL and RFA memory. Loading with zero
1685	* sets it up for regular linear addressing.
1686	*/
1687	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1688	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
1689
1690	fxp_scb_wait(sc);
1691	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
1692
1693	/*
1694	* Initialize base of dump-stats buffer.
1695	*/
1696	DBGLVL_PRINTK(5,"fxp_init: Initializing base of dump-stats buffer\n");
1697	fxp_scb_wait(sc);
1698	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats));
1699	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
1700
1701	/*
1702	* We temporarily use memory that contains the TxCB list to
1703	* construct the config CB. The TxCB list memory is rebuilt
1704	* later.
1705	*/
1706	cbp = (struct fxp_cb_config *) sc->cbl_base;
1707	DBGLVL_PRINTK(5,"fxp_init: cbp = 0x%x\n",cbp);
1708
1709	/*
1710	* This memcpy is kind of disgusting, but there are a bunch of must be
1711	* zero and must be one bits in this structure and this is the easiest
1712	* way to initialize them all to proper values.
1713	*/
1714	memcpy( (void )(u_int32_t)(volatile void *)&cbp->cb_status,
1715	fxp_cb_config_template,
1716	sizeof(fxp_cb_config_template));
1717
1718	cbp->cb_status = 0;
1719	cbp->cb_command = FXP_CB_COMMAND_CONFIG \| FXP_CB_COMMAND_EL;
1720	cbp->link_addr = -1; /* (no) next command */
1721	cbp->byte_count = 22; /* (22) bytes to config */
1722	cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
1723	cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
1724	cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
1725	cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
1726	cbp->type_enable = 0; /* actually reserved */
1727	cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
1728	cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
1729	cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
1730	cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
1731	cbp->dma_mbce = 0; /* (disable) dma max counters */
1732	cbp->late_scb = 0; /* (don't) defer SCB update */
1733	cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
1734	cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
1735	cbp->ci_int = 1; /* interrupt on CU idle */
1736	cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
1737	cbp->ext_stats_dis = 1; /* disable extended counters */
1738	cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
1739	cbp->save_bf = sc->chip == FXP_CHIP_82557 ? 1 : prm;
1740	cbp->disc_short_rx = !prm; /* discard short packets */
1741	cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
1742	cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
1743	cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */
1744	cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
1745	cbp->csma_dis = 0; /* (don't) disable link */
1746	cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */
1747	cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
1748	cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
1749	cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
1750	cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
1751	cbp->nsai = 1; /* (don't) disable source addr insert */
1752	cbp->preamble_length = 2; /* (7 byte) preamble */
1753	cbp->loopback = 0; /* (don't) loopback */
1754	cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
1755	cbp->linear_pri_mode = 0; /* (wait after xmit only) */
1756	cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
1757	cbp->promiscuous = prm; /* promiscuous mode */
1758	cbp->bcast_disable = 0; /* (don't) disable broadcasts */
1759	cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
1760	cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
1761	cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
1762	cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
1763
1764	cbp->stripping = !prm; /* truncate rx packet to byte count */
1765	cbp->padding = 1; /* (do) pad short tx packets */
1766	cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
1767	cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
1768	cbp->ia_wake_en = 0; /* (don't) wake up on address match */
1769	cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */
1770	/* must set wake_en in PMCSR also */
1771	cbp->force_fdx = 0; /* (don't) force full duplex */
1772	cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
1773	cbp->multi_ia = 0; /* (don't) accept multiple IAs */
1774	cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
1775
1776	DBGLVL_PRINTK(5,"fxp_init: cbp initialized\n");
1777	if (sc->chip == FXP_CHIP_82557) {
1778	/*
1779	* The 82557 has no hardware flow control, the values
1780	* below are the defaults for the chip.
1781	*/
1782	cbp->fc_delay_lsb = 0;
1783	cbp->fc_delay_msb = 0x40;
1784	cbp->pri_fc_thresh = 3;
1785	cbp->tx_fc_dis = 0;
1786	cbp->rx_fc_restop = 0;
1787	cbp->rx_fc_restart = 0;
1788	cbp->fc_filter = 0;
1789	cbp->pri_fc_loc = 1;
1790	} else {
1791	cbp->fc_delay_lsb = 0x1f;
1792	cbp->fc_delay_msb = 0x01;
1793	cbp->pri_fc_thresh = 3;
1794	cbp->tx_fc_dis = 0; /* enable transmit FC */
1795	cbp->rx_fc_restop = 1; /* enable FC restop frames */
1796	cbp->rx_fc_restart = 1; /* enable FC restart frames */
1797	cbp->fc_filter = !prm; /* drop FC frames to host */
1798	cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
1799	}
1800
1801	/*
1802	* Start the config command/DMA.
1803	*/
1804	DBGLVL_PRINTK(5,"fxp_init: starting config command/DMA\n");
1805	fxp_scb_wait(sc);
1806	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
1807	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1808	/* ...and wait for it to complete. */
1809	fxp_dma_wait(&cbp->cb_status, sc);
1810
1811	/*
1812	* Now initialize the station address. Temporarily use the TxCB
1813	* memory area like we did above for the config CB.
1814	*/
1815	DBGLVL_PRINTK(5,"fxp_init: initialize station address\n");
1816	cb_ias = (struct fxp_cb_ias *) sc->cbl_base;
1817	cb_ias->cb_status = 0;
1818	cb_ias->cb_command = FXP_CB_COMMAND_IAS \| FXP_CB_COMMAND_EL;
1819	cb_ias->link_addr = -1;
1820	memcpy((void )(u_int32_t)(volatile void *)cb_ias->macaddr,
1821	sc->arpcom.ac_enaddr,
1822	sizeof(sc->arpcom.ac_enaddr));
1823
1824	/*
1825	* Start the IAS (Individual Address Setup) command/DMA.
1826	*/
1827	DBGLVL_PRINTK(5,"fxp_init: start IAS command/DMA\n");
1828	fxp_scb_wait(sc);
1829	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1830	/* ...and wait for it to complete. */
1831	fxp_dma_wait(&cb_ias->cb_status, sc);
1832
1833	/*
1834	* Initialize transmit control block (TxCB) list.
1835	*/
1836
1837	DBGLVL_PRINTK(5,"fxp_init: initialize TxCB list\n");
1838	txp = sc->cbl_base;
1839	memset(txp, 0, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
1840	for (i = 0; i < FXP_NTXCB; i++) {
1841	txp[i].cb_status = FXP_CB_STATUS_C \| FXP_CB_STATUS_OK;
1842	txp[i].cb_command = FXP_CB_COMMAND_NOP;
1843	txp[i].link_addr =
1844	vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status);
1845	if (sc->flags & FXP_FLAG_EXT_TXCB)
1846	txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]);
1847	else
1848	txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]);
1849	txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK];
1850	}
1851	/*
1852	* Set the suspend flag on the first TxCB and start the control
1853	* unit. It will execute the NOP and then suspend.
1854	*/
1855	DBGLVL_PRINTK(5,"fxp_init: setup suspend flag\n");
1856	txp->cb_command = FXP_CB_COMMAND_NOP \| FXP_CB_COMMAND_S;
1857	sc->cbl_first = sc->cbl_last = txp;
1858	sc->tx_queued = 1;
1859
1860	fxp_scb_wait(sc);
1861	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1862
1863	/*
1864	* Initialize receiver buffer area - RFA.
1865	*/
1866	DBGLVL_PRINTK(5,"fxp_init: initialize RFA\n");
1867	fxp_scb_wait(sc);
1868	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1869	vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE);
1870	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1871
1872	#ifdef NOTUSED
1873	/*
1874	* Set current media.
1875	*/
1876	if (sc->miibus != NULL)
1877	mii_mediachg(device_get_softc(sc->miibus));
1878	#endif
1879
1880	ifp->if_flags \|= IFF_RUNNING;
1881	ifp->if_flags &= ~IFF_OACTIVE;
1882
1883	if (sc->daemonTid == 0) {
1884	/*
1885	* Start driver task
1886	*/
1887	sc->daemonTid = rtems_bsdnet_newproc ("FXPd", 4096, fxp_daemon, sc);
1888
1889	/*
1890	* Set up interrupts
1891	*/
1892	sc->irqInfo.hdl = (rtems_irq_hdl)fxp_intr;
1893	sc->irqInfo.on = nopOn;
1894	sc->irqInfo.off = nopOn;
1895	sc->irqInfo.isOn = fxpIsOn;
1896	rv = BSP_install_rtems_irq_handler (&sc->irqInfo);
1897	if (rv != 1) {
1898	rtems_panic ("Can't attach fxp interrupt handler for irq %d\n",
1899	sc->irqInfo.name);
1900	}
1901	}
1902
1903	/*
1904	* Enable interrupts.
1905	*/
1906	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1907	splx(s);
1908
1909	/*
1910	* Start stats updater.
1911	*/
1912	sc->stat_ch = fxp_timeout_running;
1913	DBGLVL_PRINTK(2,"fxp_init: stats updater timeout called with hz=%d\n", hz);
1914	timeout(fxp_tick, sc, hz);
1915	DBGLVL_PRINTK(2,"fxp_init finished\n");
1916	}
1917
1918	#ifdef NOTUSED
1919	static int
1920	fxp_serial_ifmedia_upd(struct ifnet *ifp)
1921	{
1922
1923	return (0);
1924	}
1925
1926	static void
1927	fxp_serial_ifmedia_sts(struct ifnet ifp, struct ifmediareq ifmr)
1928	{
1929
1930	ifmr->ifm_active = IFM_ETHER\|IFM_MANUAL;
1931	}
1932
1933	/*
1934	* Change media according to request.
1935	*/
1936	static int
1937	fxp_ifmedia_upd(struct ifnet *ifp)
1938	{
1939	struct fxp_softc *sc = ifp->if_softc;
1940	struct mii_data *mii;
1941
1942	mii = device_get_softc(sc->miibus);
1943	mii_mediachg(mii);
1944	return (0);
1945	}
1946
1947	/*
1948	* Notify the world which media we're using.
1949	*/
1950	static void
1951	fxp_ifmedia_sts(struct ifnet ifp, struct ifmediareq ifmr)
1952	{
1953	struct fxp_softc *sc = ifp->if_softc;
1954	struct mii_data *mii;
1955
1956	mii = device_get_softc(sc->miibus);
1957	mii_pollstat(mii);
1958	ifmr->ifm_active = mii->mii_media_active;
1959	ifmr->ifm_status = mii->mii_media_status;
1960
1961	if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG)
1962	sc->cu_resume_bug = 1;
1963	else
1964	sc->cu_resume_bug = 0;
1965	}
1966	#endif
1967
1968	/*
1969	* Add a buffer to the end of the RFA buffer list.
1970	* Return 0 if successful, 1 for failure. A failure results in
1971	* adding the 'oldm' (if non-NULL) on to the end of the list -
1972	* tossing out its old contents and recycling it.
1973	* The RFA struct is stuck at the beginning of mbuf cluster and the
1974	* data pointer is fixed up to point just past it.
1975	*/
1976	static int
1977	fxp_add_rfabuf(struct fxp_softc sc, struct mbuf oldm)
1978	{
1979	u_int32_t v;
1980	struct mbuf *m;
1981	struct fxp_rfa rfa, p_rfa;
1982
1983	DBGLVL_PRINTK(4,"fxp_add_rfabuf called\n");
1984
1985	MGETHDR(m, M_DONTWAIT, MT_DATA);
1986	if (m != NULL) {
1987	MCLGET(m, M_DONTWAIT);
1988	if ((m->m_flags & M_EXT) == 0) {
1989	m_freem(m);
1990	if (oldm == NULL)
1991	return 1;
1992	m = oldm;
1993	m->m_data = m->m_ext.ext_buf;
1994	}
1995	} else {
1996	if (oldm == NULL)
1997	return 1;
1998	m = oldm;
1999	m->m_data = m->m_ext.ext_buf;
2000	}
2001
2002	/*
2003	* Move the data pointer up so that the incoming data packet
2004	* will be 32-bit aligned.
2005	*/
2006	m->m_data += RFA_ALIGNMENT_FUDGE;
2007
2008	/*
2009	* Get a pointer to the base of the mbuf cluster and move
2010	* data start past it.
2011	*/
2012	rfa = mtod(m, struct fxp_rfa *);
2013	m->m_data += sizeof(struct fxp_rfa);
2014	rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE);
2015
2016	/*
2017	* Initialize the rest of the RFA. Note that since the RFA
2018	* is misaligned, we cannot store values directly. Instead,
2019	* we use an optimized, inline copy.
2020	*/
2021
2022	rfa->rfa_status = 0;
2023	rfa->rfa_control = FXP_RFA_CONTROL_EL;
2024	rfa->actual_size = 0;
2025
2026	v = -1;
2027	fxp_lwcopy(&v, (volatile u_int32_t*) rfa->link_addr);
2028	fxp_lwcopy(&v, (volatile u_int32_t*) rfa->rbd_addr);
2029
2030	/*
2031	* If there are other buffers already on the list, attach this
2032	* one to the end by fixing up the tail to point to this one.
2033	*/
2034	if (sc->rfa_headm != NULL) {
2035	p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf +
2036	RFA_ALIGNMENT_FUDGE);
2037	sc->rfa_tailm->m_next = m;
2038	v = vtophys(rfa);
2039	fxp_lwcopy(&v, (volatile u_int32_t*) p_rfa->link_addr);
2040	p_rfa->rfa_control = 0;
2041	} else {
2042	sc->rfa_headm = m;
2043	}
2044	sc->rfa_tailm = m;
2045
2046	return (m == oldm);
2047	}
2048
2049	#ifdef NOTUSED
2050	static volatile int
2051	fxp_miibus_readreg(device_t dev, int phy, int reg)
2052	{
2053	struct fxp_softc *sc = device_get_softc(dev);
2054	int count = 10000;
2055	int value;
2056
2057	CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2058	(FXP_MDI_READ << 26) \| (reg << 16) \| (phy << 21));
2059
2060	while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2061	&& count--)
2062	DELAY(10);
2063
2064	if (count <= 0)
2065	device_printf(dev, "fxp_miibus_readreg: timed out\n");
2066
2067	return (value & 0xffff);
2068	}
2069
2070	static void
2071	fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2072	{
2073	struct fxp_softc *sc = device_get_softc(dev);
2074	int count = 10000;
2075
2076	CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2077	(FXP_MDI_WRITE << 26) \| (reg << 16) \| (phy << 21) \|
2078	(value & 0xffff));
2079
2080	while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2081	count--)
2082	DELAY(10);
2083
2084	if (count <= 0)
2085	device_printf(dev, "fxp_miibus_writereg: timed out\n");
2086	}
2087	#endif
2088
2089	static int
2090	fxp_ioctl(struct ifnet *ifp, ioctl_command_t command, caddr_t data)
2091	{
2092	struct fxp_softc *sc = ifp->if_softc;
2093	#ifdef NOTUSED
2094	struct ifreq ifr = (struct ifreq )data;
2095	struct mii_data *mii;
2096	#endif
2097	int s, error = 0;
2098
2099	DBGLVL_PRINTK(2,"fxp_ioctl called\n");
2100
2101	s = splimp();
2102
2103	switch (command) {
2104	case SIOCSIFADDR:
2105	case SIOCGIFADDR:
2106	case SIOCSIFMTU:
2107	error = ether_ioctl(ifp, command, data);
2108	break;
2109
2110	case SIOCSIFFLAGS:
2111	if (ifp->if_flags & IFF_ALLMULTI)
2112	sc->flags \|= FXP_FLAG_ALL_MCAST;
2113	else
2114	sc->flags &= ~FXP_FLAG_ALL_MCAST;
2115
2116	/*
2117	* If interface is marked up and not running, then start it.
2118	* If it is marked down and running, stop it.
2119	* XXX If it's up then re-initialize it. This is so flags
2120	* such as IFF_PROMISC are handled.
2121	*/
2122	if (ifp->if_flags & IFF_UP) {
2123	fxp_init(sc);
2124	} else {
2125	if (ifp->if_flags & IFF_RUNNING)
2126	fxp_stop(sc);
2127	}
2128	break;
2129
2130	case SIOCADDMULTI:
2131	case SIOCDELMULTI:
2132	if (ifp->if_flags & IFF_ALLMULTI)
2133	sc->flags \|= FXP_FLAG_ALL_MCAST;
2134	else
2135	sc->flags &= ~FXP_FLAG_ALL_MCAST;
2136	/*
2137	* Multicast list has changed; set the hardware filter
2138	* accordingly.
2139	*/
2140	if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
2141	fxp_mc_setup(sc);
2142	/*
2143	* fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
2144	* again rather than else {}.
2145	*/
2146	if (sc->flags & FXP_FLAG_ALL_MCAST)
2147	fxp_init(sc);
2148	error = 0;
2149	break;
2150
2151	#ifdef NOTUSED
2152	case SIOCSIFMEDIA:
2153	case SIOCGIFMEDIA:
2154	if (sc->miibus != NULL) {
2155	mii = device_get_softc(sc->miibus);
2156	error = ifmedia_ioctl(ifp, ifr,
2157	&mii->mii_media, command);
2158	} else {
2159	error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2160	}
2161	break;
2162	#endif
2163
2164	case SIO_RTEMS_SHOW_STATS:
2165	fxp_stats(sc);
2166	break;
2167
2168	default:
2169	error = EINVAL;
2170	}
2171	splx(s);
2172	return (error);
2173	}
2174
2175	/*
2176	* Program the multicast filter.
2177	*
2178	* We have an artificial restriction that the multicast setup command
2179	* must be the first command in the chain, so we take steps to ensure
2180	* this. By requiring this, it allows us to keep up the performance of
2181	* the pre-initialized command ring (esp. link pointers) by not actually
2182	* inserting the mcsetup command in the ring - i.e. its link pointer
2183	* points to the TxCB ring, but the mcsetup descriptor itself is not part
2184	* of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2185	* lead into the regular TxCB ring when it completes.
2186	*
2187	* This function must be called at splimp.
2188	*/
2189	static void
2190	fxp_mc_setup(struct fxp_softc *sc)
2191	{
2192	struct fxp_cb_mcs *mcsp = sc->mcsp;
2193	struct ifnet *ifp = &sc->sc_if;
2194	#ifdef NOTUSED
2195	struct ifmultiaddr *ifma;
2196	#endif
2197	int nmcasts;
2198	int count;
2199
2200	DBGLVL_PRINTK(2,"fxp_mc_setup called\n");
2201
2202	/*
2203	* If there are queued commands, we must wait until they are all
2204	* completed. If we are already waiting, then add a NOP command
2205	* with interrupt option so that we're notified when all commands
2206	* have been completed - fxp_start() ensures that no additional
2207	* TX commands will be added when need_mcsetup is true.
2208	*/
2209	if (sc->tx_queued) {
2210	struct fxp_cb_tx *txp;
2211
2212	/*
2213	* need_mcsetup will be true if we are already waiting for the
2214	* NOP command to be completed (see below). In this case, bail.
2215	*/
2216	if (sc->need_mcsetup)
2217	return;
2218	sc->need_mcsetup = 1;
2219
2220	/*
2221	* Add a NOP command with interrupt so that we are notified when all
2222	* TX commands have been processed.
2223	*/
2224	txp = sc->cbl_last->next;
2225	txp->mb_head = NULL;
2226	txp->cb_status = 0;
2227	txp->cb_command = FXP_CB_COMMAND_NOP \|
2228	FXP_CB_COMMAND_S \| FXP_CB_COMMAND_I;
2229	/*
2230	* Advance the end of list forward.
2231	*/
2232	sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
2233	sc->cbl_last = txp;
2234	sc->tx_queued++;
2235	/*
2236	* Issue a resume in case the CU has just suspended.
2237	*/
2238	fxp_scb_wait(sc);
2239	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2240	/*
2241	* Set a 5 second timer just in case we don't hear from the
2242	* card again.
2243	*/
2244	ifp->if_timer = 5;
2245
2246	return;
2247	}
2248	sc->need_mcsetup = 0;
2249
2250	/*
2251	* Initialize multicast setup descriptor.
2252	*/
2253	mcsp->next = sc->cbl_base;
2254	mcsp->mb_head = NULL;
2255	mcsp->cb_status = 0;
2256	mcsp->cb_command = FXP_CB_COMMAND_MCAS \|
2257	FXP_CB_COMMAND_S \| FXP_CB_COMMAND_I;
2258	mcsp->link_addr = vtophys(&sc->cbl_base->cb_status);
2259
2260	nmcasts = 0;
2261	#ifdef NOTUSED /* FIXME: Multicast not supported? */
2262	if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
2263	#if __FreeBSD_version < 500000
2264	LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2265	#else
2266	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2267	#endif
2268	if (ifma->ifma_addr->sa_family != AF_LINK)
2269	continue;
2270	if (nmcasts >= MAXMCADDR) {
2271	sc->flags \|= FXP_FLAG_ALL_MCAST;
2272	nmcasts = 0;
2273	break;
2274	}
2275	memcpy((void )(uintptr_t)(volatile void )
2276	&sc->mcsp->mc_addr[nmcasts][0],
2277	LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 6);
2278	nmcasts++;
2279	}
2280	}
2281	#endif
2282	mcsp->mc_cnt = nmcasts * 6;
2283	sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp;
2284	sc->tx_queued = 1;
2285
2286	/*
2287	* Wait until command unit is not active. This should never
2288	* be the case when nothing is queued, but make sure anyway.
2289	*/
2290	count = 100;
2291	while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2292	FXP_SCB_CUS_ACTIVE && --count)
2293	DELAY(10);
2294	if (count == 0) {
2295	device_printf(sc->dev, "command queue timeout\n");
2296	return;
2297	}
2298
2299	/*
2300	* Start the multicast setup command.
2301	*/
2302	fxp_scb_wait(sc);
2303	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
2304	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2305
2306	ifp->if_timer = 2;
2307	return;
2308	}
2309
2310	#endif /* defined(__i386__) */

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source: rtems/c/src/libchip/network/if_fxp.c @ 6279149

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