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source: rtems/c/src/libchip/network/if_fxp.c @ 4dbbcb7

4.104.114.84.95

Last change on this file since 4dbbcb7 was 1402d56a, checked in by Joel Sherrill <joel.sherrill@…>, on 05/21/04 at 15:18:14

2004-05-21 Till Strauman <strauman@…>

PR/625/networking
libchip/network/dec21140.c, ... : Prevent name clashes by making 'ld_le32()' etc. static inlines. Let dec21140 attach routine return an error rather than panic if no chip is detected (thus allowing for probing).
libchip/network/elnk.c: Let elnk bail out if autoneg never completes instead of looping forever. Avoid divide by zero (crashed my PC).
libchip/network/if_fxp.c: Enable more fxp chip variants but warn that they are UNTESTED.

Property mode set to 100644

File size: 61.3 KB

Line
1	/*-
2	* Copyright (c) 1995, David Greenman
3	* Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
4	* All rights reserved.
5	*
6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions
8	* are met:
9	* 1. Redistributions of source code must retain the above copyright
10	* notice unmodified, this list of conditions, and the following
11	* disclaimer.
12	* 2. Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	*
16	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26	* SUCH DAMAGE.
27	*
28	* $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.118 2001/09/05 23:33:58 brooks Exp $
29	*/
30
31	/*
32	* Intel EtherExpress Pro/100B PCI Fast Ethernet driver
33	*/
34
35	/*
36	* RTEMS Revision Preliminary History
37	*
38	* July XXX, 2002 W. Eric Norum <eric.norum@usask.ca>
39	* Placed in RTEMS CVS repository. All further modifications will be
40	* noted in the CVS log and not in this comment.
41	*
42	* July 11, 2002 W. Eric Norum <eric.norum@usask.ca>
43	* Minor modifications to get driver working with NIC on VersaLogic
44	* Bobcat PC-104 single-board computer. The Bobcat has no video
45	* driver so printf/printk calls are directed to COM2:. This
46	* arrangement seems to require delays after the printk calls or
47	* else things lock up. Perhaps the RTEMS pc386 console code
48	* should be modified to insert these delays itself.
49	*
50	* June 27, 2002 W. Eric Norum <eric.norum@usask.ca>
51	* Obtained from Thomas Doerfler <Thomas.Doerfler@imd-systems.de>.
52	* A big thank-you to Thomas for making this available.
53	*
54	* October 01, 2001 Thomas Doerfler <Thomas.Doerfler@imd-systems.de>
55	* Original RTEMS modifications.
56	*/
57
58	#if defined(__i386__)
59
60	/#define DEBUG_OUT 0/
61
62	#include <rtems.h>
63	#include <rtems/error.h>
64	#include <rtems/rtems_bsdnet.h>
65	#include <bsp.h>
66
67	#include <sys/param.h>
68	#include <sys/mbuf.h>
69	#include <sys/socket.h>
70	#include <sys/sockio.h>
71	#include <net/if.h>
72	#include <netinet/in.h>
73	#include <netinet/if_ether.h>
74	#include <sys/malloc.h>
75	#include <sys/systm.h>
76	#include <bsp.h>
77	#include <pcibios.h>
78	#include <irq.h>
79	#include <rtems/pci.h>
80
81	#ifdef NS
82	#include <netns/ns.h>
83	#include <netns/ns_if.h>
84	#endif
85
86	#include <net/bpf.h>
87
88	#include <vm/vm.h> /* for vtophys */
89
90	#include <net/if_types.h>
91
92	#include "if_fxpreg.h"
93	#include "if_fxpvar.h"
94
95	/*
96	* some adaptation replacements for RTEMS
97	*/
98	static rtems_interval fxp_ticksPerSecond;
99	#define device_printf(device,format,args...) printk(format,## args)
100	#define DELAY(n) rtems_task_wake_after(((n)*fxp_ticksPerSecond/1000000)+1)
101	#ifdef DEBUG_OUT
102	#define DBGLVL_PRINTK(LVL,format, args...) \
103	if (DEBUG_OUT >= (LVL)) { \
104	printk(format, ## args); \
105	}
106	#else
107	#define DBGLVL_PRINTK(LVL,format, args...)
108	#endif
109
110	/*
111	* RTEMS event used by interrupt handler to signal driver tasks.
112	* This must not be any of the events used by the network task synchronization.
113	*/
114	#define INTERRUPT_EVENT RTEMS_EVENT_1
115
116	/*
117	* remapping between PCI device and CPU memmory address view...
118	*/
119	#if defined(__i386)
120	#define vtophys(p) (u_int32_t)(p)
121	#else
122	#define vtophys(p) vtophys(p)
123	#endif
124
125	#define NFXPDRIVER 1
126	static struct fxp_softc fxp_softc[NFXPDRIVER];
127	static int fxp_is_verbose = TRUE;
128	/*
129	* NOTE! On the Alpha, we have an alignment constraint. The
130	* card DMAs the packet immediately following the RFA. However,
131	* the first thing in the packet is a 14-byte Ethernet header.
132	* This means that the packet is misaligned. To compensate,
133	* we actually offset the RFA 2 bytes into the cluster. This
134	* alignes the packet after the Ethernet header at a 32-bit
135	* boundary. HOWEVER! This means that the RFA is misaligned!
136	*/
137	#define RFA_ALIGNMENT_FUDGE 2
138
139	/*
140	* Set initial transmit threshold at 64 (512 bytes). This is
141	* increased by 64 (512 bytes) at a time, to maximum of 192
142	* (1536 bytes), if an underrun occurs.
143	*/
144	static int tx_threshold = 64;
145
146	/*
147	* The configuration byte map has several undefined fields which
148	* must be one or must be zero. Set up a template for these bits
149	* only, (assuming a 82557 chip) leaving the actual configuration
150	* to fxp_init.
151	*
152	* See struct fxp_cb_config for the bit definitions.
153	*/
154	static u_char fxp_cb_config_template[] = {
155	0x0, 0x0, /* cb_status */
156	0x0, 0x0, /* cb_command */
157	0x0, 0x0, 0x0, 0x0, /* link_addr */
158	0x0, /* 0 */
159	0x0, /* 1 */
160	0x0, /* 2 */
161	0x0, /* 3 */
162	0x0, /* 4 */
163	0x0, /* 5 */
164	0x32, /* 6 */
165	0x0, /* 7 */
166	0x0, /* 8 */
167	0x0, /* 9 */
168	0x6, /* 10 */
169	0x0, /* 11 */
170	0x0, /* 12 */
171	0x0, /* 13 */
172	0xf2, /* 14 */
173	0x48, /* 15 */
174	0x0, /* 16 */
175	0x40, /* 17 */
176	0xf0, /* 18 */
177	0x0, /* 19 */
178	0x3f, /* 20 */
179	0x5 /* 21 */
180	};
181
182	struct fxp_ident {
183	u_int16_t devid;
184	char *name;
185	int warn;
186	};
187
188	#define UNTESTED 1
189
190	/*
191	* Claim various Intel PCI device identifiers for this driver. The
192	* sub-vendor and sub-device field are extensively used to identify
193	* particular variants, but we don't currently differentiate between
194	* them.
195	*/
196	static struct fxp_ident fxp_ident_table[] = {
197	{ 0x1229, "Intel Pro 10/100B/100+ Ethernet", UNTESTED },
198	{ 0x2449, "Intel Pro/100 Ethernet", UNTESTED },
199	{ 0x1209, "Intel Embedded 10/100 Ethernet", 0 },
200	{ 0x1029, "Intel Pro/100 Ethernet", UNTESTED },
201	{ 0x1030, "Intel Pro/100 Ethernet", 0 },
202	{ 0x1031, "Intel Pro/100 Ethernet", UNTESTED },
203	{ 0x1032, "Intel Pro/100 Ethernet", UNTESTED },
204	{ 0x1033, "Intel Pro/100 Ethernet", UNTESTED },
205	{ 0x1034, "Intel Pro/100 Ethernet", UNTESTED },
206	{ 0x1035, "Intel Pro/100 Ethernet", UNTESTED },
207	{ 0x1036, "Intel Pro/100 Ethernet", UNTESTED },
208	{ 0x1037, "Intel Pro/100 Ethernet", UNTESTED },
209	{ 0x1038, "Intel Pro/100 Ethernet", UNTESTED },
210	{ 0, NULL },
211	};
212
213	#if 0
214	static int fxp_probe(device_t dev);
215	static int fxp_attach(device_t dev);
216	static int fxp_detach(device_t dev);
217	static int fxp_shutdown(device_t dev);
218	#endif
219	int fxp_output (struct ifnet *,
220	struct mbuf , struct sockaddr , struct rtentry *);
221
222
223	static rtems_isr fxp_intr(rtems_vector_number v);
224	static void fxp_init(void *xsc);
225	static void fxp_tick(void *xsc);
226	static void fxp_start(struct ifnet *ifp);
227	static void fxp_stop(struct fxp_softc *sc);
228	static void fxp_release(struct fxp_softc *sc);
229	static int fxp_ioctl(struct ifnet *ifp, int command,
230	caddr_t data);
231	static void fxp_watchdog(struct ifnet *ifp);
232	static int fxp_add_rfabuf(struct fxp_softc sc, struct mbuf oldm);
233	static void fxp_mc_setup(struct fxp_softc *sc);
234	static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
235	int autosize);
236	static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
237	u_int16_t data);
238	static void fxp_autosize_eeprom(struct fxp_softc *sc);
239	static void fxp_read_eeprom(struct fxp_softc sc, u_short data,
240	int offset, int words);
241	static void fxp_write_eeprom(struct fxp_softc sc, u_short data,
242	int offset, int words);
243	#ifdef NOTUSED
244	static int fxp_ifmedia_upd(struct ifnet *ifp);
245	static void fxp_ifmedia_sts(struct ifnet *ifp,
246	struct ifmediareq *ifmr);
247	static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
248	static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
249	struct ifmediareq *ifmr);
250	static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg);
251	static void fxp_miibus_writereg(device_t dev, int phy, int reg,
252	int value);
253	#endif
254	static __inline void fxp_lwcopy(volatile u_int32_t *src,
255	volatile u_int32_t *dst);
256	static __inline void fxp_scb_wait(struct fxp_softc *sc);
257	static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
258	static __inline void fxp_dma_wait(volatile u_int16_t *status,
259	struct fxp_softc *sc);
260
261	/*
262	* Inline function to copy a 16-bit aligned 32-bit quantity.
263	*/
264	static __inline void
265	fxp_lwcopy(volatile u_int32_t src, volatile u_int32_t dst)
266	{
267	#ifdef __i386__
268	dst = src;
269	#else
270	volatile u_int16_t a = (volatile u_int16_t)src;
271	volatile u_int16_t b = (volatile u_int16_t)dst;
272
273	b[0] = a[0];
274	b[1] = a[1];
275	#endif
276	}
277
278	/*
279	* inline access functions to pci space registers
280	*/
281	static __inline u_int8_t fxp_csr_read_1(struct fxp_softc *sc,int reg) {
282	u_int8_t val;
283	if (sc->pci_regs_are_io) {
284	inport_byte(sc->pci_regs_base + reg,val);
285	}
286	else {
287	val = (u_int8_t)(sc->pci_regs_base+reg);
288	}
289	return val;
290	}
291	static __inline u_int32_t fxp_csr_read_2(struct fxp_softc *sc,int reg) {
292	u_int16_t val;
293	if (sc->pci_regs_are_io) {
294	inport_word(sc->pci_regs_base + reg,val);
295	}
296	else {
297	val = (u_int16_t)(sc->pci_regs_base+reg);
298	}
299	return val;
300	}
301	static __inline u_int32_t fxp_csr_read_4(struct fxp_softc *sc,int reg) {
302	u_int32_t val;
303	if (sc->pci_regs_are_io) {
304	inport_long(sc->pci_regs_base + reg,val);
305	}
306	else {
307	val = (u_int32_t)(sc->pci_regs_base+reg);
308	}
309	return val;
310	}
311
312	/*
313	* Wait for the previous command to be accepted (but not necessarily
314	* completed).
315	*/
316	static __inline void
317	fxp_scb_wait(struct fxp_softc *sc)
318	{
319	int i = 10000;
320
321	while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
322	DELAY(2);
323	if (i == 0)
324	device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
325	CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
326	CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
327	CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS),
328	CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
329	}
330
331	static __inline void
332	fxp_scb_cmd(struct fxp_softc *sc, int cmd)
333	{
334
335	if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
336	CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
337	fxp_scb_wait(sc);
338	}
339	CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
340	}
341
342	static __inline void
343	fxp_dma_wait(volatile u_int16_t status, struct fxp_softc sc)
344	{
345	int i = 10000;
346
347	while (!(*status & FXP_CB_STATUS_C) && --i)
348	DELAY(2);
349	if (i == 0)
350	device_printf(sc->dev, "DMA timeout\n");
351	}
352
353	static __inline unsigned int pci_get_vendor(struct fxp_softc *sc) {
354	u_int16_t vendor;
355	pcib_conf_read16(sc->pci_signature,0,&vendor);
356	return vendor;
357	}
358
359	static __inline unsigned int pci_get_device(struct fxp_softc *sc) {
360	u_int16_t device;
361	pcib_conf_read16(sc->pci_signature,2,&device);
362	return device;
363	}
364
365	static __inline unsigned int pci_get_subvendor(struct fxp_softc *sc) {
366	u_int16_t subvendor;
367	pcib_conf_read16(sc->pci_signature,0x2c,&subvendor);
368	return subvendor;
369	}
370
371	static __inline unsigned int pci_get_subdevice(struct fxp_softc *sc) {
372	u_int16_t subdevice;
373	pcib_conf_read16(sc->pci_signature,0x2e,&subdevice);
374	return subdevice;
375	}
376
377	static __inline unsigned int pci_get_revid(struct fxp_softc *sc) {
378	u_int8_t revid;
379	pcib_conf_read8(sc->pci_signature,0x08,&revid);
380	return revid;
381	}
382
383	static void nopOn(const rtems_irq_connect_data* notUsed)
384	{
385	/*
386	* code should be moved from fxp_Enet_initialize_hardware
387	* to this location
388	*/
389	}
390
391	static int fxpIsOn(const rtems_irq_connect_data* irq)
392	{
393	return BSP_irq_enabled_at_i8259s (irq->name);
394	}
395
396	int
397	rtems_fxp_attach(struct rtems_bsdnet_ifconfig *config, int attaching)
398	{
399	int error = 0;
400	struct fxp_softc *sc;
401	struct ifnet *ifp;
402	u_int16_t val16;
403	u_int32_t val32;
404	u_int16_t data;
405	int i;
406	int s;
407	int unitNumber;
408	char *unitName;
409	u_int16_t dev_id;
410	u_int8_t interrupt;
411	int mtu;
412
413	/*
414	* Set up some timing values
415	*/
416	rtems_clock_get(RTEMS_CLOCK_GET_TICKS_PER_SECOND, &fxp_ticksPerSecond);
417	DBGLVL_PRINTK(1,"fxp_attach called\n");
418
419	/*
420	* Parse driver name
421	*/
422	if ((unitNumber = rtems_bsdnet_parse_driver_name (config, &unitName)) < 0)
423	return 0;
424
425	/*
426	* Is driver free?
427	*/
428	if ((unitNumber <= 0) \|\| (unitNumber > NFXPDRIVER)) {
429	device_printf(dev,"Bad FXP unit number.\n");
430	return 0;
431	}
432	sc = &fxp_softc[unitNumber - 1];
433	ifp = &sc->arpcom.ac_if;
434	if (ifp->if_softc != NULL) {
435	device_printf(dev,"FXP Driver already in use.\n");
436	return 0;
437	}
438
439	memset(sc, 0, sizeof(*sc));
440	#ifdef NOTUSED
441	sc->dev = dev;
442	callout_handle_init(&sc->stat_ch);
443	mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF \| MTX_RECURSE);
444	#endif
445	s = splimp();
446
447	/*
448	* init PCI Bios interface...
449	*/
450	i = pcib_init();
451	DBGLVL_PRINTK(2,"fxp_attach: pcib_init returned %d\n",i);
452	if (i != PCIB_ERR_SUCCESS) {
453	device_printf(dev, "could not initialize pci bios interface\n");
454	return 0;
455	}
456
457	/*
458	* find device on pci bus
459	*/
460	{ int j;
461
462	for (j=0; fxp_ident_table[j].devid; j++ ) {
463	i = pcib_find_by_devid( 0x8086,
464	fxp_ident_table[j].devid,
465	unitNumber-1,
466	&(sc->pci_signature));
467	DBGLVL_PRINTK(2,"fxp_attach: find_devid returned %d "
468	"and pci signature 0x%x\n",
469	i,sc->pci_signature);
470	if (PCIB_ERR_SUCCESS == i) {
471	if ( UNTESTED == fxp_ident_table[j].warn ) {
472	device_printf(dev
473	"WARNING: this chip version has NOT been reported to work under RTEMS yet.\n");
474	device_printf(dev,
475	" If it works OK, report it as tested in 'c/src/libchip/network/if_fxp.c'\n");
476	}
477	break;
478	}
479	}
480	}
481
482	/*
483	* FIXME: add search for more device types...
484	*/
485	if (i != PCIB_ERR_SUCCESS) {
486	device_printf(dev, "could not find 82559ER device\n");
487	return 0;
488	}
489
490
491	/*
492	* Enable bus mastering. Enable memory space too, in case
493	* BIOS/Prom forgot about it.
494	*/
495	pcib_conf_read16(sc->pci_signature, PCI_COMMAND,&val16);
496	val16 \|= (PCI_COMMAND_MEMORY\|PCI_COMMAND_MASTER);
497	pcib_conf_write16(sc->pci_signature, PCI_COMMAND, val16);
498	DBGLVL_PRINTK(3,"fxp_attach: PCI_COMMAND_write = 0x%x\n",val16);
499	pcib_conf_read16(sc->pci_signature, PCI_COMMAND,&val16);
500	DBGLVL_PRINTK(4,"fxp_attach: PCI_COMMAND_read = 0x%x\n",val16);
501
502	/*
503	* Figure out which we should try first - memory mapping or i/o mapping?
504	* We default to memory mapping. Then we accept an override from the
505	* command line. Then we check to see which one is enabled.
506	*/
507	#ifdef NOTUSED
508	m1 = PCI_COMMAND_MEMORY;
509	m2 = PCI_COMMAND_IO;
510	prefer_iomap = 0;
511	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
512	"prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) {
513	m1 = PCI_COMMAND_IO;
514	m2 = PCI_COMMAND_MEMORY;
515	}
516
517	if (val & m1) {
518	sc->rtp = ((m1 == PCI_COMMAND_MEMORY)
519	? SYS_RES_MEMORY : SYS_RES_IOPORT);
520	sc->rgd = ((m1 == PCI_COMMAND_MEMORY)
521	? FXP_PCI_MMBA : FXP_PCI_IOBA);
522	sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
523	0, ~0, 1, RF_ACTIVE);
524	}
525	if (sc->mem == NULL && (val & m2)) {
526	sc->rtp = ((m2 == PCI_COMMAND_MEMORY)
527	? SYS_RES_MEMORY : SYS_RES_IOPORT);
528	sc->rgd = ((m2 == PCI_COMMAND_MEMORY)
529	? FXP_PCI_MMBA : FXP_PCI_IOBA);
530	sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
531	0, ~0, 1, RF_ACTIVE);
532	}
533
534	if (!sc->mem) {
535	device_printf(dev, "could not map device registers\n");
536	error = ENXIO;
537	goto fail;
538	}
539	if (fxp_is_verbose) {
540	device_printf(dev, "using %s space register mapping\n",
541	sc->rtp == SYS_RES_MEMORY? "memory" : "I/O");
542	}
543
544	sc->sc_st = rman_get_bustag(sc->mem);
545	sc->sc_sh = rman_get_bushandle(sc->mem);
546
547	/*
548	* Allocate our interrupt.
549	*/
550	rid = 0;
551	sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
552	RF_SHAREABLE \| RF_ACTIVE);
553	if (sc->irq == NULL) {
554	device_printf(dev, "could not map interrupt\n");
555	error = ENXIO;
556	goto fail;
557	}
558
559	error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
560	fxp_intr, sc, &sc->ih);
561	if (error) {
562	device_printf(dev, "could not setup irq\n");
563	goto fail;
564	}
565	#endif
566
567	/*
568	* get mapping and base address of registers
569	*/
570	pcib_conf_read16(sc->pci_signature, PCI_COMMAND,&val16);
571	DBGLVL_PRINTK(4,"fxp_attach: PCI_COMMAND_read = 0x%x\n",val16);
572	if((val16 & PCI_COMMAND_IO) != 0) {
573	sc->pci_regs_are_io = TRUE;
574	pcib_conf_read32(sc->pci_signature,
575	PCI_BASE_ADDRESS_1,
576	&val32);
577	sc->pci_regs_base = val32 & PCI_BASE_ADDRESS_IO_MASK;
578	}
579	else {
580	sc->pci_regs_are_io = FALSE;
581	pcib_conf_read32(sc->pci_signature,
582	PCI_BASE_ADDRESS_0,
583	&val32);
584	sc->pci_regs_base = val32 & PCI_BASE_ADDRESS_MEM_MASK;
585	}
586	DBGLVL_PRINTK(3,"fxp_attach: CSR registers are mapped in %s space"
587	" at address 0x%x\n",
588	sc->pci_regs_are_io ? "I/O" : "MEM",
589	sc->pci_regs_base);
590
591	/*
592	* get interrupt level to be used
593	*/
594	pcib_conf_read8(sc->pci_signature, 60, &interrupt);
595	DBGLVL_PRINTK(3,"fxp_attach: interrupt = 0x%x\n",interrupt);
596	sc->irqInfo.name = (rtems_irq_symbolic_name)interrupt;
597	/*
598	* Set up interrupts
599	*/
600	sc->irqInfo.hdl = (rtems_irq_hdl)fxp_intr;
601	sc->irqInfo.on = nopOn;
602	sc->irqInfo.off = nopOn;
603	sc->irqInfo.isOn = fxpIsOn;
604	s = BSP_install_rtems_irq_handler (&sc->irqInfo);
605	if (!s)
606	rtems_panic ("Can't attach fxp interrupt handler for irq %d\n",
607	sc->irqInfo.name);
608	/*
609	* Reset to a stable state.
610	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
611	*/
612	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
613	DELAY(10);
614
615	sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB,
616	M_DEVBUF, M_NOWAIT);
617	DBGLVL_PRINTK(3,"fxp_attach: sc->cbl_base = 0x%x\n",sc->cbl_base);
618	if (sc->cbl_base == NULL)
619	goto failmem;
620	else
621	memset(sc->cbl_base, 0, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
622
623	sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF,
624	M_NOWAIT);
625	DBGLVL_PRINTK(3,"fxp_attach: sc->fxp_stats = 0x%x\n",sc->fxp_stats);
626	if (sc->fxp_stats == NULL)
627	goto failmem;
628	else
629	memset(sc->fxp_stats, 0, sizeof(struct fxp_stats));
630
631	sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT);
632	DBGLVL_PRINTK(3,"fxp_attach: sc->mcsp = 0x%x\n",sc->mcsp);
633	if (sc->mcsp == NULL)
634	goto failmem;
635
636	/*
637	* Pre-allocate our receive buffers.
638	*/
639	for (i = 0; i < FXP_NRFABUFS; i++) {
640	if (fxp_add_rfabuf(sc, NULL) != 0) {
641	goto failmem;
642	}
643	}
644
645	/*
646	* Find out how large of an SEEPROM we have.
647	*/
648	DBGLVL_PRINTK(3,"fxp_attach: calling fxp_autosize_eeprom\n");
649	fxp_autosize_eeprom(sc);
650
651	/*
652	* Determine whether we must use the 503 serial interface.
653	*/
654	fxp_read_eeprom(sc, &data, 6, 1);
655	if ((data & FXP_PHY_DEVICE_MASK) != 0 &&
656	(data & FXP_PHY_SERIAL_ONLY))
657	sc->flags \|= FXP_FLAG_SERIAL_MEDIA;
658
659	/*
660	* Find out the basic controller type; we currently only
661	* differentiate between a 82557 and greater.
662	*/
663	fxp_read_eeprom(sc, &data, 5, 1);
664	if ((data >> 8) == 1)
665	sc->chip = FXP_CHIP_82557;
666	DBGLVL_PRINTK(3,"fxp_attach: sc->chip = %d\n",sc->chip);
667
668	/*
669	* Enable workarounds for certain chip revision deficiencies.
670	*
671	* Systems based on the ICH2/ICH2-M chip from Intel have a defect
672	* where the chip can cause a PCI protocol violation if it receives
673	* a CU_RESUME command when it is entering the IDLE state. The
674	* workaround is to disable Dynamic Standby Mode, so the chip never
675	* deasserts CLKRUN#, and always remains in an active state.
676	*
677	* See Intel 82801BA/82801BAM Specification Update, Errata #30.
678	*/
679	#ifdef NOTUSED
680	i = pci_get_device(dev);
681	#else
682	pcib_conf_read16(sc->pci_signature,2,&dev_id);
683	DBGLVL_PRINTK(3,"fxp_attach: device id = 0x%x\n",dev_id);
684	#endif
685	if (dev_id == 0x2449 \|\| (dev_id > 0x1030 && dev_id < 0x1039)) {
686	device_printf(dev, "* See Intel 82801BA/82801BAM Specification Update, Errata #30. *\n");
687	fxp_read_eeprom(sc, &data, 10, 1);
688	if (data & 0x02) { /* STB enable */
689	u_int16_t cksum;
690	int i;
691
692	device_printf(dev,
693	"* DISABLING DYNAMIC STANDBY MODE IN EEPROM *\n");
694	data &= ~0x02;
695	fxp_write_eeprom(sc, &data, 10, 1);
696	device_printf(dev, "New EEPROM ID: 0x%x\n", data);
697	cksum = 0;
698	for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
699	fxp_read_eeprom(sc, &data, i, 1);
700	cksum += data;
701	}
702	i = (1 << sc->eeprom_size) - 1;
703	cksum = 0xBABA - cksum;
704	fxp_read_eeprom(sc, &data, i, 1);
705	fxp_write_eeprom(sc, &cksum, i, 1);
706	device_printf(dev,
707	"EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
708	i, data, cksum);
709	/*
710	* We need to do a full PCI reset here. A software
711	* reset to the port doesn't cut it, but let's try
712	* anyway.
713	*/
714	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
715	DELAY(50);
716	device_printf(dev,
717	"* PLEASE REBOOT THE SYSTEM NOW FOR CORRECT OPERATION *\n");
718	#if 1
719	/*
720	* If the user elects to continue, try the software
721	* workaround, as it is better than nothing.
722	*/
723	sc->flags \|= FXP_FLAG_CU_RESUME_BUG;
724	#endif
725	}
726	}
727
728	/*
729	* If we are not a 82557 chip, we can enable extended features.
730	*/
731	if (sc->chip != FXP_CHIP_82557) {
732	u_int8_t tmp_val;
733	/*
734	* If MWI is enabled in the PCI configuration, and there
735	* is a valid cacheline size (8 or 16 dwords), then tell
736	* the board to turn on MWI.
737	*/
738	pcib_conf_read8(sc->pci_signature,
739	PCI_CACHE_LINE_SIZE,&tmp_val);
740	DBGLVL_PRINTK(3,"fxp_attach: CACHE_LINE_SIZE = %d\n",tmp_val);
741	if (val16 & PCI_COMMAND_MEMORY &&
742	tmp_val != 0)
743	sc->flags \|= FXP_FLAG_MWI_ENABLE;
744
745	/* turn on the extended TxCB feature */
746	sc->flags \|= FXP_FLAG_EXT_TXCB;
747
748	/* enable reception of long frames for VLAN */
749	sc->flags \|= FXP_FLAG_LONG_PKT_EN;
750	DBGLVL_PRINTK(3,"fxp_attach: sc->flags = 0x%x\n",
751	sc->flags);
752	}
753
754	/*
755	* Read MAC address.
756	*/
757	fxp_read_eeprom(sc, (u_int16_t*)sc->arpcom.ac_enaddr, 0, 3);
758	if (fxp_is_verbose) {
759	device_printf(dev, "Ethernet address %x:%x:%x:%x:%x:%x %s \n",
760	((u_int8_t*)sc->arpcom.ac_enaddr)[0],
761	((u_int8_t*)sc->arpcom.ac_enaddr)[1],
762	((u_int8_t*)sc->arpcom.ac_enaddr)[2],
763	((u_int8_t*)sc->arpcom.ac_enaddr)[3],
764	((u_int8_t*)sc->arpcom.ac_enaddr)[4],
765	((u_int8_t*)sc->arpcom.ac_enaddr)[5],
766	sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : "");
767	device_printf(dev, "PCI IDs: 0x%x 0x%x 0x%x 0x%x 0x%x\n",
768	pci_get_vendor(sc), pci_get_device(sc),
769	pci_get_subvendor(sc), pci_get_subdevice(sc),
770	pci_get_revid(sc));
771	device_printf(dev, "Chip Type: %d\n", sc->chip);
772	}
773
774	#ifdef NOTUSED /* do not set up interface at all... */
775	/*
776	* If this is only a 10Mbps device, then there is no MII, and
777	* the PHY will use a serial interface instead.
778	*
779	* The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
780	* doesn't have a programming interface of any sort. The
781	* media is sensed automatically based on how the link partner
782	* is configured. This is, in essence, manual configuration.
783	*/
784	if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
785	ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
786	fxp_serial_ifmedia_sts);
787	ifmedia_add(&sc->sc_media, IFM_ETHER\|IFM_MANUAL, 0, NULL);
788	ifmedia_set(&sc->sc_media, IFM_ETHER\|IFM_MANUAL);
789	} else {
790	if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
791	fxp_ifmedia_sts)) {
792	device_printf(dev, "MII without any PHY!\n");
793	error = ENXIO;
794	goto fail;
795	}
796	}
797	#endif
798	if (config->mtu)
799	mtu = config->mtu;
800	else
801	mtu = ETHERMTU;
802
803	ifp->if_softc = sc;
804	ifp->if_unit = unitNumber;
805	ifp->if_name = unitName;
806	ifp->if_mtu = mtu;
807	ifp->if_baudrate = 100000000;
808	ifp->if_init = fxp_init;
809	ifp->if_ioctl = fxp_ioctl;
810	ifp->if_start = fxp_start;
811	ifp->if_output = ether_output;
812	ifp->if_watchdog = fxp_watchdog;
813	ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX /\| IFF_MULTICAST/;
814	if (ifp->if_snd.ifq_maxlen == 0)
815	ifp->if_snd.ifq_maxlen = ifqmaxlen;
816
817	/*
818	* Attach the interface.
819	*/
820	DBGLVL_PRINTK(3,"fxp_attach: calling if_attach\n");
821	if_attach (ifp);
822	DBGLVL_PRINTK(3,"fxp_attach: calling ether_if_attach\n");
823	ether_ifattach(ifp);
824	DBGLVL_PRINTK(3,"fxp_attach: return from ether_if_attach\n");
825
826	#ifdef NOTUSED
827	/*
828	* Tell the upper layer(s) we support long frames.
829	*/
830	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
831	#endif
832	/*
833	* Let the system queue as many packets as we have available
834	* TX descriptors.
835	*/
836	ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1;
837
838	splx(s);
839	return (0);
840
841	failmem:
842	device_printf(dev, "Failed to malloc memory\n");
843	error = ENOMEM;
844	#ifdef NOTUSED
845	fail:
846	#endif
847	splx(s);
848	fxp_release(sc);
849	return (error);
850	}
851
852	/*
853	* release all resources
854	*/
855	static void
856	fxp_release(struct fxp_softc *sc)
857	{
858
859	#ifdef NOTUSED
860	bus_generic_detach(sc->dev);
861	if (sc->miibus)
862	device_delete_child(sc->dev, sc->miibus);
863	#endif
864	if (sc->cbl_base)
865	free(sc->cbl_base, M_DEVBUF);
866	if (sc->fxp_stats)
867	free(sc->fxp_stats, M_DEVBUF);
868	if (sc->mcsp)
869	free(sc->mcsp, M_DEVBUF);
870	if (sc->rfa_headm)
871	m_freem(sc->rfa_headm);
872
873	#ifdef NOTUSED
874	if (sc->ih)
875	bus_teardown_intr(sc->dev, sc->irq, sc->ih);
876	if (sc->irq)
877	bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
878	if (sc->mem)
879	bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem);
880	mtx_destroy(&sc->sc_mtx);
881	#endif
882	}
883
884	#if NOTUSED
885	/*
886	* Detach interface.
887	*/
888	static int
889	fxp_detach(device_t dev)
890	{
891	struct fxp_softc *sc = device_get_softc(dev);
892	int s;
893
894	/* disable interrupts */
895	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
896
897	s = splimp();
898
899	/*
900	* Stop DMA and drop transmit queue.
901	*/
902	fxp_stop(sc);
903
904	/*
905	* Close down routes etc.
906	*/
907	ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED);
908
909	/*
910	* Free all media structures.
911	*/
912	ifmedia_removeall(&sc->sc_media);
913
914	splx(s);
915
916	/* Release our allocated resources. */
917	fxp_release(sc);
918
919	return (0);
920	}
921
922	/*
923	* Device shutdown routine. Called at system shutdown after sync. The
924	* main purpose of this routine is to shut off receiver DMA so that
925	* kernel memory doesn't get clobbered during warmboot.
926	*/
927	static int
928	fxp_shutdown(device_t dev)
929	{
930	/*
931	* Make sure that DMA is disabled prior to reboot. Not doing
932	* do could allow DMA to corrupt kernel memory during the
933	* reboot before the driver initializes.
934	*/
935	fxp_stop((struct fxp_softc *) device_get_softc(dev));
936	return (0);
937	}
938	#endif
939
940	/*
941	* Show interface statistics
942	*/
943	static void
944	fxp_stats(struct fxp_softc *sc)
945	{
946	struct ifnet *ifp = &sc->sc_if;
947
948	printf (" Output packets:%-8lu", ifp->if_opackets);
949	printf (" Collisions:%-8lu", ifp->if_collisions);
950	printf (" Output errors:%-8lu\n", ifp->if_oerrors);
951	printf (" Input packets:%-8lu", ifp->if_ipackets);
952	printf (" Input errors:%-8lu\n", ifp->if_ierrors);
953	}
954
955	static void
956	fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
957	{
958	u_int16_t reg;
959	int x;
960
961	/*
962	* Shift in data.
963	*/
964	for (x = 1 << (length - 1); x; x >>= 1) {
965	if (data & x)
966	reg = FXP_EEPROM_EECS \| FXP_EEPROM_EEDI;
967	else
968	reg = FXP_EEPROM_EECS;
969	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
970	DELAY(1);
971	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg \| FXP_EEPROM_EESK);
972	DELAY(1);
973	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
974	DELAY(1);
975	}
976	}
977
978	/*
979	* Read from the serial EEPROM. Basically, you manually shift in
980	* the read opcode (one bit at a time) and then shift in the address,
981	* and then you shift out the data (all of this one bit at a time).
982	* The word size is 16 bits, so you have to provide the address for
983	* every 16 bits of data.
984	*/
985	static u_int16_t
986	fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
987	{
988	u_int16_t reg, data;
989	int x;
990
991	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
992	/*
993	* Shift in read opcode.
994	*/
995	fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
996	/*
997	* Shift in address.
998	*/
999	data = 0;
1000	for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
1001	if (offset & x)
1002	reg = FXP_EEPROM_EECS \| FXP_EEPROM_EEDI;
1003	else
1004	reg = FXP_EEPROM_EECS;
1005	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1006	DELAY(1);
1007	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg \| FXP_EEPROM_EESK);
1008	DELAY(1);
1009	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1010	DELAY(1);
1011	reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
1012	data++;
1013	if (autosize && reg == 0) {
1014	sc->eeprom_size = data;
1015	break;
1016	}
1017	}
1018	/*
1019	* Shift out data.
1020	*/
1021	data = 0;
1022	reg = FXP_EEPROM_EECS;
1023	for (x = 1 << 15; x; x >>= 1) {
1024	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg \| FXP_EEPROM_EESK);
1025	DELAY(1);
1026	if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1027	data \|= x;
1028	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1029	DELAY(1);
1030	}
1031	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1032	DELAY(1);
1033
1034	return (data);
1035	}
1036
1037	static void
1038	fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data)
1039	{
1040	int i;
1041
1042	/*
1043	* Erase/write enable.
1044	*/
1045	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1046	fxp_eeprom_shiftin(sc, 0x4, 3);
1047	fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1048	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1049	DELAY(1);
1050	/*
1051	* Shift in write opcode, address, data.
1052	*/
1053	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1054	fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1055	fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1056	fxp_eeprom_shiftin(sc, data, 16);
1057	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1058	DELAY(1);
1059	/*
1060	* Wait for EEPROM to finish up.
1061	*/
1062	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1063	DELAY(1);
1064	for (i = 0; i < 1000; i++) {
1065	if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1066	break;
1067	DELAY(50);
1068	}
1069	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1070	DELAY(1);
1071	/*
1072	* Erase/write disable.
1073	*/
1074	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1075	fxp_eeprom_shiftin(sc, 0x4, 3);
1076	fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1077	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1078	DELAY(1);
1079	}
1080
1081	/*
1082	* From NetBSD:
1083	*
1084	* Figure out EEPROM size.
1085	*
1086	* 559's can have either 64-word or 256-word EEPROMs, the 558
1087	* datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1088	* talks about the existance of 16 to 256 word EEPROMs.
1089	*
1090	* The only known sizes are 64 and 256, where the 256 version is used
1091	* by CardBus cards to store CIS information.
1092	*
1093	* The address is shifted in msb-to-lsb, and after the last
1094	* address-bit the EEPROM is supposed to output a `dummy zero' bit,
1095	* after which follows the actual data. We try to detect this zero, by
1096	* probing the data-out bit in the EEPROM control register just after
1097	* having shifted in a bit. If the bit is zero, we assume we've
1098	* shifted enough address bits. The data-out should be tri-state,
1099	* before this, which should translate to a logical one.
1100	*/
1101	static void
1102	fxp_autosize_eeprom(struct fxp_softc *sc)
1103	{
1104
1105	/* guess maximum size of 256 words */
1106	sc->eeprom_size = 8;
1107
1108	/* autosize */
1109	(void) fxp_eeprom_getword(sc, 0, 1);
1110	}
1111
1112	static void
1113	fxp_read_eeprom(struct fxp_softc sc, u_short data, int offset, int words)
1114	{
1115	int i;
1116
1117	for (i = 0; i < words; i++) {
1118	data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1119	DBGLVL_PRINTK(4,"fxp_eeprom_read(off=0x%x)=0x%x\n",
1120	offset+i,data[i]);
1121	}
1122	}
1123
1124	static void
1125	fxp_write_eeprom(struct fxp_softc sc, u_short data, int offset, int words)
1126	{
1127	int i;
1128
1129	for (i = 0; i < words; i++)
1130	fxp_eeprom_putword(sc, offset + i, data[i]);
1131	DBGLVL_PRINTK(4,"fxp_eeprom_write(off=0x%x,0x%x)\n",
1132	offset+i,data[i]);
1133	}
1134
1135	/*
1136	* Start packet transmission on the interface.
1137	*/
1138	static void
1139	fxp_start(struct ifnet *ifp)
1140	{
1141	struct fxp_softc *sc = ifp->if_softc;
1142	struct fxp_cb_tx *txp;
1143
1144	DBGLVL_PRINTK(3,"fxp_start called\n");
1145
1146	/*
1147	* See if we need to suspend xmit until the multicast filter
1148	* has been reprogrammed (which can only be done at the head
1149	* of the command chain).
1150	*/
1151	if (sc->need_mcsetup) {
1152	return;
1153	}
1154
1155	txp = NULL;
1156
1157	/*
1158	* We're finished if there is nothing more to add to the list or if
1159	* we're all filled up with buffers to transmit.
1160	* NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1161	* a NOP command when needed.
1162	*/
1163	while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) {
1164	struct mbuf m, mb_head;
1165	int segment;
1166
1167	/*
1168	* Grab a packet to transmit.
1169	*/
1170	IF_DEQUEUE(&ifp->if_snd, mb_head);
1171
1172	/*
1173	* Get pointer to next available tx desc.
1174	*/
1175	txp = sc->cbl_last->next;
1176
1177	/*
1178	* Go through each of the mbufs in the chain and initialize
1179	* the transmit buffer descriptors with the physical address
1180	* and size of the mbuf.
1181	*/
1182	tbdinit:
1183	for (m = mb_head, segment = 0; m != NULL; m = m->m_next) {
1184	if (m->m_len != 0) {
1185	if (segment == FXP_NTXSEG)
1186	break;
1187	txp->tbd[segment].tb_addr =
1188	vtophys(mtod(m, vm_offset_t));
1189	txp->tbd[segment].tb_size = m->m_len;
1190	segment++;
1191	}
1192	}
1193	if (m != NULL) {
1194	struct mbuf *mn;
1195
1196	/*
1197	* We ran out of segments. We have to recopy this
1198	* mbuf chain first. Bail out if we can't get the
1199	* new buffers.
1200	*/
1201	MGETHDR(mn, M_DONTWAIT, MT_DATA);
1202	if (mn == NULL) {
1203	m_freem(mb_head);
1204	break;
1205	}
1206	if (mb_head->m_pkthdr.len > MHLEN) {
1207	MCLGET(mn, M_DONTWAIT);
1208	if ((mn->m_flags & M_EXT) == 0) {
1209	m_freem(mn);
1210	m_freem(mb_head);
1211	break;
1212	}
1213	}
1214	m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
1215	mtod(mn, caddr_t));
1216	mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len;
1217	m_freem(mb_head);
1218	mb_head = mn;
1219	goto tbdinit;
1220	}
1221
1222	txp->tbd_number = segment;
1223	txp->mb_head = mb_head;
1224	txp->cb_status = 0;
1225	if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1226	txp->cb_command =
1227	FXP_CB_COMMAND_XMIT \| FXP_CB_COMMAND_SF \|
1228	FXP_CB_COMMAND_S;
1229	} else {
1230	txp->cb_command =
1231	FXP_CB_COMMAND_XMIT \| FXP_CB_COMMAND_SF \|
1232	FXP_CB_COMMAND_S \| FXP_CB_COMMAND_I;
1233	/*
1234	* Set a 5 second timer just in case we don't hear
1235	* from the card again.
1236	*/
1237	ifp->if_timer = 5;
1238	}
1239	txp->tx_threshold = tx_threshold;
1240
1241	/*
1242	* Advance the end of list forward.
1243	*/
1244
1245	#ifdef __alpha__
1246	/*
1247	* On platforms which can't access memory in 16-bit
1248	* granularities, we must prevent the card from DMA'ing
1249	* up the status while we update the command field.
1250	* This could cause us to overwrite the completion status.
1251	*/
1252	atomic_clear_short(&sc->cbl_last->cb_command,
1253	FXP_CB_COMMAND_S);
1254	#else
1255	sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
1256	#endif /__alpha__/
1257	sc->cbl_last = txp;
1258
1259	/*
1260	* Advance the beginning of the list forward if there are
1261	* no other packets queued (when nothing is queued, cbl_first
1262	* sits on the last TxCB that was sent out).
1263	*/
1264	if (sc->tx_queued == 0)
1265	sc->cbl_first = txp;
1266
1267	sc->tx_queued++;
1268
1269	#ifdef NOTUSED
1270	/*
1271	* Pass packet to bpf if there is a listener.
1272	*/
1273	if (ifp->if_bpf)
1274	bpf_mtap(ifp, mb_head);
1275	#endif
1276	}
1277
1278	/*
1279	* We're finished. If we added to the list, issue a RESUME to get DMA
1280	* going again if suspended.
1281	*/
1282	if (txp != NULL) {
1283	fxp_scb_wait(sc);
1284	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1285	}
1286	}
1287
1288	/*
1289	* Process interface interrupts.
1290	*/
1291	static rtems_isr fxp_intr(rtems_vector_number v)
1292	{
1293	/*
1294	* FIXME: currently only works with one interface...
1295	*/
1296	struct fxp_softc *sc = &(fxp_softc[0]);
1297
1298	/*
1299	* disable interrupts
1300	*/
1301	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1302	/*
1303	* send event to deamon
1304	*/
1305	rtems_event_send (sc->daemonTid, INTERRUPT_EVENT);
1306	}
1307
1308	static void fxp_daemon(void *xsc)
1309	{
1310	struct fxp_softc *sc = xsc;
1311	struct ifnet *ifp = &sc->sc_if;
1312	u_int8_t statack;
1313	rtems_event_set events;
1314	rtems_interrupt_level level;
1315
1316	#ifdef NOTUSED
1317	if (sc->suspended) {
1318	return;
1319	}
1320	#endif
1321	for (;;) {
1322
1323	DBGLVL_PRINTK(4,"fxp_daemon waiting for event\n");
1324	/*
1325	* wait for event to receive from interrupt function
1326	*/
1327	rtems_bsdnet_event_receive (INTERRUPT_EVENT,
1328	RTEMS_WAIT\|RTEMS_EVENT_ANY,
1329	RTEMS_NO_TIMEOUT,
1330	&events);
1331	while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1332	DBGLVL_PRINTK(4,"fxp_daemon: processing event, statack = 0x%x\n",
1333	statack);
1334	#ifdef NOTUSED
1335	/*
1336	* It should not be possible to have all bits set; the
1337	* FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1338	* all bits are set, this may indicate that the card has
1339	* been physically ejected, so ignore it.
1340	*/
1341	if (statack == 0xff)
1342	return;
1343	#endif
1344
1345	/*
1346	* First ACK all the interrupts in this pass.
1347	*/
1348	CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1349
1350	/*
1351	* Free any finished transmit mbuf chains.
1352	*
1353	* Handle the CNA event likt a CXTNO event. It used to
1354	* be that this event (control unit not ready) was not
1355	* encountered, but it is now with the SMPng modifications.
1356	* The exact sequence of events that occur when the interface
1357	* is brought up are different now, and if this event
1358	* goes unhandled, the configuration/rxfilter setup sequence
1359	* can stall for several seconds. The result is that no
1360	* packets go out onto the wire for about 5 to 10 seconds
1361	* after the interface is ifconfig'ed for the first time.
1362	*/
1363	if (statack & (FXP_SCB_STATACK_CXTNO \| FXP_SCB_STATACK_CNA)) {
1364	struct fxp_cb_tx *txp;
1365
1366	for (txp = sc->cbl_first; sc->tx_queued &&
1367	(txp->cb_status & FXP_CB_STATUS_C) != 0;
1368	txp = txp->next) {
1369	if (txp->mb_head != NULL) {
1370	m_freem(txp->mb_head);
1371	txp->mb_head = NULL;
1372	}
1373	sc->tx_queued--;
1374	}
1375	sc->cbl_first = txp;
1376	ifp->if_timer = 0;
1377	if (sc->tx_queued == 0) {
1378	if (sc->need_mcsetup)
1379	fxp_mc_setup(sc);
1380	}
1381	/*
1382	* Try to start more packets transmitting.
1383	*/
1384	if (ifp->if_snd.ifq_head != NULL)
1385	fxp_start(ifp);
1386	}
1387	/*
1388	* Process receiver interrupts. If a no-resource (RNR)
1389	* condition exists, get whatever packets we can and
1390	* re-start the receiver.
1391	*/
1392	if (statack & (FXP_SCB_STATACK_FR \| FXP_SCB_STATACK_RNR)) {
1393	struct mbuf *m;
1394	struct fxp_rfa *rfa;
1395	rcvloop:
1396	m = sc->rfa_headm;
1397	rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1398	RFA_ALIGNMENT_FUDGE);
1399
1400	if (rfa->rfa_status & FXP_RFA_STATUS_C) {
1401	/*
1402	* Remove first packet from the chain.
1403	*/
1404	sc->rfa_headm = m->m_next;
1405	m->m_next = NULL;
1406
1407	/*
1408	* Add a new buffer to the receive chain.
1409	* If this fails, the old buffer is recycled
1410	* instead.
1411	*/
1412	if (fxp_add_rfabuf(sc, m) == 0) {
1413	struct ether_header *eh;
1414	int total_len;
1415
1416	total_len = rfa->actual_size &
1417	(MCLBYTES - 1);
1418	if (total_len <
1419	sizeof(struct ether_header)) {
1420	m_freem(m);
1421	goto rcvloop;
1422	}
1423
1424	/*
1425	* Drop the packet if it has CRC
1426	* errors. This test is only needed
1427	* when doing 802.1q VLAN on the 82557
1428	* chip.
1429	*/
1430	if (rfa->rfa_status &
1431	FXP_RFA_STATUS_CRC) {
1432	m_freem(m);
1433	goto rcvloop;
1434	}
1435
1436	m->m_pkthdr.rcvif = ifp;
1437	m->m_pkthdr.len = m->m_len = total_len;
1438	eh = mtod(m, struct ether_header *);
1439	m->m_data +=
1440	sizeof(struct ether_header);
1441	m->m_len -=
1442	sizeof(struct ether_header);
1443	m->m_pkthdr.len = m->m_len;
1444	ether_input(ifp, eh, m);
1445	}
1446	goto rcvloop;
1447	}
1448	if (statack & FXP_SCB_STATACK_RNR) {
1449	fxp_scb_wait(sc);
1450	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1451	vtophys(sc->rfa_headm->m_ext.ext_buf) +
1452	RFA_ALIGNMENT_FUDGE);
1453	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1454	}
1455	}
1456	}
1457	/*
1458	* reenable interrupts
1459	*/
1460	rtems_interrupt_disable (level);
1461	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,0);
1462	rtems_interrupt_enable (level);
1463	}
1464	}
1465
1466	/*
1467	* Update packet in/out/collision statistics. The i82557 doesn't
1468	* allow you to access these counters without doing a fairly
1469	* expensive DMA to get _all_ of the statistics it maintains, so
1470	* we do this operation here only once per second. The statistics
1471	* counters in the kernel are updated from the previous dump-stats
1472	* DMA and then a new dump-stats DMA is started. The on-chip
1473	* counters are zeroed when the DMA completes. If we can't start
1474	* the DMA immediately, we don't wait - we just prepare to read
1475	* them again next time.
1476	*/
1477	static void
1478	fxp_tick(void *xsc)
1479	{
1480	struct fxp_softc *sc = xsc;
1481	struct ifnet *ifp = &sc->sc_if;
1482	struct fxp_stats *sp = sc->fxp_stats;
1483	struct fxp_cb_tx *txp;
1484	int s;
1485
1486	DBGLVL_PRINTK(4,"fxp_tick called\n");
1487
1488	ifp->if_opackets += sp->tx_good;
1489	ifp->if_collisions += sp->tx_total_collisions;
1490	if (sp->rx_good) {
1491	ifp->if_ipackets += sp->rx_good;
1492	sc->rx_idle_secs = 0;
1493	} else {
1494	/*
1495	* Receiver's been idle for another second.
1496	*/
1497	sc->rx_idle_secs++;
1498	}
1499	ifp->if_ierrors +=
1500	sp->rx_crc_errors +
1501	sp->rx_alignment_errors +
1502	sp->rx_rnr_errors +
1503	sp->rx_overrun_errors;
1504	/*
1505	* If any transmit underruns occured, bump up the transmit
1506	* threshold by another 512 bytes (64 * 8).
1507	*/
1508	if (sp->tx_underruns) {
1509	ifp->if_oerrors += sp->tx_underruns;
1510	if (tx_threshold < 192)
1511	tx_threshold += 64;
1512	}
1513	s = splimp();
1514	/*
1515	* Release any xmit buffers that have completed DMA. This isn't
1516	* strictly necessary to do here, but it's advantagous for mbufs
1517	* with external storage to be released in a timely manner rather
1518	* than being defered for a potentially long time. This limits
1519	* the delay to a maximum of one second.
1520	*/
1521	for (txp = sc->cbl_first; sc->tx_queued &&
1522	(txp->cb_status & FXP_CB_STATUS_C) != 0;
1523	txp = txp->next) {
1524	if (txp->mb_head != NULL) {
1525	m_freem(txp->mb_head);
1526	txp->mb_head = NULL;
1527	}
1528	sc->tx_queued--;
1529	}
1530	sc->cbl_first = txp;
1531	/*
1532	* If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1533	* then assume the receiver has locked up and attempt to clear
1534	* the condition by reprogramming the multicast filter. This is
1535	* a work-around for a bug in the 82557 where the receiver locks
1536	* up if it gets certain types of garbage in the syncronization
1537	* bits prior to the packet header. This bug is supposed to only
1538	* occur in 10Mbps mode, but has been seen to occur in 100Mbps
1539	* mode as well (perhaps due to a 10/100 speed transition).
1540	*/
1541	if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1542	sc->rx_idle_secs = 0;
1543	fxp_mc_setup(sc);
1544	}
1545	/*
1546	* If there is no pending command, start another stats
1547	* dump. Otherwise punt for now.
1548	*/
1549	if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1550	/*
1551	* Start another stats dump.
1552	*/
1553	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1554	} else {
1555	/*
1556	* A previous command is still waiting to be accepted.
1557	* Just zero our copy of the stats and wait for the
1558	* next timer event to update them.
1559	*/
1560	sp->tx_good = 0;
1561	sp->tx_underruns = 0;
1562	sp->tx_total_collisions = 0;
1563
1564	sp->rx_good = 0;
1565	sp->rx_crc_errors = 0;
1566	sp->rx_alignment_errors = 0;
1567	sp->rx_rnr_errors = 0;
1568	sp->rx_overrun_errors = 0;
1569	}
1570	#ifdef NOTUSED
1571	if (sc->miibus != NULL)
1572	mii_tick(device_get_softc(sc->miibus));
1573	#endif
1574	splx(s);
1575	/*
1576	* Schedule another timeout one second from now.
1577	*/
1578	if (sc->stat_ch == fxp_timeout_running) {
1579	timeout(fxp_tick, sc, hz);
1580	}
1581	else if (sc->stat_ch == fxp_timeout_stop_rq) {
1582	sc->stat_ch = fxp_timeout_stopped;
1583	}
1584	}
1585
1586	/*
1587	* Stop the interface. Cancels the statistics updater and resets
1588	* the interface.
1589	*/
1590	static void
1591	fxp_stop(struct fxp_softc *sc)
1592	{
1593	struct ifnet *ifp = &sc->sc_if;
1594	struct fxp_cb_tx *txp;
1595	int i;
1596
1597	DBGLVL_PRINTK(2,"fxp_stop called\n");
1598
1599	ifp->if_flags &= ~(IFF_RUNNING \| IFF_OACTIVE);
1600	ifp->if_timer = 0;
1601
1602	/*
1603	* stop stats updater.
1604	*/
1605	if (sc->stat_ch == fxp_timeout_running) {
1606	DBGLVL_PRINTK(3,"fxp_stop: trying to stop stat update tick\n");
1607	sc->stat_ch = fxp_timeout_stop_rq;
1608	while(sc->stat_ch != fxp_timeout_stopped) {
1609	rtems_bsdnet_semaphore_release();
1610	rtems_task_wake_after(fxp_ticksPerSecond);
1611	rtems_bsdnet_semaphore_obtain();
1612	}
1613	DBGLVL_PRINTK(3,"fxp_stop: stat update tick stopped\n");
1614	}
1615	/*
1616	* Issue software reset
1617	*/
1618	DBGLVL_PRINTK(3,"fxp_stop: issue software reset\n");
1619	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1620	DELAY(10);
1621
1622	/*
1623	* Release any xmit buffers.
1624	*/
1625	DBGLVL_PRINTK(3,"fxp_stop: releasing xmit buffers\n");
1626	txp = sc->cbl_base;
1627	if (txp != NULL) {
1628	for (i = 0; i < FXP_NTXCB; i++) {
1629	if (txp[i].mb_head != NULL) {
1630	m_freem(txp[i].mb_head);
1631	txp[i].mb_head = NULL;
1632	}
1633	}
1634	}
1635	sc->tx_queued = 0;
1636
1637	/*
1638	* Free all the receive buffers then reallocate/reinitialize
1639	*/
1640	DBGLVL_PRINTK(3,"fxp_stop: free and reinit all receive buffers\n");
1641	if (sc->rfa_headm != NULL)
1642	m_freem(sc->rfa_headm);
1643	sc->rfa_headm = NULL;
1644	sc->rfa_tailm = NULL;
1645	for (i = 0; i < FXP_NRFABUFS; i++) {
1646	if (fxp_add_rfabuf(sc, NULL) != 0) {
1647	/*
1648	* This "can't happen" - we're at splimp()
1649	* and we just freed all the buffers we need
1650	* above.
1651	*/
1652	panic("fxp_stop: no buffers!");
1653	}
1654	}
1655	DBGLVL_PRINTK(2,"fxp_stop: finished\n");
1656	}
1657
1658	/*
1659	* Watchdog/transmission transmit timeout handler. Called when a
1660	* transmission is started on the interface, but no interrupt is
1661	* received before the timeout. This usually indicates that the
1662	* card has wedged for some reason.
1663	*/
1664	static void
1665	fxp_watchdog(struct ifnet *ifp)
1666	{
1667	struct fxp_softc *sc = ifp->if_softc;
1668
1669	device_printf(sc->dev, "device timeout\n");
1670	ifp->if_oerrors++;
1671
1672	fxp_init(sc);
1673	}
1674
1675	static void
1676	fxp_init(void *xsc)
1677	{
1678	struct fxp_softc *sc = xsc;
1679	struct ifnet *ifp = &sc->sc_if;
1680	struct fxp_cb_config *cbp;
1681	struct fxp_cb_ias *cb_ias;
1682	struct fxp_cb_tx *txp;
1683	int i, prm, s;
1684
1685	rtems_task_wake_after(100);
1686	DBGLVL_PRINTK(2,"fxp_init called\n");
1687
1688	s = splimp();
1689	/*
1690	* Cancel any pending I/O
1691	*/
1692	fxp_stop(sc);
1693
1694	prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1695
1696	DBGLVL_PRINTK(5,"fxp_init: Initializing base of CBL and RFA memory\n");
1697	/*
1698	* Initialize base of CBL and RFA memory. Loading with zero
1699	* sets it up for regular linear addressing.
1700	*/
1701	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1702	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
1703
1704	fxp_scb_wait(sc);
1705	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
1706
1707	/*
1708	* Initialize base of dump-stats buffer.
1709	*/
1710	DBGLVL_PRINTK(5,"fxp_init: Initializing base of dump-stats buffer\n");
1711	fxp_scb_wait(sc);
1712	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats));
1713	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
1714
1715	/*
1716	* We temporarily use memory that contains the TxCB list to
1717	* construct the config CB. The TxCB list memory is rebuilt
1718	* later.
1719	*/
1720	cbp = (struct fxp_cb_config *) sc->cbl_base;
1721	DBGLVL_PRINTK(5,"fxp_init: cbp = 0x%x\n",cbp);
1722
1723	/*
1724	* This memcpy is kind of disgusting, but there are a bunch of must be
1725	* zero and must be one bits in this structure and this is the easiest
1726	* way to initialize them all to proper values.
1727	*/
1728	memcpy( (void )(u_int32_t)(volatile void *)&cbp->cb_status,
1729	fxp_cb_config_template,
1730	sizeof(fxp_cb_config_template));
1731
1732	cbp->cb_status = 0;
1733	cbp->cb_command = FXP_CB_COMMAND_CONFIG \| FXP_CB_COMMAND_EL;
1734	cbp->link_addr = -1; /* (no) next command */
1735	cbp->byte_count = 22; /* (22) bytes to config */
1736	cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
1737	cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
1738	cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
1739	cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
1740	cbp->type_enable = 0; /* actually reserved */
1741	cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
1742	cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
1743	cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
1744	cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
1745	cbp->dma_mbce = 0; /* (disable) dma max counters */
1746	cbp->late_scb = 0; /* (don't) defer SCB update */
1747	cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
1748	cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
1749	cbp->ci_int = 1; /* interrupt on CU idle */
1750	cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
1751	cbp->ext_stats_dis = 1; /* disable extended counters */
1752	cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
1753	cbp->save_bf = sc->chip == FXP_CHIP_82557 ? 1 : prm;
1754	cbp->disc_short_rx = !prm; /* discard short packets */
1755	cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
1756	cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
1757	cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */
1758	cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
1759	cbp->csma_dis = 0; /* (don't) disable link */
1760	cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */
1761	cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
1762	cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
1763	cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
1764	cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
1765	cbp->nsai = 1; /* (don't) disable source addr insert */
1766	cbp->preamble_length = 2; /* (7 byte) preamble */
1767	cbp->loopback = 0; /* (don't) loopback */
1768	cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
1769	cbp->linear_pri_mode = 0; /* (wait after xmit only) */
1770	cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
1771	cbp->promiscuous = prm; /* promiscuous mode */
1772	cbp->bcast_disable = 0; /* (don't) disable broadcasts */
1773	cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
1774	cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
1775	cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
1776	cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
1777
1778	cbp->stripping = !prm; /* truncate rx packet to byte count */
1779	cbp->padding = 1; /* (do) pad short tx packets */
1780	cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
1781	cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
1782	cbp->ia_wake_en = 0; /* (don't) wake up on address match */
1783	cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */
1784	/* must set wake_en in PMCSR also */
1785	cbp->force_fdx = 0; /* (don't) force full duplex */
1786	cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
1787	cbp->multi_ia = 0; /* (don't) accept multiple IAs */
1788	cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
1789
1790	DBGLVL_PRINTK(5,"fxp_init: cbp initialized\n");
1791	if (sc->chip == FXP_CHIP_82557) {
1792	/*
1793	* The 82557 has no hardware flow control, the values
1794	* below are the defaults for the chip.
1795	*/
1796	cbp->fc_delay_lsb = 0;
1797	cbp->fc_delay_msb = 0x40;
1798	cbp->pri_fc_thresh = 3;
1799	cbp->tx_fc_dis = 0;
1800	cbp->rx_fc_restop = 0;
1801	cbp->rx_fc_restart = 0;
1802	cbp->fc_filter = 0;
1803	cbp->pri_fc_loc = 1;
1804	} else {
1805	cbp->fc_delay_lsb = 0x1f;
1806	cbp->fc_delay_msb = 0x01;
1807	cbp->pri_fc_thresh = 3;
1808	cbp->tx_fc_dis = 0; /* enable transmit FC */
1809	cbp->rx_fc_restop = 1; /* enable FC restop frames */
1810	cbp->rx_fc_restart = 1; /* enable FC restart frames */
1811	cbp->fc_filter = !prm; /* drop FC frames to host */
1812	cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
1813	}
1814
1815	/*
1816	* Start the config command/DMA.
1817	*/
1818	DBGLVL_PRINTK(5,"fxp_init: starting config command/DMA\n");
1819	fxp_scb_wait(sc);
1820	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
1821	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1822	/* ...and wait for it to complete. */
1823	fxp_dma_wait(&cbp->cb_status, sc);
1824
1825	/*
1826	* Now initialize the station address. Temporarily use the TxCB
1827	* memory area like we did above for the config CB.
1828	*/
1829	DBGLVL_PRINTK(5,"fxp_init: initialize station address\n");
1830	cb_ias = (struct fxp_cb_ias *) sc->cbl_base;
1831	cb_ias->cb_status = 0;
1832	cb_ias->cb_command = FXP_CB_COMMAND_IAS \| FXP_CB_COMMAND_EL;
1833	cb_ias->link_addr = -1;
1834	memcpy((void )(u_int32_t)(volatile void *)cb_ias->macaddr,
1835	sc->arpcom.ac_enaddr,
1836	sizeof(sc->arpcom.ac_enaddr));
1837
1838	/*
1839	* Start the IAS (Individual Address Setup) command/DMA.
1840	*/
1841	DBGLVL_PRINTK(5,"fxp_init: start IAS command/DMA\n");
1842	fxp_scb_wait(sc);
1843	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1844	/* ...and wait for it to complete. */
1845	fxp_dma_wait(&cb_ias->cb_status, sc);
1846
1847	/*
1848	* Initialize transmit control block (TxCB) list.
1849	*/
1850
1851	DBGLVL_PRINTK(5,"fxp_init: initialize TxCB list\n");
1852	txp = sc->cbl_base;
1853	memset(txp, 0, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
1854	for (i = 0; i < FXP_NTXCB; i++) {
1855	txp[i].cb_status = FXP_CB_STATUS_C \| FXP_CB_STATUS_OK;
1856	txp[i].cb_command = FXP_CB_COMMAND_NOP;
1857	txp[i].link_addr =
1858	vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status);
1859	if (sc->flags & FXP_FLAG_EXT_TXCB)
1860	txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]);
1861	else
1862	txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]);
1863	txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK];
1864	}
1865	/*
1866	* Set the suspend flag on the first TxCB and start the control
1867	* unit. It will execute the NOP and then suspend.
1868	*/
1869	DBGLVL_PRINTK(5,"fxp_init: setup suspend flag\n");
1870	txp->cb_command = FXP_CB_COMMAND_NOP \| FXP_CB_COMMAND_S;
1871	sc->cbl_first = sc->cbl_last = txp;
1872	sc->tx_queued = 1;
1873
1874	fxp_scb_wait(sc);
1875	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1876
1877	/*
1878	* Initialize receiver buffer area - RFA.
1879	*/
1880	DBGLVL_PRINTK(5,"fxp_init: initialize RFA\n");
1881	fxp_scb_wait(sc);
1882	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1883	vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE);
1884	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1885
1886	#ifdef NOTUSED
1887	/*
1888	* Set current media.
1889	*/
1890	if (sc->miibus != NULL)
1891	mii_mediachg(device_get_softc(sc->miibus));
1892	#endif
1893
1894	ifp->if_flags \|= IFF_RUNNING;
1895	ifp->if_flags &= ~IFF_OACTIVE;
1896
1897	if (sc->daemonTid == 0) {
1898	/*
1899	* Start driver task
1900	*/
1901	sc->daemonTid = rtems_bsdnet_newproc ("FXPd", 4096, fxp_daemon, sc);
1902
1903	}
1904	/*
1905	* Enable interrupts.
1906	*/
1907	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1908	splx(s);
1909
1910	/*
1911	* Start stats updater.
1912	*/
1913	sc->stat_ch = fxp_timeout_running;
1914	DBGLVL_PRINTK(2,"fxp_init: stats updater timeout called with hz=%d\n", hz);
1915	timeout(fxp_tick, sc, hz);
1916	DBGLVL_PRINTK(2,"fxp_init finished\n");
1917	}
1918
1919	#ifdef NOTUSED
1920	static int
1921	fxp_serial_ifmedia_upd(struct ifnet *ifp)
1922	{
1923
1924	return (0);
1925	}
1926
1927	static void
1928	fxp_serial_ifmedia_sts(struct ifnet ifp, struct ifmediareq ifmr)
1929	{
1930
1931	ifmr->ifm_active = IFM_ETHER\|IFM_MANUAL;
1932	}
1933
1934	/*
1935	* Change media according to request.
1936	*/
1937	static int
1938	fxp_ifmedia_upd(struct ifnet *ifp)
1939	{
1940	struct fxp_softc *sc = ifp->if_softc;
1941	struct mii_data *mii;
1942
1943	mii = device_get_softc(sc->miibus);
1944	mii_mediachg(mii);
1945	return (0);
1946	}
1947
1948	/*
1949	* Notify the world which media we're using.
1950	*/
1951	static void
1952	fxp_ifmedia_sts(struct ifnet ifp, struct ifmediareq ifmr)
1953	{
1954	struct fxp_softc *sc = ifp->if_softc;
1955	struct mii_data *mii;
1956
1957	mii = device_get_softc(sc->miibus);
1958	mii_pollstat(mii);
1959	ifmr->ifm_active = mii->mii_media_active;
1960	ifmr->ifm_status = mii->mii_media_status;
1961
1962	if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG)
1963	sc->cu_resume_bug = 1;
1964	else
1965	sc->cu_resume_bug = 0;
1966	}
1967	#endif
1968
1969	/*
1970	* Add a buffer to the end of the RFA buffer list.
1971	* Return 0 if successful, 1 for failure. A failure results in
1972	* adding the 'oldm' (if non-NULL) on to the end of the list -
1973	* tossing out its old contents and recycling it.
1974	* The RFA struct is stuck at the beginning of mbuf cluster and the
1975	* data pointer is fixed up to point just past it.
1976	*/
1977	static int
1978	fxp_add_rfabuf(struct fxp_softc sc, struct mbuf oldm)
1979	{
1980	u_int32_t v;
1981	struct mbuf *m;
1982	struct fxp_rfa rfa, p_rfa;
1983
1984	DBGLVL_PRINTK(4,"fxp_add_rfabuf called\n");
1985
1986	MGETHDR(m, M_DONTWAIT, MT_DATA);
1987	if (m != NULL) {
1988	MCLGET(m, M_DONTWAIT);
1989	if ((m->m_flags & M_EXT) == 0) {
1990	m_freem(m);
1991	if (oldm == NULL)
1992	return 1;
1993	m = oldm;
1994	m->m_data = m->m_ext.ext_buf;
1995	}
1996	} else {
1997	if (oldm == NULL)
1998	return 1;
1999	m = oldm;
2000	m->m_data = m->m_ext.ext_buf;
2001	}
2002
2003	/*
2004	* Move the data pointer up so that the incoming data packet
2005	* will be 32-bit aligned.
2006	*/
2007	m->m_data += RFA_ALIGNMENT_FUDGE;
2008
2009	/*
2010	* Get a pointer to the base of the mbuf cluster and move
2011	* data start past it.
2012	*/
2013	rfa = mtod(m, struct fxp_rfa *);
2014	m->m_data += sizeof(struct fxp_rfa);
2015	rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE);
2016
2017	/*
2018	* Initialize the rest of the RFA. Note that since the RFA
2019	* is misaligned, we cannot store values directly. Instead,
2020	* we use an optimized, inline copy.
2021	*/
2022
2023	rfa->rfa_status = 0;
2024	rfa->rfa_control = FXP_RFA_CONTROL_EL;
2025	rfa->actual_size = 0;
2026
2027	v = -1;
2028	fxp_lwcopy(&v, (volatile u_int32_t*) rfa->link_addr);
2029	fxp_lwcopy(&v, (volatile u_int32_t*) rfa->rbd_addr);
2030
2031	/*
2032	* If there are other buffers already on the list, attach this
2033	* one to the end by fixing up the tail to point to this one.
2034	*/
2035	if (sc->rfa_headm != NULL) {
2036	p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf +
2037	RFA_ALIGNMENT_FUDGE);
2038	sc->rfa_tailm->m_next = m;
2039	v = vtophys(rfa);
2040	fxp_lwcopy(&v, (volatile u_int32_t*) p_rfa->link_addr);
2041	p_rfa->rfa_control = 0;
2042	} else {
2043	sc->rfa_headm = m;
2044	}
2045	sc->rfa_tailm = m;
2046
2047	return (m == oldm);
2048	}
2049
2050	#ifdef NOTUSED
2051	static volatile int
2052	fxp_miibus_readreg(device_t dev, int phy, int reg)
2053	{
2054	struct fxp_softc *sc = device_get_softc(dev);
2055	int count = 10000;
2056	int value;
2057
2058	CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2059	(FXP_MDI_READ << 26) \| (reg << 16) \| (phy << 21));
2060
2061	while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2062	&& count--)
2063	DELAY(10);
2064
2065	if (count <= 0)
2066	device_printf(dev, "fxp_miibus_readreg: timed out\n");
2067
2068	return (value & 0xffff);
2069	}
2070
2071	static void
2072	fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2073	{
2074	struct fxp_softc *sc = device_get_softc(dev);
2075	int count = 10000;
2076
2077	CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2078	(FXP_MDI_WRITE << 26) \| (reg << 16) \| (phy << 21) \|
2079	(value & 0xffff));
2080
2081	while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2082	count--)
2083	DELAY(10);
2084
2085	if (count <= 0)
2086	device_printf(dev, "fxp_miibus_writereg: timed out\n");
2087	}
2088	#endif
2089
2090	static int
2091	fxp_ioctl(struct ifnet *ifp, int command, caddr_t data)
2092	{
2093	struct fxp_softc *sc = ifp->if_softc;
2094	#ifdef NOTUSED
2095	struct ifreq ifr = (struct ifreq )data;
2096	struct mii_data *mii;
2097	#endif
2098	int s, error = 0;
2099
2100	DBGLVL_PRINTK(2,"fxp_ioctl called\n");
2101
2102	s = splimp();
2103
2104	switch (command) {
2105	case SIOCSIFADDR:
2106	case SIOCGIFADDR:
2107	case SIOCSIFMTU:
2108	error = ether_ioctl(ifp, command, data);
2109	break;
2110
2111	case SIOCSIFFLAGS:
2112	if (ifp->if_flags & IFF_ALLMULTI)
2113	sc->flags \|= FXP_FLAG_ALL_MCAST;
2114	else
2115	sc->flags &= ~FXP_FLAG_ALL_MCAST;
2116
2117	/*
2118	* If interface is marked up and not running, then start it.
2119	* If it is marked down and running, stop it.
2120	* XXX If it's up then re-initialize it. This is so flags
2121	* such as IFF_PROMISC are handled.
2122	*/
2123	if (ifp->if_flags & IFF_UP) {
2124	fxp_init(sc);
2125	} else {
2126	if (ifp->if_flags & IFF_RUNNING)
2127	fxp_stop(sc);
2128	}
2129	break;
2130
2131	case SIOCADDMULTI:
2132	case SIOCDELMULTI:
2133	if (ifp->if_flags & IFF_ALLMULTI)
2134	sc->flags \|= FXP_FLAG_ALL_MCAST;
2135	else
2136	sc->flags &= ~FXP_FLAG_ALL_MCAST;
2137	/*
2138	* Multicast list has changed; set the hardware filter
2139	* accordingly.
2140	*/
2141	if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
2142	fxp_mc_setup(sc);
2143	/*
2144	* fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
2145	* again rather than else {}.
2146	*/
2147	if (sc->flags & FXP_FLAG_ALL_MCAST)
2148	fxp_init(sc);
2149	error = 0;
2150	break;
2151
2152	#ifdef NOTUSED
2153	case SIOCSIFMEDIA:
2154	case SIOCGIFMEDIA:
2155	if (sc->miibus != NULL) {
2156	mii = device_get_softc(sc->miibus);
2157	error = ifmedia_ioctl(ifp, ifr,
2158	&mii->mii_media, command);
2159	} else {
2160	error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2161	}
2162	break;
2163	#endif
2164
2165	case SIO_RTEMS_SHOW_STATS:
2166	fxp_stats(sc);
2167	break;
2168
2169	default:
2170	error = EINVAL;
2171	}
2172	splx(s);
2173	return (error);
2174	}
2175
2176	/*
2177	* Program the multicast filter.
2178	*
2179	* We have an artificial restriction that the multicast setup command
2180	* must be the first command in the chain, so we take steps to ensure
2181	* this. By requiring this, it allows us to keep up the performance of
2182	* the pre-initialized command ring (esp. link pointers) by not actually
2183	* inserting the mcsetup command in the ring - i.e. its link pointer
2184	* points to the TxCB ring, but the mcsetup descriptor itself is not part
2185	* of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2186	* lead into the regular TxCB ring when it completes.
2187	*
2188	* This function must be called at splimp.
2189	*/
2190	static void
2191	fxp_mc_setup(struct fxp_softc *sc)
2192	{
2193	struct fxp_cb_mcs *mcsp = sc->mcsp;
2194	struct ifnet *ifp = &sc->sc_if;
2195	#ifdef NOTUSED
2196	struct ifmultiaddr *ifma;
2197	#endif
2198	int nmcasts;
2199	int count;
2200
2201	DBGLVL_PRINTK(2,"fxp_mc_setup called\n");
2202
2203	/*
2204	* If there are queued commands, we must wait until they are all
2205	* completed. If we are already waiting, then add a NOP command
2206	* with interrupt option so that we're notified when all commands
2207	* have been completed - fxp_start() ensures that no additional
2208	* TX commands will be added when need_mcsetup is true.
2209	*/
2210	if (sc->tx_queued) {
2211	struct fxp_cb_tx *txp;
2212
2213	/*
2214	* need_mcsetup will be true if we are already waiting for the
2215	* NOP command to be completed (see below). In this case, bail.
2216	*/
2217	if (sc->need_mcsetup)
2218	return;
2219	sc->need_mcsetup = 1;
2220
2221	/*
2222	* Add a NOP command with interrupt so that we are notified when all
2223	* TX commands have been processed.
2224	*/
2225	txp = sc->cbl_last->next;
2226	txp->mb_head = NULL;
2227	txp->cb_status = 0;
2228	txp->cb_command = FXP_CB_COMMAND_NOP \|
2229	FXP_CB_COMMAND_S \| FXP_CB_COMMAND_I;
2230	/*
2231	* Advance the end of list forward.
2232	*/
2233	sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
2234	sc->cbl_last = txp;
2235	sc->tx_queued++;
2236	/*
2237	* Issue a resume in case the CU has just suspended.
2238	*/
2239	fxp_scb_wait(sc);
2240	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2241	/*
2242	* Set a 5 second timer just in case we don't hear from the
2243	* card again.
2244	*/
2245	ifp->if_timer = 5;
2246
2247	return;
2248	}
2249	sc->need_mcsetup = 0;
2250
2251	/*
2252	* Initialize multicast setup descriptor.
2253	*/
2254	mcsp->next = sc->cbl_base;
2255	mcsp->mb_head = NULL;
2256	mcsp->cb_status = 0;
2257	mcsp->cb_command = FXP_CB_COMMAND_MCAS \|
2258	FXP_CB_COMMAND_S \| FXP_CB_COMMAND_I;
2259	mcsp->link_addr = vtophys(&sc->cbl_base->cb_status);
2260
2261	nmcasts = 0;
2262	#ifdef NOTUSED /* FIXME: Multicast not supported? */
2263	if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
2264	#if __FreeBSD_version < 500000
2265	LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2266	#else
2267	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2268	#endif
2269	if (ifma->ifma_addr->sa_family != AF_LINK)
2270	continue;
2271	if (nmcasts >= MAXMCADDR) {
2272	sc->flags \|= FXP_FLAG_ALL_MCAST;
2273	nmcasts = 0;
2274	break;
2275	}
2276	memcpy((void )(uintptr_t)(volatile void )
2277	&sc->mcsp->mc_addr[nmcasts][0],
2278	LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 6);
2279	nmcasts++;
2280	}
2281	}
2282	#endif
2283	mcsp->mc_cnt = nmcasts * 6;
2284	sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp;
2285	sc->tx_queued = 1;
2286
2287	/*
2288	* Wait until command unit is not active. This should never
2289	* be the case when nothing is queued, but make sure anyway.
2290	*/
2291	count = 100;
2292	while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2293	FXP_SCB_CUS_ACTIVE && --count)
2294	DELAY(10);
2295	if (count == 0) {
2296	device_printf(sc->dev, "command queue timeout\n");
2297	return;
2298	}
2299
2300	/*
2301	* Start the multicast setup command.
2302	*/
2303	fxp_scb_wait(sc);
2304	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
2305	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2306
2307	ifp->if_timer = 2;
2308	return;
2309	}
2310
2311	#endif /* defined(__i386__) */

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