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if_fxp.c @ 4d3c866

Last change on this file since 4d3c866 was 4d3c866, checked in by Pavel Pisa <pisa@…>, on 09/20/16 at 22:14:45

classic networking: adapt FXP driver to work with actual PCI and IRQ code.

Tested to work with QEMU provided Intel i82557b network controller emulation.

qemu-system-x86_64 -enable-kvm -kernel $APP_BINARY \

-vga cirrus \
-append "--console=/dev/com1" \
-serial stdio \
-net nic,vlan=1,macaddr=be:be:be:10:00:01,model=i82557b \
-net tap,ifname=tap1,vlan=1,script=no,downscript=no

Property mode set to 100644

File size: 62.4 KB

Line
1	/*-
2	* Copyright (c) 1995, David Greenman
3	* Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
4	* All rights reserved.
5	*
6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions
8	* are met:
9	* 1. Redistributions of source code must retain the above copyright
10	* notice unmodified, this list of conditions, and the following
11	* disclaimer.
12	* 2. Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	*
16	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26	* SUCH DAMAGE.
27	*
28	* $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.118 2001/09/05 23:33:58 brooks Exp $
29	*/
30
31	/*
32	* Intel EtherExpress Pro/100B PCI Fast Ethernet driver
33	*/
34
35	/*
36	* RTEMS Revision Preliminary History
37	*
38	* July XXX, 2002 W. Eric Norum <eric.norum@usask.ca>
39	* Placed in RTEMS CVS repository. All further modifications will be
40	* noted in the CVS log and not in this comment.
41	*
42	* July 11, 2002 W. Eric Norum <eric.norum@usask.ca>
43	* Minor modifications to get driver working with NIC on VersaLogic
44	* Bobcat PC-104 single-board computer. The Bobcat has no video
45	* driver so printf/printk calls are directed to COM2:. This
46	* arrangement seems to require delays after the printk calls or
47	* else things lock up. Perhaps the RTEMS pc386 console code
48	* should be modified to insert these delays itself.
49	*
50	* June 27, 2002 W. Eric Norum <eric.norum@usask.ca>
51	* Obtained from Thomas Doerfler <Thomas.Doerfler@imd-systems.de>.
52	* A big thank-you to Thomas for making this available.
53	*
54	* October 01, 2001 Thomas Doerfler <Thomas.Doerfler@imd-systems.de>
55	* Original RTEMS modifications.
56	*/
57
58	#if defined(__i386__)
59
60	/#define DEBUG_OUT 0/
61
62	#include <rtems.h>
63	#include <rtems/error.h>
64	#include <rtems/rtems_bsdnet.h>
65	#include <bsp.h>
66
67	#include <errno.h>
68	#include <sys/param.h>
69	#include <sys/mbuf.h>
70	#include <sys/socket.h>
71	#include <sys/sockio.h>
72	#include <net/if.h>
73	#include <netinet/in.h>
74	#include <netinet/if_ether.h>
75	#include <sys/malloc.h>
76	#include <sys/systm.h>
77	#include <bsp.h>
78	#include <bsp/irq.h>
79	#include <bsp/irq-generic.h>
80	#include <rtems/pci.h>
81
82	#ifdef NS
83	#include <netns/ns.h>
84	#include <netns/ns_if.h>
85	#endif
86
87	#include <net/bpf.h>
88
89	#include <vm/vm.h> /* for vtophys */
90
91	#include <net/if_types.h>
92
93	#include "if_fxpreg.h"
94	#include "if_fxpvar.h"
95
96	/*
97	* some adaptation replacements for RTEMS
98	*/
99	static rtems_interval fxp_ticksPerSecond;
100	#define device_printf(device,format,args...) printk(format,## args)
101	#define DELAY(n) rtems_task_wake_after(((n)*fxp_ticksPerSecond/1000000)+1)
102	#ifdef DEBUG_OUT
103	#define DBGLVL_PRINTK(LVL,format, args...) \
104	if (DEBUG_OUT >= (LVL)) { \
105	printk(format, ## args); \
106	}
107	#else
108	#define DBGLVL_PRINTK(LVL,format, args...)
109	#endif
110
111	/*
112	* RTEMS event used by interrupt handler to signal driver tasks.
113	* This must not be any of the events used by the network task synchronization.
114	*/
115	#define INTERRUPT_EVENT RTEMS_EVENT_1
116
117	/*
118	* remapping between PCI device and CPU memmory address view...
119	*/
120	#if defined(__i386)
121	#define vtophys(p) (u_int32_t)(p)
122	#else
123	#define vtophys(p) vtophys(p)
124	#endif
125
126	#define NFXPDRIVER 1
127	static struct fxp_softc fxp_softc[NFXPDRIVER];
128	static bool fxp_is_verbose = true;
129	/*
130	* NOTE! On the Alpha, we have an alignment constraint. The
131	* card DMAs the packet immediately following the RFA. However,
132	* the first thing in the packet is a 14-byte Ethernet header.
133	* This means that the packet is misaligned. To compensate,
134	* we actually offset the RFA 2 bytes into the cluster. This
135	* alignes the packet after the Ethernet header at a 32-bit
136	* boundary. HOWEVER! This means that the RFA is misaligned!
137	*/
138	#define RFA_ALIGNMENT_FUDGE 2
139
140	/*
141	* Set initial transmit threshold at 64 (512 bytes). This is
142	* increased by 64 (512 bytes) at a time, to maximum of 192
143	* (1536 bytes), if an underrun occurs.
144	*/
145	static int tx_threshold = 64;
146
147	/*
148	* The configuration byte map has several undefined fields which
149	* must be one or must be zero. Set up a template for these bits
150	* only, (assuming a 82557 chip) leaving the actual configuration
151	* to fxp_init.
152	*
153	* See struct fxp_cb_config for the bit definitions.
154	*/
155	static u_char fxp_cb_config_template[] = {
156	0x0, 0x0, /* cb_status */
157	0x0, 0x0, /* cb_command */
158	0x0, 0x0, 0x0, 0x0, /* link_addr */
159	0x0, /* 0 */
160	0x0, /* 1 */
161	0x0, /* 2 */
162	0x0, /* 3 */
163	0x0, /* 4 */
164	0x0, /* 5 */
165	0x32, /* 6 */
166	0x0, /* 7 */
167	0x0, /* 8 */
168	0x0, /* 9 */
169	0x6, /* 10 */
170	0x0, /* 11 */
171	0x0, /* 12 */
172	0x0, /* 13 */
173	0xf2, /* 14 */
174	0x48, /* 15 */
175	0x0, /* 16 */
176	0x40, /* 17 */
177	0xf0, /* 18 */
178	0x0, /* 19 */
179	0x3f, /* 20 */
180	0x5 /* 21 */
181	};
182
183	struct fxp_ident {
184	u_int16_t devid;
185	char *name;
186	int warn;
187	};
188
189	#define UNTESTED 1
190
191	/*
192	* Claim various Intel PCI device identifiers for this driver. The
193	* sub-vendor and sub-device field are extensively used to identify
194	* particular variants, but we don't currently differentiate between
195	* them.
196	*/
197	static struct fxp_ident fxp_ident_table[] = {
198	{ 0x1229, "Intel Pro 10/100B/100+ Ethernet", 0 },
199	{ 0x2449, "Intel Pro/100 Ethernet", UNTESTED },
200	{ 0x1209, "Intel Embedded 10/100 Ethernet", 0 },
201	{ 0x1029, "Intel Pro/100 Ethernet", UNTESTED },
202	{ 0x1030, "Intel Pro/100 Ethernet", 0 },
203	{ 0x1031, "Intel Pro/100 Ethernet", UNTESTED },
204	{ 0x1032, "Intel Pro/100 Ethernet", UNTESTED },
205	{ 0x1033, "Intel Pro/100 Ethernet", UNTESTED },
206	{ 0x1034, "Intel Pro/100 Ethernet", UNTESTED },
207	{ 0x1035, "Intel Pro/100 Ethernet", UNTESTED },
208	{ 0x1036, "Intel Pro/100 Ethernet", UNTESTED },
209	{ 0x1037, "Intel Pro/100 Ethernet", UNTESTED },
210	{ 0x1038, "Intel Pro/100 Ethernet", UNTESTED },
211	{ 0x103B, "Intel Pro/100 Ethernet (82801BD PRO/100 VM (LOM))", 0 },
212	{ 0, NULL, 0 }
213	};
214
215	#if 0
216	static int fxp_probe(device_t dev);
217	static int fxp_attach(device_t dev);
218	static int fxp_detach(device_t dev);
219	static int fxp_shutdown(device_t dev);
220	#endif
221	int fxp_output (struct ifnet *,
222	struct mbuf , struct sockaddr , struct rtentry *);
223
224
225	static void fxp_intr(void *arg);
226	static void fxp_init(void *xsc);
227	static void fxp_tick(void *xsc);
228	static void fxp_start(struct ifnet *ifp);
229	static void fxp_stop(struct fxp_softc *sc);
230	static void fxp_release(struct fxp_softc *sc);
231	static int fxp_ioctl(struct ifnet *ifp, ioctl_command_t command,
232	caddr_t data);
233	static void fxp_watchdog(struct ifnet *ifp);
234	static int fxp_add_rfabuf(struct fxp_softc sc, struct mbuf oldm);
235	static void fxp_mc_setup(struct fxp_softc *sc);
236	static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
237	int autosize);
238	static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
239	u_int16_t data);
240	static void fxp_autosize_eeprom(struct fxp_softc *sc);
241	static void fxp_read_eeprom(struct fxp_softc sc, u_short data,
242	int offset, int words);
243	static void fxp_write_eeprom(struct fxp_softc sc, u_short data,
244	int offset, int words);
245	#ifdef NOTUSED
246	static int fxp_ifmedia_upd(struct ifnet *ifp);
247	static void fxp_ifmedia_sts(struct ifnet *ifp,
248	struct ifmediareq *ifmr);
249	static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
250	static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
251	struct ifmediareq *ifmr);
252	static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg);
253	static void fxp_miibus_writereg(device_t dev, int phy, int reg,
254	int value);
255	#endif
256	static __inline void fxp_lwcopy(volatile u_int32_t *src,
257	volatile u_int32_t *dst);
258	static __inline void fxp_scb_wait(struct fxp_softc *sc);
259	static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
260	static __inline void fxp_dma_wait(volatile u_int16_t *status,
261	struct fxp_softc *sc);
262
263	/*
264	* Inline function to copy a 16-bit aligned 32-bit quantity.
265	*/
266	static __inline void
267	fxp_lwcopy(volatile u_int32_t src, volatile u_int32_t dst)
268	{
269	#ifdef __i386__
270	dst = src;
271	#else
272	volatile u_int16_t a = (volatile u_int16_t)src;
273	volatile u_int16_t b = (volatile u_int16_t)dst;
274
275	b[0] = a[0];
276	b[1] = a[1];
277	#endif
278	}
279
280	/*
281	* inline access functions to pci space registers
282	*/
283	static __inline u_int8_t fxp_csr_read_1(struct fxp_softc *sc,int reg) {
284	u_int8_t val;
285	if (sc->pci_regs_are_io) {
286	inport_byte(sc->pci_regs_base + reg,val);
287	}
288	else {
289	val = (volatile u_int8_t)(sc->pci_regs_base+reg);
290	}
291	return val;
292	}
293	static __inline u_int32_t fxp_csr_read_2(struct fxp_softc *sc,int reg) {
294	u_int16_t val;
295	if (sc->pci_regs_are_io) {
296	inport_word(sc->pci_regs_base + reg,val);
297	}
298	else {
299	val = (volatile u_int16_t)(sc->pci_regs_base+reg);
300	}
301	return val;
302	}
303	static __inline u_int32_t fxp_csr_read_4(struct fxp_softc *sc,int reg) {
304	u_int32_t val;
305	if (sc->pci_regs_are_io) {
306	inport_long(sc->pci_regs_base + reg,val);
307	}
308	else {
309	val = (volatile u_int32_t)(sc->pci_regs_base+reg);
310	}
311	return val;
312	}
313
314	/*
315	* Wait for the previous command to be accepted (but not necessarily
316	* completed).
317	*/
318	static __inline void
319	fxp_scb_wait(struct fxp_softc *sc)
320	{
321	int i = 10000;
322
323	while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
324	DELAY(2);
325	if (i == 0)
326	device_printf(sc->dev, "SCB timeout: 0x%d 0x%d"
327	"0x%d" PRIx32 "0x%" PRIx32 "\n",
328	CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
329	CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
330	CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS),
331	CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
332	}
333
334	static __inline void
335	fxp_scb_cmd(struct fxp_softc *sc, int cmd)
336	{
337
338	if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
339	CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
340	fxp_scb_wait(sc);
341	}
342	CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
343	}
344
345	static __inline void
346	fxp_dma_wait(volatile u_int16_t status, struct fxp_softc sc)
347	{
348	int i = 10000;
349
350	while (!(*status & FXP_CB_STATUS_C) && --i)
351	DELAY(2);
352	if (i == 0)
353	device_printf(sc->dev, "DMA timeout\n");
354	}
355
356
357	#define FXP_PCI_CONF_ACCESSOR(_confop, _baseop, _type) \
358	\
359	static inline int _confop ( \
360	struct fxp_softc *sc, \
361	int offset, \
362	_type data ) \
363	{ \
364	_baseop( \
365	sc->pci_bus, \
366	sc->pci_dev, \
367	sc->pci_fun, \
368	offset, \
369	data \
370	); \
371	return PCIB_ERR_SUCCESS; \
372	}
373
374	FXP_PCI_CONF_ACCESSOR( fxp_pci_conf_read8, pci_read_config_byte, uint8_t * );
375	FXP_PCI_CONF_ACCESSOR( fxp_pci_conf_read16, pci_read_config_word, uint16_t * );
376	FXP_PCI_CONF_ACCESSOR( fxp_pci_conf_read32, pci_read_config_dword, uint32_t * );
377	FXP_PCI_CONF_ACCESSOR( fxp_pci_conf_write8, pci_write_config_byte, uint8_t );
378	FXP_PCI_CONF_ACCESSOR( fxp_pci_conf_write16, pci_write_config_word, uint16_t );
379	FXP_PCI_CONF_ACCESSOR( fxp_pci_conf_write32, pci_write_config_dword, uint32_t );
380
381	static __inline unsigned int fxp_pci_get_vendor(struct fxp_softc *sc) {
382	u_int16_t vendor;
383	fxp_pci_conf_read16(sc, PCI_VENDOR_ID, &vendor);
384	return vendor;
385	}
386
387	static __inline unsigned int fxp_pci_get_device(struct fxp_softc *sc) {
388	u_int16_t device;
389	fxp_pci_conf_read16(sc, PCI_DEVICE_ID, &device);
390	return device;
391	}
392
393	static __inline unsigned int fxp_pci_get_subvendor(struct fxp_softc *sc) {
394	u_int16_t subvendor;
395	fxp_pci_conf_read16(sc, PCI_SUBSYSTEM_VENDOR_ID, &subvendor);
396	return subvendor;
397	}
398
399	static __inline unsigned int fxp_pci_get_subdevice(struct fxp_softc *sc) {
400	u_int16_t subdevice;
401	fxp_pci_conf_read16(sc, PCI_SUBSYSTEM_ID, &subdevice);
402	return subdevice;
403	}
404
405	static __inline unsigned int fxp_pci_get_revid(struct fxp_softc *sc) {
406	u_int8_t revid;
407	fxp_pci_conf_read8(sc, PCI_REVISION_ID, &revid);
408	return revid;
409	}
410
411	int
412	rtems_fxp_attach(struct rtems_bsdnet_ifconfig *config, int attaching)
413	{
414	int error = 0;
415	struct fxp_softc *sc;
416	struct ifnet *ifp;
417	uint16_t val16;
418	uint32_t val32;
419	uint16_t data;
420	int i;
421	int s;
422	int unitNumber;
423	char *unitName;
424	u_int16_t dev_id;
425	u_int8_t interrupt;
426	int mtu;
427
428	/*
429	* Set up some timing values
430	*/
431	fxp_ticksPerSecond = rtems_clock_get_ticks_per_second();
432	DBGLVL_PRINTK(1,"fxp_attach called\n");
433
434	/*
435	* Parse driver name
436	*/
437	if ((unitNumber = rtems_bsdnet_parse_driver_name (config, &unitName)) < 0)
438	return 0;
439
440	/*
441	* Is driver free?
442	*/
443	if ((unitNumber <= 0) \|\| (unitNumber > NFXPDRIVER)) {
444	device_printf(dev,"Bad FXP unit number.\n");
445	return 0;
446	}
447	sc = &fxp_softc[unitNumber - 1];
448	ifp = &sc->arpcom.ac_if;
449	if (ifp->if_softc != NULL) {
450	device_printf(dev,"FXP Driver already in use.\n");
451	return 0;
452	}
453
454	memset(sc, 0, sizeof(*sc));
455	#ifdef NOTUSED
456	sc->dev = dev;
457	callout_handle_init(&sc->stat_ch);
458	mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF \| MTX_RECURSE);
459	#endif
460	s = splimp();
461
462	/*
463	* find device on pci bus
464	*/
465	{ int j; int pbus, pdev, pfun;
466
467	for (j=0; fxp_ident_table[j].devid; j++ ) {
468	i = pci_find_device( 0x8086, fxp_ident_table[j].devid,
469	unitNumber-1, &pbus, &pdev, &pfun );
470	sc->pci_bus = pbus;
471	sc->pci_dev = pdev;
472	sc->pci_fun = pfun;
473	DBGLVL_PRINTK(2,"fxp_attach: find_devid returned %d ,"
474	"pci bus %d dev %d fun %d \n",
475	i, sc->pci_bus, sc->pci_dev, sc->pci_fun);
476	if (PCIB_ERR_SUCCESS == i) {
477	if ( UNTESTED == fxp_ident_table[j].warn ) {
478	device_printf(dev,
479	"WARNING: this chip version has NOT been reported to work under RTEMS yet.\n");
480	device_printf(dev,
481	" If it works OK, report it as tested in 'c/src/libchip/network/if_fxp.c'\n");
482	}
483	break;
484	}
485	}
486	}
487
488	/*
489	* FIXME: add search for more device types...
490	*/
491	if (i != PCIB_ERR_SUCCESS) {
492	device_printf(dev, "could not find 82559ER device\n");
493	return 0;
494	}
495
496
497	/*
498	* Enable bus mastering. Enable memory space too, in case
499	* BIOS/Prom forgot about it.
500	*/
501	fxp_pci_conf_read16(sc, PCI_COMMAND,&val16);
502	val16 \|= (PCI_COMMAND_MEMORY\|PCI_COMMAND_MASTER);
503	fxp_pci_conf_write16(sc, PCI_COMMAND, val16);
504	DBGLVL_PRINTK(3,"fxp_attach: PCI_COMMAND_write = 0x%x\n",val16);
505	fxp_pci_conf_read16(sc, PCI_COMMAND,&val16);
506	DBGLVL_PRINTK(4,"fxp_attach: PCI_COMMAND_read = 0x%x\n",val16);
507
508	/*
509	* Figure out which we should try first - memory mapping or i/o mapping?
510	* We default to memory mapping. Then we accept an override from the
511	* command line. Then we check to see which one is enabled.
512	*/
513	#ifdef NOTUSED
514	m1 = PCI_COMMAND_MEMORY;
515	m2 = PCI_COMMAND_IO;
516	prefer_iomap = 0;
517	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
518	"prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) {
519	m1 = PCI_COMMAND_IO;
520	m2 = PCI_COMMAND_MEMORY;
521	}
522
523	if (val & m1) {
524	sc->rtp = ((m1 == PCI_COMMAND_MEMORY)
525	? SYS_RES_MEMORY : SYS_RES_IOPORT);
526	sc->rgd = ((m1 == PCI_COMMAND_MEMORY)
527	? FXP_PCI_MMBA : FXP_PCI_IOBA);
528	sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
529	0, ~0, 1, RF_ACTIVE);
530	}
531	if (sc->mem == NULL && (val & m2)) {
532	sc->rtp = ((m2 == PCI_COMMAND_MEMORY)
533	? SYS_RES_MEMORY : SYS_RES_IOPORT);
534	sc->rgd = ((m2 == PCI_COMMAND_MEMORY)
535	? FXP_PCI_MMBA : FXP_PCI_IOBA);
536	sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
537	0, ~0, 1, RF_ACTIVE);
538	}
539
540	if (!sc->mem) {
541	device_printf(dev, "could not map device registers\n");
542	error = ENXIO;
543	goto fail;
544	}
545	if (fxp_is_verbose) {
546	device_printf(dev, "using %s space register mapping\n",
547	sc->rtp == SYS_RES_MEMORY? "memory" : "I/O");
548	}
549
550	sc->sc_st = rman_get_bustag(sc->mem);
551	sc->sc_sh = rman_get_bushandle(sc->mem);
552
553	/*
554	* Allocate our interrupt.
555	*/
556	rid = 0;
557	sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
558	RF_SHAREABLE \| RF_ACTIVE);
559	if (sc->irq == NULL) {
560	device_printf(dev, "could not map interrupt\n");
561	error = ENXIO;
562	goto fail;
563	}
564
565	error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
566	fxp_intr, sc, &sc->ih);
567	if (error) {
568	device_printf(dev, "could not setup irq\n");
569	goto fail;
570	}
571	#endif
572
573	/*
574	* get mapping and base address of registers
575	*/
576	fxp_pci_conf_read16(sc, PCI_COMMAND,&val16);
577	DBGLVL_PRINTK(4,"fxp_attach: PCI_COMMAND_read = 0x%x\n",val16);
578	if((val16 & PCI_COMMAND_IO) != 0) {
579	sc->pci_regs_are_io = true;
580	fxp_pci_conf_read32(sc, PCI_BASE_ADDRESS_1, &val32);
581	sc->pci_regs_base = val32 & PCI_BASE_ADDRESS_IO_MASK;
582	}
583	else {
584	sc->pci_regs_are_io = false;
585	fxp_pci_conf_read32(sc, PCI_BASE_ADDRESS_0, &val32);
586	sc->pci_regs_base = val32 & PCI_BASE_ADDRESS_MEM_MASK;
587	}
588	DBGLVL_PRINTK(3,"fxp_attach: CSR registers are mapped in %s space"
589	" at address 0x%x\n",
590	sc->pci_regs_are_io ? "I/O" : "MEM",
591	sc->pci_regs_base);
592
593	/*
594	* get interrupt level to be used
595	*/
596	fxp_pci_conf_read8(sc, PCI_INTERRUPT_LINE, &interrupt);
597	DBGLVL_PRINTK(3,"fxp_attach: interrupt = 0x%x\n",interrupt);
598	sc->irq_num = interrupt;
599	/*
600	* Reset to a stable state.
601	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
602	*/
603	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
604	DELAY(10);
605
606	sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB,
607	M_DEVBUF, M_NOWAIT);
608	DBGLVL_PRINTK(3,"fxp_attach: sc->cbl_base = 0x%x\n",sc->cbl_base);
609	if (sc->cbl_base == NULL)
610	goto failmem;
611	else
612	memset(sc->cbl_base, 0, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
613
614	sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF,
615	M_NOWAIT);
616	DBGLVL_PRINTK(3,"fxp_attach: sc->fxp_stats = 0x%x\n",sc->fxp_stats);
617	if (sc->fxp_stats == NULL)
618	goto failmem;
619	else
620	memset(sc->fxp_stats, 0, sizeof(struct fxp_stats));
621
622	sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT);
623	DBGLVL_PRINTK(3,"fxp_attach: sc->mcsp = 0x%x\n",sc->mcsp);
624	if (sc->mcsp == NULL)
625	goto failmem;
626
627	/*
628	* Pre-allocate our receive buffers.
629	*/
630	for (i = 0; i < FXP_NRFABUFS; i++) {
631	if (fxp_add_rfabuf(sc, NULL) != 0) {
632	goto failmem;
633	}
634	}
635
636	/*
637	* Find out how large of an SEEPROM we have.
638	*/
639	DBGLVL_PRINTK(3,"fxp_attach: calling fxp_autosize_eeprom\n");
640	fxp_autosize_eeprom(sc);
641
642	/*
643	* Determine whether we must use the 503 serial interface.
644	*/
645	fxp_read_eeprom(sc, &data, 6, 1);
646	if ((data & FXP_PHY_DEVICE_MASK) != 0 &&
647	(data & FXP_PHY_SERIAL_ONLY))
648	sc->flags \|= FXP_FLAG_SERIAL_MEDIA;
649
650	/*
651	* Find out the basic controller type; we currently only
652	* differentiate between a 82557 and greater.
653	*/
654	fxp_read_eeprom(sc, &data, 5, 1);
655	if ((data >> 8) == 1)
656	sc->chip = FXP_CHIP_82557;
657	DBGLVL_PRINTK(3,"fxp_attach: sc->chip = %d\n",sc->chip);
658
659	/*
660	* Enable workarounds for certain chip revision deficiencies.
661	*
662	* Systems based on the ICH2/ICH2-M chip from Intel have a defect
663	* where the chip can cause a PCI protocol violation if it receives
664	* a CU_RESUME command when it is entering the IDLE state. The
665	* workaround is to disable Dynamic Standby Mode, so the chip never
666	* deasserts CLKRUN#, and always remains in an active state.
667	*
668	* See Intel 82801BA/82801BAM Specification Update, Errata #30.
669	*/
670	#ifdef NOTUSED
671	i = fxp_pci_get_device(dev);
672	#else
673	fxp_pci_conf_read16(sc, PCI_DEVICE_ID, &dev_id);
674	DBGLVL_PRINTK(3,"fxp_attach: device id = 0x%x\n",dev_id);
675	#endif
676	if (dev_id == 0x2449 \|\| (dev_id > 0x1030 && dev_id < 0x1039)) {
677	device_printf(dev, "* See Intel 82801BA/82801BAM Specification Update, Errata #30. *\n");
678	fxp_read_eeprom(sc, &data, 10, 1);
679	if (data & 0x02) { /* STB enable */
680	u_int16_t cksum;
681	int i;
682
683	device_printf(dev,
684	"* DISABLING DYNAMIC STANDBY MODE IN EEPROM *\n");
685	data &= ~0x02;
686	fxp_write_eeprom(sc, &data, 10, 1);
687	device_printf(dev, "New EEPROM ID: 0x%x\n", data);
688	cksum = 0;
689	for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
690	fxp_read_eeprom(sc, &data, i, 1);
691	cksum += data;
692	}
693	i = (1 << sc->eeprom_size) - 1;
694	cksum = 0xBABA - cksum;
695	fxp_read_eeprom(sc, &data, i, 1);
696	fxp_write_eeprom(sc, &cksum, i, 1);
697	device_printf(dev,
698	"EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
699	i, data, cksum);
700	/*
701	* We need to do a full PCI reset here. A software
702	* reset to the port doesn't cut it, but let's try
703	* anyway.
704	*/
705	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
706	DELAY(50);
707	device_printf(dev,
708	"* PLEASE REBOOT THE SYSTEM NOW FOR CORRECT OPERATION *\n");
709	#if 1
710	/*
711	* If the user elects to continue, try the software
712	* workaround, as it is better than nothing.
713	*/
714	sc->flags \|= FXP_FLAG_CU_RESUME_BUG;
715	#endif
716	}
717	}
718
719	/*
720	* If we are not a 82557 chip, we can enable extended features.
721	*/
722	if (sc->chip != FXP_CHIP_82557) {
723	u_int8_t tmp_val;
724	/*
725	* If MWI is enabled in the PCI configuration, and there
726	* is a valid cacheline size (8 or 16 dwords), then tell
727	* the board to turn on MWI.
728	*/
729	fxp_pci_conf_read8(sc, PCI_CACHE_LINE_SIZE, &tmp_val);
730	DBGLVL_PRINTK(3,"fxp_attach: CACHE_LINE_SIZE = %d\n",tmp_val);
731	if (val16 & PCI_COMMAND_MEMORY &&
732	tmp_val != 0)
733	sc->flags \|= FXP_FLAG_MWI_ENABLE;
734
735	/* turn on the extended TxCB feature */
736	sc->flags \|= FXP_FLAG_EXT_TXCB;
737
738	/* enable reception of long frames for VLAN */
739	sc->flags \|= FXP_FLAG_LONG_PKT_EN;
740	DBGLVL_PRINTK(3,"fxp_attach: sc->flags = 0x%x\n",
741	sc->flags);
742	}
743
744	/*
745	* Read MAC address.
746	*/
747	fxp_read_eeprom(sc, (u_int16_t*)sc->arpcom.ac_enaddr, 0, 3);
748	if (fxp_is_verbose) {
749	device_printf(dev, "Ethernet address %x:%x:%x:%x:%x:%x %s \n",
750	((u_int8_t*)sc->arpcom.ac_enaddr)[0],
751	((u_int8_t*)sc->arpcom.ac_enaddr)[1],
752	((u_int8_t*)sc->arpcom.ac_enaddr)[2],
753	((u_int8_t*)sc->arpcom.ac_enaddr)[3],
754	((u_int8_t*)sc->arpcom.ac_enaddr)[4],
755	((u_int8_t*)sc->arpcom.ac_enaddr)[5],
756	sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : "");
757	device_printf(dev, "PCI IDs: 0x%x 0x%x 0x%x 0x%x 0x%x\n",
758	fxp_pci_get_vendor(sc), fxp_pci_get_device(sc),
759	fxp_pci_get_subvendor(sc), fxp_pci_get_subdevice(sc),
760	fxp_pci_get_revid(sc));
761	device_printf(dev, "Chip Type: %d\n", sc->chip);
762	}
763
764	#ifdef NOTUSED /* do not set up interface at all... */
765	/*
766	* If this is only a 10Mbps device, then there is no MII, and
767	* the PHY will use a serial interface instead.
768	*
769	* The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
770	* doesn't have a programming interface of any sort. The
771	* media is sensed automatically based on how the link partner
772	* is configured. This is, in essence, manual configuration.
773	*/
774	if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
775	ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
776	fxp_serial_ifmedia_sts);
777	ifmedia_add(&sc->sc_media, IFM_ETHER\|IFM_MANUAL, 0, NULL);
778	ifmedia_set(&sc->sc_media, IFM_ETHER\|IFM_MANUAL);
779	} else {
780	if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
781	fxp_ifmedia_sts)) {
782	device_printf(dev, "MII without any PHY!\n");
783	error = ENXIO;
784	goto fail;
785	}
786	}
787	#endif
788	if (config->mtu)
789	mtu = config->mtu;
790	else
791	mtu = ETHERMTU;
792
793	ifp->if_softc = sc;
794	ifp->if_unit = unitNumber;
795	ifp->if_name = unitName;
796	ifp->if_mtu = mtu;
797	ifp->if_baudrate = 100000000;
798	ifp->if_init = fxp_init;
799	ifp->if_ioctl = fxp_ioctl;
800	ifp->if_start = fxp_start;
801	ifp->if_output = ether_output;
802	ifp->if_watchdog = fxp_watchdog;
803	ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX /\| IFF_MULTICAST/;
804	if (ifp->if_snd.ifq_maxlen == 0)
805	ifp->if_snd.ifq_maxlen = ifqmaxlen;
806
807	/*
808	* Attach the interface.
809	*/
810	DBGLVL_PRINTK(3,"fxp_attach: calling if_attach\n");
811	if_attach (ifp);
812	DBGLVL_PRINTK(3,"fxp_attach: calling ether_if_attach\n");
813	ether_ifattach(ifp);
814	DBGLVL_PRINTK(3,"fxp_attach: return from ether_if_attach\n");
815
816	#ifdef NOTUSED
817	/*
818	* Tell the upper layer(s) we support long frames.
819	*/
820	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
821	#endif
822	/*
823	* Let the system queue as many packets as we have available
824	* TX descriptors.
825	*/
826	ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1;
827
828	splx(s);
829	return (0);
830
831	failmem:
832	device_printf(dev, "Failed to malloc memory\n");
833	error = ENOMEM;
834	#ifdef NOTUSED
835	fail:
836	#endif
837	splx(s);
838	fxp_release(sc);
839	return (error);
840	}
841
842	/*
843	* release all resources
844	*/
845	static void
846	fxp_release(struct fxp_softc *sc)
847	{
848
849	#ifdef NOTUSED
850	bus_generic_detach(sc->dev);
851	if (sc->miibus)
852	device_delete_child(sc->dev, sc->miibus);
853	#endif
854	if (sc->cbl_base)
855	free(sc->cbl_base, M_DEVBUF);
856	if (sc->fxp_stats)
857	free(sc->fxp_stats, M_DEVBUF);
858	if (sc->mcsp)
859	free(sc->mcsp, M_DEVBUF);
860	if (sc->rfa_headm)
861	m_freem(sc->rfa_headm);
862
863	#ifdef NOTUSED
864	if (sc->ih)
865	bus_teardown_intr(sc->dev, sc->irq, sc->ih);
866	if (sc->irq)
867	bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
868	if (sc->mem)
869	bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem);
870	mtx_destroy(&sc->sc_mtx);
871	#endif
872	}
873
874	#if NOTUSED
875	/*
876	* Detach interface.
877	*/
878	static int
879	fxp_detach(device_t dev)
880	{
881	struct fxp_softc *sc = device_get_softc(dev);
882	int s;
883
884	/* disable interrupts */
885	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
886
887	s = splimp();
888
889	/*
890	* Stop DMA and drop transmit queue.
891	*/
892	fxp_stop(sc);
893
894	/*
895	* Close down routes etc.
896	*/
897	ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED);
898
899	/*
900	* Free all media structures.
901	*/
902	ifmedia_removeall(&sc->sc_media);
903
904	splx(s);
905
906	/* Release our allocated resources. */
907	fxp_release(sc);
908
909	return (0);
910	}
911
912	/*
913	* Device shutdown routine. Called at system shutdown after sync. The
914	* main purpose of this routine is to shut off receiver DMA so that
915	* kernel memory doesn't get clobbered during warmboot.
916	*/
917	static int
918	fxp_shutdown(device_t dev)
919	{
920	/*
921	* Make sure that DMA is disabled prior to reboot. Not doing
922	* do could allow DMA to corrupt kernel memory during the
923	* reboot before the driver initializes.
924	*/
925	fxp_stop((struct fxp_softc *) device_get_softc(dev));
926	return (0);
927	}
928	#endif
929
930	/*
931	* Show interface statistics
932	*/
933	static void
934	fxp_stats(struct fxp_softc *sc)
935	{
936	struct ifnet *ifp = &sc->sc_if;
937
938	printf (" Output packets:%-8lu", ifp->if_opackets);
939	printf (" Collisions:%-8lu", ifp->if_collisions);
940	printf (" Output errors:%-8lu\n", ifp->if_oerrors);
941	printf (" Input packets:%-8lu", ifp->if_ipackets);
942	printf (" Input errors:%-8lu\n", ifp->if_ierrors);
943	}
944
945	static void
946	fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
947	{
948	u_int16_t reg;
949	int x;
950
951	/*
952	* Shift in data.
953	*/
954	for (x = 1 << (length - 1); x; x >>= 1) {
955	if (data & x)
956	reg = FXP_EEPROM_EECS \| FXP_EEPROM_EEDI;
957	else
958	reg = FXP_EEPROM_EECS;
959	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
960	DELAY(1);
961	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg \| FXP_EEPROM_EESK);
962	DELAY(1);
963	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
964	DELAY(1);
965	}
966	}
967
968	/*
969	* Read from the serial EEPROM. Basically, you manually shift in
970	* the read opcode (one bit at a time) and then shift in the address,
971	* and then you shift out the data (all of this one bit at a time).
972	* The word size is 16 bits, so you have to provide the address for
973	* every 16 bits of data.
974	*/
975	static u_int16_t
976	fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
977	{
978	u_int16_t reg, data;
979	int x;
980
981	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
982	/*
983	* Shift in read opcode.
984	*/
985	fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
986	/*
987	* Shift in address.
988	*/
989	data = 0;
990	for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
991	if (offset & x)
992	reg = FXP_EEPROM_EECS \| FXP_EEPROM_EEDI;
993	else
994	reg = FXP_EEPROM_EECS;
995	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
996	DELAY(1);
997	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg \| FXP_EEPROM_EESK);
998	DELAY(1);
999	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1000	DELAY(1);
1001	reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
1002	data++;
1003	if (autosize && reg == 0) {
1004	sc->eeprom_size = data;
1005	break;
1006	}
1007	}
1008	/*
1009	* Shift out data.
1010	*/
1011	data = 0;
1012	reg = FXP_EEPROM_EECS;
1013	for (x = 1 << 15; x; x >>= 1) {
1014	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg \| FXP_EEPROM_EESK);
1015	DELAY(1);
1016	if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1017	data \|= x;
1018	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1019	DELAY(1);
1020	}
1021	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1022	DELAY(1);
1023
1024	return (data);
1025	}
1026
1027	static void
1028	fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data)
1029	{
1030	int i;
1031
1032	/*
1033	* Erase/write enable.
1034	*/
1035	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1036	fxp_eeprom_shiftin(sc, 0x4, 3);
1037	fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1038	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1039	DELAY(1);
1040	/*
1041	* Shift in write opcode, address, data.
1042	*/
1043	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1044	fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1045	fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1046	fxp_eeprom_shiftin(sc, data, 16);
1047	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1048	DELAY(1);
1049	/*
1050	* Wait for EEPROM to finish up.
1051	*/
1052	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1053	DELAY(1);
1054	for (i = 0; i < 1000; i++) {
1055	if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1056	break;
1057	DELAY(50);
1058	}
1059	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1060	DELAY(1);
1061	/*
1062	* Erase/write disable.
1063	*/
1064	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1065	fxp_eeprom_shiftin(sc, 0x4, 3);
1066	fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1067	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1068	DELAY(1);
1069	}
1070
1071	/*
1072	* From NetBSD:
1073	*
1074	* Figure out EEPROM size.
1075	*
1076	* 559's can have either 64-word or 256-word EEPROMs, the 558
1077	* datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1078	* talks about the existance of 16 to 256 word EEPROMs.
1079	*
1080	* The only known sizes are 64 and 256, where the 256 version is used
1081	* by CardBus cards to store CIS information.
1082	*
1083	* The address is shifted in msb-to-lsb, and after the last
1084	* address-bit the EEPROM is supposed to output a `dummy zero' bit,
1085	* after which follows the actual data. We try to detect this zero, by
1086	* probing the data-out bit in the EEPROM control register just after
1087	* having shifted in a bit. If the bit is zero, we assume we've
1088	* shifted enough address bits. The data-out should be tri-state,
1089	* before this, which should translate to a logical one.
1090	*/
1091	static void
1092	fxp_autosize_eeprom(struct fxp_softc *sc)
1093	{
1094
1095	/* guess maximum size of 256 words */
1096	sc->eeprom_size = 8;
1097
1098	/* autosize */
1099	(void) fxp_eeprom_getword(sc, 0, 1);
1100	}
1101
1102	static void
1103	fxp_read_eeprom(struct fxp_softc sc, u_short data, int offset, int words)
1104	{
1105	int i;
1106
1107	for (i = 0; i < words; i++) {
1108	data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1109	DBGLVL_PRINTK(4,"fxp_eeprom_read(off=0x%x)=0x%x\n",
1110	offset+i,data[i]);
1111	}
1112	}
1113
1114	static void
1115	fxp_write_eeprom(struct fxp_softc sc, u_short data, int offset, int words)
1116	{
1117	int i;
1118
1119	for (i = 0; i < words; i++)
1120	fxp_eeprom_putword(sc, offset + i, data[i]);
1121	DBGLVL_PRINTK(4,"fxp_eeprom_write(off=0x%x,0x%x)\n",
1122	offset+i,data[i]);
1123	}
1124
1125	/*
1126	* Start packet transmission on the interface.
1127	*/
1128	static void
1129	fxp_start(struct ifnet *ifp)
1130	{
1131	struct fxp_softc *sc = ifp->if_softc;
1132	struct fxp_cb_tx *txp;
1133	rtems_interrupt_level level;
1134
1135	DBGLVL_PRINTK(3,"fxp_start called\n");
1136
1137	/*
1138	* See if we need to suspend xmit until the multicast filter
1139	* has been reprogrammed (which can only be done at the head
1140	* of the command chain).
1141	*/
1142	if (sc->need_mcsetup) {
1143	DBGLVL_PRINTK(3,"fxp_start need_mcsetup\n");
1144	return;
1145	}
1146
1147	txp = NULL;
1148
1149	/*
1150	* We're finished if there is nothing more to add to the list or if
1151	* we're all filled up with buffers to transmit.
1152	* NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1153	* a NOP command when needed.
1154	*/
1155	while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) {
1156	struct mbuf m, mb_head;
1157	int segment;
1158
1159	/*
1160	* Grab a packet to transmit.
1161	*/
1162	IF_DEQUEUE(&ifp->if_snd, mb_head);
1163
1164	/*
1165	* Get pointer to next available tx desc.
1166	*/
1167	txp = sc->cbl_last->next;
1168
1169	/*
1170	* Go through each of the mbufs in the chain and initialize
1171	* the transmit buffer descriptors with the physical address
1172	* and size of the mbuf.
1173	*/
1174	tbdinit:
1175	for (m = mb_head, segment = 0; m != NULL; m = m->m_next) {
1176	if (m->m_len != 0) {
1177	if (segment == FXP_NTXSEG)
1178	break;
1179	txp->tbd[segment].tb_addr =
1180	vtophys(mtod(m, vm_offset_t));
1181	txp->tbd[segment].tb_size = m->m_len;
1182	segment++;
1183	}
1184	}
1185	if (m != NULL) {
1186	struct mbuf *mn;
1187
1188	/*
1189	* We ran out of segments. We have to recopy this
1190	* mbuf chain first. Bail out if we can't get the
1191	* new buffers.
1192	*/
1193	MGETHDR(mn, M_DONTWAIT, MT_DATA);
1194	if (mn == NULL) {
1195	m_freem(mb_head);
1196	break;
1197	}
1198	if (mb_head->m_pkthdr.len > MHLEN) {
1199	MCLGET(mn, M_DONTWAIT);
1200	if ((mn->m_flags & M_EXT) == 0) {
1201	m_freem(mn);
1202	m_freem(mb_head);
1203	break;
1204	}
1205	}
1206	m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
1207	mtod(mn, caddr_t));
1208	mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len;
1209	m_freem(mb_head);
1210	mb_head = mn;
1211	goto tbdinit;
1212	}
1213
1214	txp->tbd_number = segment;
1215	txp->mb_head = mb_head;
1216	txp->cb_status = 0;
1217	if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1218	txp->cb_command =
1219	FXP_CB_COMMAND_XMIT \| FXP_CB_COMMAND_SF \|
1220	FXP_CB_COMMAND_S;
1221	} else {
1222	txp->cb_command =
1223	FXP_CB_COMMAND_XMIT \| FXP_CB_COMMAND_SF \|
1224	FXP_CB_COMMAND_S \| FXP_CB_COMMAND_I;
1225	/*
1226	* Set a 5 second timer just in case we don't hear
1227	* from the card again.
1228	*/
1229	ifp->if_timer = 5;
1230	}
1231	txp->tx_threshold = tx_threshold;
1232
1233	/*
1234	* Advance the end of list forward.
1235	*/
1236
1237	#ifdef __alpha__
1238	/*
1239	* On platforms which can't access memory in 16-bit
1240	* granularities, we must prevent the card from DMA'ing
1241	* up the status while we update the command field.
1242	* This could cause us to overwrite the completion status.
1243	*/
1244	atomic_clear_short(&sc->cbl_last->cb_command,
1245	FXP_CB_COMMAND_S);
1246	#else
1247	sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
1248	#endif /__alpha__/
1249	sc->cbl_last = txp;
1250
1251	/*
1252	* Advance the beginning of the list forward if there are
1253	* no other packets queued (when nothing is queued, cbl_first
1254	* sits on the last TxCB that was sent out).
1255	*/
1256	if (sc->tx_queued == 0)
1257	sc->cbl_first = txp;
1258
1259	sc->tx_queued++;
1260
1261	#ifdef NOTUSED
1262	/*
1263	* Pass packet to bpf if there is a listener.
1264	*/
1265	if (ifp->if_bpf)
1266	bpf_mtap(ifp, mb_head);
1267	#endif
1268	}
1269
1270	/*
1271	* We're finished. If we added to the list, issue a RESUME to get DMA
1272	* going again if suspended.
1273	*/
1274	if (txp != NULL) {
1275	fxp_scb_wait(sc);
1276	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1277	}
1278
1279	/*
1280	* reenable interrupts
1281	*/
1282	rtems_interrupt_disable (level);
1283	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,0);
1284	bsp_interrupt_vector_enable(sc->irq_num);
1285	rtems_interrupt_enable (level);
1286	}
1287
1288	/*
1289	* Process interface interrupts.
1290	*/
1291	static void fxp_intr(void *arg)
1292	{
1293	/*
1294	* Obtain device state
1295	*/
1296	struct fxp_softc sc = (struct fxp_softc )arg;
1297
1298	/*
1299	* disable interrupts
1300	*/
1301	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1302	/*
1303	* send event to deamon
1304	*/
1305	rtems_bsdnet_event_send (sc->daemonTid, INTERRUPT_EVENT);
1306	}
1307
1308	static void fxp_daemon(void *xsc)
1309	{
1310	struct fxp_softc *sc = xsc;
1311	struct ifnet *ifp = &sc->sc_if;
1312	u_int8_t statack;
1313	rtems_event_set events;
1314	rtems_interrupt_level level;
1315
1316	#ifdef NOTUSED
1317	if (sc->suspended) {
1318	return;
1319	}
1320	#endif
1321	for (;;) {
1322
1323	DBGLVL_PRINTK(4,"fxp_daemon waiting for event, INTRCNTL 0x%02x\n",
1324	CSR_READ_1(sc, FXP_CSR_SCB_INTRCNTL));
1325	/*
1326	* wait for event to receive from interrupt function
1327	*/
1328	rtems_bsdnet_event_receive (INTERRUPT_EVENT,
1329	RTEMS_WAIT\|RTEMS_EVENT_ANY,
1330	RTEMS_NO_TIMEOUT,
1331	&events);
1332	while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1333	DBGLVL_PRINTK(4,"fxp_daemon: processing event, statack = 0x%x\n",
1334	statack);
1335	#ifdef NOTUSED
1336	/*
1337	* It should not be possible to have all bits set; the
1338	* FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1339	* all bits are set, this may indicate that the card has
1340	* been physically ejected, so ignore it.
1341	*/
1342	if (statack == 0xff)
1343	return;
1344	#endif
1345
1346	/*
1347	* First ACK all the interrupts in this pass.
1348	*/
1349	CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1350
1351	/*
1352	* Free any finished transmit mbuf chains.
1353	*
1354	* Handle the CNA event likt a CXTNO event. It used to
1355	* be that this event (control unit not ready) was not
1356	* encountered, but it is now with the SMPng modifications.
1357	* The exact sequence of events that occur when the interface
1358	* is brought up are different now, and if this event
1359	* goes unhandled, the configuration/rxfilter setup sequence
1360	* can stall for several seconds. The result is that no
1361	* packets go out onto the wire for about 5 to 10 seconds
1362	* after the interface is ifconfig'ed for the first time.
1363	*/
1364	if (statack & (FXP_SCB_STATACK_CXTNO \| FXP_SCB_STATACK_CNA)) {
1365	struct fxp_cb_tx *txp;
1366
1367	for (txp = sc->cbl_first; sc->tx_queued &&
1368	(txp->cb_status & FXP_CB_STATUS_C) != 0;
1369	txp = txp->next) {
1370	if (txp->mb_head != NULL) {
1371	m_freem(txp->mb_head);
1372	txp->mb_head = NULL;
1373	}
1374	sc->tx_queued--;
1375	}
1376	sc->cbl_first = txp;
1377	ifp->if_timer = 0;
1378	if (sc->tx_queued == 0) {
1379	if (sc->need_mcsetup)
1380	fxp_mc_setup(sc);
1381	}
1382	/*
1383	* Try to start more packets transmitting.
1384	*/
1385	if (ifp->if_snd.ifq_head != NULL)
1386	fxp_start(ifp);
1387	}
1388	/*
1389	* Process receiver interrupts. If a no-resource (RNR)
1390	* condition exists, get whatever packets we can and
1391	* re-start the receiver.
1392	*/
1393	if (statack & (FXP_SCB_STATACK_FR \| FXP_SCB_STATACK_RNR)) {
1394	struct mbuf *m;
1395	struct fxp_rfa *rfa;
1396	rcvloop:
1397	m = sc->rfa_headm;
1398	rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1399	RFA_ALIGNMENT_FUDGE);
1400
1401	if (rfa->rfa_status & FXP_RFA_STATUS_C) {
1402	/*
1403	* Remove first packet from the chain.
1404	*/
1405	sc->rfa_headm = m->m_next;
1406	m->m_next = NULL;
1407
1408	/*
1409	* Add a new buffer to the receive chain.
1410	* If this fails, the old buffer is recycled
1411	* instead.
1412	*/
1413	if (fxp_add_rfabuf(sc, m) == 0) {
1414	struct ether_header *eh;
1415	int total_len;
1416
1417	total_len = rfa->actual_size &
1418	(MCLBYTES - 1);
1419	if (total_len <
1420	sizeof(struct ether_header)) {
1421	m_freem(m);
1422	goto rcvloop;
1423	}
1424
1425	/*
1426	* Drop the packet if it has CRC
1427	* errors. This test is only needed
1428	* when doing 802.1q VLAN on the 82557
1429	* chip.
1430	*/
1431	if (rfa->rfa_status &
1432	FXP_RFA_STATUS_CRC) {
1433	m_freem(m);
1434	goto rcvloop;
1435	}
1436
1437	m->m_pkthdr.rcvif = ifp;
1438	m->m_pkthdr.len = m->m_len = total_len;
1439	eh = mtod(m, struct ether_header *);
1440	m->m_data +=
1441	sizeof(struct ether_header);
1442	m->m_len -=
1443	sizeof(struct ether_header);
1444	m->m_pkthdr.len = m->m_len;
1445	ether_input(ifp, eh, m);
1446	}
1447	goto rcvloop;
1448	}
1449	if (statack & FXP_SCB_STATACK_RNR) {
1450	fxp_scb_wait(sc);
1451	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1452	vtophys(sc->rfa_headm->m_ext.ext_buf) +
1453	RFA_ALIGNMENT_FUDGE);
1454	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1455	}
1456	}
1457	}
1458	/*
1459	* reenable interrupts
1460	*/
1461	rtems_interrupt_disable (level);
1462	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,0);
1463	bsp_interrupt_vector_enable(sc->irq_num);
1464	rtems_interrupt_enable (level);
1465	}
1466	}
1467
1468	/*
1469	* Update packet in/out/collision statistics. The i82557 doesn't
1470	* allow you to access these counters without doing a fairly
1471	* expensive DMA to get _all_ of the statistics it maintains, so
1472	* we do this operation here only once per second. The statistics
1473	* counters in the kernel are updated from the previous dump-stats
1474	* DMA and then a new dump-stats DMA is started. The on-chip
1475	* counters are zeroed when the DMA completes. If we can't start
1476	* the DMA immediately, we don't wait - we just prepare to read
1477	* them again next time.
1478	*/
1479	static void
1480	fxp_tick(void *xsc)
1481	{
1482	struct fxp_softc *sc = xsc;
1483	struct ifnet *ifp = &sc->sc_if;
1484	struct fxp_stats *sp = sc->fxp_stats;
1485	struct fxp_cb_tx *txp;
1486	int s;
1487
1488	DBGLVL_PRINTK(4,"fxp_tick called\n");
1489
1490	ifp->if_opackets += sp->tx_good;
1491	ifp->if_collisions += sp->tx_total_collisions;
1492	if (sp->rx_good) {
1493	ifp->if_ipackets += sp->rx_good;
1494	sc->rx_idle_secs = 0;
1495	} else {
1496	/*
1497	* Receiver's been idle for another second.
1498	*/
1499	sc->rx_idle_secs++;
1500	}
1501	ifp->if_ierrors +=
1502	sp->rx_crc_errors +
1503	sp->rx_alignment_errors +
1504	sp->rx_rnr_errors +
1505	sp->rx_overrun_errors;
1506	/*
1507	* If any transmit underruns occured, bump up the transmit
1508	* threshold by another 512 bytes (64 * 8).
1509	*/
1510	if (sp->tx_underruns) {
1511	ifp->if_oerrors += sp->tx_underruns;
1512	if (tx_threshold < 192)
1513	tx_threshold += 64;
1514	}
1515	s = splimp();
1516	/*
1517	* Release any xmit buffers that have completed DMA. This isn't
1518	* strictly necessary to do here, but it's advantagous for mbufs
1519	* with external storage to be released in a timely manner rather
1520	* than being defered for a potentially long time. This limits
1521	* the delay to a maximum of one second.
1522	*/
1523	for (txp = sc->cbl_first; sc->tx_queued &&
1524	(txp->cb_status & FXP_CB_STATUS_C) != 0;
1525	txp = txp->next) {
1526	if (txp->mb_head != NULL) {
1527	m_freem(txp->mb_head);
1528	txp->mb_head = NULL;
1529	}
1530	sc->tx_queued--;
1531	}
1532	sc->cbl_first = txp;
1533	/*
1534	* If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1535	* then assume the receiver has locked up and attempt to clear
1536	* the condition by reprogramming the multicast filter. This is
1537	* a work-around for a bug in the 82557 where the receiver locks
1538	* up if it gets certain types of garbage in the syncronization
1539	* bits prior to the packet header. This bug is supposed to only
1540	* occur in 10Mbps mode, but has been seen to occur in 100Mbps
1541	* mode as well (perhaps due to a 10/100 speed transition).
1542	*/
1543	if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1544	sc->rx_idle_secs = 0;
1545	fxp_mc_setup(sc);
1546	}
1547	/*
1548	* If there is no pending command, start another stats
1549	* dump. Otherwise punt for now.
1550	*/
1551	if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1552	/*
1553	* Start another stats dump.
1554	*/
1555	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1556	} else {
1557	/*
1558	* A previous command is still waiting to be accepted.
1559	* Just zero our copy of the stats and wait for the
1560	* next timer event to update them.
1561	*/
1562	sp->tx_good = 0;
1563	sp->tx_underruns = 0;
1564	sp->tx_total_collisions = 0;
1565
1566	sp->rx_good = 0;
1567	sp->rx_crc_errors = 0;
1568	sp->rx_alignment_errors = 0;
1569	sp->rx_rnr_errors = 0;
1570	sp->rx_overrun_errors = 0;
1571	}
1572	#ifdef NOTUSED
1573	if (sc->miibus != NULL)
1574	mii_tick(device_get_softc(sc->miibus));
1575	#endif
1576	splx(s);
1577	/*
1578	* Schedule another timeout one second from now.
1579	*/
1580	if (sc->stat_ch == fxp_timeout_running) {
1581	timeout(fxp_tick, sc, hz);
1582	}
1583	else if (sc->stat_ch == fxp_timeout_stop_rq) {
1584	sc->stat_ch = fxp_timeout_stopped;
1585	}
1586	}
1587
1588	/*
1589	* Stop the interface. Cancels the statistics updater and resets
1590	* the interface.
1591	*/
1592	static void
1593	fxp_stop(struct fxp_softc *sc)
1594	{
1595	struct ifnet *ifp = &sc->sc_if;
1596	struct fxp_cb_tx *txp;
1597	int i;
1598
1599	DBGLVL_PRINTK(2,"fxp_stop called\n");
1600
1601	ifp->if_flags &= ~(IFF_RUNNING \| IFF_OACTIVE);
1602	ifp->if_timer = 0;
1603
1604	/*
1605	* stop stats updater.
1606	*/
1607	if (sc->stat_ch == fxp_timeout_running) {
1608	DBGLVL_PRINTK(3,"fxp_stop: trying to stop stat update tick\n");
1609	sc->stat_ch = fxp_timeout_stop_rq;
1610	while(sc->stat_ch != fxp_timeout_stopped) {
1611	rtems_bsdnet_semaphore_release();
1612	rtems_task_wake_after(fxp_ticksPerSecond);
1613	rtems_bsdnet_semaphore_obtain();
1614	}
1615	DBGLVL_PRINTK(3,"fxp_stop: stat update tick stopped\n");
1616	}
1617	/*
1618	* Issue software reset
1619	*/
1620	DBGLVL_PRINTK(3,"fxp_stop: issue software reset\n");
1621	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1622	DELAY(10);
1623
1624	/*
1625	* Release any xmit buffers.
1626	*/
1627	DBGLVL_PRINTK(3,"fxp_stop: releasing xmit buffers\n");
1628	txp = sc->cbl_base;
1629	if (txp != NULL) {
1630	for (i = 0; i < FXP_NTXCB; i++) {
1631	if (txp[i].mb_head != NULL) {
1632	m_freem(txp[i].mb_head);
1633	txp[i].mb_head = NULL;
1634	}
1635	}
1636	}
1637	sc->tx_queued = 0;
1638
1639	/*
1640	* Free all the receive buffers then reallocate/reinitialize
1641	*/
1642	DBGLVL_PRINTK(3,"fxp_stop: free and reinit all receive buffers\n");
1643	if (sc->rfa_headm != NULL)
1644	m_freem(sc->rfa_headm);
1645	sc->rfa_headm = NULL;
1646	sc->rfa_tailm = NULL;
1647	for (i = 0; i < FXP_NRFABUFS; i++) {
1648	if (fxp_add_rfabuf(sc, NULL) != 0) {
1649	/*
1650	* This "can't happen" - we're at splimp()
1651	* and we just freed all the buffers we need
1652	* above.
1653	*/
1654	panic("fxp_stop: no buffers!");
1655	}
1656	}
1657	DBGLVL_PRINTK(2,"fxp_stop: finished\n");
1658	}
1659
1660	/*
1661	* Watchdog/transmission transmit timeout handler. Called when a
1662	* transmission is started on the interface, but no interrupt is
1663	* received before the timeout. This usually indicates that the
1664	* card has wedged for some reason.
1665	*/
1666	static void
1667	fxp_watchdog(struct ifnet *ifp)
1668	{
1669	struct fxp_softc *sc = ifp->if_softc;
1670
1671	device_printf(sc->dev, "device timeout\n");
1672	ifp->if_oerrors++;
1673
1674	fxp_init(sc);
1675	}
1676
1677	static void
1678	fxp_init(void *xsc)
1679	{
1680	struct fxp_softc *sc = xsc;
1681	struct ifnet *ifp = &sc->sc_if;
1682	struct fxp_cb_config *cbp;
1683	struct fxp_cb_ias *cb_ias;
1684	struct fxp_cb_tx *txp;
1685	int i, prm, s, rv;
1686	rtems_status_code statcode;
1687
1688	rtems_task_wake_after(100);
1689	DBGLVL_PRINTK(2,"fxp_init called\n");
1690
1691	s = splimp();
1692	/*
1693	* Cancel any pending I/O
1694	*/
1695	/*
1696	* E. Norum 2004-10-11
1697	* Add line suggested by "Eugene Denisov" <dea@sendmail.ru>.
1698	* Prevents lockup at initialization.
1699	*/
1700	sc->stat_ch = fxp_timeout_stopped;
1701	fxp_stop(sc);
1702
1703	prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1704
1705	DBGLVL_PRINTK(5,"fxp_init: Initializing base of CBL and RFA memory\n");
1706	/*
1707	* Initialize base of CBL and RFA memory. Loading with zero
1708	* sets it up for regular linear addressing.
1709	*/
1710	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1711	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
1712
1713	fxp_scb_wait(sc);
1714	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
1715
1716	/*
1717	* Initialize base of dump-stats buffer.
1718	*/
1719	DBGLVL_PRINTK(5,"fxp_init: Initializing base of dump-stats buffer\n");
1720	fxp_scb_wait(sc);
1721	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats));
1722	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
1723
1724	/*
1725	* We temporarily use memory that contains the TxCB list to
1726	* construct the config CB. The TxCB list memory is rebuilt
1727	* later.
1728	*/
1729	cbp = (struct fxp_cb_config *) sc->cbl_base;
1730	DBGLVL_PRINTK(5,"fxp_init: cbp = 0x%x\n",cbp);
1731
1732	/*
1733	* This memcpy is kind of disgusting, but there are a bunch of must be
1734	* zero and must be one bits in this structure and this is the easiest
1735	* way to initialize them all to proper values.
1736	*/
1737	memcpy( (void )(u_int32_t)(volatile void *)&cbp->cb_status,
1738	fxp_cb_config_template,
1739	sizeof(fxp_cb_config_template));
1740
1741	cbp->cb_status = 0;
1742	cbp->cb_command = FXP_CB_COMMAND_CONFIG \| FXP_CB_COMMAND_EL;
1743	cbp->link_addr = -1; /* (no) next command */
1744	cbp->byte_count = 22; /* (22) bytes to config */
1745	cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
1746	cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
1747	cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
1748	cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
1749	cbp->type_enable = 0; /* actually reserved */
1750	cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
1751	cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
1752	cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
1753	cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
1754	cbp->dma_mbce = 0; /* (disable) dma max counters */
1755	cbp->late_scb = 0; /* (don't) defer SCB update */
1756	cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
1757	cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
1758	cbp->ci_int = 1; /* interrupt on CU idle */
1759	cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
1760	cbp->ext_stats_dis = 1; /* disable extended counters */
1761	cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
1762	cbp->save_bf = sc->chip == FXP_CHIP_82557 ? 1 : prm;
1763	cbp->disc_short_rx = !prm; /* discard short packets */
1764	cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
1765	cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
1766	cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */
1767	cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
1768	cbp->csma_dis = 0; /* (don't) disable link */
1769	cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */
1770	cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
1771	cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
1772	cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
1773	cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
1774	cbp->nsai = 1; /* (don't) disable source addr insert */
1775	cbp->preamble_length = 2; /* (7 byte) preamble */
1776	cbp->loopback = 0; /* (don't) loopback */
1777	cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
1778	cbp->linear_pri_mode = 0; /* (wait after xmit only) */
1779	cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
1780	cbp->promiscuous = prm; /* promiscuous mode */
1781	cbp->bcast_disable = 0; /* (don't) disable broadcasts */
1782	cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
1783	cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
1784	cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
1785	cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
1786
1787	cbp->stripping = !prm; /* truncate rx packet to byte count */
1788	cbp->padding = 1; /* (do) pad short tx packets */
1789	cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
1790	cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
1791	cbp->ia_wake_en = 0; /* (don't) wake up on address match */
1792	cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */
1793	/* must set wake_en in PMCSR also */
1794	cbp->force_fdx = 0; /* (don't) force full duplex */
1795	cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
1796	cbp->multi_ia = 0; /* (don't) accept multiple IAs */
1797	cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
1798
1799	DBGLVL_PRINTK(5,"fxp_init: cbp initialized\n");
1800	if (sc->chip == FXP_CHIP_82557) {
1801	/*
1802	* The 82557 has no hardware flow control, the values
1803	* below are the defaults for the chip.
1804	*/
1805	cbp->fc_delay_lsb = 0;
1806	cbp->fc_delay_msb = 0x40;
1807	cbp->pri_fc_thresh = 3;
1808	cbp->tx_fc_dis = 0;
1809	cbp->rx_fc_restop = 0;
1810	cbp->rx_fc_restart = 0;
1811	cbp->fc_filter = 0;
1812	cbp->pri_fc_loc = 1;
1813	} else {
1814	cbp->fc_delay_lsb = 0x1f;
1815	cbp->fc_delay_msb = 0x01;
1816	cbp->pri_fc_thresh = 3;
1817	cbp->tx_fc_dis = 0; /* enable transmit FC */
1818	cbp->rx_fc_restop = 1; /* enable FC restop frames */
1819	cbp->rx_fc_restart = 1; /* enable FC restart frames */
1820	cbp->fc_filter = !prm; /* drop FC frames to host */
1821	cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
1822	}
1823
1824	/*
1825	* Start the config command/DMA.
1826	*/
1827	DBGLVL_PRINTK(5,"fxp_init: starting config command/DMA\n");
1828	fxp_scb_wait(sc);
1829	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
1830	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1831	/* ...and wait for it to complete. */
1832	fxp_dma_wait(&cbp->cb_status, sc);
1833
1834	/*
1835	* Now initialize the station address. Temporarily use the TxCB
1836	* memory area like we did above for the config CB.
1837	*/
1838	DBGLVL_PRINTK(5,"fxp_init: initialize station address\n");
1839	cb_ias = (struct fxp_cb_ias *) sc->cbl_base;
1840	cb_ias->cb_status = 0;
1841	cb_ias->cb_command = FXP_CB_COMMAND_IAS \| FXP_CB_COMMAND_EL;
1842	cb_ias->link_addr = -1;
1843	memcpy((void )(u_int32_t)(volatile void *)cb_ias->macaddr,
1844	sc->arpcom.ac_enaddr,
1845	sizeof(sc->arpcom.ac_enaddr));
1846
1847	/*
1848	* Start the IAS (Individual Address Setup) command/DMA.
1849	*/
1850	DBGLVL_PRINTK(5,"fxp_init: start IAS command/DMA\n");
1851	fxp_scb_wait(sc);
1852	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1853	/* ...and wait for it to complete. */
1854	fxp_dma_wait(&cb_ias->cb_status, sc);
1855
1856	/*
1857	* Initialize transmit control block (TxCB) list.
1858	*/
1859
1860	DBGLVL_PRINTK(5,"fxp_init: initialize TxCB list\n");
1861	txp = sc->cbl_base;
1862	memset(txp, 0, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
1863	for (i = 0; i < FXP_NTXCB; i++) {
1864	txp[i].cb_status = FXP_CB_STATUS_C \| FXP_CB_STATUS_OK;
1865	txp[i].cb_command = FXP_CB_COMMAND_NOP;
1866	txp[i].link_addr =
1867	vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status);
1868	if (sc->flags & FXP_FLAG_EXT_TXCB)
1869	txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]);
1870	else
1871	txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]);
1872	txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK];
1873	}
1874	/*
1875	* Set the suspend flag on the first TxCB and start the control
1876	* unit. It will execute the NOP and then suspend.
1877	*/
1878	DBGLVL_PRINTK(5,"fxp_init: setup suspend flag\n");
1879	txp->cb_command = FXP_CB_COMMAND_NOP \| FXP_CB_COMMAND_S;
1880	sc->cbl_first = sc->cbl_last = txp;
1881	sc->tx_queued = 1;
1882
1883	fxp_scb_wait(sc);
1884	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1885
1886	/*
1887	* Initialize receiver buffer area - RFA.
1888	*/
1889	DBGLVL_PRINTK(5,"fxp_init: initialize RFA\n");
1890	fxp_scb_wait(sc);
1891	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1892	vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE);
1893	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1894
1895	#ifdef NOTUSED
1896	/*
1897	* Set current media.
1898	*/
1899	if (sc->miibus != NULL)
1900	mii_mediachg(device_get_softc(sc->miibus));
1901	#endif
1902
1903	ifp->if_flags \|= IFF_RUNNING;
1904	ifp->if_flags &= ~IFF_OACTIVE;
1905
1906	if (sc->daemonTid == 0) {
1907	/*
1908	* Start driver task
1909	*/
1910	sc->daemonTid = rtems_bsdnet_newproc ("FXPd", 4096, fxp_daemon, sc);
1911
1912	/*
1913	* Set up interrupts
1914	*/
1915	statcode = rtems_interrupt_handler_install(
1916	sc->irq_num,
1917	"fxp_intr",
1918	RTEMS_INTERRUPT_SHARED,
1919	fxp_intr,
1920	sc
1921	);
1922
1923	if ( statcode != RTEMS_SUCCESSFUL ) {
1924	rtems_panic ("Can't attach fxp interrupt handler for irq %d\n",
1925	sc->irq_num);
1926	}
1927	}
1928
1929	/*
1930	* Enable interrupts.
1931	*/
1932	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1933	splx(s);
1934
1935	/*
1936	* Start stats updater.
1937	*/
1938	sc->stat_ch = fxp_timeout_running;
1939	DBGLVL_PRINTK(2,"fxp_init: stats updater timeout called with hz=%d\n", hz);
1940	timeout(fxp_tick, sc, hz);
1941	DBGLVL_PRINTK(2,"fxp_init finished\n");
1942	}
1943
1944	#ifdef NOTUSED
1945	static int
1946	fxp_serial_ifmedia_upd(struct ifnet *ifp)
1947	{
1948
1949	return (0);
1950	}
1951
1952	static void
1953	fxp_serial_ifmedia_sts(struct ifnet ifp, struct ifmediareq ifmr)
1954	{
1955
1956	ifmr->ifm_active = IFM_ETHER\|IFM_MANUAL;
1957	}
1958
1959	/*
1960	* Change media according to request.
1961	*/
1962	static int
1963	fxp_ifmedia_upd(struct ifnet *ifp)
1964	{
1965	struct fxp_softc *sc = ifp->if_softc;
1966	struct mii_data *mii;
1967
1968	mii = device_get_softc(sc->miibus);
1969	mii_mediachg(mii);
1970	return (0);
1971	}
1972
1973	/*
1974	* Notify the world which media we're using.
1975	*/
1976	static void
1977	fxp_ifmedia_sts(struct ifnet ifp, struct ifmediareq ifmr)
1978	{
1979	struct fxp_softc *sc = ifp->if_softc;
1980	struct mii_data *mii;
1981
1982	mii = device_get_softc(sc->miibus);
1983	mii_pollstat(mii);
1984	ifmr->ifm_active = mii->mii_media_active;
1985	ifmr->ifm_status = mii->mii_media_status;
1986
1987	if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG)
1988	sc->cu_resume_bug = 1;
1989	else
1990	sc->cu_resume_bug = 0;
1991	}
1992	#endif
1993
1994	/*
1995	* Add a buffer to the end of the RFA buffer list.
1996	* Return 0 if successful, 1 for failure. A failure results in
1997	* adding the 'oldm' (if non-NULL) on to the end of the list -
1998	* tossing out its old contents and recycling it.
1999	* The RFA struct is stuck at the beginning of mbuf cluster and the
2000	* data pointer is fixed up to point just past it.
2001	*/
2002	static int
2003	fxp_add_rfabuf(struct fxp_softc sc, struct mbuf oldm)
2004	{
2005	u_int32_t v;
2006	struct mbuf *m;
2007	struct fxp_rfa rfa, p_rfa;
2008
2009	DBGLVL_PRINTK(4,"fxp_add_rfabuf called\n");
2010
2011	MGETHDR(m, M_DONTWAIT, MT_DATA);
2012	if (m != NULL) {
2013	MCLGET(m, M_DONTWAIT);
2014	if ((m->m_flags & M_EXT) == 0) {
2015	m_freem(m);
2016	if (oldm == NULL)
2017	return 1;
2018	m = oldm;
2019	m->m_data = m->m_ext.ext_buf;
2020	}
2021	} else {
2022	if (oldm == NULL)
2023	return 1;
2024	m = oldm;
2025	m->m_data = m->m_ext.ext_buf;
2026	}
2027
2028	/*
2029	* Move the data pointer up so that the incoming data packet
2030	* will be 32-bit aligned.
2031	*/
2032	m->m_data += RFA_ALIGNMENT_FUDGE;
2033
2034	/*
2035	* Get a pointer to the base of the mbuf cluster and move
2036	* data start past it.
2037	*/
2038	rfa = mtod(m, struct fxp_rfa *);
2039	m->m_data += sizeof(struct fxp_rfa);
2040	rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE);
2041
2042	/*
2043	* Initialize the rest of the RFA. Note that since the RFA
2044	* is misaligned, we cannot store values directly. Instead,
2045	* we use an optimized, inline copy.
2046	*/
2047
2048	rfa->rfa_status = 0;
2049	rfa->rfa_control = FXP_RFA_CONTROL_EL;
2050	rfa->actual_size = 0;
2051
2052	v = -1;
2053	fxp_lwcopy(&v, (volatile u_int32_t*) rfa->link_addr);
2054	fxp_lwcopy(&v, (volatile u_int32_t*) rfa->rbd_addr);
2055
2056	/*
2057	* If there are other buffers already on the list, attach this
2058	* one to the end by fixing up the tail to point to this one.
2059	*/
2060	if (sc->rfa_headm != NULL) {
2061	p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf +
2062	RFA_ALIGNMENT_FUDGE);
2063	sc->rfa_tailm->m_next = m;
2064	v = vtophys(rfa);
2065	fxp_lwcopy(&v, (volatile u_int32_t*) p_rfa->link_addr);
2066	p_rfa->rfa_control = 0;
2067	} else {
2068	sc->rfa_headm = m;
2069	}
2070	sc->rfa_tailm = m;
2071
2072	return (m == oldm);
2073	}
2074
2075	#ifdef NOTUSED
2076	static volatile int
2077	fxp_miibus_readreg(device_t dev, int phy, int reg)
2078	{
2079	struct fxp_softc *sc = device_get_softc(dev);
2080	int count = 10000;
2081	int value;
2082
2083	CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2084	(FXP_MDI_READ << 26) \| (reg << 16) \| (phy << 21));
2085
2086	while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2087	&& count--)
2088	DELAY(10);
2089
2090	if (count <= 0)
2091	device_printf(dev, "fxp_miibus_readreg: timed out\n");
2092
2093	return (value & 0xffff);
2094	}
2095
2096	static void
2097	fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2098	{
2099	struct fxp_softc *sc = device_get_softc(dev);
2100	int count = 10000;
2101
2102	CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2103	(FXP_MDI_WRITE << 26) \| (reg << 16) \| (phy << 21) \|
2104	(value & 0xffff));
2105
2106	while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2107	count--)
2108	DELAY(10);
2109
2110	if (count <= 0)
2111	device_printf(dev, "fxp_miibus_writereg: timed out\n");
2112	}
2113	#endif
2114
2115	static int
2116	fxp_ioctl(struct ifnet *ifp, ioctl_command_t command, caddr_t data)
2117	{
2118	struct fxp_softc *sc = ifp->if_softc;
2119	#ifdef NOTUSED
2120	struct ifreq ifr = (struct ifreq )data;
2121	struct mii_data *mii;
2122	#endif
2123	int s, error = 0;
2124
2125	DBGLVL_PRINTK(2,"fxp_ioctl called\n");
2126
2127	s = splimp();
2128
2129	switch (command) {
2130	case SIOCSIFADDR:
2131	case SIOCGIFADDR:
2132	case SIOCSIFMTU:
2133	error = ether_ioctl(ifp, command, data);
2134	break;
2135
2136	case SIOCSIFFLAGS:
2137	if (ifp->if_flags & IFF_ALLMULTI)
2138	sc->flags \|= FXP_FLAG_ALL_MCAST;
2139	else
2140	sc->flags &= ~FXP_FLAG_ALL_MCAST;
2141
2142	/*
2143	* If interface is marked up and not running, then start it.
2144	* If it is marked down and running, stop it.
2145	* XXX If it's up then re-initialize it. This is so flags
2146	* such as IFF_PROMISC are handled.
2147	*/
2148	if (ifp->if_flags & IFF_UP) {
2149	fxp_init(sc);
2150	} else {
2151	if (ifp->if_flags & IFF_RUNNING)
2152	fxp_stop(sc);
2153	}
2154	break;
2155
2156	case SIOCADDMULTI:
2157	case SIOCDELMULTI:
2158	if (ifp->if_flags & IFF_ALLMULTI)
2159	sc->flags \|= FXP_FLAG_ALL_MCAST;
2160	else
2161	sc->flags &= ~FXP_FLAG_ALL_MCAST;
2162	/*
2163	* Multicast list has changed; set the hardware filter
2164	* accordingly.
2165	*/
2166	if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
2167	fxp_mc_setup(sc);
2168	/*
2169	* fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
2170	* again rather than else {}.
2171	*/
2172	if (sc->flags & FXP_FLAG_ALL_MCAST)
2173	fxp_init(sc);
2174	error = 0;
2175	break;
2176
2177	#ifdef NOTUSED
2178	case SIOCSIFMEDIA:
2179	case SIOCGIFMEDIA:
2180	if (sc->miibus != NULL) {
2181	mii = device_get_softc(sc->miibus);
2182	error = ifmedia_ioctl(ifp, ifr,
2183	&mii->mii_media, command);
2184	} else {
2185	error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2186	}
2187	break;
2188	#endif
2189
2190	case SIO_RTEMS_SHOW_STATS:
2191	fxp_stats(sc);
2192	break;
2193
2194	default:
2195	error = EINVAL;
2196	}
2197	splx(s);
2198	return (error);
2199	}
2200
2201	/*
2202	* Program the multicast filter.
2203	*
2204	* We have an artificial restriction that the multicast setup command
2205	* must be the first command in the chain, so we take steps to ensure
2206	* this. By requiring this, it allows us to keep up the performance of
2207	* the pre-initialized command ring (esp. link pointers) by not actually
2208	* inserting the mcsetup command in the ring - i.e. its link pointer
2209	* points to the TxCB ring, but the mcsetup descriptor itself is not part
2210	* of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2211	* lead into the regular TxCB ring when it completes.
2212	*
2213	* This function must be called at splimp.
2214	*/
2215	static void
2216	fxp_mc_setup(struct fxp_softc *sc)
2217	{
2218	struct fxp_cb_mcs *mcsp = sc->mcsp;
2219	struct ifnet *ifp = &sc->sc_if;
2220	#ifdef NOTUSED
2221	struct ifmultiaddr *ifma;
2222	#endif
2223	int nmcasts;
2224	int count;
2225
2226	DBGLVL_PRINTK(2,"fxp_mc_setup called\n");
2227
2228	/*
2229	* If there are queued commands, we must wait until they are all
2230	* completed. If we are already waiting, then add a NOP command
2231	* with interrupt option so that we're notified when all commands
2232	* have been completed - fxp_start() ensures that no additional
2233	* TX commands will be added when need_mcsetup is true.
2234	*/
2235	if (sc->tx_queued) {
2236	struct fxp_cb_tx *txp;
2237
2238	/*
2239	* need_mcsetup will be true if we are already waiting for the
2240	* NOP command to be completed (see below). In this case, bail.
2241	*/
2242	if (sc->need_mcsetup)
2243	return;
2244	sc->need_mcsetup = 1;
2245
2246	/*
2247	* Add a NOP command with interrupt so that we are notified when all
2248	* TX commands have been processed.
2249	*/
2250	txp = sc->cbl_last->next;
2251	txp->mb_head = NULL;
2252	txp->cb_status = 0;
2253	txp->cb_command = FXP_CB_COMMAND_NOP \|
2254	FXP_CB_COMMAND_S \| FXP_CB_COMMAND_I;
2255	/*
2256	* Advance the end of list forward.
2257	*/
2258	sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
2259	sc->cbl_last = txp;
2260	sc->tx_queued++;
2261	/*
2262	* Issue a resume in case the CU has just suspended.
2263	*/
2264	fxp_scb_wait(sc);
2265	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2266	/*
2267	* Set a 5 second timer just in case we don't hear from the
2268	* card again.
2269	*/
2270	ifp->if_timer = 5;
2271
2272	return;
2273	}
2274	sc->need_mcsetup = 0;
2275
2276	/*
2277	* Initialize multicast setup descriptor.
2278	*/
2279	mcsp->next = sc->cbl_base;
2280	mcsp->mb_head = NULL;
2281	mcsp->cb_status = 0;
2282	mcsp->cb_command = FXP_CB_COMMAND_MCAS \|
2283	FXP_CB_COMMAND_S \| FXP_CB_COMMAND_I;
2284	mcsp->link_addr = vtophys(&sc->cbl_base->cb_status);
2285
2286	nmcasts = 0;
2287	#ifdef NOTUSED /* FIXME: Multicast not supported? */
2288	if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
2289	#if __FreeBSD_version < 500000
2290	LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2291	#else
2292	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2293	#endif
2294	if (ifma->ifma_addr->sa_family != AF_LINK)
2295	continue;
2296	if (nmcasts >= MAXMCADDR) {
2297	sc->flags \|= FXP_FLAG_ALL_MCAST;
2298	nmcasts = 0;
2299	break;
2300	}
2301	memcpy((void )(uintptr_t)(volatile void )
2302	&sc->mcsp->mc_addr[nmcasts][0],
2303	LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 6);
2304	nmcasts++;
2305	}
2306	}
2307	#endif
2308	mcsp->mc_cnt = nmcasts * 6;
2309	sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp;
2310	sc->tx_queued = 1;
2311
2312	/*
2313	* Wait until command unit is not active. This should never
2314	* be the case when nothing is queued, but make sure anyway.
2315	*/
2316	count = 100;
2317	while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2318	FXP_SCB_CUS_ACTIVE && --count)
2319	DELAY(10);
2320	if (count == 0) {
2321	device_printf(sc->dev, "command queue timeout\n");
2322	return;
2323	}
2324
2325	/*
2326	* Start the multicast setup command.
2327	*/
2328	fxp_scb_wait(sc);
2329	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
2330	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2331
2332	ifp->if_timer = 2;
2333	return;
2334	}
2335
2336	#endif /* defined(__i386__) */

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source: rtems/c/src/libchip/network/if_fxp.c @ 4d3c866

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