1 | /*- |
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2 | * Copyright (c) 1995, David Greenman |
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3 | * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> |
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4 | * All rights reserved. |
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5 | * |
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6 | * Redistribution and use in source and binary forms, with or without |
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7 | * modification, are permitted provided that the following conditions |
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8 | * are met: |
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9 | * 1. Redistributions of source code must retain the above copyright |
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10 | * notice unmodified, this list of conditions, and the following |
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11 | * disclaimer. |
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12 | * 2. Redistributions in binary form must reproduce the above copyright |
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13 | * notice, this list of conditions and the following disclaimer in the |
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14 | * documentation and/or other materials provided with the distribution. |
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15 | * |
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16 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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17 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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20 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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21 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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22 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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23 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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24 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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25 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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26 | * SUCH DAMAGE. |
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27 | * |
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28 | * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.118 2001/09/05 23:33:58 brooks Exp $ |
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29 | */ |
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30 | |
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31 | /* |
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32 | * Intel EtherExpress Pro/100B PCI Fast Ethernet driver |
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33 | */ |
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34 | |
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35 | /* |
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36 | * RTEMS Revision Preliminary History |
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37 | * |
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38 | * July XXX, 2002 W. Eric Norum <eric.norum@usask.ca> |
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39 | * Placed in RTEMS CVS repository. All further modifications will be |
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40 | * noted in the CVS log and not in this comment. |
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41 | * |
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42 | * July 11, 2002 W. Eric Norum <eric.norum@usask.ca> |
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43 | * Minor modifications to get driver working with NIC on VersaLogic |
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44 | * Bobcat PC-104 single-board computer. The Bobcat has no video |
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45 | * driver so printf/printk calls are directed to COM2:. This |
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46 | * arrangement seems to require delays after the printk calls or |
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47 | * else things lock up. Perhaps the RTEMS pc386 console code |
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48 | * should be modified to insert these delays itself. |
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49 | * |
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50 | * June 27, 2002 W. Eric Norum <eric.norum@usask.ca> |
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51 | * Obtained from Thomas Doerfler <Thomas.Doerfler@imd-systems.de>. |
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52 | * A big thank-you to Thomas for making this available. |
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53 | * |
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54 | * October 01, 2001 Thomas Doerfler <Thomas.Doerfler@imd-systems.de> |
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55 | * Original RTEMS modifications. |
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56 | */ |
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57 | |
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58 | #if defined(__i386__) |
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59 | |
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60 | /*#define DEBUG_OUT 0*/ |
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61 | |
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62 | #include <rtems.h> |
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63 | #include <rtems/error.h> |
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64 | #include <rtems/rtems_bsdnet.h> |
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65 | #include <bsp.h> |
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66 | |
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67 | #include <sys/errno.h> |
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68 | #include <sys/param.h> |
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69 | #include <sys/mbuf.h> |
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70 | #include <sys/socket.h> |
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71 | #include <sys/sockio.h> |
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72 | #include <net/if.h> |
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73 | #include <netinet/in.h> |
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74 | #include <netinet/if_ether.h> |
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75 | #include <sys/malloc.h> |
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76 | #include <sys/systm.h> |
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77 | #include <bsp.h> |
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78 | #include <pcibios.h> |
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79 | #include <irq.h> |
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80 | #include <rtems/pci.h> |
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81 | |
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82 | #ifdef NS |
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83 | #include <netns/ns.h> |
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84 | #include <netns/ns_if.h> |
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85 | #endif |
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86 | |
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87 | #include <net/bpf.h> |
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88 | |
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89 | #include <vm/vm.h> /* for vtophys */ |
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90 | |
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91 | #include <net/if_types.h> |
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92 | |
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93 | #include "if_fxpreg.h" |
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94 | #include "if_fxpvar.h" |
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95 | |
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96 | /* |
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97 | * some adaptation replacements for RTEMS |
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98 | */ |
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99 | static rtems_interval fxp_ticksPerSecond; |
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100 | #define device_printf(device,format,args...) printk(format,## args) |
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101 | #define DELAY(n) rtems_task_wake_after(((n)*fxp_ticksPerSecond/1000000)+1) |
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102 | #ifdef DEBUG_OUT |
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103 | #define DBGLVL_PRINTK(LVL,format, args...) \ |
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104 | if (DEBUG_OUT >= (LVL)) { \ |
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105 | printk(format, ## args); \ |
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106 | } |
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107 | #else |
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108 | #define DBGLVL_PRINTK(LVL,format, args...) |
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109 | #endif |
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110 | |
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111 | /* |
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112 | * RTEMS event used by interrupt handler to signal driver tasks. |
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113 | * This must not be any of the events used by the network task synchronization. |
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114 | */ |
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115 | #define INTERRUPT_EVENT RTEMS_EVENT_1 |
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116 | |
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117 | /* |
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118 | * remapping between PCI device and CPU memmory address view... |
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119 | */ |
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120 | #if defined(__i386) |
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121 | #define vtophys(p) (u_int32_t)(p) |
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122 | #else |
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123 | #define vtophys(p) vtophys(p) |
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124 | #endif |
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125 | |
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126 | #define NFXPDRIVER 1 |
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127 | static struct fxp_softc fxp_softc[NFXPDRIVER]; |
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128 | static int fxp_is_verbose = TRUE; |
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129 | /* |
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130 | * NOTE! On the Alpha, we have an alignment constraint. The |
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131 | * card DMAs the packet immediately following the RFA. However, |
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132 | * the first thing in the packet is a 14-byte Ethernet header. |
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133 | * This means that the packet is misaligned. To compensate, |
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134 | * we actually offset the RFA 2 bytes into the cluster. This |
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135 | * alignes the packet after the Ethernet header at a 32-bit |
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136 | * boundary. HOWEVER! This means that the RFA is misaligned! |
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137 | */ |
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138 | #define RFA_ALIGNMENT_FUDGE 2 |
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139 | |
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140 | /* |
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141 | * Set initial transmit threshold at 64 (512 bytes). This is |
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142 | * increased by 64 (512 bytes) at a time, to maximum of 192 |
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143 | * (1536 bytes), if an underrun occurs. |
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144 | */ |
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145 | static int tx_threshold = 64; |
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146 | |
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147 | /* |
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148 | * The configuration byte map has several undefined fields which |
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149 | * must be one or must be zero. Set up a template for these bits |
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150 | * only, (assuming a 82557 chip) leaving the actual configuration |
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151 | * to fxp_init. |
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152 | * |
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153 | * See struct fxp_cb_config for the bit definitions. |
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154 | */ |
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155 | static u_char fxp_cb_config_template[] = { |
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156 | 0x0, 0x0, /* cb_status */ |
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157 | 0x0, 0x0, /* cb_command */ |
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158 | 0x0, 0x0, 0x0, 0x0, /* link_addr */ |
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159 | 0x0, /* 0 */ |
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160 | 0x0, /* 1 */ |
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161 | 0x0, /* 2 */ |
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162 | 0x0, /* 3 */ |
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163 | 0x0, /* 4 */ |
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164 | 0x0, /* 5 */ |
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165 | 0x32, /* 6 */ |
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166 | 0x0, /* 7 */ |
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167 | 0x0, /* 8 */ |
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168 | 0x0, /* 9 */ |
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169 | 0x6, /* 10 */ |
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170 | 0x0, /* 11 */ |
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171 | 0x0, /* 12 */ |
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172 | 0x0, /* 13 */ |
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173 | 0xf2, /* 14 */ |
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174 | 0x48, /* 15 */ |
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175 | 0x0, /* 16 */ |
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176 | 0x40, /* 17 */ |
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177 | 0xf0, /* 18 */ |
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178 | 0x0, /* 19 */ |
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179 | 0x3f, /* 20 */ |
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180 | 0x5 /* 21 */ |
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181 | }; |
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182 | |
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183 | struct fxp_ident { |
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184 | u_int16_t devid; |
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185 | char *name; |
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186 | int warn; |
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187 | }; |
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188 | |
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189 | #define UNTESTED 1 |
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190 | |
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191 | /* |
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192 | * Claim various Intel PCI device identifiers for this driver. The |
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193 | * sub-vendor and sub-device field are extensively used to identify |
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194 | * particular variants, but we don't currently differentiate between |
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195 | * them. |
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196 | */ |
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197 | static struct fxp_ident fxp_ident_table[] = { |
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198 | { 0x1229, "Intel Pro 10/100B/100+ Ethernet", UNTESTED }, |
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199 | { 0x2449, "Intel Pro/100 Ethernet", UNTESTED }, |
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200 | { 0x1209, "Intel Embedded 10/100 Ethernet", 0 }, |
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201 | { 0x1029, "Intel Pro/100 Ethernet", UNTESTED }, |
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202 | { 0x1030, "Intel Pro/100 Ethernet", 0 }, |
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203 | { 0x1031, "Intel Pro/100 Ethernet", UNTESTED }, |
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204 | { 0x1032, "Intel Pro/100 Ethernet", UNTESTED }, |
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205 | { 0x1033, "Intel Pro/100 Ethernet", UNTESTED }, |
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206 | { 0x1034, "Intel Pro/100 Ethernet", UNTESTED }, |
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207 | { 0x1035, "Intel Pro/100 Ethernet", UNTESTED }, |
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208 | { 0x1036, "Intel Pro/100 Ethernet", UNTESTED }, |
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209 | { 0x1037, "Intel Pro/100 Ethernet", UNTESTED }, |
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210 | { 0x1038, "Intel Pro/100 Ethernet", UNTESTED }, |
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211 | { 0, NULL }, |
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212 | }; |
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213 | |
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214 | #if 0 |
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215 | static int fxp_probe(device_t dev); |
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216 | static int fxp_attach(device_t dev); |
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217 | static int fxp_detach(device_t dev); |
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218 | static int fxp_shutdown(device_t dev); |
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219 | #endif |
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220 | int fxp_output (struct ifnet *, |
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221 | struct mbuf *, struct sockaddr *, struct rtentry *); |
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222 | |
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223 | |
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224 | static rtems_isr fxp_intr(rtems_vector_number v); |
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225 | static void fxp_init(void *xsc); |
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226 | static void fxp_tick(void *xsc); |
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227 | static void fxp_start(struct ifnet *ifp); |
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228 | static void fxp_stop(struct fxp_softc *sc); |
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229 | static void fxp_release(struct fxp_softc *sc); |
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230 | static int fxp_ioctl(struct ifnet *ifp, int command, |
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231 | caddr_t data); |
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232 | static void fxp_watchdog(struct ifnet *ifp); |
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233 | static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); |
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234 | static void fxp_mc_setup(struct fxp_softc *sc); |
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235 | static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, |
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236 | int autosize); |
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237 | static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, |
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238 | u_int16_t data); |
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239 | static void fxp_autosize_eeprom(struct fxp_softc *sc); |
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240 | static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, |
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241 | int offset, int words); |
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242 | static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, |
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243 | int offset, int words); |
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244 | #ifdef NOTUSED |
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245 | static int fxp_ifmedia_upd(struct ifnet *ifp); |
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246 | static void fxp_ifmedia_sts(struct ifnet *ifp, |
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247 | struct ifmediareq *ifmr); |
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248 | static int fxp_serial_ifmedia_upd(struct ifnet *ifp); |
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249 | static void fxp_serial_ifmedia_sts(struct ifnet *ifp, |
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250 | struct ifmediareq *ifmr); |
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251 | static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); |
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252 | static void fxp_miibus_writereg(device_t dev, int phy, int reg, |
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253 | int value); |
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254 | #endif |
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255 | static __inline void fxp_lwcopy(volatile u_int32_t *src, |
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256 | volatile u_int32_t *dst); |
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257 | static __inline void fxp_scb_wait(struct fxp_softc *sc); |
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258 | static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); |
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259 | static __inline void fxp_dma_wait(volatile u_int16_t *status, |
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260 | struct fxp_softc *sc); |
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261 | |
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262 | /* |
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263 | * Inline function to copy a 16-bit aligned 32-bit quantity. |
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264 | */ |
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265 | static __inline void |
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266 | fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) |
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267 | { |
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268 | #ifdef __i386__ |
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269 | *dst = *src; |
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270 | #else |
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271 | volatile u_int16_t *a = (volatile u_int16_t*)src; |
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272 | volatile u_int16_t *b = (volatile u_int16_t*)dst; |
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273 | |
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274 | b[0] = a[0]; |
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275 | b[1] = a[1]; |
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276 | #endif |
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277 | } |
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278 | |
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279 | /* |
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280 | * inline access functions to pci space registers |
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281 | */ |
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282 | static __inline u_int8_t fxp_csr_read_1(struct fxp_softc *sc,int reg) { |
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283 | u_int8_t val; |
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284 | if (sc->pci_regs_are_io) { |
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285 | inport_byte(sc->pci_regs_base + reg,val); |
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286 | } |
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287 | else { |
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288 | val = *(u_int8_t*)(sc->pci_regs_base+reg); |
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289 | } |
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290 | return val; |
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291 | } |
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292 | static __inline u_int32_t fxp_csr_read_2(struct fxp_softc *sc,int reg) { |
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293 | u_int16_t val; |
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294 | if (sc->pci_regs_are_io) { |
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295 | inport_word(sc->pci_regs_base + reg,val); |
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296 | } |
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297 | else { |
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298 | val = *(u_int16_t*)(sc->pci_regs_base+reg); |
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299 | } |
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300 | return val; |
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301 | } |
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302 | static __inline u_int32_t fxp_csr_read_4(struct fxp_softc *sc,int reg) { |
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303 | u_int32_t val; |
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304 | if (sc->pci_regs_are_io) { |
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305 | inport_long(sc->pci_regs_base + reg,val); |
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306 | } |
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307 | else { |
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308 | val = *(u_int32_t*)(sc->pci_regs_base+reg); |
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309 | } |
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310 | return val; |
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311 | } |
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312 | |
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313 | /* |
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314 | * Wait for the previous command to be accepted (but not necessarily |
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315 | * completed). |
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316 | */ |
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317 | static __inline void |
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318 | fxp_scb_wait(struct fxp_softc *sc) |
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319 | { |
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320 | int i = 10000; |
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321 | |
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322 | while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) |
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323 | DELAY(2); |
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324 | if (i == 0) |
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325 | device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", |
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326 | CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), |
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327 | CSR_READ_1(sc, FXP_CSR_SCB_STATACK), |
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328 | CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), |
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329 | CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); |
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330 | } |
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331 | |
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332 | static __inline void |
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333 | fxp_scb_cmd(struct fxp_softc *sc, int cmd) |
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334 | { |
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335 | |
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336 | if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { |
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337 | CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); |
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338 | fxp_scb_wait(sc); |
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339 | } |
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340 | CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); |
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341 | } |
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342 | |
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343 | static __inline void |
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344 | fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) |
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345 | { |
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346 | int i = 10000; |
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347 | |
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348 | while (!(*status & FXP_CB_STATUS_C) && --i) |
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349 | DELAY(2); |
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350 | if (i == 0) |
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351 | device_printf(sc->dev, "DMA timeout\n"); |
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352 | } |
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353 | |
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354 | static __inline unsigned int pci_get_vendor(struct fxp_softc *sc) { |
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355 | u_int16_t vendor; |
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356 | pcib_conf_read16(sc->pci_signature,0,&vendor); |
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357 | return vendor; |
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358 | } |
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359 | |
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360 | static __inline unsigned int pci_get_device(struct fxp_softc *sc) { |
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361 | u_int16_t device; |
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362 | pcib_conf_read16(sc->pci_signature,2,&device); |
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363 | return device; |
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364 | } |
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365 | |
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366 | static __inline unsigned int pci_get_subvendor(struct fxp_softc *sc) { |
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367 | u_int16_t subvendor; |
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368 | pcib_conf_read16(sc->pci_signature,0x2c,&subvendor); |
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369 | return subvendor; |
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370 | } |
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371 | |
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372 | static __inline unsigned int pci_get_subdevice(struct fxp_softc *sc) { |
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373 | u_int16_t subdevice; |
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374 | pcib_conf_read16(sc->pci_signature,0x2e,&subdevice); |
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375 | return subdevice; |
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376 | } |
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377 | |
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378 | static __inline unsigned int pci_get_revid(struct fxp_softc *sc) { |
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379 | u_int8_t revid; |
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380 | pcib_conf_read8(sc->pci_signature,0x08,&revid); |
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381 | return revid; |
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382 | } |
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383 | |
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384 | static void nopOn(const rtems_irq_connect_data* notUsed) |
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385 | { |
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386 | /* |
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387 | * code should be moved from fxp_Enet_initialize_hardware |
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388 | * to this location |
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389 | */ |
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390 | } |
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391 | |
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392 | static int fxpIsOn(const rtems_irq_connect_data* irq) |
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393 | { |
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394 | return BSP_irq_enabled_at_i8259s (irq->name); |
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395 | } |
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396 | |
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397 | int |
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398 | rtems_fxp_attach(struct rtems_bsdnet_ifconfig *config, int attaching) |
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399 | { |
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400 | int error = 0; |
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401 | struct fxp_softc *sc; |
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402 | struct ifnet *ifp; |
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403 | u_int16_t val16; |
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404 | u_int32_t val32; |
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405 | u_int16_t data; |
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406 | int i; |
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407 | int s; |
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408 | int unitNumber; |
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409 | char *unitName; |
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410 | u_int16_t dev_id; |
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411 | u_int8_t interrupt; |
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412 | int mtu; |
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413 | |
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414 | /* |
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415 | * Set up some timing values |
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416 | */ |
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417 | rtems_clock_get(RTEMS_CLOCK_GET_TICKS_PER_SECOND, &fxp_ticksPerSecond); |
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418 | DBGLVL_PRINTK(1,"fxp_attach called\n"); |
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419 | |
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420 | /* |
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421 | * Parse driver name |
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422 | */ |
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423 | if ((unitNumber = rtems_bsdnet_parse_driver_name (config, &unitName)) < 0) |
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424 | return 0; |
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425 | |
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426 | /* |
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427 | * Is driver free? |
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428 | */ |
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429 | if ((unitNumber <= 0) || (unitNumber > NFXPDRIVER)) { |
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430 | device_printf(dev,"Bad FXP unit number.\n"); |
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431 | return 0; |
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432 | } |
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433 | sc = &fxp_softc[unitNumber - 1]; |
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434 | ifp = &sc->arpcom.ac_if; |
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435 | if (ifp->if_softc != NULL) { |
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436 | device_printf(dev,"FXP Driver already in use.\n"); |
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437 | return 0; |
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438 | } |
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439 | |
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440 | memset(sc, 0, sizeof(*sc)); |
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441 | #ifdef NOTUSED |
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442 | sc->dev = dev; |
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443 | callout_handle_init(&sc->stat_ch); |
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444 | mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); |
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445 | #endif |
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446 | s = splimp(); |
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447 | |
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448 | /* |
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449 | * init PCI Bios interface... |
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450 | */ |
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451 | i = pcib_init(); |
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452 | DBGLVL_PRINTK(2,"fxp_attach: pcib_init returned %d\n",i); |
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453 | if (i != PCIB_ERR_SUCCESS) { |
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454 | device_printf(dev, "could not initialize pci bios interface\n"); |
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455 | return 0; |
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456 | } |
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457 | |
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458 | /* |
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459 | * find device on pci bus |
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460 | */ |
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461 | { int j; |
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462 | |
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463 | for (j=0; fxp_ident_table[j].devid; j++ ) { |
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464 | i = pcib_find_by_devid( 0x8086, |
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465 | fxp_ident_table[j].devid, |
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466 | unitNumber-1, |
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467 | &(sc->pci_signature)); |
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468 | DBGLVL_PRINTK(2,"fxp_attach: find_devid returned %d " |
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469 | "and pci signature 0x%x\n", |
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470 | i,sc->pci_signature); |
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471 | if (PCIB_ERR_SUCCESS == i) { |
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472 | if ( UNTESTED == fxp_ident_table[j].warn ) { |
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473 | device_printf(dev, |
---|
474 | "WARNING: this chip version has NOT been reported to work under RTEMS yet.\n"); |
---|
475 | device_printf(dev, |
---|
476 | " If it works OK, report it as tested in 'c/src/libchip/network/if_fxp.c'\n"); |
---|
477 | } |
---|
478 | break; |
---|
479 | } |
---|
480 | } |
---|
481 | } |
---|
482 | |
---|
483 | /* |
---|
484 | * FIXME: add search for more device types... |
---|
485 | */ |
---|
486 | if (i != PCIB_ERR_SUCCESS) { |
---|
487 | device_printf(dev, "could not find 82559ER device\n"); |
---|
488 | return 0; |
---|
489 | } |
---|
490 | |
---|
491 | |
---|
492 | /* |
---|
493 | * Enable bus mastering. Enable memory space too, in case |
---|
494 | * BIOS/Prom forgot about it. |
---|
495 | */ |
---|
496 | pcib_conf_read16(sc->pci_signature, PCI_COMMAND,&val16); |
---|
497 | val16 |= (PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER); |
---|
498 | pcib_conf_write16(sc->pci_signature, PCI_COMMAND, val16); |
---|
499 | DBGLVL_PRINTK(3,"fxp_attach: PCI_COMMAND_write = 0x%x\n",val16); |
---|
500 | pcib_conf_read16(sc->pci_signature, PCI_COMMAND,&val16); |
---|
501 | DBGLVL_PRINTK(4,"fxp_attach: PCI_COMMAND_read = 0x%x\n",val16); |
---|
502 | |
---|
503 | /* |
---|
504 | * Figure out which we should try first - memory mapping or i/o mapping? |
---|
505 | * We default to memory mapping. Then we accept an override from the |
---|
506 | * command line. Then we check to see which one is enabled. |
---|
507 | */ |
---|
508 | #ifdef NOTUSED |
---|
509 | m1 = PCI_COMMAND_MEMORY; |
---|
510 | m2 = PCI_COMMAND_IO; |
---|
511 | prefer_iomap = 0; |
---|
512 | if (resource_int_value(device_get_name(dev), device_get_unit(dev), |
---|
513 | "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { |
---|
514 | m1 = PCI_COMMAND_IO; |
---|
515 | m2 = PCI_COMMAND_MEMORY; |
---|
516 | } |
---|
517 | |
---|
518 | if (val & m1) { |
---|
519 | sc->rtp = ((m1 == PCI_COMMAND_MEMORY) |
---|
520 | ? SYS_RES_MEMORY : SYS_RES_IOPORT); |
---|
521 | sc->rgd = ((m1 == PCI_COMMAND_MEMORY) |
---|
522 | ? FXP_PCI_MMBA : FXP_PCI_IOBA); |
---|
523 | sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, |
---|
524 | 0, ~0, 1, RF_ACTIVE); |
---|
525 | } |
---|
526 | if (sc->mem == NULL && (val & m2)) { |
---|
527 | sc->rtp = ((m2 == PCI_COMMAND_MEMORY) |
---|
528 | ? SYS_RES_MEMORY : SYS_RES_IOPORT); |
---|
529 | sc->rgd = ((m2 == PCI_COMMAND_MEMORY) |
---|
530 | ? FXP_PCI_MMBA : FXP_PCI_IOBA); |
---|
531 | sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, |
---|
532 | 0, ~0, 1, RF_ACTIVE); |
---|
533 | } |
---|
534 | |
---|
535 | if (!sc->mem) { |
---|
536 | device_printf(dev, "could not map device registers\n"); |
---|
537 | error = ENXIO; |
---|
538 | goto fail; |
---|
539 | } |
---|
540 | if (fxp_is_verbose) { |
---|
541 | device_printf(dev, "using %s space register mapping\n", |
---|
542 | sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); |
---|
543 | } |
---|
544 | |
---|
545 | sc->sc_st = rman_get_bustag(sc->mem); |
---|
546 | sc->sc_sh = rman_get_bushandle(sc->mem); |
---|
547 | |
---|
548 | /* |
---|
549 | * Allocate our interrupt. |
---|
550 | */ |
---|
551 | rid = 0; |
---|
552 | sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, |
---|
553 | RF_SHAREABLE | RF_ACTIVE); |
---|
554 | if (sc->irq == NULL) { |
---|
555 | device_printf(dev, "could not map interrupt\n"); |
---|
556 | error = ENXIO; |
---|
557 | goto fail; |
---|
558 | } |
---|
559 | |
---|
560 | error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, |
---|
561 | fxp_intr, sc, &sc->ih); |
---|
562 | if (error) { |
---|
563 | device_printf(dev, "could not setup irq\n"); |
---|
564 | goto fail; |
---|
565 | } |
---|
566 | #endif |
---|
567 | |
---|
568 | /* |
---|
569 | * get mapping and base address of registers |
---|
570 | */ |
---|
571 | pcib_conf_read16(sc->pci_signature, PCI_COMMAND,&val16); |
---|
572 | DBGLVL_PRINTK(4,"fxp_attach: PCI_COMMAND_read = 0x%x\n",val16); |
---|
573 | if((val16 & PCI_COMMAND_IO) != 0) { |
---|
574 | sc->pci_regs_are_io = TRUE; |
---|
575 | pcib_conf_read32(sc->pci_signature, |
---|
576 | PCI_BASE_ADDRESS_1, |
---|
577 | &val32); |
---|
578 | sc->pci_regs_base = val32 & PCI_BASE_ADDRESS_IO_MASK; |
---|
579 | } |
---|
580 | else { |
---|
581 | sc->pci_regs_are_io = FALSE; |
---|
582 | pcib_conf_read32(sc->pci_signature, |
---|
583 | PCI_BASE_ADDRESS_0, |
---|
584 | &val32); |
---|
585 | sc->pci_regs_base = val32 & PCI_BASE_ADDRESS_MEM_MASK; |
---|
586 | } |
---|
587 | DBGLVL_PRINTK(3,"fxp_attach: CSR registers are mapped in %s space" |
---|
588 | " at address 0x%x\n", |
---|
589 | sc->pci_regs_are_io ? "I/O" : "MEM", |
---|
590 | sc->pci_regs_base); |
---|
591 | |
---|
592 | /* |
---|
593 | * get interrupt level to be used |
---|
594 | */ |
---|
595 | pcib_conf_read8(sc->pci_signature, 60, &interrupt); |
---|
596 | DBGLVL_PRINTK(3,"fxp_attach: interrupt = 0x%x\n",interrupt); |
---|
597 | sc->irqInfo.name = (rtems_irq_symbolic_name)interrupt; |
---|
598 | /* |
---|
599 | * Set up interrupts |
---|
600 | */ |
---|
601 | sc->irqInfo.hdl = (rtems_irq_hdl)fxp_intr; |
---|
602 | sc->irqInfo.on = nopOn; |
---|
603 | sc->irqInfo.off = nopOn; |
---|
604 | sc->irqInfo.isOn = fxpIsOn; |
---|
605 | s = BSP_install_rtems_irq_handler (&sc->irqInfo); |
---|
606 | if (!s) |
---|
607 | rtems_panic ("Can't attach fxp interrupt handler for irq %d\n", |
---|
608 | sc->irqInfo.name); |
---|
609 | /* |
---|
610 | * Reset to a stable state. |
---|
611 | CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); |
---|
612 | */ |
---|
613 | CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); |
---|
614 | DELAY(10); |
---|
615 | |
---|
616 | sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, |
---|
617 | M_DEVBUF, M_NOWAIT); |
---|
618 | DBGLVL_PRINTK(3,"fxp_attach: sc->cbl_base = 0x%x\n",sc->cbl_base); |
---|
619 | if (sc->cbl_base == NULL) |
---|
620 | goto failmem; |
---|
621 | else |
---|
622 | memset(sc->cbl_base, 0, sizeof(struct fxp_cb_tx) * FXP_NTXCB); |
---|
623 | |
---|
624 | sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, |
---|
625 | M_NOWAIT); |
---|
626 | DBGLVL_PRINTK(3,"fxp_attach: sc->fxp_stats = 0x%x\n",sc->fxp_stats); |
---|
627 | if (sc->fxp_stats == NULL) |
---|
628 | goto failmem; |
---|
629 | else |
---|
630 | memset(sc->fxp_stats, 0, sizeof(struct fxp_stats)); |
---|
631 | |
---|
632 | sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT); |
---|
633 | DBGLVL_PRINTK(3,"fxp_attach: sc->mcsp = 0x%x\n",sc->mcsp); |
---|
634 | if (sc->mcsp == NULL) |
---|
635 | goto failmem; |
---|
636 | |
---|
637 | /* |
---|
638 | * Pre-allocate our receive buffers. |
---|
639 | */ |
---|
640 | for (i = 0; i < FXP_NRFABUFS; i++) { |
---|
641 | if (fxp_add_rfabuf(sc, NULL) != 0) { |
---|
642 | goto failmem; |
---|
643 | } |
---|
644 | } |
---|
645 | |
---|
646 | /* |
---|
647 | * Find out how large of an SEEPROM we have. |
---|
648 | */ |
---|
649 | DBGLVL_PRINTK(3,"fxp_attach: calling fxp_autosize_eeprom\n"); |
---|
650 | fxp_autosize_eeprom(sc); |
---|
651 | |
---|
652 | /* |
---|
653 | * Determine whether we must use the 503 serial interface. |
---|
654 | */ |
---|
655 | fxp_read_eeprom(sc, &data, 6, 1); |
---|
656 | if ((data & FXP_PHY_DEVICE_MASK) != 0 && |
---|
657 | (data & FXP_PHY_SERIAL_ONLY)) |
---|
658 | sc->flags |= FXP_FLAG_SERIAL_MEDIA; |
---|
659 | |
---|
660 | /* |
---|
661 | * Find out the basic controller type; we currently only |
---|
662 | * differentiate between a 82557 and greater. |
---|
663 | */ |
---|
664 | fxp_read_eeprom(sc, &data, 5, 1); |
---|
665 | if ((data >> 8) == 1) |
---|
666 | sc->chip = FXP_CHIP_82557; |
---|
667 | DBGLVL_PRINTK(3,"fxp_attach: sc->chip = %d\n",sc->chip); |
---|
668 | |
---|
669 | /* |
---|
670 | * Enable workarounds for certain chip revision deficiencies. |
---|
671 | * |
---|
672 | * Systems based on the ICH2/ICH2-M chip from Intel have a defect |
---|
673 | * where the chip can cause a PCI protocol violation if it receives |
---|
674 | * a CU_RESUME command when it is entering the IDLE state. The |
---|
675 | * workaround is to disable Dynamic Standby Mode, so the chip never |
---|
676 | * deasserts CLKRUN#, and always remains in an active state. |
---|
677 | * |
---|
678 | * See Intel 82801BA/82801BAM Specification Update, Errata #30. |
---|
679 | */ |
---|
680 | #ifdef NOTUSED |
---|
681 | i = pci_get_device(dev); |
---|
682 | #else |
---|
683 | pcib_conf_read16(sc->pci_signature,2,&dev_id); |
---|
684 | DBGLVL_PRINTK(3,"fxp_attach: device id = 0x%x\n",dev_id); |
---|
685 | #endif |
---|
686 | if (dev_id == 0x2449 || (dev_id > 0x1030 && dev_id < 0x1039)) { |
---|
687 | device_printf(dev, "*** See Intel 82801BA/82801BAM Specification Update, Errata #30. ***\n"); |
---|
688 | fxp_read_eeprom(sc, &data, 10, 1); |
---|
689 | if (data & 0x02) { /* STB enable */ |
---|
690 | u_int16_t cksum; |
---|
691 | int i; |
---|
692 | |
---|
693 | device_printf(dev, |
---|
694 | "*** DISABLING DYNAMIC STANDBY MODE IN EEPROM ***\n"); |
---|
695 | data &= ~0x02; |
---|
696 | fxp_write_eeprom(sc, &data, 10, 1); |
---|
697 | device_printf(dev, "New EEPROM ID: 0x%x\n", data); |
---|
698 | cksum = 0; |
---|
699 | for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { |
---|
700 | fxp_read_eeprom(sc, &data, i, 1); |
---|
701 | cksum += data; |
---|
702 | } |
---|
703 | i = (1 << sc->eeprom_size) - 1; |
---|
704 | cksum = 0xBABA - cksum; |
---|
705 | fxp_read_eeprom(sc, &data, i, 1); |
---|
706 | fxp_write_eeprom(sc, &cksum, i, 1); |
---|
707 | device_printf(dev, |
---|
708 | "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", |
---|
709 | i, data, cksum); |
---|
710 | /* |
---|
711 | * We need to do a full PCI reset here. A software |
---|
712 | * reset to the port doesn't cut it, but let's try |
---|
713 | * anyway. |
---|
714 | */ |
---|
715 | CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); |
---|
716 | DELAY(50); |
---|
717 | device_printf(dev, |
---|
718 | "*** PLEASE REBOOT THE SYSTEM NOW FOR CORRECT OPERATION ***\n"); |
---|
719 | #if 1 |
---|
720 | /* |
---|
721 | * If the user elects to continue, try the software |
---|
722 | * workaround, as it is better than nothing. |
---|
723 | */ |
---|
724 | sc->flags |= FXP_FLAG_CU_RESUME_BUG; |
---|
725 | #endif |
---|
726 | } |
---|
727 | } |
---|
728 | |
---|
729 | /* |
---|
730 | * If we are not a 82557 chip, we can enable extended features. |
---|
731 | */ |
---|
732 | if (sc->chip != FXP_CHIP_82557) { |
---|
733 | u_int8_t tmp_val; |
---|
734 | /* |
---|
735 | * If MWI is enabled in the PCI configuration, and there |
---|
736 | * is a valid cacheline size (8 or 16 dwords), then tell |
---|
737 | * the board to turn on MWI. |
---|
738 | */ |
---|
739 | pcib_conf_read8(sc->pci_signature, |
---|
740 | PCI_CACHE_LINE_SIZE,&tmp_val); |
---|
741 | DBGLVL_PRINTK(3,"fxp_attach: CACHE_LINE_SIZE = %d\n",tmp_val); |
---|
742 | if (val16 & PCI_COMMAND_MEMORY && |
---|
743 | tmp_val != 0) |
---|
744 | sc->flags |= FXP_FLAG_MWI_ENABLE; |
---|
745 | |
---|
746 | /* turn on the extended TxCB feature */ |
---|
747 | sc->flags |= FXP_FLAG_EXT_TXCB; |
---|
748 | |
---|
749 | /* enable reception of long frames for VLAN */ |
---|
750 | sc->flags |= FXP_FLAG_LONG_PKT_EN; |
---|
751 | DBGLVL_PRINTK(3,"fxp_attach: sc->flags = 0x%x\n", |
---|
752 | sc->flags); |
---|
753 | } |
---|
754 | |
---|
755 | /* |
---|
756 | * Read MAC address. |
---|
757 | */ |
---|
758 | fxp_read_eeprom(sc, (u_int16_t*)sc->arpcom.ac_enaddr, 0, 3); |
---|
759 | if (fxp_is_verbose) { |
---|
760 | device_printf(dev, "Ethernet address %x:%x:%x:%x:%x:%x %s \n", |
---|
761 | ((u_int8_t*)sc->arpcom.ac_enaddr)[0], |
---|
762 | ((u_int8_t*)sc->arpcom.ac_enaddr)[1], |
---|
763 | ((u_int8_t*)sc->arpcom.ac_enaddr)[2], |
---|
764 | ((u_int8_t*)sc->arpcom.ac_enaddr)[3], |
---|
765 | ((u_int8_t*)sc->arpcom.ac_enaddr)[4], |
---|
766 | ((u_int8_t*)sc->arpcom.ac_enaddr)[5], |
---|
767 | sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); |
---|
768 | device_printf(dev, "PCI IDs: 0x%x 0x%x 0x%x 0x%x 0x%x\n", |
---|
769 | pci_get_vendor(sc), pci_get_device(sc), |
---|
770 | pci_get_subvendor(sc), pci_get_subdevice(sc), |
---|
771 | pci_get_revid(sc)); |
---|
772 | device_printf(dev, "Chip Type: %d\n", sc->chip); |
---|
773 | } |
---|
774 | |
---|
775 | #ifdef NOTUSED /* do not set up interface at all... */ |
---|
776 | /* |
---|
777 | * If this is only a 10Mbps device, then there is no MII, and |
---|
778 | * the PHY will use a serial interface instead. |
---|
779 | * |
---|
780 | * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter |
---|
781 | * doesn't have a programming interface of any sort. The |
---|
782 | * media is sensed automatically based on how the link partner |
---|
783 | * is configured. This is, in essence, manual configuration. |
---|
784 | */ |
---|
785 | if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { |
---|
786 | ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, |
---|
787 | fxp_serial_ifmedia_sts); |
---|
788 | ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); |
---|
789 | ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); |
---|
790 | } else { |
---|
791 | if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, |
---|
792 | fxp_ifmedia_sts)) { |
---|
793 | device_printf(dev, "MII without any PHY!\n"); |
---|
794 | error = ENXIO; |
---|
795 | goto fail; |
---|
796 | } |
---|
797 | } |
---|
798 | #endif |
---|
799 | if (config->mtu) |
---|
800 | mtu = config->mtu; |
---|
801 | else |
---|
802 | mtu = ETHERMTU; |
---|
803 | |
---|
804 | ifp->if_softc = sc; |
---|
805 | ifp->if_unit = unitNumber; |
---|
806 | ifp->if_name = unitName; |
---|
807 | ifp->if_mtu = mtu; |
---|
808 | ifp->if_baudrate = 100000000; |
---|
809 | ifp->if_init = fxp_init; |
---|
810 | ifp->if_ioctl = fxp_ioctl; |
---|
811 | ifp->if_start = fxp_start; |
---|
812 | ifp->if_output = ether_output; |
---|
813 | ifp->if_watchdog = fxp_watchdog; |
---|
814 | ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX /*| IFF_MULTICAST*/; |
---|
815 | if (ifp->if_snd.ifq_maxlen == 0) |
---|
816 | ifp->if_snd.ifq_maxlen = ifqmaxlen; |
---|
817 | |
---|
818 | /* |
---|
819 | * Attach the interface. |
---|
820 | */ |
---|
821 | DBGLVL_PRINTK(3,"fxp_attach: calling if_attach\n"); |
---|
822 | if_attach (ifp); |
---|
823 | DBGLVL_PRINTK(3,"fxp_attach: calling ether_if_attach\n"); |
---|
824 | ether_ifattach(ifp); |
---|
825 | DBGLVL_PRINTK(3,"fxp_attach: return from ether_if_attach\n"); |
---|
826 | |
---|
827 | #ifdef NOTUSED |
---|
828 | /* |
---|
829 | * Tell the upper layer(s) we support long frames. |
---|
830 | */ |
---|
831 | ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); |
---|
832 | #endif |
---|
833 | /* |
---|
834 | * Let the system queue as many packets as we have available |
---|
835 | * TX descriptors. |
---|
836 | */ |
---|
837 | ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; |
---|
838 | |
---|
839 | splx(s); |
---|
840 | return (0); |
---|
841 | |
---|
842 | failmem: |
---|
843 | device_printf(dev, "Failed to malloc memory\n"); |
---|
844 | error = ENOMEM; |
---|
845 | #ifdef NOTUSED |
---|
846 | fail: |
---|
847 | #endif |
---|
848 | splx(s); |
---|
849 | fxp_release(sc); |
---|
850 | return (error); |
---|
851 | } |
---|
852 | |
---|
853 | /* |
---|
854 | * release all resources |
---|
855 | */ |
---|
856 | static void |
---|
857 | fxp_release(struct fxp_softc *sc) |
---|
858 | { |
---|
859 | |
---|
860 | #ifdef NOTUSED |
---|
861 | bus_generic_detach(sc->dev); |
---|
862 | if (sc->miibus) |
---|
863 | device_delete_child(sc->dev, sc->miibus); |
---|
864 | #endif |
---|
865 | if (sc->cbl_base) |
---|
866 | free(sc->cbl_base, M_DEVBUF); |
---|
867 | if (sc->fxp_stats) |
---|
868 | free(sc->fxp_stats, M_DEVBUF); |
---|
869 | if (sc->mcsp) |
---|
870 | free(sc->mcsp, M_DEVBUF); |
---|
871 | if (sc->rfa_headm) |
---|
872 | m_freem(sc->rfa_headm); |
---|
873 | |
---|
874 | #ifdef NOTUSED |
---|
875 | if (sc->ih) |
---|
876 | bus_teardown_intr(sc->dev, sc->irq, sc->ih); |
---|
877 | if (sc->irq) |
---|
878 | bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); |
---|
879 | if (sc->mem) |
---|
880 | bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); |
---|
881 | mtx_destroy(&sc->sc_mtx); |
---|
882 | #endif |
---|
883 | } |
---|
884 | |
---|
885 | #if NOTUSED |
---|
886 | /* |
---|
887 | * Detach interface. |
---|
888 | */ |
---|
889 | static int |
---|
890 | fxp_detach(device_t dev) |
---|
891 | { |
---|
892 | struct fxp_softc *sc = device_get_softc(dev); |
---|
893 | int s; |
---|
894 | |
---|
895 | /* disable interrupts */ |
---|
896 | CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); |
---|
897 | |
---|
898 | s = splimp(); |
---|
899 | |
---|
900 | /* |
---|
901 | * Stop DMA and drop transmit queue. |
---|
902 | */ |
---|
903 | fxp_stop(sc); |
---|
904 | |
---|
905 | /* |
---|
906 | * Close down routes etc. |
---|
907 | */ |
---|
908 | ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED); |
---|
909 | |
---|
910 | /* |
---|
911 | * Free all media structures. |
---|
912 | */ |
---|
913 | ifmedia_removeall(&sc->sc_media); |
---|
914 | |
---|
915 | splx(s); |
---|
916 | |
---|
917 | /* Release our allocated resources. */ |
---|
918 | fxp_release(sc); |
---|
919 | |
---|
920 | return (0); |
---|
921 | } |
---|
922 | |
---|
923 | /* |
---|
924 | * Device shutdown routine. Called at system shutdown after sync. The |
---|
925 | * main purpose of this routine is to shut off receiver DMA so that |
---|
926 | * kernel memory doesn't get clobbered during warmboot. |
---|
927 | */ |
---|
928 | static int |
---|
929 | fxp_shutdown(device_t dev) |
---|
930 | { |
---|
931 | /* |
---|
932 | * Make sure that DMA is disabled prior to reboot. Not doing |
---|
933 | * do could allow DMA to corrupt kernel memory during the |
---|
934 | * reboot before the driver initializes. |
---|
935 | */ |
---|
936 | fxp_stop((struct fxp_softc *) device_get_softc(dev)); |
---|
937 | return (0); |
---|
938 | } |
---|
939 | #endif |
---|
940 | |
---|
941 | /* |
---|
942 | * Show interface statistics |
---|
943 | */ |
---|
944 | static void |
---|
945 | fxp_stats(struct fxp_softc *sc) |
---|
946 | { |
---|
947 | struct ifnet *ifp = &sc->sc_if; |
---|
948 | |
---|
949 | printf (" Output packets:%-8lu", ifp->if_opackets); |
---|
950 | printf (" Collisions:%-8lu", ifp->if_collisions); |
---|
951 | printf (" Output errors:%-8lu\n", ifp->if_oerrors); |
---|
952 | printf (" Input packets:%-8lu", ifp->if_ipackets); |
---|
953 | printf (" Input errors:%-8lu\n", ifp->if_ierrors); |
---|
954 | } |
---|
955 | |
---|
956 | static void |
---|
957 | fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) |
---|
958 | { |
---|
959 | u_int16_t reg; |
---|
960 | int x; |
---|
961 | |
---|
962 | /* |
---|
963 | * Shift in data. |
---|
964 | */ |
---|
965 | for (x = 1 << (length - 1); x; x >>= 1) { |
---|
966 | if (data & x) |
---|
967 | reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; |
---|
968 | else |
---|
969 | reg = FXP_EEPROM_EECS; |
---|
970 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); |
---|
971 | DELAY(1); |
---|
972 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); |
---|
973 | DELAY(1); |
---|
974 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); |
---|
975 | DELAY(1); |
---|
976 | } |
---|
977 | } |
---|
978 | |
---|
979 | /* |
---|
980 | * Read from the serial EEPROM. Basically, you manually shift in |
---|
981 | * the read opcode (one bit at a time) and then shift in the address, |
---|
982 | * and then you shift out the data (all of this one bit at a time). |
---|
983 | * The word size is 16 bits, so you have to provide the address for |
---|
984 | * every 16 bits of data. |
---|
985 | */ |
---|
986 | static u_int16_t |
---|
987 | fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) |
---|
988 | { |
---|
989 | u_int16_t reg, data; |
---|
990 | int x; |
---|
991 | |
---|
992 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); |
---|
993 | /* |
---|
994 | * Shift in read opcode. |
---|
995 | */ |
---|
996 | fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); |
---|
997 | /* |
---|
998 | * Shift in address. |
---|
999 | */ |
---|
1000 | data = 0; |
---|
1001 | for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { |
---|
1002 | if (offset & x) |
---|
1003 | reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; |
---|
1004 | else |
---|
1005 | reg = FXP_EEPROM_EECS; |
---|
1006 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); |
---|
1007 | DELAY(1); |
---|
1008 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); |
---|
1009 | DELAY(1); |
---|
1010 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); |
---|
1011 | DELAY(1); |
---|
1012 | reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; |
---|
1013 | data++; |
---|
1014 | if (autosize && reg == 0) { |
---|
1015 | sc->eeprom_size = data; |
---|
1016 | break; |
---|
1017 | } |
---|
1018 | } |
---|
1019 | /* |
---|
1020 | * Shift out data. |
---|
1021 | */ |
---|
1022 | data = 0; |
---|
1023 | reg = FXP_EEPROM_EECS; |
---|
1024 | for (x = 1 << 15; x; x >>= 1) { |
---|
1025 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); |
---|
1026 | DELAY(1); |
---|
1027 | if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) |
---|
1028 | data |= x; |
---|
1029 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); |
---|
1030 | DELAY(1); |
---|
1031 | } |
---|
1032 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); |
---|
1033 | DELAY(1); |
---|
1034 | |
---|
1035 | return (data); |
---|
1036 | } |
---|
1037 | |
---|
1038 | static void |
---|
1039 | fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) |
---|
1040 | { |
---|
1041 | int i; |
---|
1042 | |
---|
1043 | /* |
---|
1044 | * Erase/write enable. |
---|
1045 | */ |
---|
1046 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); |
---|
1047 | fxp_eeprom_shiftin(sc, 0x4, 3); |
---|
1048 | fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); |
---|
1049 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); |
---|
1050 | DELAY(1); |
---|
1051 | /* |
---|
1052 | * Shift in write opcode, address, data. |
---|
1053 | */ |
---|
1054 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); |
---|
1055 | fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); |
---|
1056 | fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); |
---|
1057 | fxp_eeprom_shiftin(sc, data, 16); |
---|
1058 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); |
---|
1059 | DELAY(1); |
---|
1060 | /* |
---|
1061 | * Wait for EEPROM to finish up. |
---|
1062 | */ |
---|
1063 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); |
---|
1064 | DELAY(1); |
---|
1065 | for (i = 0; i < 1000; i++) { |
---|
1066 | if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) |
---|
1067 | break; |
---|
1068 | DELAY(50); |
---|
1069 | } |
---|
1070 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); |
---|
1071 | DELAY(1); |
---|
1072 | /* |
---|
1073 | * Erase/write disable. |
---|
1074 | */ |
---|
1075 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); |
---|
1076 | fxp_eeprom_shiftin(sc, 0x4, 3); |
---|
1077 | fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); |
---|
1078 | CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); |
---|
1079 | DELAY(1); |
---|
1080 | } |
---|
1081 | |
---|
1082 | /* |
---|
1083 | * From NetBSD: |
---|
1084 | * |
---|
1085 | * Figure out EEPROM size. |
---|
1086 | * |
---|
1087 | * 559's can have either 64-word or 256-word EEPROMs, the 558 |
---|
1088 | * datasheet only talks about 64-word EEPROMs, and the 557 datasheet |
---|
1089 | * talks about the existance of 16 to 256 word EEPROMs. |
---|
1090 | * |
---|
1091 | * The only known sizes are 64 and 256, where the 256 version is used |
---|
1092 | * by CardBus cards to store CIS information. |
---|
1093 | * |
---|
1094 | * The address is shifted in msb-to-lsb, and after the last |
---|
1095 | * address-bit the EEPROM is supposed to output a `dummy zero' bit, |
---|
1096 | * after which follows the actual data. We try to detect this zero, by |
---|
1097 | * probing the data-out bit in the EEPROM control register just after |
---|
1098 | * having shifted in a bit. If the bit is zero, we assume we've |
---|
1099 | * shifted enough address bits. The data-out should be tri-state, |
---|
1100 | * before this, which should translate to a logical one. |
---|
1101 | */ |
---|
1102 | static void |
---|
1103 | fxp_autosize_eeprom(struct fxp_softc *sc) |
---|
1104 | { |
---|
1105 | |
---|
1106 | /* guess maximum size of 256 words */ |
---|
1107 | sc->eeprom_size = 8; |
---|
1108 | |
---|
1109 | /* autosize */ |
---|
1110 | (void) fxp_eeprom_getword(sc, 0, 1); |
---|
1111 | } |
---|
1112 | |
---|
1113 | static void |
---|
1114 | fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) |
---|
1115 | { |
---|
1116 | int i; |
---|
1117 | |
---|
1118 | for (i = 0; i < words; i++) { |
---|
1119 | data[i] = fxp_eeprom_getword(sc, offset + i, 0); |
---|
1120 | DBGLVL_PRINTK(4,"fxp_eeprom_read(off=0x%x)=0x%x\n", |
---|
1121 | offset+i,data[i]); |
---|
1122 | } |
---|
1123 | } |
---|
1124 | |
---|
1125 | static void |
---|
1126 | fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) |
---|
1127 | { |
---|
1128 | int i; |
---|
1129 | |
---|
1130 | for (i = 0; i < words; i++) |
---|
1131 | fxp_eeprom_putword(sc, offset + i, data[i]); |
---|
1132 | DBGLVL_PRINTK(4,"fxp_eeprom_write(off=0x%x,0x%x)\n", |
---|
1133 | offset+i,data[i]); |
---|
1134 | } |
---|
1135 | |
---|
1136 | /* |
---|
1137 | * Start packet transmission on the interface. |
---|
1138 | */ |
---|
1139 | static void |
---|
1140 | fxp_start(struct ifnet *ifp) |
---|
1141 | { |
---|
1142 | struct fxp_softc *sc = ifp->if_softc; |
---|
1143 | struct fxp_cb_tx *txp; |
---|
1144 | |
---|
1145 | DBGLVL_PRINTK(3,"fxp_start called\n"); |
---|
1146 | |
---|
1147 | /* |
---|
1148 | * See if we need to suspend xmit until the multicast filter |
---|
1149 | * has been reprogrammed (which can only be done at the head |
---|
1150 | * of the command chain). |
---|
1151 | */ |
---|
1152 | if (sc->need_mcsetup) { |
---|
1153 | return; |
---|
1154 | } |
---|
1155 | |
---|
1156 | txp = NULL; |
---|
1157 | |
---|
1158 | /* |
---|
1159 | * We're finished if there is nothing more to add to the list or if |
---|
1160 | * we're all filled up with buffers to transmit. |
---|
1161 | * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add |
---|
1162 | * a NOP command when needed. |
---|
1163 | */ |
---|
1164 | while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { |
---|
1165 | struct mbuf *m, *mb_head; |
---|
1166 | int segment; |
---|
1167 | |
---|
1168 | /* |
---|
1169 | * Grab a packet to transmit. |
---|
1170 | */ |
---|
1171 | IF_DEQUEUE(&ifp->if_snd, mb_head); |
---|
1172 | |
---|
1173 | /* |
---|
1174 | * Get pointer to next available tx desc. |
---|
1175 | */ |
---|
1176 | txp = sc->cbl_last->next; |
---|
1177 | |
---|
1178 | /* |
---|
1179 | * Go through each of the mbufs in the chain and initialize |
---|
1180 | * the transmit buffer descriptors with the physical address |
---|
1181 | * and size of the mbuf. |
---|
1182 | */ |
---|
1183 | tbdinit: |
---|
1184 | for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { |
---|
1185 | if (m->m_len != 0) { |
---|
1186 | if (segment == FXP_NTXSEG) |
---|
1187 | break; |
---|
1188 | txp->tbd[segment].tb_addr = |
---|
1189 | vtophys(mtod(m, vm_offset_t)); |
---|
1190 | txp->tbd[segment].tb_size = m->m_len; |
---|
1191 | segment++; |
---|
1192 | } |
---|
1193 | } |
---|
1194 | if (m != NULL) { |
---|
1195 | struct mbuf *mn; |
---|
1196 | |
---|
1197 | /* |
---|
1198 | * We ran out of segments. We have to recopy this |
---|
1199 | * mbuf chain first. Bail out if we can't get the |
---|
1200 | * new buffers. |
---|
1201 | */ |
---|
1202 | MGETHDR(mn, M_DONTWAIT, MT_DATA); |
---|
1203 | if (mn == NULL) { |
---|
1204 | m_freem(mb_head); |
---|
1205 | break; |
---|
1206 | } |
---|
1207 | if (mb_head->m_pkthdr.len > MHLEN) { |
---|
1208 | MCLGET(mn, M_DONTWAIT); |
---|
1209 | if ((mn->m_flags & M_EXT) == 0) { |
---|
1210 | m_freem(mn); |
---|
1211 | m_freem(mb_head); |
---|
1212 | break; |
---|
1213 | } |
---|
1214 | } |
---|
1215 | m_copydata(mb_head, 0, mb_head->m_pkthdr.len, |
---|
1216 | mtod(mn, caddr_t)); |
---|
1217 | mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; |
---|
1218 | m_freem(mb_head); |
---|
1219 | mb_head = mn; |
---|
1220 | goto tbdinit; |
---|
1221 | } |
---|
1222 | |
---|
1223 | txp->tbd_number = segment; |
---|
1224 | txp->mb_head = mb_head; |
---|
1225 | txp->cb_status = 0; |
---|
1226 | if (sc->tx_queued != FXP_CXINT_THRESH - 1) { |
---|
1227 | txp->cb_command = |
---|
1228 | FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | |
---|
1229 | FXP_CB_COMMAND_S; |
---|
1230 | } else { |
---|
1231 | txp->cb_command = |
---|
1232 | FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | |
---|
1233 | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; |
---|
1234 | /* |
---|
1235 | * Set a 5 second timer just in case we don't hear |
---|
1236 | * from the card again. |
---|
1237 | */ |
---|
1238 | ifp->if_timer = 5; |
---|
1239 | } |
---|
1240 | txp->tx_threshold = tx_threshold; |
---|
1241 | |
---|
1242 | /* |
---|
1243 | * Advance the end of list forward. |
---|
1244 | */ |
---|
1245 | |
---|
1246 | #ifdef __alpha__ |
---|
1247 | /* |
---|
1248 | * On platforms which can't access memory in 16-bit |
---|
1249 | * granularities, we must prevent the card from DMA'ing |
---|
1250 | * up the status while we update the command field. |
---|
1251 | * This could cause us to overwrite the completion status. |
---|
1252 | */ |
---|
1253 | atomic_clear_short(&sc->cbl_last->cb_command, |
---|
1254 | FXP_CB_COMMAND_S); |
---|
1255 | #else |
---|
1256 | sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; |
---|
1257 | #endif /*__alpha__*/ |
---|
1258 | sc->cbl_last = txp; |
---|
1259 | |
---|
1260 | /* |
---|
1261 | * Advance the beginning of the list forward if there are |
---|
1262 | * no other packets queued (when nothing is queued, cbl_first |
---|
1263 | * sits on the last TxCB that was sent out). |
---|
1264 | */ |
---|
1265 | if (sc->tx_queued == 0) |
---|
1266 | sc->cbl_first = txp; |
---|
1267 | |
---|
1268 | sc->tx_queued++; |
---|
1269 | |
---|
1270 | #ifdef NOTUSED |
---|
1271 | /* |
---|
1272 | * Pass packet to bpf if there is a listener. |
---|
1273 | */ |
---|
1274 | if (ifp->if_bpf) |
---|
1275 | bpf_mtap(ifp, mb_head); |
---|
1276 | #endif |
---|
1277 | } |
---|
1278 | |
---|
1279 | /* |
---|
1280 | * We're finished. If we added to the list, issue a RESUME to get DMA |
---|
1281 | * going again if suspended. |
---|
1282 | */ |
---|
1283 | if (txp != NULL) { |
---|
1284 | fxp_scb_wait(sc); |
---|
1285 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); |
---|
1286 | } |
---|
1287 | } |
---|
1288 | |
---|
1289 | /* |
---|
1290 | * Process interface interrupts. |
---|
1291 | */ |
---|
1292 | static rtems_isr fxp_intr(rtems_vector_number v) |
---|
1293 | { |
---|
1294 | /* |
---|
1295 | * FIXME: currently only works with one interface... |
---|
1296 | */ |
---|
1297 | struct fxp_softc *sc = &(fxp_softc[0]); |
---|
1298 | |
---|
1299 | /* |
---|
1300 | * disable interrupts |
---|
1301 | */ |
---|
1302 | CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); |
---|
1303 | /* |
---|
1304 | * send event to deamon |
---|
1305 | */ |
---|
1306 | rtems_event_send (sc->daemonTid, INTERRUPT_EVENT); |
---|
1307 | } |
---|
1308 | |
---|
1309 | static void fxp_daemon(void *xsc) |
---|
1310 | { |
---|
1311 | struct fxp_softc *sc = xsc; |
---|
1312 | struct ifnet *ifp = &sc->sc_if; |
---|
1313 | u_int8_t statack; |
---|
1314 | rtems_event_set events; |
---|
1315 | rtems_interrupt_level level; |
---|
1316 | |
---|
1317 | #ifdef NOTUSED |
---|
1318 | if (sc->suspended) { |
---|
1319 | return; |
---|
1320 | } |
---|
1321 | #endif |
---|
1322 | for (;;) { |
---|
1323 | |
---|
1324 | DBGLVL_PRINTK(4,"fxp_daemon waiting for event\n"); |
---|
1325 | /* |
---|
1326 | * wait for event to receive from interrupt function |
---|
1327 | */ |
---|
1328 | rtems_bsdnet_event_receive (INTERRUPT_EVENT, |
---|
1329 | RTEMS_WAIT|RTEMS_EVENT_ANY, |
---|
1330 | RTEMS_NO_TIMEOUT, |
---|
1331 | &events); |
---|
1332 | while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { |
---|
1333 | DBGLVL_PRINTK(4,"fxp_daemon: processing event, statack = 0x%x\n", |
---|
1334 | statack); |
---|
1335 | #ifdef NOTUSED |
---|
1336 | /* |
---|
1337 | * It should not be possible to have all bits set; the |
---|
1338 | * FXP_SCB_INTR_SWI bit always returns 0 on a read. If |
---|
1339 | * all bits are set, this may indicate that the card has |
---|
1340 | * been physically ejected, so ignore it. |
---|
1341 | */ |
---|
1342 | if (statack == 0xff) |
---|
1343 | return; |
---|
1344 | #endif |
---|
1345 | |
---|
1346 | /* |
---|
1347 | * First ACK all the interrupts in this pass. |
---|
1348 | */ |
---|
1349 | CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); |
---|
1350 | |
---|
1351 | /* |
---|
1352 | * Free any finished transmit mbuf chains. |
---|
1353 | * |
---|
1354 | * Handle the CNA event likt a CXTNO event. It used to |
---|
1355 | * be that this event (control unit not ready) was not |
---|
1356 | * encountered, but it is now with the SMPng modifications. |
---|
1357 | * The exact sequence of events that occur when the interface |
---|
1358 | * is brought up are different now, and if this event |
---|
1359 | * goes unhandled, the configuration/rxfilter setup sequence |
---|
1360 | * can stall for several seconds. The result is that no |
---|
1361 | * packets go out onto the wire for about 5 to 10 seconds |
---|
1362 | * after the interface is ifconfig'ed for the first time. |
---|
1363 | */ |
---|
1364 | if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { |
---|
1365 | struct fxp_cb_tx *txp; |
---|
1366 | |
---|
1367 | for (txp = sc->cbl_first; sc->tx_queued && |
---|
1368 | (txp->cb_status & FXP_CB_STATUS_C) != 0; |
---|
1369 | txp = txp->next) { |
---|
1370 | if (txp->mb_head != NULL) { |
---|
1371 | m_freem(txp->mb_head); |
---|
1372 | txp->mb_head = NULL; |
---|
1373 | } |
---|
1374 | sc->tx_queued--; |
---|
1375 | } |
---|
1376 | sc->cbl_first = txp; |
---|
1377 | ifp->if_timer = 0; |
---|
1378 | if (sc->tx_queued == 0) { |
---|
1379 | if (sc->need_mcsetup) |
---|
1380 | fxp_mc_setup(sc); |
---|
1381 | } |
---|
1382 | /* |
---|
1383 | * Try to start more packets transmitting. |
---|
1384 | */ |
---|
1385 | if (ifp->if_snd.ifq_head != NULL) |
---|
1386 | fxp_start(ifp); |
---|
1387 | } |
---|
1388 | /* |
---|
1389 | * Process receiver interrupts. If a no-resource (RNR) |
---|
1390 | * condition exists, get whatever packets we can and |
---|
1391 | * re-start the receiver. |
---|
1392 | */ |
---|
1393 | if (statack & (FXP_SCB_STATACK_FR | FXP_SCB_STATACK_RNR)) { |
---|
1394 | struct mbuf *m; |
---|
1395 | struct fxp_rfa *rfa; |
---|
1396 | rcvloop: |
---|
1397 | m = sc->rfa_headm; |
---|
1398 | rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + |
---|
1399 | RFA_ALIGNMENT_FUDGE); |
---|
1400 | |
---|
1401 | if (rfa->rfa_status & FXP_RFA_STATUS_C) { |
---|
1402 | /* |
---|
1403 | * Remove first packet from the chain. |
---|
1404 | */ |
---|
1405 | sc->rfa_headm = m->m_next; |
---|
1406 | m->m_next = NULL; |
---|
1407 | |
---|
1408 | /* |
---|
1409 | * Add a new buffer to the receive chain. |
---|
1410 | * If this fails, the old buffer is recycled |
---|
1411 | * instead. |
---|
1412 | */ |
---|
1413 | if (fxp_add_rfabuf(sc, m) == 0) { |
---|
1414 | struct ether_header *eh; |
---|
1415 | int total_len; |
---|
1416 | |
---|
1417 | total_len = rfa->actual_size & |
---|
1418 | (MCLBYTES - 1); |
---|
1419 | if (total_len < |
---|
1420 | sizeof(struct ether_header)) { |
---|
1421 | m_freem(m); |
---|
1422 | goto rcvloop; |
---|
1423 | } |
---|
1424 | |
---|
1425 | /* |
---|
1426 | * Drop the packet if it has CRC |
---|
1427 | * errors. This test is only needed |
---|
1428 | * when doing 802.1q VLAN on the 82557 |
---|
1429 | * chip. |
---|
1430 | */ |
---|
1431 | if (rfa->rfa_status & |
---|
1432 | FXP_RFA_STATUS_CRC) { |
---|
1433 | m_freem(m); |
---|
1434 | goto rcvloop; |
---|
1435 | } |
---|
1436 | |
---|
1437 | m->m_pkthdr.rcvif = ifp; |
---|
1438 | m->m_pkthdr.len = m->m_len = total_len; |
---|
1439 | eh = mtod(m, struct ether_header *); |
---|
1440 | m->m_data += |
---|
1441 | sizeof(struct ether_header); |
---|
1442 | m->m_len -= |
---|
1443 | sizeof(struct ether_header); |
---|
1444 | m->m_pkthdr.len = m->m_len; |
---|
1445 | ether_input(ifp, eh, m); |
---|
1446 | } |
---|
1447 | goto rcvloop; |
---|
1448 | } |
---|
1449 | if (statack & FXP_SCB_STATACK_RNR) { |
---|
1450 | fxp_scb_wait(sc); |
---|
1451 | CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, |
---|
1452 | vtophys(sc->rfa_headm->m_ext.ext_buf) + |
---|
1453 | RFA_ALIGNMENT_FUDGE); |
---|
1454 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); |
---|
1455 | } |
---|
1456 | } |
---|
1457 | } |
---|
1458 | /* |
---|
1459 | * reenable interrupts |
---|
1460 | */ |
---|
1461 | rtems_interrupt_disable (level); |
---|
1462 | CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,0); |
---|
1463 | rtems_interrupt_enable (level); |
---|
1464 | } |
---|
1465 | } |
---|
1466 | |
---|
1467 | /* |
---|
1468 | * Update packet in/out/collision statistics. The i82557 doesn't |
---|
1469 | * allow you to access these counters without doing a fairly |
---|
1470 | * expensive DMA to get _all_ of the statistics it maintains, so |
---|
1471 | * we do this operation here only once per second. The statistics |
---|
1472 | * counters in the kernel are updated from the previous dump-stats |
---|
1473 | * DMA and then a new dump-stats DMA is started. The on-chip |
---|
1474 | * counters are zeroed when the DMA completes. If we can't start |
---|
1475 | * the DMA immediately, we don't wait - we just prepare to read |
---|
1476 | * them again next time. |
---|
1477 | */ |
---|
1478 | static void |
---|
1479 | fxp_tick(void *xsc) |
---|
1480 | { |
---|
1481 | struct fxp_softc *sc = xsc; |
---|
1482 | struct ifnet *ifp = &sc->sc_if; |
---|
1483 | struct fxp_stats *sp = sc->fxp_stats; |
---|
1484 | struct fxp_cb_tx *txp; |
---|
1485 | int s; |
---|
1486 | |
---|
1487 | DBGLVL_PRINTK(4,"fxp_tick called\n"); |
---|
1488 | |
---|
1489 | ifp->if_opackets += sp->tx_good; |
---|
1490 | ifp->if_collisions += sp->tx_total_collisions; |
---|
1491 | if (sp->rx_good) { |
---|
1492 | ifp->if_ipackets += sp->rx_good; |
---|
1493 | sc->rx_idle_secs = 0; |
---|
1494 | } else { |
---|
1495 | /* |
---|
1496 | * Receiver's been idle for another second. |
---|
1497 | */ |
---|
1498 | sc->rx_idle_secs++; |
---|
1499 | } |
---|
1500 | ifp->if_ierrors += |
---|
1501 | sp->rx_crc_errors + |
---|
1502 | sp->rx_alignment_errors + |
---|
1503 | sp->rx_rnr_errors + |
---|
1504 | sp->rx_overrun_errors; |
---|
1505 | /* |
---|
1506 | * If any transmit underruns occured, bump up the transmit |
---|
1507 | * threshold by another 512 bytes (64 * 8). |
---|
1508 | */ |
---|
1509 | if (sp->tx_underruns) { |
---|
1510 | ifp->if_oerrors += sp->tx_underruns; |
---|
1511 | if (tx_threshold < 192) |
---|
1512 | tx_threshold += 64; |
---|
1513 | } |
---|
1514 | s = splimp(); |
---|
1515 | /* |
---|
1516 | * Release any xmit buffers that have completed DMA. This isn't |
---|
1517 | * strictly necessary to do here, but it's advantagous for mbufs |
---|
1518 | * with external storage to be released in a timely manner rather |
---|
1519 | * than being defered for a potentially long time. This limits |
---|
1520 | * the delay to a maximum of one second. |
---|
1521 | */ |
---|
1522 | for (txp = sc->cbl_first; sc->tx_queued && |
---|
1523 | (txp->cb_status & FXP_CB_STATUS_C) != 0; |
---|
1524 | txp = txp->next) { |
---|
1525 | if (txp->mb_head != NULL) { |
---|
1526 | m_freem(txp->mb_head); |
---|
1527 | txp->mb_head = NULL; |
---|
1528 | } |
---|
1529 | sc->tx_queued--; |
---|
1530 | } |
---|
1531 | sc->cbl_first = txp; |
---|
1532 | /* |
---|
1533 | * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, |
---|
1534 | * then assume the receiver has locked up and attempt to clear |
---|
1535 | * the condition by reprogramming the multicast filter. This is |
---|
1536 | * a work-around for a bug in the 82557 where the receiver locks |
---|
1537 | * up if it gets certain types of garbage in the syncronization |
---|
1538 | * bits prior to the packet header. This bug is supposed to only |
---|
1539 | * occur in 10Mbps mode, but has been seen to occur in 100Mbps |
---|
1540 | * mode as well (perhaps due to a 10/100 speed transition). |
---|
1541 | */ |
---|
1542 | if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { |
---|
1543 | sc->rx_idle_secs = 0; |
---|
1544 | fxp_mc_setup(sc); |
---|
1545 | } |
---|
1546 | /* |
---|
1547 | * If there is no pending command, start another stats |
---|
1548 | * dump. Otherwise punt for now. |
---|
1549 | */ |
---|
1550 | if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { |
---|
1551 | /* |
---|
1552 | * Start another stats dump. |
---|
1553 | */ |
---|
1554 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); |
---|
1555 | } else { |
---|
1556 | /* |
---|
1557 | * A previous command is still waiting to be accepted. |
---|
1558 | * Just zero our copy of the stats and wait for the |
---|
1559 | * next timer event to update them. |
---|
1560 | */ |
---|
1561 | sp->tx_good = 0; |
---|
1562 | sp->tx_underruns = 0; |
---|
1563 | sp->tx_total_collisions = 0; |
---|
1564 | |
---|
1565 | sp->rx_good = 0; |
---|
1566 | sp->rx_crc_errors = 0; |
---|
1567 | sp->rx_alignment_errors = 0; |
---|
1568 | sp->rx_rnr_errors = 0; |
---|
1569 | sp->rx_overrun_errors = 0; |
---|
1570 | } |
---|
1571 | #ifdef NOTUSED |
---|
1572 | if (sc->miibus != NULL) |
---|
1573 | mii_tick(device_get_softc(sc->miibus)); |
---|
1574 | #endif |
---|
1575 | splx(s); |
---|
1576 | /* |
---|
1577 | * Schedule another timeout one second from now. |
---|
1578 | */ |
---|
1579 | if (sc->stat_ch == fxp_timeout_running) { |
---|
1580 | timeout(fxp_tick, sc, hz); |
---|
1581 | } |
---|
1582 | else if (sc->stat_ch == fxp_timeout_stop_rq) { |
---|
1583 | sc->stat_ch = fxp_timeout_stopped; |
---|
1584 | } |
---|
1585 | } |
---|
1586 | |
---|
1587 | /* |
---|
1588 | * Stop the interface. Cancels the statistics updater and resets |
---|
1589 | * the interface. |
---|
1590 | */ |
---|
1591 | static void |
---|
1592 | fxp_stop(struct fxp_softc *sc) |
---|
1593 | { |
---|
1594 | struct ifnet *ifp = &sc->sc_if; |
---|
1595 | struct fxp_cb_tx *txp; |
---|
1596 | int i; |
---|
1597 | |
---|
1598 | DBGLVL_PRINTK(2,"fxp_stop called\n"); |
---|
1599 | |
---|
1600 | ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); |
---|
1601 | ifp->if_timer = 0; |
---|
1602 | |
---|
1603 | /* |
---|
1604 | * stop stats updater. |
---|
1605 | */ |
---|
1606 | if (sc->stat_ch == fxp_timeout_running) { |
---|
1607 | DBGLVL_PRINTK(3,"fxp_stop: trying to stop stat update tick\n"); |
---|
1608 | sc->stat_ch = fxp_timeout_stop_rq; |
---|
1609 | while(sc->stat_ch != fxp_timeout_stopped) { |
---|
1610 | rtems_bsdnet_semaphore_release(); |
---|
1611 | rtems_task_wake_after(fxp_ticksPerSecond); |
---|
1612 | rtems_bsdnet_semaphore_obtain(); |
---|
1613 | } |
---|
1614 | DBGLVL_PRINTK(3,"fxp_stop: stat update tick stopped\n"); |
---|
1615 | } |
---|
1616 | /* |
---|
1617 | * Issue software reset |
---|
1618 | */ |
---|
1619 | DBGLVL_PRINTK(3,"fxp_stop: issue software reset\n"); |
---|
1620 | CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); |
---|
1621 | DELAY(10); |
---|
1622 | |
---|
1623 | /* |
---|
1624 | * Release any xmit buffers. |
---|
1625 | */ |
---|
1626 | DBGLVL_PRINTK(3,"fxp_stop: releasing xmit buffers\n"); |
---|
1627 | txp = sc->cbl_base; |
---|
1628 | if (txp != NULL) { |
---|
1629 | for (i = 0; i < FXP_NTXCB; i++) { |
---|
1630 | if (txp[i].mb_head != NULL) { |
---|
1631 | m_freem(txp[i].mb_head); |
---|
1632 | txp[i].mb_head = NULL; |
---|
1633 | } |
---|
1634 | } |
---|
1635 | } |
---|
1636 | sc->tx_queued = 0; |
---|
1637 | |
---|
1638 | /* |
---|
1639 | * Free all the receive buffers then reallocate/reinitialize |
---|
1640 | */ |
---|
1641 | DBGLVL_PRINTK(3,"fxp_stop: free and reinit all receive buffers\n"); |
---|
1642 | if (sc->rfa_headm != NULL) |
---|
1643 | m_freem(sc->rfa_headm); |
---|
1644 | sc->rfa_headm = NULL; |
---|
1645 | sc->rfa_tailm = NULL; |
---|
1646 | for (i = 0; i < FXP_NRFABUFS; i++) { |
---|
1647 | if (fxp_add_rfabuf(sc, NULL) != 0) { |
---|
1648 | /* |
---|
1649 | * This "can't happen" - we're at splimp() |
---|
1650 | * and we just freed all the buffers we need |
---|
1651 | * above. |
---|
1652 | */ |
---|
1653 | panic("fxp_stop: no buffers!"); |
---|
1654 | } |
---|
1655 | } |
---|
1656 | DBGLVL_PRINTK(2,"fxp_stop: finished\n"); |
---|
1657 | } |
---|
1658 | |
---|
1659 | /* |
---|
1660 | * Watchdog/transmission transmit timeout handler. Called when a |
---|
1661 | * transmission is started on the interface, but no interrupt is |
---|
1662 | * received before the timeout. This usually indicates that the |
---|
1663 | * card has wedged for some reason. |
---|
1664 | */ |
---|
1665 | static void |
---|
1666 | fxp_watchdog(struct ifnet *ifp) |
---|
1667 | { |
---|
1668 | struct fxp_softc *sc = ifp->if_softc; |
---|
1669 | |
---|
1670 | device_printf(sc->dev, "device timeout\n"); |
---|
1671 | ifp->if_oerrors++; |
---|
1672 | |
---|
1673 | fxp_init(sc); |
---|
1674 | } |
---|
1675 | |
---|
1676 | static void |
---|
1677 | fxp_init(void *xsc) |
---|
1678 | { |
---|
1679 | struct fxp_softc *sc = xsc; |
---|
1680 | struct ifnet *ifp = &sc->sc_if; |
---|
1681 | struct fxp_cb_config *cbp; |
---|
1682 | struct fxp_cb_ias *cb_ias; |
---|
1683 | struct fxp_cb_tx *txp; |
---|
1684 | int i, prm, s; |
---|
1685 | |
---|
1686 | rtems_task_wake_after(100); |
---|
1687 | DBGLVL_PRINTK(2,"fxp_init called\n"); |
---|
1688 | |
---|
1689 | s = splimp(); |
---|
1690 | /* |
---|
1691 | * Cancel any pending I/O |
---|
1692 | */ |
---|
1693 | fxp_stop(sc); |
---|
1694 | |
---|
1695 | prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; |
---|
1696 | |
---|
1697 | DBGLVL_PRINTK(5,"fxp_init: Initializing base of CBL and RFA memory\n"); |
---|
1698 | /* |
---|
1699 | * Initialize base of CBL and RFA memory. Loading with zero |
---|
1700 | * sets it up for regular linear addressing. |
---|
1701 | */ |
---|
1702 | CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); |
---|
1703 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); |
---|
1704 | |
---|
1705 | fxp_scb_wait(sc); |
---|
1706 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); |
---|
1707 | |
---|
1708 | /* |
---|
1709 | * Initialize base of dump-stats buffer. |
---|
1710 | */ |
---|
1711 | DBGLVL_PRINTK(5,"fxp_init: Initializing base of dump-stats buffer\n"); |
---|
1712 | fxp_scb_wait(sc); |
---|
1713 | CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); |
---|
1714 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); |
---|
1715 | |
---|
1716 | /* |
---|
1717 | * We temporarily use memory that contains the TxCB list to |
---|
1718 | * construct the config CB. The TxCB list memory is rebuilt |
---|
1719 | * later. |
---|
1720 | */ |
---|
1721 | cbp = (struct fxp_cb_config *) sc->cbl_base; |
---|
1722 | DBGLVL_PRINTK(5,"fxp_init: cbp = 0x%x\n",cbp); |
---|
1723 | |
---|
1724 | /* |
---|
1725 | * This memcpy is kind of disgusting, but there are a bunch of must be |
---|
1726 | * zero and must be one bits in this structure and this is the easiest |
---|
1727 | * way to initialize them all to proper values. |
---|
1728 | */ |
---|
1729 | memcpy( (void *)(u_int32_t*)(volatile void *)&cbp->cb_status, |
---|
1730 | fxp_cb_config_template, |
---|
1731 | sizeof(fxp_cb_config_template)); |
---|
1732 | |
---|
1733 | cbp->cb_status = 0; |
---|
1734 | cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; |
---|
1735 | cbp->link_addr = -1; /* (no) next command */ |
---|
1736 | cbp->byte_count = 22; /* (22) bytes to config */ |
---|
1737 | cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ |
---|
1738 | cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ |
---|
1739 | cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ |
---|
1740 | cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; |
---|
1741 | cbp->type_enable = 0; /* actually reserved */ |
---|
1742 | cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; |
---|
1743 | cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; |
---|
1744 | cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ |
---|
1745 | cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ |
---|
1746 | cbp->dma_mbce = 0; /* (disable) dma max counters */ |
---|
1747 | cbp->late_scb = 0; /* (don't) defer SCB update */ |
---|
1748 | cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ |
---|
1749 | cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ |
---|
1750 | cbp->ci_int = 1; /* interrupt on CU idle */ |
---|
1751 | cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; |
---|
1752 | cbp->ext_stats_dis = 1; /* disable extended counters */ |
---|
1753 | cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ |
---|
1754 | cbp->save_bf = sc->chip == FXP_CHIP_82557 ? 1 : prm; |
---|
1755 | cbp->disc_short_rx = !prm; /* discard short packets */ |
---|
1756 | cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ |
---|
1757 | cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ |
---|
1758 | cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ |
---|
1759 | cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; |
---|
1760 | cbp->csma_dis = 0; /* (don't) disable link */ |
---|
1761 | cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ |
---|
1762 | cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ |
---|
1763 | cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ |
---|
1764 | cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ |
---|
1765 | cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ |
---|
1766 | cbp->nsai = 1; /* (don't) disable source addr insert */ |
---|
1767 | cbp->preamble_length = 2; /* (7 byte) preamble */ |
---|
1768 | cbp->loopback = 0; /* (don't) loopback */ |
---|
1769 | cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ |
---|
1770 | cbp->linear_pri_mode = 0; /* (wait after xmit only) */ |
---|
1771 | cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ |
---|
1772 | cbp->promiscuous = prm; /* promiscuous mode */ |
---|
1773 | cbp->bcast_disable = 0; /* (don't) disable broadcasts */ |
---|
1774 | cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ |
---|
1775 | cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ |
---|
1776 | cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ |
---|
1777 | cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; |
---|
1778 | |
---|
1779 | cbp->stripping = !prm; /* truncate rx packet to byte count */ |
---|
1780 | cbp->padding = 1; /* (do) pad short tx packets */ |
---|
1781 | cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ |
---|
1782 | cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; |
---|
1783 | cbp->ia_wake_en = 0; /* (don't) wake up on address match */ |
---|
1784 | cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ |
---|
1785 | /* must set wake_en in PMCSR also */ |
---|
1786 | cbp->force_fdx = 0; /* (don't) force full duplex */ |
---|
1787 | cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ |
---|
1788 | cbp->multi_ia = 0; /* (don't) accept multiple IAs */ |
---|
1789 | cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; |
---|
1790 | |
---|
1791 | DBGLVL_PRINTK(5,"fxp_init: cbp initialized\n"); |
---|
1792 | if (sc->chip == FXP_CHIP_82557) { |
---|
1793 | /* |
---|
1794 | * The 82557 has no hardware flow control, the values |
---|
1795 | * below are the defaults for the chip. |
---|
1796 | */ |
---|
1797 | cbp->fc_delay_lsb = 0; |
---|
1798 | cbp->fc_delay_msb = 0x40; |
---|
1799 | cbp->pri_fc_thresh = 3; |
---|
1800 | cbp->tx_fc_dis = 0; |
---|
1801 | cbp->rx_fc_restop = 0; |
---|
1802 | cbp->rx_fc_restart = 0; |
---|
1803 | cbp->fc_filter = 0; |
---|
1804 | cbp->pri_fc_loc = 1; |
---|
1805 | } else { |
---|
1806 | cbp->fc_delay_lsb = 0x1f; |
---|
1807 | cbp->fc_delay_msb = 0x01; |
---|
1808 | cbp->pri_fc_thresh = 3; |
---|
1809 | cbp->tx_fc_dis = 0; /* enable transmit FC */ |
---|
1810 | cbp->rx_fc_restop = 1; /* enable FC restop frames */ |
---|
1811 | cbp->rx_fc_restart = 1; /* enable FC restart frames */ |
---|
1812 | cbp->fc_filter = !prm; /* drop FC frames to host */ |
---|
1813 | cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ |
---|
1814 | } |
---|
1815 | |
---|
1816 | /* |
---|
1817 | * Start the config command/DMA. |
---|
1818 | */ |
---|
1819 | DBGLVL_PRINTK(5,"fxp_init: starting config command/DMA\n"); |
---|
1820 | fxp_scb_wait(sc); |
---|
1821 | CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); |
---|
1822 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); |
---|
1823 | /* ...and wait for it to complete. */ |
---|
1824 | fxp_dma_wait(&cbp->cb_status, sc); |
---|
1825 | |
---|
1826 | /* |
---|
1827 | * Now initialize the station address. Temporarily use the TxCB |
---|
1828 | * memory area like we did above for the config CB. |
---|
1829 | */ |
---|
1830 | DBGLVL_PRINTK(5,"fxp_init: initialize station address\n"); |
---|
1831 | cb_ias = (struct fxp_cb_ias *) sc->cbl_base; |
---|
1832 | cb_ias->cb_status = 0; |
---|
1833 | cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; |
---|
1834 | cb_ias->link_addr = -1; |
---|
1835 | memcpy((void *)(u_int32_t*)(volatile void *)cb_ias->macaddr, |
---|
1836 | sc->arpcom.ac_enaddr, |
---|
1837 | sizeof(sc->arpcom.ac_enaddr)); |
---|
1838 | |
---|
1839 | /* |
---|
1840 | * Start the IAS (Individual Address Setup) command/DMA. |
---|
1841 | */ |
---|
1842 | DBGLVL_PRINTK(5,"fxp_init: start IAS command/DMA\n"); |
---|
1843 | fxp_scb_wait(sc); |
---|
1844 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); |
---|
1845 | /* ...and wait for it to complete. */ |
---|
1846 | fxp_dma_wait(&cb_ias->cb_status, sc); |
---|
1847 | |
---|
1848 | /* |
---|
1849 | * Initialize transmit control block (TxCB) list. |
---|
1850 | */ |
---|
1851 | |
---|
1852 | DBGLVL_PRINTK(5,"fxp_init: initialize TxCB list\n"); |
---|
1853 | txp = sc->cbl_base; |
---|
1854 | memset(txp, 0, sizeof(struct fxp_cb_tx) * FXP_NTXCB); |
---|
1855 | for (i = 0; i < FXP_NTXCB; i++) { |
---|
1856 | txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; |
---|
1857 | txp[i].cb_command = FXP_CB_COMMAND_NOP; |
---|
1858 | txp[i].link_addr = |
---|
1859 | vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); |
---|
1860 | if (sc->flags & FXP_FLAG_EXT_TXCB) |
---|
1861 | txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); |
---|
1862 | else |
---|
1863 | txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); |
---|
1864 | txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; |
---|
1865 | } |
---|
1866 | /* |
---|
1867 | * Set the suspend flag on the first TxCB and start the control |
---|
1868 | * unit. It will execute the NOP and then suspend. |
---|
1869 | */ |
---|
1870 | DBGLVL_PRINTK(5,"fxp_init: setup suspend flag\n"); |
---|
1871 | txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; |
---|
1872 | sc->cbl_first = sc->cbl_last = txp; |
---|
1873 | sc->tx_queued = 1; |
---|
1874 | |
---|
1875 | fxp_scb_wait(sc); |
---|
1876 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); |
---|
1877 | |
---|
1878 | /* |
---|
1879 | * Initialize receiver buffer area - RFA. |
---|
1880 | */ |
---|
1881 | DBGLVL_PRINTK(5,"fxp_init: initialize RFA\n"); |
---|
1882 | fxp_scb_wait(sc); |
---|
1883 | CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, |
---|
1884 | vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); |
---|
1885 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); |
---|
1886 | |
---|
1887 | #ifdef NOTUSED |
---|
1888 | /* |
---|
1889 | * Set current media. |
---|
1890 | */ |
---|
1891 | if (sc->miibus != NULL) |
---|
1892 | mii_mediachg(device_get_softc(sc->miibus)); |
---|
1893 | #endif |
---|
1894 | |
---|
1895 | ifp->if_flags |= IFF_RUNNING; |
---|
1896 | ifp->if_flags &= ~IFF_OACTIVE; |
---|
1897 | |
---|
1898 | if (sc->daemonTid == 0) { |
---|
1899 | /* |
---|
1900 | * Start driver task |
---|
1901 | */ |
---|
1902 | sc->daemonTid = rtems_bsdnet_newproc ("FXPd", 4096, fxp_daemon, sc); |
---|
1903 | |
---|
1904 | } |
---|
1905 | /* |
---|
1906 | * Enable interrupts. |
---|
1907 | */ |
---|
1908 | CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); |
---|
1909 | splx(s); |
---|
1910 | |
---|
1911 | /* |
---|
1912 | * Start stats updater. |
---|
1913 | */ |
---|
1914 | sc->stat_ch = fxp_timeout_running; |
---|
1915 | DBGLVL_PRINTK(2,"fxp_init: stats updater timeout called with hz=%d\n", hz); |
---|
1916 | timeout(fxp_tick, sc, hz); |
---|
1917 | DBGLVL_PRINTK(2,"fxp_init finished\n"); |
---|
1918 | } |
---|
1919 | |
---|
1920 | #ifdef NOTUSED |
---|
1921 | static int |
---|
1922 | fxp_serial_ifmedia_upd(struct ifnet *ifp) |
---|
1923 | { |
---|
1924 | |
---|
1925 | return (0); |
---|
1926 | } |
---|
1927 | |
---|
1928 | static void |
---|
1929 | fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) |
---|
1930 | { |
---|
1931 | |
---|
1932 | ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; |
---|
1933 | } |
---|
1934 | |
---|
1935 | /* |
---|
1936 | * Change media according to request. |
---|
1937 | */ |
---|
1938 | static int |
---|
1939 | fxp_ifmedia_upd(struct ifnet *ifp) |
---|
1940 | { |
---|
1941 | struct fxp_softc *sc = ifp->if_softc; |
---|
1942 | struct mii_data *mii; |
---|
1943 | |
---|
1944 | mii = device_get_softc(sc->miibus); |
---|
1945 | mii_mediachg(mii); |
---|
1946 | return (0); |
---|
1947 | } |
---|
1948 | |
---|
1949 | /* |
---|
1950 | * Notify the world which media we're using. |
---|
1951 | */ |
---|
1952 | static void |
---|
1953 | fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) |
---|
1954 | { |
---|
1955 | struct fxp_softc *sc = ifp->if_softc; |
---|
1956 | struct mii_data *mii; |
---|
1957 | |
---|
1958 | mii = device_get_softc(sc->miibus); |
---|
1959 | mii_pollstat(mii); |
---|
1960 | ifmr->ifm_active = mii->mii_media_active; |
---|
1961 | ifmr->ifm_status = mii->mii_media_status; |
---|
1962 | |
---|
1963 | if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) |
---|
1964 | sc->cu_resume_bug = 1; |
---|
1965 | else |
---|
1966 | sc->cu_resume_bug = 0; |
---|
1967 | } |
---|
1968 | #endif |
---|
1969 | |
---|
1970 | /* |
---|
1971 | * Add a buffer to the end of the RFA buffer list. |
---|
1972 | * Return 0 if successful, 1 for failure. A failure results in |
---|
1973 | * adding the 'oldm' (if non-NULL) on to the end of the list - |
---|
1974 | * tossing out its old contents and recycling it. |
---|
1975 | * The RFA struct is stuck at the beginning of mbuf cluster and the |
---|
1976 | * data pointer is fixed up to point just past it. |
---|
1977 | */ |
---|
1978 | static int |
---|
1979 | fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) |
---|
1980 | { |
---|
1981 | u_int32_t v; |
---|
1982 | struct mbuf *m; |
---|
1983 | struct fxp_rfa *rfa, *p_rfa; |
---|
1984 | |
---|
1985 | DBGLVL_PRINTK(4,"fxp_add_rfabuf called\n"); |
---|
1986 | |
---|
1987 | MGETHDR(m, M_DONTWAIT, MT_DATA); |
---|
1988 | if (m != NULL) { |
---|
1989 | MCLGET(m, M_DONTWAIT); |
---|
1990 | if ((m->m_flags & M_EXT) == 0) { |
---|
1991 | m_freem(m); |
---|
1992 | if (oldm == NULL) |
---|
1993 | return 1; |
---|
1994 | m = oldm; |
---|
1995 | m->m_data = m->m_ext.ext_buf; |
---|
1996 | } |
---|
1997 | } else { |
---|
1998 | if (oldm == NULL) |
---|
1999 | return 1; |
---|
2000 | m = oldm; |
---|
2001 | m->m_data = m->m_ext.ext_buf; |
---|
2002 | } |
---|
2003 | |
---|
2004 | /* |
---|
2005 | * Move the data pointer up so that the incoming data packet |
---|
2006 | * will be 32-bit aligned. |
---|
2007 | */ |
---|
2008 | m->m_data += RFA_ALIGNMENT_FUDGE; |
---|
2009 | |
---|
2010 | /* |
---|
2011 | * Get a pointer to the base of the mbuf cluster and move |
---|
2012 | * data start past it. |
---|
2013 | */ |
---|
2014 | rfa = mtod(m, struct fxp_rfa *); |
---|
2015 | m->m_data += sizeof(struct fxp_rfa); |
---|
2016 | rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); |
---|
2017 | |
---|
2018 | /* |
---|
2019 | * Initialize the rest of the RFA. Note that since the RFA |
---|
2020 | * is misaligned, we cannot store values directly. Instead, |
---|
2021 | * we use an optimized, inline copy. |
---|
2022 | */ |
---|
2023 | |
---|
2024 | rfa->rfa_status = 0; |
---|
2025 | rfa->rfa_control = FXP_RFA_CONTROL_EL; |
---|
2026 | rfa->actual_size = 0; |
---|
2027 | |
---|
2028 | v = -1; |
---|
2029 | fxp_lwcopy(&v, (volatile u_int32_t*) rfa->link_addr); |
---|
2030 | fxp_lwcopy(&v, (volatile u_int32_t*) rfa->rbd_addr); |
---|
2031 | |
---|
2032 | /* |
---|
2033 | * If there are other buffers already on the list, attach this |
---|
2034 | * one to the end by fixing up the tail to point to this one. |
---|
2035 | */ |
---|
2036 | if (sc->rfa_headm != NULL) { |
---|
2037 | p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + |
---|
2038 | RFA_ALIGNMENT_FUDGE); |
---|
2039 | sc->rfa_tailm->m_next = m; |
---|
2040 | v = vtophys(rfa); |
---|
2041 | fxp_lwcopy(&v, (volatile u_int32_t*) p_rfa->link_addr); |
---|
2042 | p_rfa->rfa_control = 0; |
---|
2043 | } else { |
---|
2044 | sc->rfa_headm = m; |
---|
2045 | } |
---|
2046 | sc->rfa_tailm = m; |
---|
2047 | |
---|
2048 | return (m == oldm); |
---|
2049 | } |
---|
2050 | |
---|
2051 | #ifdef NOTUSED |
---|
2052 | static volatile int |
---|
2053 | fxp_miibus_readreg(device_t dev, int phy, int reg) |
---|
2054 | { |
---|
2055 | struct fxp_softc *sc = device_get_softc(dev); |
---|
2056 | int count = 10000; |
---|
2057 | int value; |
---|
2058 | |
---|
2059 | CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, |
---|
2060 | (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); |
---|
2061 | |
---|
2062 | while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 |
---|
2063 | && count--) |
---|
2064 | DELAY(10); |
---|
2065 | |
---|
2066 | if (count <= 0) |
---|
2067 | device_printf(dev, "fxp_miibus_readreg: timed out\n"); |
---|
2068 | |
---|
2069 | return (value & 0xffff); |
---|
2070 | } |
---|
2071 | |
---|
2072 | static void |
---|
2073 | fxp_miibus_writereg(device_t dev, int phy, int reg, int value) |
---|
2074 | { |
---|
2075 | struct fxp_softc *sc = device_get_softc(dev); |
---|
2076 | int count = 10000; |
---|
2077 | |
---|
2078 | CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, |
---|
2079 | (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | |
---|
2080 | (value & 0xffff)); |
---|
2081 | |
---|
2082 | while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && |
---|
2083 | count--) |
---|
2084 | DELAY(10); |
---|
2085 | |
---|
2086 | if (count <= 0) |
---|
2087 | device_printf(dev, "fxp_miibus_writereg: timed out\n"); |
---|
2088 | } |
---|
2089 | #endif |
---|
2090 | |
---|
2091 | static int |
---|
2092 | fxp_ioctl(struct ifnet *ifp, int command, caddr_t data) |
---|
2093 | { |
---|
2094 | struct fxp_softc *sc = ifp->if_softc; |
---|
2095 | #ifdef NOTUSED |
---|
2096 | struct ifreq *ifr = (struct ifreq *)data; |
---|
2097 | struct mii_data *mii; |
---|
2098 | #endif |
---|
2099 | int s, error = 0; |
---|
2100 | |
---|
2101 | DBGLVL_PRINTK(2,"fxp_ioctl called\n"); |
---|
2102 | |
---|
2103 | s = splimp(); |
---|
2104 | |
---|
2105 | switch (command) { |
---|
2106 | case SIOCSIFADDR: |
---|
2107 | case SIOCGIFADDR: |
---|
2108 | case SIOCSIFMTU: |
---|
2109 | error = ether_ioctl(ifp, command, data); |
---|
2110 | break; |
---|
2111 | |
---|
2112 | case SIOCSIFFLAGS: |
---|
2113 | if (ifp->if_flags & IFF_ALLMULTI) |
---|
2114 | sc->flags |= FXP_FLAG_ALL_MCAST; |
---|
2115 | else |
---|
2116 | sc->flags &= ~FXP_FLAG_ALL_MCAST; |
---|
2117 | |
---|
2118 | /* |
---|
2119 | * If interface is marked up and not running, then start it. |
---|
2120 | * If it is marked down and running, stop it. |
---|
2121 | * XXX If it's up then re-initialize it. This is so flags |
---|
2122 | * such as IFF_PROMISC are handled. |
---|
2123 | */ |
---|
2124 | if (ifp->if_flags & IFF_UP) { |
---|
2125 | fxp_init(sc); |
---|
2126 | } else { |
---|
2127 | if (ifp->if_flags & IFF_RUNNING) |
---|
2128 | fxp_stop(sc); |
---|
2129 | } |
---|
2130 | break; |
---|
2131 | |
---|
2132 | case SIOCADDMULTI: |
---|
2133 | case SIOCDELMULTI: |
---|
2134 | if (ifp->if_flags & IFF_ALLMULTI) |
---|
2135 | sc->flags |= FXP_FLAG_ALL_MCAST; |
---|
2136 | else |
---|
2137 | sc->flags &= ~FXP_FLAG_ALL_MCAST; |
---|
2138 | /* |
---|
2139 | * Multicast list has changed; set the hardware filter |
---|
2140 | * accordingly. |
---|
2141 | */ |
---|
2142 | if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) |
---|
2143 | fxp_mc_setup(sc); |
---|
2144 | /* |
---|
2145 | * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it |
---|
2146 | * again rather than else {}. |
---|
2147 | */ |
---|
2148 | if (sc->flags & FXP_FLAG_ALL_MCAST) |
---|
2149 | fxp_init(sc); |
---|
2150 | error = 0; |
---|
2151 | break; |
---|
2152 | |
---|
2153 | #ifdef NOTUSED |
---|
2154 | case SIOCSIFMEDIA: |
---|
2155 | case SIOCGIFMEDIA: |
---|
2156 | if (sc->miibus != NULL) { |
---|
2157 | mii = device_get_softc(sc->miibus); |
---|
2158 | error = ifmedia_ioctl(ifp, ifr, |
---|
2159 | &mii->mii_media, command); |
---|
2160 | } else { |
---|
2161 | error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); |
---|
2162 | } |
---|
2163 | break; |
---|
2164 | #endif |
---|
2165 | |
---|
2166 | case SIO_RTEMS_SHOW_STATS: |
---|
2167 | fxp_stats(sc); |
---|
2168 | break; |
---|
2169 | |
---|
2170 | default: |
---|
2171 | error = EINVAL; |
---|
2172 | } |
---|
2173 | splx(s); |
---|
2174 | return (error); |
---|
2175 | } |
---|
2176 | |
---|
2177 | /* |
---|
2178 | * Program the multicast filter. |
---|
2179 | * |
---|
2180 | * We have an artificial restriction that the multicast setup command |
---|
2181 | * must be the first command in the chain, so we take steps to ensure |
---|
2182 | * this. By requiring this, it allows us to keep up the performance of |
---|
2183 | * the pre-initialized command ring (esp. link pointers) by not actually |
---|
2184 | * inserting the mcsetup command in the ring - i.e. its link pointer |
---|
2185 | * points to the TxCB ring, but the mcsetup descriptor itself is not part |
---|
2186 | * of it. We then can do 'CU_START' on the mcsetup descriptor and have it |
---|
2187 | * lead into the regular TxCB ring when it completes. |
---|
2188 | * |
---|
2189 | * This function must be called at splimp. |
---|
2190 | */ |
---|
2191 | static void |
---|
2192 | fxp_mc_setup(struct fxp_softc *sc) |
---|
2193 | { |
---|
2194 | struct fxp_cb_mcs *mcsp = sc->mcsp; |
---|
2195 | struct ifnet *ifp = &sc->sc_if; |
---|
2196 | #ifdef NOTUSED |
---|
2197 | struct ifmultiaddr *ifma; |
---|
2198 | #endif |
---|
2199 | int nmcasts; |
---|
2200 | int count; |
---|
2201 | |
---|
2202 | DBGLVL_PRINTK(2,"fxp_mc_setup called\n"); |
---|
2203 | |
---|
2204 | /* |
---|
2205 | * If there are queued commands, we must wait until they are all |
---|
2206 | * completed. If we are already waiting, then add a NOP command |
---|
2207 | * with interrupt option so that we're notified when all commands |
---|
2208 | * have been completed - fxp_start() ensures that no additional |
---|
2209 | * TX commands will be added when need_mcsetup is true. |
---|
2210 | */ |
---|
2211 | if (sc->tx_queued) { |
---|
2212 | struct fxp_cb_tx *txp; |
---|
2213 | |
---|
2214 | /* |
---|
2215 | * need_mcsetup will be true if we are already waiting for the |
---|
2216 | * NOP command to be completed (see below). In this case, bail. |
---|
2217 | */ |
---|
2218 | if (sc->need_mcsetup) |
---|
2219 | return; |
---|
2220 | sc->need_mcsetup = 1; |
---|
2221 | |
---|
2222 | /* |
---|
2223 | * Add a NOP command with interrupt so that we are notified when all |
---|
2224 | * TX commands have been processed. |
---|
2225 | */ |
---|
2226 | txp = sc->cbl_last->next; |
---|
2227 | txp->mb_head = NULL; |
---|
2228 | txp->cb_status = 0; |
---|
2229 | txp->cb_command = FXP_CB_COMMAND_NOP | |
---|
2230 | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; |
---|
2231 | /* |
---|
2232 | * Advance the end of list forward. |
---|
2233 | */ |
---|
2234 | sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; |
---|
2235 | sc->cbl_last = txp; |
---|
2236 | sc->tx_queued++; |
---|
2237 | /* |
---|
2238 | * Issue a resume in case the CU has just suspended. |
---|
2239 | */ |
---|
2240 | fxp_scb_wait(sc); |
---|
2241 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); |
---|
2242 | /* |
---|
2243 | * Set a 5 second timer just in case we don't hear from the |
---|
2244 | * card again. |
---|
2245 | */ |
---|
2246 | ifp->if_timer = 5; |
---|
2247 | |
---|
2248 | return; |
---|
2249 | } |
---|
2250 | sc->need_mcsetup = 0; |
---|
2251 | |
---|
2252 | /* |
---|
2253 | * Initialize multicast setup descriptor. |
---|
2254 | */ |
---|
2255 | mcsp->next = sc->cbl_base; |
---|
2256 | mcsp->mb_head = NULL; |
---|
2257 | mcsp->cb_status = 0; |
---|
2258 | mcsp->cb_command = FXP_CB_COMMAND_MCAS | |
---|
2259 | FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; |
---|
2260 | mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); |
---|
2261 | |
---|
2262 | nmcasts = 0; |
---|
2263 | #ifdef NOTUSED /* FIXME: Multicast not supported? */ |
---|
2264 | if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { |
---|
2265 | #if __FreeBSD_version < 500000 |
---|
2266 | LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { |
---|
2267 | #else |
---|
2268 | TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { |
---|
2269 | #endif |
---|
2270 | if (ifma->ifma_addr->sa_family != AF_LINK) |
---|
2271 | continue; |
---|
2272 | if (nmcasts >= MAXMCADDR) { |
---|
2273 | sc->flags |= FXP_FLAG_ALL_MCAST; |
---|
2274 | nmcasts = 0; |
---|
2275 | break; |
---|
2276 | } |
---|
2277 | memcpy((void *)(uintptr_t)(volatile void *) |
---|
2278 | &sc->mcsp->mc_addr[nmcasts][0], |
---|
2279 | LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 6); |
---|
2280 | nmcasts++; |
---|
2281 | } |
---|
2282 | } |
---|
2283 | #endif |
---|
2284 | mcsp->mc_cnt = nmcasts * 6; |
---|
2285 | sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; |
---|
2286 | sc->tx_queued = 1; |
---|
2287 | |
---|
2288 | /* |
---|
2289 | * Wait until command unit is not active. This should never |
---|
2290 | * be the case when nothing is queued, but make sure anyway. |
---|
2291 | */ |
---|
2292 | count = 100; |
---|
2293 | while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == |
---|
2294 | FXP_SCB_CUS_ACTIVE && --count) |
---|
2295 | DELAY(10); |
---|
2296 | if (count == 0) { |
---|
2297 | device_printf(sc->dev, "command queue timeout\n"); |
---|
2298 | return; |
---|
2299 | } |
---|
2300 | |
---|
2301 | /* |
---|
2302 | * Start the multicast setup command. |
---|
2303 | */ |
---|
2304 | fxp_scb_wait(sc); |
---|
2305 | CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); |
---|
2306 | fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); |
---|
2307 | |
---|
2308 | ifp->if_timer = 2; |
---|
2309 | return; |
---|
2310 | } |
---|
2311 | |
---|
2312 | #endif /* defined(__i386__) */ |
---|