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source: rtems/c/src/libchip/network/if_dc.c @ ccb670c

4.104.115

Last change on this file since ccb670c was 260e6fb3, checked in by Ralf Corsepius <ralf.corsepius@…>, on 11/06/09 at 04:36:13

2009-11-06 Ralf Corsépius <ralf.corsepius@…>

libchip/network/if_dc.c: Fix type mismatch.

Property mode set to 100644

File size: 93.1 KB

Line
1	/* $Id$
2	*
3	* Ported from FreeBSD --> RTEMS, december 03.
4	* Daron Chabot <daron@nucleus.usask.ca>
5	* -- only tested with i386 bsp.
6	* -- supports one card (until the PCI & IRQ APIs get sorted out ;-))
7	*
8	*
9	* Copyright (c) 1997, 1998, 1999
10	* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
11	*
12	* Redistribution and use in source and binary forms, with or without
13	* modification, are permitted provided that the following conditions
14	* are met:
15	* 1. Redistributions of source code must retain the above copyright
16	* notice, this list of conditions and the following disclaimer.
17	* 2. Redistributions in binary form must reproduce the above copyright
18	* notice, this list of conditions and the following disclaimer in the
19	* documentation and/or other materials provided with the distribution.
20	* 3. All advertising materials mentioning features or use of this software
21	* must display the following acknowledgement:
22	* This product includes software developed by Bill Paul.
23	* 4. Neither the name of the author nor the names of any co-contributors
24	* may be used to endorse or promote products derived from this software
25	* without specific prior written permission.
26	*
27	* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
28	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30	* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
31	* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
37	* THE POSSIBILITY OF SUCH DAMAGE.
38	*
39	* $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.41 2003/03/05 18:42:33 njl Exp $
40	*/
41
42	/*
43	* DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
44	* series chips and several workalikes including the following:
45	*
46	* Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
47	* Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
48	* Lite-On 82c168/82c169 PNIC (www.litecom.com)
49	* ASIX Electronics AX88140A (www.asix.com.tw)
50	* ASIX Electronics AX88141 (www.asix.com.tw)
51	* ADMtek AL981 (www.admtek.com.tw)
52	* ADMtek AN985 (www.admtek.com.tw)
53	* Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
54	* Accton EN1217 (www.accton.com)
55	* Conexant LANfinity (www.conexant.com)
56	*
57	* Datasheets for the 21143 are available at developer.intel.com.
58	* Datasheets for the clone parts can be found at their respective sites.
59	* (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
60	* The PNIC II is essentially a Macronix 98715A chip; the only difference
61	* worth noting is that its multicast hash table is only 128 bits wide
62	* instead of 512.
63	*
64	* Written by Bill Paul <wpaul@ee.columbia.edu>
65	* Electrical Engineering Department
66	* Columbia University, New York City
67	*/
68
69	/*
70	* The Intel 21143 is the successor to the DEC 21140. It is basically
71	* the same as the 21140 but with a few new features. The 21143 supports
72	* three kinds of media attachments:
73	*
74	* o MII port, for 10Mbps and 100Mbps support and NWAY
75	* autonegotiation provided by an external PHY.
76	* o SYM port, for symbol mode 100Mbps support.
77	* o 10baseT port.
78	* o AUI/BNC port.
79	*
80	* The 100Mbps SYM port and 10baseT port can be used together in
81	* combination with the internal NWAY support to create a 10/100
82	* autosensing configuration.
83	*
84	* Note that not all tulip workalikes are handled in this driver: we only
85	* deal with those which are relatively well behaved. The Winbond is
86	* handled separately due to its different register offsets and the
87	* special handling needed for its various bugs. The PNIC is handled
88	* here, but I'm not thrilled about it.
89	*
90	* All of the workalike chips use some form of MII transceiver support
91	* with the exception of the Macronix chips, which also have a SYM port.
92	* The ASIX AX88140A is also documented to have a SYM port, but all
93	* the cards I've seen use an MII transceiver, probably because the
94	* AX88140A doesn't support internal NWAY.
95	*/
96
97	/*
98	* This driver only supports architectures with the new style
99	* exception processing. The following checks try to keep this
100	* from being compiled on systems which can't support this driver.
101	*/
102
103	#if defined(DRIVER_SUPPORTED)
104	#undef DRIVER_SUPPORTED
105	#endif
106
107	#if defined(__i386__)
108	#define DRIVER_SUPPORTED
109	#endif
110
111	#if defined(__PPC__) && (defined(mpc604) \|\| defined(mpc750) \|\| defined(ppc603e))
112	#define DRIVER_SUPPORTED
113	#warning The if_dc driver is untested on the PPC platform !!!
114	#endif
115
116
117	#if defined(DRIVER_SUPPORTED) /* this covers the file "globally"... */
118	#include <bsp.h>
119	#include <rtems.h>
120	#include <rtems/pci.h>
121
122	#include <rtems/error.h>
123	#include <errno.h>
124	#include <rtems/rtems_bsdnet.h>
125
126	#include <net/if_types.h>
127
128	#include <sys/param.h>
129	#include <sys/sockio.h>
130	#include <sys/socket.h>
131	#include <sys/mbuf.h>
132	#include <net/if.h>
133	#include <netinet/in.h>
134	#include <netinet/if_ether.h>
135	#include <sys/malloc.h>
136	#include <sys/systm.h>
137	#include <bsp.h>
138
139	/* moved to cpukit/include/rtems in CVS current ! */
140	/#include "if_media.h" /
141	/#include "pci.h" /
142	#include <net/if_media.h>
143	#include <rtems/pci.h>
144	/*
145	#include <sys/kernel.h>
146	#include <sys/sysctl.h>
147	*/
148
149	#include <vm/vm.h> /* for vtophys */
150
151
152	#if defined(__i386__)
153	#define vtophys(p) (u_int32_t)(p)
154	#else
155	#define vtophys(p) vtophys(p)
156	#endif
157
158	/*
159	#include <net/if_arp.h>
160	#include <net/if_vlan_var.h>
161	#include <net/bpf.h>
162	*/
163
164	#if 0
165	#include <vm/pmap.h> /* for vtophys */
166	#include <machine/clock.h> /* for DELAY */
167	#include <machine/bus_pio.h>
168	#include <machine/bus_memio.h>
169	#include <machine/bus.h>
170	#include <machine/resource.h>
171	#include <sys/bus.h>
172	#include <sys/rman.h>
173	#endif
174	#include <dev/mii/mii.h>
175	#if 0
176	#include <dev/mii/miivar.h>
177
178	#include <pci/pcireg.h>
179	#include <pci/pcivar.h>
180	#endif
181
182	/* NOTE: use mem space mapping (for now ...)
183	#define DC_USEIOSPACE
184	*/
185
186	#ifdef __alpha__
187	#define SRM_MEDIA
188	#endif
189
190	#include <bsp/irq.h>
191
192
193	#include "if_dcreg.h"
194
195
196	#define DRIVER_PREFIX "tl"
197	#define NDRIVER 1
198	#define IRQ_EVENT RTEMS_EVENT_13 /* Ha ... */
199	static struct dc_softc dc_softc_devs[NDRIVER];
200
201	#define UNUSED
202
203	#if 0
204	/* "controller miibus0" required. See GENERIC if you get errors here. */
205	#include "miibus_if.h"
206
207
208
209	#ifndef lint
210	static const char rcsid[] =
211	"$FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.41 2003/03/05 18:42:33 njl Exp $";
212	#endif
213
214	#endif
215
216
217	/*
218	* Various supported device vendors/types and their names.
219	* NOTE:
220	* -----
221	* Only the "ADMtek AN985" has been tested under RTEMS !!!
222	*/
223	static struct dc_type dc_devs[] = {
224	{ DC_VENDORID_DEC, DC_DEVICEID_21143,
225	"Intel 21143 10/100BaseTX", 0 },
226	{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009,
227	"Davicom DM9009 10/100BaseTX", 0 },
228	{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100,
229	"Davicom DM9100 10/100BaseTX", 0 },
230	{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
231	"Davicom DM9102 10/100BaseTX", 0 },
232	{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
233	"Davicom DM9102A 10/100BaseTX", 0 },
234	{ DC_VENDORID_ADMTEK, DC_DEVICEID_AL981,
235	"ADMtek AL981 10/100BaseTX", 0 },
236	{ DC_VENDORID_ADMTEK, DC_DEVICEID_AN985,
237	"ADMtek AN985 10/100BaseTX", 0 },
238	{ DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
239	"ASIX AX88140A 10/100BaseTX", 0 },
240	{ DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
241	"ASIX AX88141 10/100BaseTX", 0 },
242	{ DC_VENDORID_MX, DC_DEVICEID_98713,
243	"Macronix 98713 10/100BaseTX", 0 },
244	{ DC_VENDORID_MX, DC_DEVICEID_98713,
245	"Macronix 98713A 10/100BaseTX", 0 },
246	{ DC_VENDORID_CP, DC_DEVICEID_98713_CP,
247	"Compex RL100-TX 10/100BaseTX", 0 },
248	{ DC_VENDORID_CP, DC_DEVICEID_98713_CP,
249	"Compex RL100-TX 10/100BaseTX", 0 },
250	{ DC_VENDORID_MX, DC_DEVICEID_987x5,
251	"Macronix 98715/98715A 10/100BaseTX", 0 },
252	{ DC_VENDORID_MX, DC_DEVICEID_987x5,
253	"Macronix 98715AEC-C 10/100BaseTX", 0 },
254	{ DC_VENDORID_MX, DC_DEVICEID_987x5,
255	"Macronix 98725 10/100BaseTX", 0 },
256	{ DC_VENDORID_MX, DC_DEVICEID_98727,
257	"Macronix 98727/98732 10/100BaseTX", 0 },
258	{ DC_VENDORID_LO, DC_DEVICEID_82C115,
259	"LC82C115 PNIC II 10/100BaseTX", 0 },
260	{ DC_VENDORID_LO, DC_DEVICEID_82C168,
261	"82c168 PNIC 10/100BaseTX", 0 },
262	{ DC_VENDORID_LO, DC_DEVICEID_82C168,
263	"82c169 PNIC 10/100BaseTX", 0 },
264	{ DC_VENDORID_ACCTON, DC_DEVICEID_EN1217,
265	"Accton EN1217 10/100BaseTX", 0 },
266	{ DC_VENDORID_ACCTON, DC_DEVICEID_EN2242,
267	"Accton EN2242 MiniPCI 10/100BaseTX", 0 },
268	{ DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112,
269	"Conexant LANfinity MiniPCI 10/100BaseTX", 0 },
270	{ 0, 0, NULL, 0 }
271	};
272
273	#if 0
274	static int dc_probe __P((device_t));
275	static int dc_attach __P((device_t));
276	static int dc_detach __P((device_t));
277	static int dc_suspend __P((device_t));
278	static int dc_resume __P((device_t));
279	static void dc_shutdown __P((device_t));
280	static void dc_acpi __P((device_t));
281	#endif
282
283	static struct dc_type *dc_devtype(int);
284	static int dc_newbuf(struct dc_softc , int, struct mbuf );
285	static int dc_encap(struct dc_softc , struct mbuf ,
286	u_int32_t *);
287	static int dc_coal(struct dc_softc , struct mbuf *);
288	static void dc_pnic_rx_bug_war(struct dc_softc *, int);
289	static int dc_rx_resync(struct dc_softc *);
290	static void dc_rxeof(struct dc_softc *);
291	static void dc_txeof(struct dc_softc *);
292	/static void dc_tick((void ));*/
293	static void dc_tx_underrun(struct dc_softc *);
294	static void dc_intr(void *);
295	static void dc_daemon(void *);
296	static void dc_start(struct ifnet *);
297	static int dc_ioctl(struct ifnet *, ioctl_command_t, caddr_t);
298	static void dc_init(void *);
299	static void dc_stop(struct dc_softc *);
300	static void dc_watchdog(struct ifnet *);
301	#if 0
302	static int dc_ifmedia_upd __P((struct ifnet *));
303	static void dc_ifmedia_sts __P((struct ifnet , struct ifmediareq ));
304	#endif
305
306	static void dc_delay(struct dc_softc *);
307	static void dc_eeprom_idle(struct dc_softc *);
308	static void dc_eeprom_putbyte(struct dc_softc *, int);
309	static void dc_eeprom_getword(struct dc_softc , int, u_int16_t );
310	static void dc_eeprom_getword_pnic(struct dc_softc , int, u_int16_t );
311	static void dc_eeprom_width(struct dc_softc *);
312	static void dc_read_eeprom(struct dc_softc *, caddr_t, int,int, int);
313
314	#if 0
315	static void dc_mii_writebit __P((struct dc_softc *, int));
316	static int dc_mii_readbit __P((struct dc_softc *));
317	static void dc_mii_sync __P((struct dc_softc *));
318	static void dc_mii_send __P((struct dc_softc *, u_int32_t, int));
319	static int dc_mii_readreg __P((struct dc_softc , struct dc_mii_frame ));
320	static int dc_mii_writereg __P((struct dc_softc , struct dc_mii_frame ));
321	static int dc_miibus_readreg __P((device_t, int, int));
322	static int dc_miibus_writereg __P((device_t, int, int, int));
323	static void dc_miibus_statchg __P((device_t));
324	static void dc_miibus_mediainit __P((device_t));
325	#endif
326
327	static void dc_setcfg(struct dc_softc *, int);
328	static u_int32_t dc_crc_le(struct dc_softc *, caddr_t);
329	#ifndef UNUSED
330	static u_int32_t dc_crc_be(caddr_t);
331	#endif
332	static void dc_setfilt_21143(struct dc_softc *);
333	static void dc_setfilt_asix(struct dc_softc *);
334	static void dc_setfilt_admtek(struct dc_softc *);
335	static void dc_setfilt(struct dc_softc *);
336	static void dc_reset(struct dc_softc *);
337	static int dc_list_rx_init(struct dc_softc *);
338	static int dc_list_tx_init(struct dc_softc *);
339	static void dc_read_srom(struct dc_softc *, int);
340	static void dc_parse_21143_srom(struct dc_softc *);
341	static void dc_apply_fixup(struct dc_softc *, int);
342
343	#if 0
344	static void dc_decode_leaf_sia __P((struct dc_softc *,
345	struct dc_eblock_sia *));
346	static void dc_decode_leaf_mii __P((struct dc_softc *,
347	struct dc_eblock_mii *));
348	static void dc_decode_leaf_sym __P((struct dc_softc *,
349	struct dc_eblock_sym *));
350	#endif
351
352
353	#ifdef DC_USEIOSPACE
354	#define DC_RES SYS_RES_IOPORT
355	#define DC_RID DC_PCI_CFBIO
356	#else
357	#define DC_RES SYS_RES_MEMORY
358	#define DC_RID DC_PCI_CFBMA
359	#endif
360
361	#if 0
362	static device_method_t dc_methods[] = {
363	/* Device interface */
364	DEVMETHOD(device_probe, dc_probe),
365	DEVMETHOD(device_attach, dc_attach),
366	DEVMETHOD(device_detach, dc_detach),
367	DEVMETHOD(device_suspend, dc_suspend),
368	DEVMETHOD(device_resume, dc_resume),
369	DEVMETHOD(device_shutdown, dc_shutdown),
370
371	/* bus interface */
372	DEVMETHOD(bus_print_child, bus_generic_print_child),
373	DEVMETHOD(bus_driver_added, bus_generic_driver_added),
374
375	/* MII interface */
376	DEVMETHOD(miibus_readreg, dc_miibus_readreg),
377	DEVMETHOD(miibus_writereg, dc_miibus_writereg),
378	DEVMETHOD(miibus_statchg, dc_miibus_statchg),
379	DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
380
381	{ 0, 0 }
382	};
383
384	static driver_t dc_driver = {
385	"dc",
386	dc_methods,
387	sizeof(struct dc_softc)
388	};
389
390	static devclass_t dc_devclass;
391	#endif
392
393
394	#ifdef __i386__
395	static int dc_quick=1;
396	#if 0
397	SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW,
398	&dc_quick,0,"do not mdevget in dc driver");
399	#endif
400	#endif
401
402	#if 0
403	DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0);
404	DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
405	#endif
406
407
408	#define DC_SETBIT(sc, reg, x) \
409	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) \| (x))
410
411	#define DC_CLRBIT(sc, reg, x) \
412	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
413
414	#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
415	#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
416
417
418	/* XXX Fixme: rtems_bsp_delay( ) for the pc386 BSP (at least)
419	* needs work... see pc386/include/bsp.h.
420	* I have "a" solution, utilizing the 2nd i8254 timer,
421	* if anyone is interested (first timer is used for clock_tick ISR)...
422	*/
423	#ifdef __i386__
424	extern void Wait_X_ms( unsigned int );
425	#define DELAY(n) Wait_X_ms( (unsigned int)((n)/100) )
426	#else
427	#define DELAY(n) rtems_bsp_delay(n)
428	#endif
429
430
431	static void dc_delay(sc)
432	struct dc_softc *sc;
433	{
434	int idx;
435
436	for (idx = (300 / 33) + 1; idx > 0; idx--)
437	CSR_READ_4(sc, DC_BUSCTL);
438	}
439
440	static void dc_eeprom_width(sc)
441	struct dc_softc *sc;
442	{
443	int i;
444
445	/* Force EEPROM to idle state. */
446	dc_eeprom_idle(sc);
447
448	/* Enter EEPROM access mode. */
449	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
450	dc_delay(sc);
451	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
452	dc_delay(sc);
453	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
454	dc_delay(sc);
455	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
456	dc_delay(sc);
457
458	for (i = 3; i--;) {
459	if (6 & (1 << i))
460	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
461	else
462	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
463	dc_delay(sc);
464	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
465	dc_delay(sc);
466	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
467	dc_delay(sc);
468	}
469
470	for (i = 1; i <= 12; i++) {
471	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
472	dc_delay(sc);
473	if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
474	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
475	dc_delay(sc);
476	break;
477	}
478	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
479	dc_delay(sc);
480	}
481
482	/* Turn off EEPROM access mode. */
483	dc_eeprom_idle(sc);
484
485	if (i < 4 \|\| i > 12)
486	sc->dc_romwidth = 6;
487	else
488	sc->dc_romwidth = i;
489
490	/* Enter EEPROM access mode. */
491	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
492	dc_delay(sc);
493	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
494	dc_delay(sc);
495	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
496	dc_delay(sc);
497	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
498	dc_delay(sc);
499
500	/* Turn off EEPROM access mode. */
501	dc_eeprom_idle(sc);
502	}
503
504	static void dc_eeprom_idle(sc)
505	struct dc_softc *sc;
506	{
507	register int i;
508
509	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
510	dc_delay(sc);
511	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
512	dc_delay(sc);
513	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
514	dc_delay(sc);
515	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
516	dc_delay(sc);
517
518	for (i = 0; i < 25; i++) {
519	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
520	dc_delay(sc);
521	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
522	dc_delay(sc);
523	}
524
525	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
526	dc_delay(sc);
527	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
528	dc_delay(sc);
529	CSR_WRITE_4(sc, DC_SIO, 0x00000000);
530
531	return;
532	}
533
534	/*
535	* Send a read command and address to the EEPROM, check for ACK.
536	*/
537	static void dc_eeprom_putbyte(sc, addr)
538	struct dc_softc *sc;
539	int addr;
540	{
541	register int d, i;
542
543	d = DC_EECMD_READ >> 6;
544	for (i = 3; i--; ) {
545	if (d & (1 << i))
546	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
547	else
548	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
549	dc_delay(sc);
550	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
551	dc_delay(sc);
552	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
553	dc_delay(sc);
554	}
555
556	/*
557	* Feed in each bit and strobe the clock.
558	*/
559	for (i = sc->dc_romwidth; i--;) {
560	if (addr & (1 << i)) {
561	SIO_SET(DC_SIO_EE_DATAIN);
562	} else {
563	SIO_CLR(DC_SIO_EE_DATAIN);
564	}
565	dc_delay(sc);
566	SIO_SET(DC_SIO_EE_CLK);
567	dc_delay(sc);
568	SIO_CLR(DC_SIO_EE_CLK);
569	dc_delay(sc);
570	}
571
572	return;
573	}
574
575	/*
576	* Read a word of data stored in the EEPROM at address 'addr.'
577	* The PNIC 82c168/82c169 has its own non-standard way to read
578	* the EEPROM.
579	*/
580	static void dc_eeprom_getword_pnic(sc, addr, dest)
581	struct dc_softc *sc;
582	int addr;
583	u_int16_t *dest;
584	{
585	register int i;
586	u_int32_t r;
587
588	CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ\|addr);
589
590	for (i = 0; i < DC_TIMEOUT; i++) {
591	DELAY(1);
592	r = CSR_READ_4(sc, DC_SIO);
593	if (!(r & DC_PN_SIOCTL_BUSY)) {
594	*dest = (u_int16_t)(r & 0xFFFF);
595	return;
596	}
597	}
598
599	return;
600	}
601
602	/*
603	* Read a word of data stored in the EEPROM at address 'addr.'
604	*/
605	static void dc_eeprom_getword(sc, addr, dest)
606	struct dc_softc *sc;
607	int addr;
608	u_int16_t *dest;
609	{
610	register int i;
611	u_int16_t word = 0;
612
613	/* Force EEPROM to idle state. */
614	dc_eeprom_idle(sc);
615
616	/* Enter EEPROM access mode. */
617	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
618	dc_delay(sc);
619	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
620	dc_delay(sc);
621	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
622	dc_delay(sc);
623	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
624	dc_delay(sc);
625
626	/*
627	* Send address of word we want to read.
628	*/
629	dc_eeprom_putbyte(sc, addr);
630
631	/*
632	* Start reading bits from EEPROM.
633	*/
634	for (i = 0x8000; i; i >>= 1) {
635	SIO_SET(DC_SIO_EE_CLK);
636	dc_delay(sc);
637	if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
638	word \|= i;
639	dc_delay(sc);
640	SIO_CLR(DC_SIO_EE_CLK);
641	dc_delay(sc);
642	}
643
644	/* Turn off EEPROM access mode. */
645	dc_eeprom_idle(sc);
646
647	*dest = word;
648
649	return;
650	}
651
652	/*
653	* Read a sequence of words from the EEPROM.
654	*/
655	static void dc_read_eeprom(sc, dest, off, cnt, swap)
656	struct dc_softc *sc;
657	caddr_t dest;
658	int off;
659	int cnt;
660	int swap;
661	{
662	int i;
663	u_int16_t word = 0, *ptr;
664
665	for (i = 0; i < cnt; i++) {
666	if (DC_IS_PNIC(sc))
667	dc_eeprom_getword_pnic(sc, off + i, &word);
668	else
669	dc_eeprom_getword(sc, off + i, &word);
670	ptr = (u_int16_t )(dest + (i 2));
671	if (swap)
672	*ptr = ntohs(word);
673	else
674	*ptr = word;
675	}
676
677	return;
678	}
679
680
681	#if 0
682	/*
683	* The following two routines are taken from the Macronix 98713
684	* Application Notes pp.19-21.
685	*/
686	/*
687	* Write a bit to the MII bus.
688	*/
689	static void dc_mii_writebit(sc, bit)
690	struct dc_softc *sc;
691	int bit;
692	{
693	if (bit)
694	CSR_WRITE_4(sc, DC_SIO,
695	DC_SIO_ROMCTL_WRITE\|DC_SIO_MII_DATAOUT);
696	else
697	CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
698
699	DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
700	DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
701
702	return;
703	}
704
705	/*
706	* Read a bit from the MII bus.
707	*/
708	static int dc_mii_readbit(sc)
709	struct dc_softc *sc;
710	{
711	CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ\|DC_SIO_MII_DIR);
712	CSR_READ_4(sc, DC_SIO);
713	DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
714	DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
715	if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
716	return(1);
717
718	return(0);
719	}
720
721	/*
722	* Sync the PHYs by setting data bit and strobing the clock 32 times.
723	*/
724	static void dc_mii_sync(sc)
725	struct dc_softc *sc;
726	{
727	register int i;
728
729	CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
730
731	for (i = 0; i < 32; i++)
732	dc_mii_writebit(sc, 1);
733
734	return;
735	}
736
737	/*
738	* Clock a series of bits through the MII.
739	*/
740	static void dc_mii_send(sc, bits, cnt)
741	struct dc_softc *sc;
742	u_int32_t bits;
743	int cnt;
744	{
745	int i;
746
747	for (i = (0x1 << (cnt - 1)); i; i >>= 1)
748	dc_mii_writebit(sc, bits & i);
749	}
750
751	/*
752	* Read an PHY register through the MII.
753	*/
754	static int dc_mii_readreg(sc, frame)
755	struct dc_softc *sc;
756	struct dc_mii_frame *frame;
757
758	{
759	int i, ack, s;
760
761
762	/*
763	* Set up frame for RX.
764	*/
765	frame->mii_stdelim = DC_MII_STARTDELIM;
766	frame->mii_opcode = DC_MII_READOP;
767	frame->mii_turnaround = 0;
768	frame->mii_data = 0;
769
770	/*
771	* Sync the PHYs.
772	*/
773	dc_mii_sync(sc);
774
775	/*
776	* Send command/address info.
777	*/
778	dc_mii_send(sc, frame->mii_stdelim, 2);
779	dc_mii_send(sc, frame->mii_opcode, 2);
780	dc_mii_send(sc, frame->mii_phyaddr, 5);
781	dc_mii_send(sc, frame->mii_regaddr, 5);
782
783	#ifdef notdef
784	/* Idle bit */
785	dc_mii_writebit(sc, 1);
786	dc_mii_writebit(sc, 0);
787	#endif
788
789	/* Check for ack */
790	ack = dc_mii_readbit(sc);
791
792	/*
793	* Now try reading data bits. If the ack failed, we still
794	* need to clock through 16 cycles to keep the PHY(s) in sync.
795	*/
796	if (ack) {
797	for(i = 0; i < 16; i++) {
798	dc_mii_readbit(sc);
799	}
800	goto fail;
801	}
802
803	for (i = 0x8000; i; i >>= 1) {
804	if (!ack) {
805	if (dc_mii_readbit(sc))
806	frame->mii_data \|= i;
807	}
808	}
809
810	fail:
811
812	dc_mii_writebit(sc, 0);
813	dc_mii_writebit(sc, 0);
814
815
816	if (ack)
817	return(1);
818	return(0);
819	}
820
821	/*
822	* Write to a PHY register through the MII.
823	*/
824	static int dc_mii_writereg(sc, frame)
825	struct dc_softc *sc;
826	struct dc_mii_frame *frame;
827
828	{
829	int s;
830
831	/*
832	* Set up frame for TX.
833	*/
834
835	frame->mii_stdelim = DC_MII_STARTDELIM;
836	frame->mii_opcode = DC_MII_WRITEOP;
837	frame->mii_turnaround = DC_MII_TURNAROUND;
838
839	/*
840	* Sync the PHYs.
841	*/
842	dc_mii_sync(sc);
843
844	dc_mii_send(sc, frame->mii_stdelim, 2);
845	dc_mii_send(sc, frame->mii_opcode, 2);
846	dc_mii_send(sc, frame->mii_phyaddr, 5);
847	dc_mii_send(sc, frame->mii_regaddr, 5);
848	dc_mii_send(sc, frame->mii_turnaround, 2);
849	dc_mii_send(sc, frame->mii_data, 16);
850
851	/* Idle bit. */
852	dc_mii_writebit(sc, 0);
853	dc_mii_writebit(sc, 0);
854
855
856	return(0);
857	}
858
859	static int dc_miibus_readreg(dev, phy, reg)
860	device_t dev;
861	int phy, reg;
862	{
863	struct dc_mii_frame frame;
864	struct dc_softc *sc;
865	int i, rval, phy_reg = 0;
866
867	sc = device_get_softc(dev);
868	bzero((char *)&frame, sizeof(frame));
869
870	/*
871	* Note: both the AL981 and AN985 have internal PHYs,
872	* however the AL981 provides direct access to the PHY
873	* registers while the AN985 uses a serial MII interface.
874	* The AN985's MII interface is also buggy in that you
875	* can read from any MII address (0 to 31), but only address 1
876	* behaves normally. To deal with both cases, we pretend
877	* that the PHY is at MII address 1.
878	*/
879	if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
880	return(0);
881
882	/*
883	* Note: the ukphy probes of the RS7112 report a PHY at
884	* MII address 0 (possibly HomePNA?) and 1 (ethernet)
885	* so we only respond to correct one.
886	*/
887	if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
888	return(0);
889
890	if (sc->dc_pmode != DC_PMODE_MII) {
891	if (phy == (MII_NPHY - 1)) {
892	switch(reg) {
893	case MII_BMSR:
894	/*
895	* Fake something to make the probe
896	* code think there's a PHY here.
897	*/
898	return(BMSR_MEDIAMASK);
899	break;
900	case MII_PHYIDR1:
901	if (DC_IS_PNIC(sc))
902	return(DC_VENDORID_LO);
903	return(DC_VENDORID_DEC);
904	break;
905	case MII_PHYIDR2:
906	if (DC_IS_PNIC(sc))
907	return(DC_DEVICEID_82C168);
908	return(DC_DEVICEID_21143);
909	break;
910	default:
911	return(0);
912	break;
913	}
914	} else
915	return(0);
916	}
917
918	if (DC_IS_PNIC(sc)) {
919	CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ \|
920	(phy << 23) \| (reg << 18));
921	for (i = 0; i < DC_TIMEOUT; i++) {
922	DELAY(1);
923	rval = CSR_READ_4(sc, DC_PN_MII);
924	if (!(rval & DC_PN_MII_BUSY)) {
925	rval &= 0xFFFF;
926	return(rval == 0xFFFF ? 0 : rval);
927	}
928	}
929	return(0);
930	}
931
932	if (DC_IS_COMET(sc)) {
933	switch(reg) {
934	case MII_BMCR:
935	phy_reg = DC_AL_BMCR;
936	break;
937	case MII_BMSR:
938	phy_reg = DC_AL_BMSR;
939	break;
940	case MII_PHYIDR1:
941	phy_reg = DC_AL_VENID;
942	break;
943	case MII_PHYIDR2:
944	phy_reg = DC_AL_DEVID;
945	break;
946	case MII_ANAR:
947	phy_reg = DC_AL_ANAR;
948	break;
949	case MII_ANLPAR:
950	phy_reg = DC_AL_LPAR;
951	break;
952	case MII_ANER:
953	phy_reg = DC_AL_ANER;
954	break;
955	default:
956	printk("dc%d: phy_read: bad phy register %x\n",
957	sc->dc_unit, reg);
958	return(0);
959	break;
960	}
961
962	rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
963
964	if (rval == 0xFFFF)
965	return(0);
966	return(rval);
967	}
968
969	frame.mii_phyaddr = phy;
970	frame.mii_regaddr = reg;
971	if (sc->dc_type == DC_TYPE_98713) {
972	phy_reg = CSR_READ_4(sc, DC_NETCFG);
973	CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
974	}
975	dc_mii_readreg(sc, &frame);
976	if (sc->dc_type == DC_TYPE_98713)
977	CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
978
979	return(frame.mii_data);
980	}
981
982	static int dc_miibus_writereg(dev, phy, reg, data)
983	device_t dev;
984	int phy, reg, data;
985	{
986	struct dc_softc *sc;
987	struct dc_mii_frame frame;
988	int i, phy_reg = 0;
989
990	sc = device_get_softc(dev);
991	bzero((char *)&frame, sizeof(frame));
992
993	if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
994	return(0);
995
996	if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
997	return(0);
998
999	if (DC_IS_PNIC(sc)) {
1000	CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE \|
1001	(phy << 23) \| (reg << 10) \| data);
1002	for (i = 0; i < DC_TIMEOUT; i++) {
1003	if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
1004	break;
1005	}
1006	return(0);
1007	}
1008
1009	if (DC_IS_COMET(sc)) {
1010	switch(reg) {
1011	case MII_BMCR:
1012	phy_reg = DC_AL_BMCR;
1013	break;
1014	case MII_BMSR:
1015	phy_reg = DC_AL_BMSR;
1016	break;
1017	case MII_PHYIDR1:
1018	phy_reg = DC_AL_VENID;
1019	break;
1020	case MII_PHYIDR2:
1021	phy_reg = DC_AL_DEVID;
1022	break;
1023	case MII_ANAR:
1024	phy_reg = DC_AL_ANAR;
1025	break;
1026	case MII_ANLPAR:
1027	phy_reg = DC_AL_LPAR;
1028	break;
1029	case MII_ANER:
1030	phy_reg = DC_AL_ANER;
1031	break;
1032	default:
1033	printk("dc%d: phy_write: bad phy register %x\n",
1034	sc->dc_unit, reg);
1035	return(0);
1036	break;
1037	}
1038
1039	CSR_WRITE_4(sc, phy_reg, data);
1040	return(0);
1041	}
1042
1043	frame.mii_phyaddr = phy;
1044	frame.mii_regaddr = reg;
1045	frame.mii_data = data;
1046
1047	if (sc->dc_type == DC_TYPE_98713) {
1048	phy_reg = CSR_READ_4(sc, DC_NETCFG);
1049	CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
1050	}
1051	dc_mii_writereg(sc, &frame);
1052	if (sc->dc_type == DC_TYPE_98713)
1053	CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
1054
1055	return(0);
1056	}
1057
1058	static void dc_miibus_statchg(dev)
1059	device_t dev;
1060	{
1061	struct dc_softc *sc;
1062	struct mii_data *mii;
1063	struct ifmedia *ifm;
1064
1065	sc = device_get_softc(dev);
1066	if (DC_IS_ADMTEK(sc))
1067	return;
1068
1069	mii = device_get_softc(sc->dc_miibus);
1070	ifm = &mii->mii_media;
1071	if (DC_IS_DAVICOM(sc) &&
1072	IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) {
1073	dc_setcfg(sc, ifm->ifm_media);
1074	sc->dc_if_media = ifm->ifm_media;
1075	} else {
1076	dc_setcfg(sc, mii->mii_media_active);
1077	sc->dc_if_media = mii->mii_media_active;
1078	}
1079
1080	return;
1081	}
1082
1083	/*
1084	* Special support for DM9102A cards with HomePNA PHYs. Note:
1085	* with the Davicom DM9102A/DM9801 eval board that I have, it seems
1086	* to be impossible to talk to the management interface of the DM9801
1087	* PHY (its MDIO pin is not connected to anything). Consequently,
1088	* the driver has to just 'know' about the additional mode and deal
1089	* with it itself. sigh
1090	*/
1091	static void dc_miibus_mediainit(dev)
1092	device_t dev;
1093	{
1094	struct dc_softc *sc;
1095	struct mii_data *mii;
1096	struct ifmedia *ifm;
1097	int rev;
1098
1099	rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF;
1100
1101	sc = device_get_softc(dev);
1102	mii = device_get_softc(sc->dc_miibus);
1103	ifm = &mii->mii_media;
1104
1105	if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
1106	ifmedia_add(ifm, IFM_ETHER\|IFM_homePNA, 0, NULL);
1107
1108	return;
1109	}
1110	#endif
1111
1112	#define DC_POLY 0xEDB88320
1113	#define DC_BITS_512 9
1114	#define DC_BITS_128 7
1115	#define DC_BITS_64 6
1116
1117	static u_int32_t dc_crc_le(sc, addr)
1118	struct dc_softc *sc;
1119	caddr_t addr;
1120	{
1121	u_int32_t idx, bit, data, crc;
1122
1123	/* Compute CRC for the address value. */
1124	crc = 0xFFFFFFFF; /* initial value */
1125
1126	for (idx = 0; idx < 6; idx++) {
1127	for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
1128	crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0);
1129	}
1130
1131	/*
1132	* The hash table on the PNIC II and the MX98715AEC-C/D/E
1133	* chips is only 128 bits wide.
1134	*/
1135	if (sc->dc_flags & DC_128BIT_HASH)
1136	return (crc & ((1 << DC_BITS_128) - 1));
1137
1138	/* The hash table on the MX98715BEC is only 64 bits wide. */
1139	if (sc->dc_flags & DC_64BIT_HASH)
1140	return (crc & ((1 << DC_BITS_64) - 1));
1141
1142	return (crc & ((1 << DC_BITS_512) - 1));
1143	}
1144
1145	#ifndef UNUSED
1146	/*
1147	* Calculate CRC of a multicast group address, return the lower 6 bits.
1148	*/
1149	static u_int32_t dc_crc_be(addr)
1150	caddr_t addr;
1151	{
1152	u_int32_t crc, carry;
1153	int i, j;
1154	u_int8_t c;
1155
1156	/* Compute CRC for the address value. */
1157	crc = 0xFFFFFFFF; /* initial value */
1158
1159	for (i = 0; i < 6; i++) {
1160	c = *(addr + i);
1161	for (j = 0; j < 8; j++) {
1162	carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
1163	crc <<= 1;
1164	c >>= 1;
1165	if (carry)
1166	crc = (crc ^ 0x04c11db6) \| carry;
1167	}
1168	}
1169
1170	/* return the filter bit position */
1171	return((crc >> 26) & 0x0000003F);
1172	}
1173	#endif
1174
1175	/*
1176	* 21143-style RX filter setup routine. Filter programming is done by
1177	* downloading a special setup frame into the TX engine. 21143, Macronix,
1178	* PNIC, PNIC II and Davicom chips are programmed this way.
1179	*
1180	* We always program the chip using 'hash perfect' mode, i.e. one perfect
1181	* address (our node address) and a 512-bit hash filter for multicast
1182	* frames. We also sneak the broadcast address into the hash filter since
1183	* we need that too.
1184	*/
1185	void dc_setfilt_21143(sc)
1186	struct dc_softc *sc;
1187	{
1188	struct dc_desc *sframe;
1189	u_int32_t h, *sp;
1190	/struct ifmultiaddr ifma;*/
1191	struct ifnet *ifp;
1192	int i;
1193	u_int16_t *ac_enaddr;
1194
1195	ifp = &sc->arpcom.ac_if;
1196
1197	i = sc->dc_cdata.dc_tx_prod;
1198	DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1199	sc->dc_cdata.dc_tx_cnt++;
1200	sframe = &sc->dc_ldata->dc_tx_list[i];
1201	sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf;
1202	bzero((char *)sp, DC_SFRAME_LEN);
1203
1204	sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf);
1205	sframe->dc_ctl = DC_SFRAME_LEN \| DC_TXCTL_SETUP \| DC_TXCTL_TLINK \|
1206	DC_FILTER_HASHPERF \| DC_TXCTL_FINT;
1207
1208	sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf;
1209
1210	/* If we want promiscuous mode, set the allframes bit. */
1211	if (ifp->if_flags & IFF_PROMISC)
1212	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1213	else
1214	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1215
1216	if (ifp->if_flags & IFF_ALLMULTI)
1217	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1218	else
1219	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1220	#if 0
1221	for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1222	ifma = ifma->ifma_link.le_next) {
1223	if (ifma->ifma_addr->sa_family != AF_LINK)
1224	continue;
1225	h = dc_crc_le(sc,
1226	LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1227	sp[h >> 4] \|= 1 << (h & 0xF);
1228	}
1229	#endif
1230
1231	if (ifp->if_flags & IFF_BROADCAST) {
1232	h = dc_crc_le(sc, (caddr_t)&etherbroadcastaddr);
1233	sp[h >> 4] \|= 1 << (h & 0xF);
1234	}
1235
1236	/* Set our MAC address */
1237	ac_enaddr = (u_int16_t *)sc->arpcom.ac_enaddr;
1238	sp[39] = ac_enaddr[0];
1239	sp[40] = ac_enaddr[1];
1240	sp[41] = ac_enaddr[2];
1241
1242	sframe->dc_status = DC_TXSTAT_OWN;
1243	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1244
1245	/*
1246	* The PNIC takes an exceedingly long time to process its
1247	* setup frame; wait 10ms after posting the setup frame
1248	* before proceeding, just so it has time to swallow its
1249	* medicine.
1250	*/
1251	DELAY(10000);
1252
1253	ifp->if_timer = 5;
1254
1255	return;
1256	}
1257
1258	void dc_setfilt_admtek(sc)
1259	struct dc_softc *sc;
1260	{
1261	struct ifnet *ifp;
1262	#if 0
1263	int h = 0;
1264	u_int32_t hashes[2] = { 0, 0 };
1265	struct ifmultiaddr *ifma;
1266	#endif
1267	u_int32_t *ac_enaddr;
1268
1269	ifp = &sc->arpcom.ac_if;
1270
1271	/* Init our MAC address */
1272	ac_enaddr = (u_int32_t *)&sc->arpcom.ac_enaddr[0];
1273	CSR_WRITE_4(sc, DC_AL_PAR0, *ac_enaddr);
1274	ac_enaddr = (u_int32_t *)&sc->arpcom.ac_enaddr[4];
1275	CSR_WRITE_4(sc, DC_AL_PAR1, *ac_enaddr);
1276
1277	/* If we want promiscuous mode, set the allframes bit. */
1278	if (ifp->if_flags & IFF_PROMISC)
1279	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1280	else
1281	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1282
1283	if (ifp->if_flags & IFF_ALLMULTI)
1284	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1285	else
1286	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1287
1288	/* first, zot all the existing hash bits */
1289	CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1290	CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1291
1292	#if 0
1293	/*
1294	* If we're already in promisc or allmulti mode, we
1295	* don't have to bother programming the multicast filter.
1296	*/
1297	if (ifp->if_flags & (IFF_PROMISC\|IFF_ALLMULTI))
1298	return;
1299
1300	/* now program new ones */
1301	for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1302	ifma = ifma->ifma_link.le_next) {
1303	if (ifma->ifma_addr->sa_family != AF_LINK)
1304	continue;
1305	h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1306	if (h < 32)
1307	hashes[0] \|= (1 << h);
1308	else
1309	hashes[1] \|= (1 << (h - 32));
1310	}
1311
1312	CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1313	CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1314	#endif
1315	return;
1316	}
1317
1318	void dc_setfilt_asix(sc)
1319	struct dc_softc *sc;
1320	{
1321	struct ifnet *ifp;
1322	#if 0
1323	int h = 0;
1324	u_int32_t hashes[2] = { 0, 0 };
1325	struct ifmultiaddr *ifma;
1326	#endif
1327	u_int32_t *ac_enaddr;
1328
1329	ifp = &sc->arpcom.ac_if;
1330
1331	/* Init our MAC address */
1332	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1333	ac_enaddr = (u_int32_t *)&sc->arpcom.ac_enaddr[0];
1334	CSR_WRITE_4(sc, DC_AX_FILTDATA, *ac_enaddr);
1335
1336	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1337
1338	ac_enaddr = (u_int32_t *)&sc->arpcom.ac_enaddr[4];
1339	CSR_WRITE_4(sc, DC_AX_FILTDATA, *ac_enaddr);
1340
1341	/* If we want promiscuous mode, set the allframes bit. */
1342	if (ifp->if_flags & IFF_PROMISC)
1343	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1344	else
1345	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1346
1347	if (ifp->if_flags & IFF_ALLMULTI)
1348	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1349	else
1350	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1351
1352	/*
1353	* The ASIX chip has a special bit to enable reception
1354	* of broadcast frames.
1355	*/
1356	if (ifp->if_flags & IFF_BROADCAST)
1357	DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1358	else
1359	DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1360
1361	/* first, zot all the existing hash bits */
1362	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1363	CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1364	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1365	CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1366
1367	#if 0
1368	/*
1369	* If we're already in promisc or allmulti mode, we
1370	* don't have to bother programming the multicast filter.
1371	*/
1372	if (ifp->if_flags & (IFF_PROMISC\|IFF_ALLMULTI))
1373	return;
1374
1375	/* now program new ones */
1376	for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1377	ifma = ifma->ifma_link.le_next) {
1378	if (ifma->ifma_addr->sa_family != AF_LINK)
1379	continue;
1380	h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1381	if (h < 32)
1382	hashes[0] \|= (1 << h);
1383	else
1384	hashes[1] \|= (1 << (h - 32));
1385	}
1386
1387	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1388	CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1389	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1390	CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1391	#endif
1392	return;
1393	}
1394
1395	static void dc_setfilt(sc)
1396	struct dc_softc *sc;
1397	{
1398	if (DC_IS_INTEL(sc) \|\| DC_IS_MACRONIX(sc) \|\| DC_IS_PNIC(sc) \|\|
1399	DC_IS_PNICII(sc) \|\| DC_IS_DAVICOM(sc) \|\| DC_IS_CONEXANT(sc))
1400	dc_setfilt_21143(sc);
1401
1402	if (DC_IS_ASIX(sc))
1403	dc_setfilt_asix(sc);
1404
1405	if (DC_IS_ADMTEK(sc))
1406	dc_setfilt_admtek(sc);
1407
1408	return;
1409	}
1410
1411	/*
1412	* In order to fiddle with the
1413	* 'full-duplex' and '100Mbps' bits in the netconfig register, we
1414	* first have to put the transmit and/or receive logic in the idle state.
1415	*/
1416	static void dc_setcfg(sc, media)
1417	struct dc_softc *sc;
1418	int media;
1419	{
1420	int i, restart = 0;
1421	u_int32_t isr;
1422
1423	if (IFM_SUBTYPE(media) == IFM_NONE)
1424	return;
1425
1426	if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON\|DC_NETCFG_RX_ON)) {
1427	restart = 1;
1428	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON\|DC_NETCFG_RX_ON));
1429
1430	for (i = 0; i < DC_TIMEOUT; i++) {
1431	isr = CSR_READ_4(sc, DC_ISR);
1432	if (isr & DC_ISR_TX_IDLE \|\|
1433	(isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED)
1434	break;
1435	DELAY(10);
1436	}
1437
1438	if (i == DC_TIMEOUT)
1439	printk("dc%d: failed to force tx and "
1440	"rx to idle state\n", sc->dc_unit);
1441	}
1442
1443	if (IFM_SUBTYPE(media) == IFM_100_TX) {
1444	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1445	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1446	if (sc->dc_pmode == DC_PMODE_MII) {
1447	int watchdogreg;
1448
1449	if (DC_IS_INTEL(sc)) {
1450	/* there's a write enable bit here that reads as 1 */
1451	watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1452	watchdogreg &= ~DC_WDOG_CTLWREN;
1453	watchdogreg \|= DC_WDOG_JABBERDIS;
1454	CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1455	} else {
1456	DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1457	}
1458	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS\|
1459	DC_NETCFG_PORTSEL\|DC_NETCFG_SCRAMBLER));
1460	if (sc->dc_type == DC_TYPE_98713)
1461	DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS\|
1462	DC_NETCFG_SCRAMBLER));
1463	if (!DC_IS_DAVICOM(sc))
1464	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1465	DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1466	if (DC_IS_INTEL(sc))
1467	dc_apply_fixup(sc, IFM_AUTO);
1468	} else {
1469	if (DC_IS_PNIC(sc)) {
1470	DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1471	DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1472	DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1473	}
1474	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1475	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1476	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1477	if (DC_IS_INTEL(sc))
1478	dc_apply_fixup(sc,
1479	(media & IFM_GMASK) == IFM_FDX ?
1480	IFM_100_TX\|IFM_FDX : IFM_100_TX);
1481	}
1482	}
1483
1484	if (IFM_SUBTYPE(media) == IFM_10_T) {
1485	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1486	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1487	if (sc->dc_pmode == DC_PMODE_MII) {
1488	int watchdogreg;
1489
1490	/* there's a write enable bit here that reads as 1 */
1491	if (DC_IS_INTEL(sc)) {
1492	watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1493	watchdogreg &= ~DC_WDOG_CTLWREN;
1494	watchdogreg \|= DC_WDOG_JABBERDIS;
1495	CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1496	} else {
1497	DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1498	}
1499	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS\|
1500	DC_NETCFG_PORTSEL\|DC_NETCFG_SCRAMBLER));
1501	if (sc->dc_type == DC_TYPE_98713)
1502	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1503	if (!DC_IS_DAVICOM(sc))
1504	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1505	DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1506	if (DC_IS_INTEL(sc))
1507	dc_apply_fixup(sc, IFM_AUTO);
1508	} else {
1509	if (DC_IS_PNIC(sc)) {
1510	DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1511	DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1512	DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1513	}
1514	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1515	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1516	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1517	if (DC_IS_INTEL(sc)) {
1518	DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1519	DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1520	if ((media & IFM_GMASK) == IFM_FDX)
1521	DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1522	else
1523	DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1524	DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1525	DC_CLRBIT(sc, DC_10BTCTRL,
1526	DC_TCTL_AUTONEGENBL);
1527	dc_apply_fixup(sc,
1528	(media & IFM_GMASK) == IFM_FDX ?
1529	IFM_10_T\|IFM_FDX : IFM_10_T);
1530	DELAY(20000);
1531	}
1532	}
1533	}
1534
1535	#if 0
1536	/*
1537	* If this is a Davicom DM9102A card with a DM9801 HomePNA
1538	* PHY and we want HomePNA mode, set the portsel bit to turn
1539	* on the external MII port.
1540	*/
1541	if (DC_IS_DAVICOM(sc)) {
1542	if (IFM_SUBTYPE(media) == IFM_homePNA) {
1543	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1544	sc->dc_link = 1;
1545	} else {
1546	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1547	}
1548	}
1549	#endif
1550
1551	if ((media & IFM_GMASK) == IFM_FDX) {
1552	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1553	if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1554	DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1555	} else {
1556	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1557	if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1558	DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1559	}
1560
1561	if (restart)
1562	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON\|DC_NETCFG_RX_ON);
1563
1564	return;
1565	}
1566
1567	static void dc_reset(sc)
1568	struct dc_softc *sc;
1569	{
1570	register int i;
1571
1572	DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1573
1574	for (i = 0; i < DC_TIMEOUT; i++) {
1575	DELAY(10);
1576	if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1577	break;
1578	}
1579
1580	if (DC_IS_ASIX(sc) \|\| DC_IS_ADMTEK(sc) \|\| DC_IS_CONEXANT(sc)) {
1581	DELAY(10000);
1582	DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1583	i = 0;
1584	}
1585
1586	if (i == DC_TIMEOUT)
1587	printk("dc%d: reset never completed!\n", sc->dc_unit);
1588
1589	/* Wait a little while for the chip to get its brains in order. */
1590	DELAY(1000);
1591
1592	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1593	CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1594	CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1595
1596	/*
1597	* Bring the SIA out of reset. In some cases, it looks
1598	* like failing to unreset the SIA soon enough gets it
1599	* into a state where it will never come out of reset
1600	* until we reset the whole chip again.
1601	*/
1602	if (DC_IS_INTEL(sc)) {
1603	DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1604	CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1605	CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1606	}
1607
1608	return;
1609	}
1610
1611	static
1612	struct dc_type *dc_devtype( int unitnum )
1613	{
1614	struct dc_type *t;
1615	uint32_t rev;
1616	int rc;
1617
1618
1619	t = dc_devs;
1620
1621	while(t->dc_name != NULL) {
1622	rc = pci_find_device(t->dc_vid, t->dc_did, \
1623	(unitnum - 1), &t->dc_bus, &t->dc_dev, &t->dc_fun);
1624	if (rc == PCIB_ERR_SUCCESS) {
1625	/* Check the PCI revision */
1626	/pcib_conf_read32(t->dc_devsig, DC_PCI_CFRV, &rev); /
1627	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
1628	DC_PCI_CFRV, &rev);
1629	rev &= 0xFF;
1630
1631	if (t->dc_did == DC_DEVICEID_98713 &&
1632	rev >= DC_REVISION_98713A)
1633	t++;
1634	if (t->dc_did == DC_DEVICEID_98713_CP &&
1635	rev >= DC_REVISION_98713A)
1636	t++;
1637	if (t->dc_did == DC_DEVICEID_987x5 &&
1638	rev >= DC_REVISION_98715AEC_C)
1639	t++;
1640	if (t->dc_did == DC_DEVICEID_987x5 &&
1641	rev >= DC_REVISION_98725)
1642	t++;
1643	if (t->dc_did == DC_DEVICEID_AX88140A &&
1644	rev >= DC_REVISION_88141)
1645	t++;
1646	if (t->dc_did == DC_DEVICEID_82C168 &&
1647	rev >= DC_REVISION_82C169)
1648	t++;
1649	if (t->dc_did == DC_DEVICEID_DM9102 &&
1650	rev >= DC_REVISION_DM9102A)
1651	t++;
1652	return(t);
1653	}
1654	t++;
1655	}
1656
1657	return(NULL);
1658	}
1659
1660	#if 0
1661	/*
1662	* Probe for a 21143 or clone chip. Check the PCI vendor and device
1663	* IDs against our list and return a device name if we find a match.
1664	* We do a little bit of extra work to identify the exact type of
1665	* chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1666	* but different revision IDs. The same is true for 98715/98715A
1667	* chips and the 98725, as well as the ASIX and ADMtek chips. In some
1668	* cases, the exact chip revision affects driver behavior.
1669	*/
1670	static int dc_probe(dev)
1671	device_t dev;
1672	{
1673	struct dc_type *t;
1674
1675	t = dc_devtype(dev);
1676
1677	if (t != NULL) {
1678	device_set_desc(dev, t->dc_name);
1679	return(0);
1680	}
1681
1682	return(ENXIO);
1683	}
1684
1685
1686	static void dc_acpi(dev)
1687	device_t dev;
1688	{
1689	u_int32_t r, cptr;
1690	int unit;
1691
1692	unit = device_get_unit(dev);
1693
1694	/* Find the location of the capabilities block */
1695	cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF;
1696
1697	r = pci_read_config(dev, cptr, 4) & 0xFF;
1698	if (r == 0x01) {
1699
1700	r = pci_read_config(dev, cptr + 4, 4);
1701	if (r & DC_PSTATE_D3) {
1702	u_int32_t iobase, membase, irq;
1703
1704	/* Save important PCI config data. */
1705	iobase = pci_read_config(dev, DC_PCI_CFBIO, 4);
1706	membase = pci_read_config(dev, DC_PCI_CFBMA, 4);
1707	irq = pci_read_config(dev, DC_PCI_CFIT, 4);
1708
1709	/* Reset the power state. */
1710	printk("dc%d: chip is in D%d power mode "
1711	"-- setting to D0\n", unit, r & DC_PSTATE_D3);
1712	r &= 0xFFFFFFFC;
1713	pci_write_config(dev, cptr + 4, r, 4);
1714
1715	/* Restore PCI config data. */
1716	pci_write_config(dev, DC_PCI_CFBIO, iobase, 4);
1717	pci_write_config(dev, DC_PCI_CFBMA, membase, 4);
1718	pci_write_config(dev, DC_PCI_CFIT, irq, 4);
1719	}
1720	}
1721	return;
1722	}
1723	#endif
1724
1725
1726	static void dc_apply_fixup(sc, media)
1727	struct dc_softc *sc;
1728	int media;
1729	{
1730	struct dc_mediainfo *m;
1731	u_int8_t *p;
1732	int i;
1733	u_int32_t reg;
1734
1735	m = sc->dc_mi;
1736
1737	while (m != NULL) {
1738	if (m->dc_media == media)
1739	break;
1740	m = m->dc_next;
1741	}
1742
1743	if (m == NULL)
1744	return;
1745
1746	for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1747	reg = (p[0] \| (p[1] << 8)) << 16;
1748	CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1749	}
1750
1751	for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1752	reg = (p[0] \| (p[1] << 8)) << 16;
1753	CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1754	}
1755
1756	return;
1757	}
1758
1759	#if 0
1760	static void dc_decode_leaf_sia(sc, l)
1761	struct dc_softc *sc;
1762	struct dc_eblock_sia *l;
1763	{
1764	struct dc_mediainfo *m;
1765
1766	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1767	bzero(m, sizeof(struct dc_mediainfo));
1768	if (l->dc_sia_code == DC_SIA_CODE_10BT)
1769	m->dc_media = IFM_10_T;
1770
1771	if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX)
1772	m->dc_media = IFM_10_T\|IFM_FDX;
1773
1774	if (l->dc_sia_code == DC_SIA_CODE_10B2)
1775	m->dc_media = IFM_10_2;
1776
1777	if (l->dc_sia_code == DC_SIA_CODE_10B5)
1778	m->dc_media = IFM_10_5;
1779
1780	m->dc_gp_len = 2;
1781	m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl;
1782
1783	m->dc_next = sc->dc_mi;
1784	sc->dc_mi = m;
1785
1786	sc->dc_pmode = DC_PMODE_SIA;
1787
1788	return;
1789	}
1790
1791	static void dc_decode_leaf_sym(sc, l)
1792	struct dc_softc *sc;
1793	struct dc_eblock_sym *l;
1794	{
1795	struct dc_mediainfo *m;
1796
1797	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1798	bzero(m, sizeof(struct dc_mediainfo));
1799	if (l->dc_sym_code == DC_SYM_CODE_100BT)
1800	m->dc_media = IFM_100_TX;
1801
1802	if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1803	m->dc_media = IFM_100_TX\|IFM_FDX;
1804
1805	m->dc_gp_len = 2;
1806	m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
1807
1808	m->dc_next = sc->dc_mi;
1809	sc->dc_mi = m;
1810
1811	sc->dc_pmode = DC_PMODE_SYM;
1812
1813	return;
1814	}
1815
1816	static void dc_decode_leaf_mii(sc, l)
1817	struct dc_softc *sc;
1818	struct dc_eblock_mii *l;
1819	{
1820	u_int8_t *p;
1821	struct dc_mediainfo *m;
1822
1823	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1824	bzero(m, sizeof(struct dc_mediainfo));
1825	/* We abuse IFM_AUTO to represent MII. */
1826	m->dc_media = IFM_AUTO;
1827	m->dc_gp_len = l->dc_gpr_len;
1828
1829	p = (u_int8_t *)l;
1830	p += sizeof(struct dc_eblock_mii);
1831	m->dc_gp_ptr = p;
1832	p += 2 * l->dc_gpr_len;
1833	m->dc_reset_len = *p;
1834	p++;
1835	m->dc_reset_ptr = p;
1836
1837	m->dc_next = sc->dc_mi;
1838	sc->dc_mi = m;
1839
1840	return;
1841	}
1842	#endif
1843
1844	static void dc_read_srom(sc, bits)
1845	struct dc_softc *sc;
1846	int bits;
1847	{
1848	int size;
1849
1850	size = 2 << bits;
1851	sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT);
1852	dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1853	}
1854
1855	static void dc_parse_21143_srom(sc)
1856	struct dc_softc *sc;
1857	{
1858	struct dc_leaf_hdr *lhdr;
1859	struct dc_eblock_hdr *hdr;
1860	int i, loff;
1861	char *ptr;
1862
1863	loff = sc->dc_srom[27];
1864	lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1865
1866	ptr = (char *)lhdr;
1867	ptr += sizeof(struct dc_leaf_hdr) - 1;
1868	for (i = 0; i < lhdr->dc_mcnt; i++) {
1869	hdr = (struct dc_eblock_hdr *)ptr;
1870	switch(hdr->dc_type) {
1871	#if 0
1872	case DC_EBLOCK_MII:
1873	dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1874	break;
1875	case DC_EBLOCK_SIA:
1876	dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr);
1877	break;
1878	case DC_EBLOCK_SYM:
1879	dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr);
1880	break;
1881	#endif
1882	default:
1883	/* Don't care. Yet. */
1884	break;
1885	}
1886	ptr += (hdr->dc_len & 0x7F);
1887	ptr++;
1888	}
1889
1890	return;
1891	}
1892
1893
1894	static void
1895	nop(const rtems_irq_connect_data* unused)
1896	{
1897	}
1898
1899	static int
1900	decISON(const rtems_irq_connect_data* irq)
1901	{
1902	return (BSP_irq_enabled_at_i8259s(irq->name));
1903	}
1904
1905
1906	/*
1907	* Attach the interface. Allocate softc structures, do ifmedia
1908	* setup and ethernet/BPF attach.
1909	*/
1910	int
1911	rtems_dc_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching)
1912	{
1913	int rc;
1914	u_char eaddr[ETHER_ADDR_LEN];
1915
1916	char *unitName;
1917	int unitNumber;
1918
1919	uint32_t command;
1920	struct dc_softc *sc;
1921	struct ifnet *ifp;
1922	struct dc_type *t;
1923	uint32_t revision;
1924	int error = 0, mac_offset;
1925	uint32_t value;
1926
1927	/*
1928	* Get the instance number for the board we're going to configure
1929	* from the user.
1930	*/
1931	unitNumber = rtems_bsdnet_parse_driver_name(config, &unitName);
1932	if( unitNumber < 0) {
1933	return 0;
1934	}
1935	if( strcmp(unitName, DRIVER_PREFIX) ) {
1936	printk("dec2114x : unit name '%s' not %s\n", \
1937	unitName, DRIVER_PREFIX );
1938	return 0;
1939	}
1940
1941	sc = &dc_softc_devs[unitNumber - 1];
1942	ifp = &sc->arpcom.ac_if;
1943
1944	if(ifp->if_softc != NULL) {
1945	printk("dec2114x[%d]: unit number already in use.\n", \
1946	unitNumber);
1947	return (0);
1948	}
1949	memset(sc, 0, sizeof(struct dc_softc));
1950
1951	/unit = device_get_unit(dev);/
1952	sc->dc_unit = unitNumber;
1953	sc->dc_name = unitName;
1954
1955	/*
1956	* Handle power management nonsense.
1957	*
1958	dc_acpi(dev);
1959	*/
1960
1961	/* Scan for dec2114x cards in pci config space */
1962	if( (sc->dc_info = dc_devtype(unitNumber)) == NULL) {
1963	printk("Can't find any dec2114x NICs in PCI space.\n");
1964	return 0;
1965	}
1966	t = sc->dc_info;
1967
1968
1969	/*
1970	* Map control/status registers.
1971	*/
1972	/sig = sc->dc_info->dc_devsig; /
1973	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
1974	PCI_COMMAND, &command);
1975	/pcib_conf_read32(sig, PCI_COMMAND, &command); /
1976	command \|= (PCI_COMMAND_IO \| PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
1977	pci_write_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
1978	PCI_COMMAND, command);
1979	/pcib_conf_write32(sig, PCI_COMMAND, command); /
1980	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
1981	PCI_COMMAND, &command);
1982	/pcib_conf_read32(sig, PCI_COMMAND, &command); /
1983
1984	#ifdef DC_USEIOSPACE
1985	if (!(command & PCI_COMMAND_IO)) {
1986	printk("dc%d: failed to enable I/O ports!\n", sc->dc_unit);
1987	error = ENXIO;
1988	goto fail;
1989	}
1990	#else
1991	if (!(command & PCI_COMMAND_MEMORY)) {
1992	printk("dc%d: failed to enable memory mapping!\n", sc->dc_unit);
1993	error = ENXIO;
1994	goto fail;
1995	}
1996	#endif
1997
1998	#if 0
1999	rid = DC_RID;
2000	sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid,
2001	0, ~0, 1, RF_ACTIVE);
2002
2003	if (sc->dc_res == NULL) {
2004	printk("dc%d: couldn't map ports/memory\n", unit);
2005	error = ENXIO;
2006	goto fail;
2007	}
2008	sc->dc_btag = rman_get_bustag(sc->dc_res);
2009	sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
2010	#endif
2011
2012	/* sc->membase is the address of the card's CSRs !!! */
2013	/pcib_conf_read32(sig, DC_PCI_CFBMA, &value); /
2014	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2015	DC_PCI_CFBMA, &value);
2016	sc->membase = value;
2017
2018	/* Allocate interrupt */
2019	memset(&sc->irqInfo, 0, sizeof(rtems_irq_connect_data));
2020	/pcib_conf_read32(sig, DC_PCI_CFIT, &value); /
2021	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2022	DC_PCI_CFIT, &value);
2023
2024	sc->irqInfo.name = value & 0xFF;
2025	sc->irqInfo.hdl = (rtems_irq_hdl)dc_intr;
2026	sc->irqInfo.handle = (void )sc; / new parameter */
2027	sc->irqInfo.on = nop;
2028	sc->irqInfo.off = nop;
2029	sc->irqInfo.isOn = decISON;
2030
2031	#ifdef BSP_SHARED_HANDLER_SUPPORT
2032	rc = BSP_install_rtems_shared_irq_handler( &sc->irqInfo );
2033	#else
2034	rc = BSP_install_rtems_irq_handler( &sc->irqInfo );
2035	#endif
2036	if(!rc) {
2037	rtems_panic("Can't install dec2114x irq handler.\n");
2038	}
2039
2040
2041	#if 0
2042	rid = 0;
2043	sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
2044	RF_SHAREABLE \| RF_ACTIVE);
2045
2046	if (sc->dc_irq == NULL) {
2047	printk("dc%d: couldn't map interrupt\n", unit);
2048	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2049	error = ENXIO;
2050	goto fail;
2051	}
2052
2053	error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET,
2054	dc_intr, sc, &sc->dc_intrhand);
2055
2056	if (error) {
2057	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2058	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2059	printk("dc%d: couldn't set up irq\n", unit);
2060	goto fail;
2061	}
2062	#endif
2063
2064
2065	/* Need this info to decide on a chip type.
2066	sc->dc_info = dc_devtype(dev);
2067	*/
2068	/pcib_conf_read32(sig, DC_PCI_CFRV, &revision); /
2069	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2070	DC_PCI_CFRV, &revision);
2071	revision &= 0x000000FF;
2072
2073	/* Get the eeprom width, but PNIC has diff eeprom */
2074	if (sc->dc_info->dc_did != DC_DEVICEID_82C168)
2075	dc_eeprom_width(sc);
2076
2077	switch(sc->dc_info->dc_did) {
2078	case DC_DEVICEID_21143:
2079	sc->dc_type = DC_TYPE_21143;
2080	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR;
2081	sc->dc_flags \|= DC_REDUCED_MII_POLL;
2082	/* Save EEPROM contents so we can parse them later. */
2083	dc_read_srom(sc, sc->dc_romwidth);
2084	break;
2085	case DC_DEVICEID_DM9009:
2086	case DC_DEVICEID_DM9100:
2087	case DC_DEVICEID_DM9102:
2088	sc->dc_type = DC_TYPE_DM9102;
2089	sc->dc_flags \|= DC_TX_COALESCE\|DC_TX_INTR_ALWAYS;
2090	sc->dc_flags \|= DC_REDUCED_MII_POLL\|DC_TX_STORENFWD;
2091	sc->dc_pmode = DC_PMODE_MII;
2092	/* Increase the latency timer value. */
2093	/pcib_conf_read32(sig, DC_PCI_CFLT, &command); /
2094	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2095	DC_PCI_CFLT, &command);
2096	command &= 0xFFFF00FF;
2097	command \|= 0x00008000;
2098	/pcib_conf_write32(sig, DC_PCI_CFLT, command); /
2099	pci_write_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2100	DC_PCI_CFLT, command);
2101	break;
2102	case DC_DEVICEID_AL981:
2103	sc->dc_type = DC_TYPE_AL981;
2104	sc->dc_flags \|= DC_TX_USE_TX_INTR;
2105	sc->dc_flags \|= DC_TX_ADMTEK_WAR;
2106	sc->dc_pmode = DC_PMODE_MII;
2107	dc_read_srom(sc, sc->dc_romwidth);
2108	break;
2109	case DC_DEVICEID_AN985:
2110	case DC_DEVICEID_EN2242:
2111	sc->dc_type = DC_TYPE_AN985;
2112	sc->dc_flags \|= DC_TX_USE_TX_INTR;
2113	sc->dc_flags \|= DC_TX_ADMTEK_WAR;
2114	sc->dc_pmode = DC_PMODE_MII;
2115	dc_read_srom(sc, sc->dc_romwidth);
2116	break;
2117	case DC_DEVICEID_98713:
2118	case DC_DEVICEID_98713_CP:
2119	if (revision < DC_REVISION_98713A) {
2120	sc->dc_type = DC_TYPE_98713;
2121	}
2122	if (revision >= DC_REVISION_98713A) {
2123	sc->dc_type = DC_TYPE_98713A;
2124	sc->dc_flags \|= DC_21143_NWAY;
2125	}
2126	sc->dc_flags \|= DC_REDUCED_MII_POLL;
2127	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR;
2128	break;
2129	case DC_DEVICEID_987x5:
2130	case DC_DEVICEID_EN1217:
2131	/*
2132	* Macronix MX98715AEC-C/D/E parts have only a
2133	* 128-bit hash table. We need to deal with these
2134	* in the same manner as the PNIC II so that we
2135	* get the right number of bits out of the
2136	* CRC routine.
2137	*/
2138	if (revision >= DC_REVISION_98715AEC_C &&
2139	revision < DC_REVISION_98725)
2140	sc->dc_flags \|= DC_128BIT_HASH;
2141	sc->dc_type = DC_TYPE_987x5;
2142	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR;
2143	sc->dc_flags \|= DC_REDUCED_MII_POLL\|DC_21143_NWAY;
2144	break;
2145	case DC_DEVICEID_98727:
2146	sc->dc_type = DC_TYPE_987x5;
2147	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR;
2148	sc->dc_flags \|= DC_REDUCED_MII_POLL\|DC_21143_NWAY;
2149	break;
2150	case DC_DEVICEID_82C115:
2151	sc->dc_type = DC_TYPE_PNICII;
2152	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR\|DC_128BIT_HASH;
2153	sc->dc_flags \|= DC_REDUCED_MII_POLL\|DC_21143_NWAY;
2154	break;
2155	case DC_DEVICEID_82C168:
2156	sc->dc_type = DC_TYPE_PNIC;
2157	sc->dc_flags \|= DC_TX_STORENFWD\|DC_TX_INTR_ALWAYS;
2158	sc->dc_flags \|= DC_PNIC_RX_BUG_WAR;
2159	sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT);
2160	if (revision < DC_REVISION_82C169)
2161	sc->dc_pmode = DC_PMODE_SYM;
2162	break;
2163	case DC_DEVICEID_AX88140A:
2164	sc->dc_type = DC_TYPE_ASIX;
2165	sc->dc_flags \|= DC_TX_USE_TX_INTR\|DC_TX_INTR_FIRSTFRAG;
2166	sc->dc_flags \|= DC_REDUCED_MII_POLL;
2167	sc->dc_pmode = DC_PMODE_MII;
2168	break;
2169	case DC_DEVICEID_RS7112:
2170	sc->dc_type = DC_TYPE_CONEXANT;
2171	sc->dc_flags \|= DC_TX_INTR_ALWAYS;
2172	sc->dc_flags \|= DC_REDUCED_MII_POLL;
2173	sc->dc_pmode = DC_PMODE_MII;
2174	dc_read_srom(sc, sc->dc_romwidth);
2175	break;
2176	default:
2177	printk("dc%d: unknown device: %x\n", sc->dc_unit,
2178	sc->dc_info->dc_did);
2179	break;
2180	}
2181
2182	/* Save the cache line size. */
2183	if (DC_IS_DAVICOM(sc)) {
2184	sc->dc_cachesize = 0;
2185	}
2186	else {
2187	/pcib_conf_read32(sig, DC_PCI_CFLT, &value); /
2188	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2189	DC_PCI_CFLT, &value);
2190	sc->dc_cachesize = (u_int8_t)(value & 0xFF);
2191	}
2192
2193	/* Reset the adapter. */
2194	dc_reset(sc);
2195
2196	/* Take 21143 out of snooze mode */
2197	if (DC_IS_INTEL(sc)) {
2198	/pcib_conf_read32(sig, DC_PCI_CFDD, &command); /
2199	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2200	DC_PCI_CFDD, &command);
2201	command &= ~(DC_CFDD_SNOOZE_MODE\|DC_CFDD_SLEEP_MODE);
2202	/pcib_conf_write32(sig, DC_PCI_CFDD, command); /
2203	pci_write_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2204	DC_PCI_CFDD, command);
2205	}
2206
2207
2208	/*
2209	* Try to learn something about the supported media.
2210	* We know that ASIX and ADMtek and Davicom devices
2211	* will always be using MII media, so that's a no-brainer.
2212	* The tricky ones are the Macronix/PNIC II and the
2213	* Intel 21143.
2214	*/
2215	if (DC_IS_INTEL(sc))
2216	dc_parse_21143_srom(sc);
2217	else if (DC_IS_MACRONIX(sc) \|\| DC_IS_PNICII(sc)) {
2218	if (sc->dc_type == DC_TYPE_98713)
2219	sc->dc_pmode = DC_PMODE_MII;
2220	else
2221	sc->dc_pmode = DC_PMODE_SYM;
2222	} else if (!sc->dc_pmode)
2223	sc->dc_pmode = DC_PMODE_MII;
2224
2225	/*
2226	* Get station address from the EEPROM.
2227	*/
2228	switch(sc->dc_type) {
2229	case DC_TYPE_98713:
2230	case DC_TYPE_98713A:
2231	case DC_TYPE_987x5:
2232	case DC_TYPE_PNICII:
2233	dc_read_eeprom(sc, (caddr_t)&mac_offset,
2234	(DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2235	dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2236	break;
2237	case DC_TYPE_PNIC:
2238	dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2239	break;
2240	case DC_TYPE_DM9102:
2241	case DC_TYPE_21143:
2242	case DC_TYPE_ASIX:
2243	dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2244	break;
2245	case DC_TYPE_AL981:
2246	case DC_TYPE_AN985:
2247	bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr,
2248	ETHER_ADDR_LEN);
2249	dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0);
2250	break;
2251	case DC_TYPE_CONEXANT:
2252	bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6);
2253	break;
2254	default:
2255	dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2256	break;
2257	}
2258
2259	/*
2260	* A 21143 or clone chip was detected. Inform the world.
2261	*/
2262	bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
2263	printk("dc%d: MAC address -- %02x:%02x:%02x:%02x:%02x:%02x\n", \
2264	sc->dc_unit,sc->arpcom.ac_enaddr[0], \
2265	sc->arpcom.ac_enaddr[1], sc->arpcom.ac_enaddr[2], \
2266	sc->arpcom.ac_enaddr[3], sc->arpcom.ac_enaddr[4], \
2267	sc->arpcom.ac_enaddr[5]);
2268
2269
2270	sc->dc_ldata = malloc(sizeof(struct dc_list_data), M_DEVBUF, M_NOWAIT);
2271
2272	if (sc->dc_ldata == NULL) {
2273	printk("dc%d: no memory for list buffers!\n", sc->dc_unit);
2274	if (sc->dc_pnic_rx_buf != NULL)
2275	free(sc->dc_pnic_rx_buf, M_DEVBUF);
2276	#if 0
2277	bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2278	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2279	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2280	#endif
2281	error = ENXIO;
2282	goto fail;
2283	}
2284
2285	bzero(sc->dc_ldata, sizeof(struct dc_list_data));
2286
2287	ifp = &sc->arpcom.ac_if;
2288	ifp->if_softc = sc;
2289	ifp->if_unit = unitNumber; /sc->dc_unit;/
2290	ifp->if_name = unitName; /sc->dc_name;/
2291	ifp->if_mtu = ETHERMTU;
2292	ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX; /* \| IFF_MULTICAST;*/
2293	ifp->if_ioctl = dc_ioctl;
2294	ifp->if_output = ether_output;
2295	ifp->if_start = dc_start;
2296	ifp->if_watchdog = dc_watchdog;
2297	ifp->if_init = dc_init;
2298	ifp->if_baudrate = 100000000;
2299	ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1;
2300
2301	#if 0
2302	/*
2303	* Do MII setup. If this is a 21143, check for a PHY on the
2304	* MII bus after applying any necessary fixups to twiddle the
2305	* GPIO bits. If we don't end up finding a PHY, restore the
2306	* old selection (SIA only or SIA/SYM) and attach the dcphy
2307	* driver instead.
2308	*/
2309	if (DC_IS_INTEL(sc)) {
2310	dc_apply_fixup(sc, IFM_AUTO);
2311	tmp = sc->dc_pmode;
2312	sc->dc_pmode = DC_PMODE_MII;
2313	}
2314
2315	error = mii_phy_probe(dev, &sc->dc_miibus,
2316	dc_ifmedia_upd, dc_ifmedia_sts);
2317
2318	if (error && DC_IS_INTEL(sc)) {
2319	sc->dc_pmode = tmp;
2320	if (sc->dc_pmode != DC_PMODE_SIA)
2321	sc->dc_pmode = DC_PMODE_SYM;
2322	sc->dc_flags \|= DC_21143_NWAY;
2323	mii_phy_probe(dev, &sc->dc_miibus,
2324	dc_ifmedia_upd, dc_ifmedia_sts);
2325	/*
2326	* For non-MII cards, we need to have the 21143
2327	* drive the LEDs. Except there are some systems
2328	* like the NEC VersaPro NoteBook PC which have no
2329	* LEDs, and twiddling these bits has adverse effects
2330	* on them. (I.e. you suddenly can't get a link.)
2331	*/
2332	if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033)
2333	sc->dc_flags \|= DC_TULIP_LEDS;
2334	error = 0;
2335	}
2336
2337	if (error) {
2338	printk("dc%d: MII without any PHY!\n", sc->dc_unit);
2339	contigfree(sc->dc_ldata, sizeof(struct dc_list_data),
2340	M_DEVBUF);
2341	if (sc->dc_pnic_rx_buf != NULL)
2342	free(sc->dc_pnic_rx_buf, M_DEVBUF);
2343	bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2344	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2345	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2346	error = ENXIO;
2347	goto fail;
2348	}
2349	#endif
2350
2351	/*
2352	* Call MI attach routine.
2353	*/
2354	if_attach(ifp);
2355	ether_ifattach(ifp);
2356	/callout_handle_init(&sc->dc_stat_ch);/
2357
2358	if (DC_IS_ADMTEK(sc)) {
2359	/*
2360	* Set automatic TX underrun recovery for the ADMtek chips
2361	*/
2362	DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2363	}
2364
2365	if(sc->daemontid == 0) {
2366	sc->daemontid = rtems_bsdnet_newproc("decD",4096, \
2367	dc_daemon,(void *)sc);
2368	printk("dec[%d]: daemon process started\n", sc->dc_unit);
2369	}
2370
2371	/*
2372	* Tell the upper layer(s) we support long frames.
2373	*
2374	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2375	*/
2376
2377	#ifdef SRM_MEDIA /* only defined if __alpha__ is defined... */
2378	sc->dc_srm_media = 0;
2379
2380	/* Remember the SRM console media setting */
2381	if (DC_IS_INTEL(sc)) {
2382	command = pci_read_config(dev, DC_PCI_CFDD, 4);
2383	command &= ~(DC_CFDD_SNOOZE_MODE\|DC_CFDD_SLEEP_MODE);
2384	switch ((command >> 8) & 0xff) {
2385	case 3:
2386	sc->dc_srm_media = IFM_10_T;
2387	break;
2388	case 4:
2389	sc->dc_srm_media = IFM_10_T \| IFM_FDX;
2390	break;
2391	case 5:
2392	sc->dc_srm_media = IFM_100_TX;
2393	break;
2394	case 6:
2395	sc->dc_srm_media = IFM_100_TX \| IFM_FDX;
2396	break;
2397	}
2398	if (sc->dc_srm_media)
2399	sc->dc_srm_media \|= IFM_ACTIVE \| IFM_ETHER;
2400	}
2401	#endif
2402
2403
2404	fail:
2405
2406	return (1); /(error);/
2407	}
2408
2409	#if 0
2410	static int dc_detach(dev)
2411	device_t dev;
2412	{
2413	struct dc_softc *sc;
2414	struct ifnet *ifp;
2415	int s;
2416	struct dc_mediainfo *m;
2417
2418
2419	sc = device_get_softc(dev);
2420	ifp = &sc->arpcom.ac_if;
2421
2422	dc_stop(sc);
2423	ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
2424
2425	bus_generic_detach(dev);
2426	device_delete_child(dev, sc->dc_miibus);
2427
2428	bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2429	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2430	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2431
2432	contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF);
2433	if (sc->dc_pnic_rx_buf != NULL)
2434	free(sc->dc_pnic_rx_buf, M_DEVBUF);
2435
2436	while(sc->dc_mi != NULL) {
2437	m = sc->dc_mi->dc_next;
2438	free(sc->dc_mi, M_DEVBUF);
2439	sc->dc_mi = m;
2440	}
2441	free(sc->dc_srom, M_DEVBUF);
2442
2443
2444	return(0);
2445	}
2446	#endif
2447
2448
2449	/*
2450	* Initialize the transmit descriptors.
2451	*/
2452	static int dc_list_tx_init(sc)
2453	struct dc_softc *sc;
2454	{
2455	struct dc_chain_data *cd;
2456	struct dc_list_data *ld;
2457	int i;
2458
2459	cd = &sc->dc_cdata;
2460	ld = sc->dc_ldata;
2461	for (i = 0; i < DC_TX_LIST_CNT; i++) {
2462	if (i == (DC_TX_LIST_CNT - 1)) {
2463	ld->dc_tx_list[i].dc_next =
2464	vtophys(&ld->dc_tx_list[0]);
2465	} else {
2466	ld->dc_tx_list[i].dc_next =
2467	vtophys(&ld->dc_tx_list[i + 1]);
2468	}
2469	cd->dc_tx_chain[i] = NULL;
2470	ld->dc_tx_list[i].dc_data = 0;
2471	ld->dc_tx_list[i].dc_ctl = 0;
2472	}
2473
2474	cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2475
2476	return(0);
2477	}
2478
2479
2480	/*
2481	* Initialize the RX descriptors and allocate mbufs for them. Note that
2482	* we arrange the descriptors in a closed ring, so that the last descriptor
2483	* points back to the first.
2484	*/
2485	static int dc_list_rx_init(sc)
2486	struct dc_softc *sc;
2487	{
2488	struct dc_chain_data *cd;
2489	struct dc_list_data *ld;
2490	int i;
2491
2492	cd = &sc->dc_cdata;
2493	ld = sc->dc_ldata;
2494
2495	for (i = 0; i < DC_RX_LIST_CNT; i++) {
2496	if (dc_newbuf(sc, i, NULL) == ENOBUFS)
2497	return(ENOBUFS);
2498	if (i == (DC_RX_LIST_CNT - 1)) {
2499	ld->dc_rx_list[i].dc_next =
2500	vtophys(&ld->dc_rx_list[0]);
2501	} else {
2502	ld->dc_rx_list[i].dc_next =
2503	vtophys(&ld->dc_rx_list[i + 1]);
2504	}
2505	}
2506
2507	cd->dc_rx_prod = 0;
2508
2509	return(0);
2510	}
2511
2512	/*
2513	* Initialize an RX descriptor and attach an MBUF cluster.
2514	*/
2515	static int dc_newbuf(sc, i, m)
2516	struct dc_softc *sc;
2517	int i;
2518	struct mbuf *m;
2519	{
2520	struct mbuf *m_new = NULL;
2521	struct dc_desc *c;
2522
2523	c = &sc->dc_ldata->dc_rx_list[i];
2524
2525	if (m == NULL) {
2526	MGETHDR(m_new, M_DONTWAIT, MT_DATA);
2527	if (m_new == NULL)
2528	return(ENOBUFS);
2529
2530	MCLGET(m_new, M_DONTWAIT);
2531	if (!(m_new->m_flags & M_EXT)) {
2532	m_freem(m_new);
2533	return(ENOBUFS);
2534	}
2535	m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2536	} else {
2537	m_new = m;
2538	m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2539	m_new->m_data = m_new->m_ext.ext_buf;
2540	}
2541
2542	m_adj(m_new, sizeof(u_int64_t));
2543
2544	/*
2545	* If this is a PNIC chip, zero the buffer. This is part
2546	* of the workaround for the receive bug in the 82c168 and
2547	* 82c169 chips.
2548	*/
2549	if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2550	bzero((char )mtod(m_new, char ), m_new->m_len);
2551
2552	sc->dc_cdata.dc_rx_chain[i] = m_new;
2553	c->dc_data = vtophys(mtod(m_new, caddr_t));
2554	c->dc_ctl = DC_RXCTL_RLINK \| DC_RXLEN;
2555	c->dc_status = DC_RXSTAT_OWN;
2556
2557	return(0);
2558	}
2559
2560	/*
2561	* Grrrrr.
2562	* The PNIC chip has a terrible bug in it that manifests itself during
2563	* periods of heavy activity. The exact mode of failure if difficult to
2564	* pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2565	* will happen on slow machines. The bug is that sometimes instead of
2566	* uploading one complete frame during reception, it uploads what looks
2567	* like the entire contents of its FIFO memory. The frame we want is at
2568	* the end of the whole mess, but we never know exactly how much data has
2569	* been uploaded, so salvaging the frame is hard.
2570	*
2571	* There is only one way to do it reliably, and it's disgusting.
2572	* Here's what we know:
2573	*
2574	* - We know there will always be somewhere between one and three extra
2575	* descriptors uploaded.
2576	*
2577	* - We know the desired received frame will always be at the end of the
2578	* total data upload.
2579	*
2580	* - We know the size of the desired received frame because it will be
2581	* provided in the length field of the status word in the last descriptor.
2582	*
2583	* Here's what we do:
2584	*
2585	* - When we allocate buffers for the receive ring, we bzero() them.
2586	* This means that we know that the buffer contents should be all
2587	* zeros, except for data uploaded by the chip.
2588	*
2589	* - We also force the PNIC chip to upload frames that include the
2590	* ethernet CRC at the end.
2591	*
2592	* - We gather all of the bogus frame data into a single buffer.
2593	*
2594	* - We then position a pointer at the end of this buffer and scan
2595	* backwards until we encounter the first non-zero byte of data.
2596	* This is the end of the received frame. We know we will encounter
2597	* some data at the end of the frame because the CRC will always be
2598	* there, so even if the sender transmits a packet of all zeros,
2599	* we won't be fooled.
2600	*
2601	* - We know the size of the actual received frame, so we subtract
2602	* that value from the current pointer location. This brings us
2603	* to the start of the actual received packet.
2604	*
2605	* - We copy this into an mbuf and pass it on, along with the actual
2606	* frame length.
2607	*
2608	* The performance hit is tremendous, but it beats dropping frames all
2609	* the time.
2610	*/
2611
2612	#define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG\|DC_RXSTAT_LASTFRAG)
2613	static void dc_pnic_rx_bug_war(sc, idx)
2614	struct dc_softc *sc;
2615	int idx;
2616	{
2617	struct dc_desc *cur_rx;
2618	struct dc_desc *c = NULL;
2619	struct mbuf *m = NULL;
2620	unsigned char *ptr;
2621	int i, total_len;
2622	u_int32_t rxstat = 0;
2623
2624	i = sc->dc_pnic_rx_bug_save;
2625	cur_rx = &sc->dc_ldata->dc_rx_list[idx];
2626	ptr = sc->dc_pnic_rx_buf;
2627	bzero(ptr, sizeof(DC_RXLEN * 5));
2628
2629	/* Copy all the bytes from the bogus buffers. */
2630	while (1) {
2631	c = &sc->dc_ldata->dc_rx_list[i];
2632	rxstat = c->dc_status;
2633	m = sc->dc_cdata.dc_rx_chain[i];
2634	bcopy(mtod(m, char *), ptr, DC_RXLEN);
2635	ptr += DC_RXLEN;
2636	/* If this is the last buffer, break out. */
2637	if (i == idx \|\| rxstat & DC_RXSTAT_LASTFRAG)
2638	break;
2639	dc_newbuf(sc, i, m);
2640	DC_INC(i, DC_RX_LIST_CNT);
2641	}
2642
2643	/* Find the length of the actual receive frame. */
2644	total_len = DC_RXBYTES(rxstat);
2645
2646	/* Scan backwards until we hit a non-zero byte. */
2647	while(*ptr == 0x00)
2648	ptr--;
2649	#if 0
2650	/* Round off. */
2651	if ((uintptr_t)(ptr) & 0x3)
2652	ptr -= 1;
2653	#endif
2654
2655	/* Now find the start of the frame. */
2656	ptr -= total_len;
2657	if (ptr < sc->dc_pnic_rx_buf)
2658	ptr = sc->dc_pnic_rx_buf;
2659
2660	/*
2661	* Now copy the salvaged frame to the last mbuf and fake up
2662	* the status word to make it look like a successful
2663	* frame reception.
2664	*/
2665	dc_newbuf(sc, i, m);
2666	bcopy(ptr, mtod(m, char *), total_len);
2667	cur_rx->dc_status = rxstat \| DC_RXSTAT_FIRSTFRAG;
2668
2669	return;
2670	}
2671
2672	/*
2673	* This routine searches the RX ring for dirty descriptors in the
2674	* event that the rxeof routine falls out of sync with the chip's
2675	* current descriptor pointer. This may happen sometimes as a result
2676	* of a "no RX buffer available" condition that happens when the chip
2677	* consumes all of the RX buffers before the driver has a chance to
2678	* process the RX ring. This routine may need to be called more than
2679	* once to bring the driver back in sync with the chip, however we
2680	* should still be getting RX DONE interrupts to drive the search
2681	* for new packets in the RX ring, so we should catch up eventually.
2682	*/
2683	static int dc_rx_resync(sc)
2684	struct dc_softc *sc;
2685	{
2686	int i, pos;
2687	struct dc_desc *cur_rx;
2688
2689	pos = sc->dc_cdata.dc_rx_prod;
2690
2691	for (i = 0; i < DC_RX_LIST_CNT; i++) {
2692	cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2693	if (!(cur_rx->dc_status & DC_RXSTAT_OWN))
2694	break;
2695	DC_INC(pos, DC_RX_LIST_CNT);
2696	}
2697
2698	/* If the ring really is empty, then just return. */
2699	if (i == DC_RX_LIST_CNT)
2700	return(0);
2701
2702	/* We've fallen behing the chip: catch it. */
2703	sc->dc_cdata.dc_rx_prod = pos;
2704
2705	return(EAGAIN);
2706	}
2707
2708	/*
2709	* A frame has been uploaded: pass the resulting mbuf chain up to
2710	* the higher level protocols.
2711	*/
2712	static void dc_rxeof(sc)
2713	struct dc_softc *sc;
2714	{
2715	struct ether_header *eh;
2716	struct mbuf *m;
2717	struct ifnet *ifp;
2718	struct dc_desc *cur_rx;
2719	int i, total_len = 0;
2720	u_int32_t rxstat;
2721
2722	ifp = &sc->arpcom.ac_if;
2723	i = sc->dc_cdata.dc_rx_prod;
2724
2725	while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) {
2726
2727	#ifdef DEVICE_POLLING
2728	if (ifp->if_ipending & IFF_POLLING) {
2729	if (sc->rxcycles <= 0)
2730	break;
2731	sc->rxcycles--;
2732	}
2733	#endif /* DEVICE_POLLING */
2734	cur_rx = &sc->dc_ldata->dc_rx_list[i];
2735	rxstat = cur_rx->dc_status;
2736	m = sc->dc_cdata.dc_rx_chain[i];
2737	total_len = DC_RXBYTES(rxstat);
2738
2739	if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2740	if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2741	if (rxstat & DC_RXSTAT_FIRSTFRAG)
2742	sc->dc_pnic_rx_bug_save = i;
2743	if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
2744	DC_INC(i, DC_RX_LIST_CNT);
2745	continue;
2746	}
2747	dc_pnic_rx_bug_war(sc, i);
2748	rxstat = cur_rx->dc_status;
2749	total_len = DC_RXBYTES(rxstat);
2750	}
2751	}
2752
2753	sc->dc_cdata.dc_rx_chain[i] = NULL;
2754
2755	/*
2756	* If an error occurs, update stats, clear the
2757	* status word and leave the mbuf cluster in place:
2758	* it should simply get re-used next time this descriptor
2759	* comes up in the ring. However, don't report long
2760	* frames as errors since they could be vlans
2761	*/
2762	if ((rxstat & DC_RXSTAT_RXERR)){
2763	if (!(rxstat & DC_RXSTAT_GIANT) \|\|
2764	(rxstat & (DC_RXSTAT_CRCERR \| DC_RXSTAT_DRIBBLE \|
2765	DC_RXSTAT_MIIERE \| DC_RXSTAT_COLLSEEN \|
2766	DC_RXSTAT_RUNT \| DC_RXSTAT_DE))) {
2767	ifp->if_ierrors++;
2768	if (rxstat & DC_RXSTAT_COLLSEEN)
2769	ifp->if_collisions++;
2770	dc_newbuf(sc, i, m);
2771	if (rxstat & DC_RXSTAT_CRCERR) {
2772	DC_INC(i, DC_RX_LIST_CNT);
2773	continue;
2774	} else {
2775	dc_init(sc);
2776	return;
2777	}
2778	}
2779	}
2780
2781	/* No errors; receive the packet. */
2782	total_len -= ETHER_CRC_LEN;
2783
2784	#ifdef __i386__
2785	/*
2786	* On the x86 we do not have alignment problems, so try to
2787	* allocate a new buffer for the receive ring, and pass up
2788	* the one where the packet is already, saving the expensive
2789	* copy done in m_devget().
2790	* If we are on an architecture with alignment problems, or
2791	* if the allocation fails, then use m_devget and leave the
2792	* existing buffer in the receive ring.
2793	*/
2794	if (dc_quick && dc_newbuf(sc, i, NULL) == 0) {
2795	m->m_pkthdr.rcvif = ifp;
2796	m->m_pkthdr.len = m->m_len = total_len;
2797	DC_INC(i, DC_RX_LIST_CNT);
2798	} else
2799	#endif
2800	{
2801	struct mbuf *m0;
2802
2803	m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
2804	total_len + ETHER_ALIGN, 0, ifp, NULL);
2805	dc_newbuf(sc, i, m);
2806	DC_INC(i, DC_RX_LIST_CNT);
2807	if (m0 == NULL) {
2808	ifp->if_ierrors++;
2809	continue;
2810	}
2811	m_adj(m0, ETHER_ALIGN);
2812	m = m0;
2813	}
2814
2815	ifp->if_ipackets++;
2816	eh = mtod(m, struct ether_header *);
2817
2818	/* Remove header from mbuf and pass it on. */
2819	m_adj(m, sizeof(struct ether_header));
2820	ether_input(ifp, eh, m);
2821	}
2822
2823	sc->dc_cdata.dc_rx_prod = i;
2824	}
2825
2826	/*
2827	* A frame was downloaded to the chip. It's safe for us to clean up
2828	* the list buffers.
2829	*/
2830
2831	static void
2832	dc_txeof(sc)
2833	struct dc_softc *sc;
2834	{
2835	struct dc_desc *cur_tx = NULL;
2836	struct ifnet *ifp;
2837	int idx;
2838
2839	ifp = &sc->arpcom.ac_if;
2840
2841	/*
2842	* Go through our tx list and free mbufs for those
2843	* frames that have been transmitted.
2844	*/
2845	idx = sc->dc_cdata.dc_tx_cons;
2846	while(idx != sc->dc_cdata.dc_tx_prod) {
2847	u_int32_t txstat;
2848
2849	cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2850	txstat = cur_tx->dc_status;
2851
2852	if (txstat & DC_TXSTAT_OWN)
2853	break;
2854
2855	if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) \|\|
2856	cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2857	if (cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2858	/*
2859	* Yes, the PNIC is so brain damaged
2860	* that it will sometimes generate a TX
2861	* underrun error while DMAing the RX
2862	* filter setup frame. If we detect this,
2863	* we have to send the setup frame again,
2864	* or else the filter won't be programmed
2865	* correctly.
2866	*/
2867	if (DC_IS_PNIC(sc)) {
2868	if (txstat & DC_TXSTAT_ERRSUM)
2869	dc_setfilt(sc);
2870	}
2871	sc->dc_cdata.dc_tx_chain[idx] = NULL;
2872	}
2873	sc->dc_cdata.dc_tx_cnt--;
2874	DC_INC(idx, DC_TX_LIST_CNT);
2875	continue;
2876	}
2877
2878	if (DC_IS_CONEXANT(sc)) {
2879	/*
2880	* For some reason Conexant chips like
2881	* setting the CARRLOST flag even when
2882	* the carrier is there. In CURRENT we
2883	* have the same problem for Xircom
2884	* cards !
2885	*/
2886	if (/sc->dc_type == DC_TYPE_21143 &&/
2887	sc->dc_pmode == DC_PMODE_MII &&
2888	((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM\|
2889	DC_TXSTAT_NOCARRIER)))
2890	txstat &= ~DC_TXSTAT_ERRSUM;
2891	} else {
2892	if (/sc->dc_type == DC_TYPE_21143 &&/
2893	sc->dc_pmode == DC_PMODE_MII &&
2894	((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM\|
2895	DC_TXSTAT_NOCARRIER\|DC_TXSTAT_CARRLOST)))
2896	txstat &= ~DC_TXSTAT_ERRSUM;
2897	}
2898
2899	if (txstat & DC_TXSTAT_ERRSUM) {
2900	ifp->if_oerrors++;
2901	if (txstat & DC_TXSTAT_EXCESSCOLL)
2902	ifp->if_collisions++;
2903	if (txstat & DC_TXSTAT_LATECOLL)
2904	ifp->if_collisions++;
2905	if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2906	dc_init(sc);
2907	return;
2908	}
2909	}
2910
2911	ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2912
2913	ifp->if_opackets++;
2914	if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
2915	m_freem(sc->dc_cdata.dc_tx_chain[idx]);
2916	sc->dc_cdata.dc_tx_chain[idx] = NULL;
2917	}
2918
2919	sc->dc_cdata.dc_tx_cnt--;
2920	DC_INC(idx, DC_TX_LIST_CNT);
2921	}
2922
2923	if (idx != sc->dc_cdata.dc_tx_cons) {
2924	/* some buffers have been freed */
2925	sc->dc_cdata.dc_tx_cons = idx;
2926	ifp->if_flags &= ~IFF_OACTIVE;
2927	}
2928	ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5;
2929
2930	return;
2931	}
2932
2933
2934	#if 0
2935	static void dc_tick(xsc)
2936	void *xsc;
2937	{
2938	struct dc_softc *sc;
2939	/struct mii_data mii;*/
2940	struct ifnet *ifp;
2941	int s;
2942	u_int32_t r;
2943
2944
2945	sc = xsc;
2946	ifp = &sc->arpcom.ac_if;
2947	mii = device_get_softc(sc->dc_miibus);
2948
2949	if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2950	if (sc->dc_flags & DC_21143_NWAY) {
2951	r = CSR_READ_4(sc, DC_10BTSTAT);
2952	if (IFM_SUBTYPE(mii->mii_media_active) ==
2953	IFM_100_TX && (r & DC_TSTAT_LS100)) {
2954	sc->dc_link = 0;
2955	mii_mediachg(mii);
2956	}
2957	if (IFM_SUBTYPE(mii->mii_media_active) ==
2958	IFM_10_T && (r & DC_TSTAT_LS10)) {
2959	sc->dc_link = 0;
2960	mii_mediachg(mii);
2961	}
2962	if (sc->dc_link == 0)
2963	mii_tick(mii);
2964	} else {
2965	r = CSR_READ_4(sc, DC_ISR);
2966	if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT &&
2967	sc->dc_cdata.dc_tx_cnt == 0)
2968	mii_tick(mii);
2969	if (!(mii->mii_media_status & IFM_ACTIVE))
2970	sc->dc_link = 0;
2971	}
2972	} else
2973	mii_tick(mii);
2974
2975	/*
2976	* When the init routine completes, we expect to be able to send
2977	* packets right away, and in fact the network code will send a
2978	* gratuitous ARP the moment the init routine marks the interface
2979	* as running. However, even though the MAC may have been initialized,
2980	* there may be a delay of a few seconds before the PHY completes
2981	* autonegotiation and the link is brought up. Any transmissions
2982	* made during that delay will be lost. Dealing with this is tricky:
2983	* we can't just pause in the init routine while waiting for the
2984	* PHY to come ready since that would bring the whole system to
2985	* a screeching halt for several seconds.
2986	*
2987	* What we do here is prevent the TX start routine from sending
2988	* any packets until a link has been established. After the
2989	* interface has been initialized, the tick routine will poll
2990	* the state of the PHY until the IFM_ACTIVE flag is set. Until
2991	* that time, packets will stay in the send queue, and once the
2992	* link comes up, they will be flushed out to the wire.
2993	*/
2994	if (!sc->dc_link) {
2995	mii_pollstat(mii);
2996	if (mii->mii_media_status & IFM_ACTIVE &&
2997	IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2998	sc->dc_link++;
2999	if (ifp->if_snd.ifq_head != NULL)
3000	dc_start(ifp);
3001	}
3002	}
3003
3004	if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
3005	sc->dc_stat_ch = timeout(dc_tick, sc, hz/10);
3006	else
3007	sc->dc_stat_ch = timeout(dc_tick, sc, hz);
3008
3009	return;
3010	}
3011	#endif
3012
3013	/*
3014	* A transmit underrun has occurred. Back off the transmit threshold,
3015	* or switch to store and forward mode if we have to.
3016	*/
3017	static void dc_tx_underrun(sc)
3018	struct dc_softc *sc;
3019	{
3020	u_int32_t isr;
3021	int i;
3022
3023	if (DC_IS_DAVICOM(sc))
3024	dc_init(sc);
3025
3026	if (DC_IS_INTEL(sc)) {
3027	/*
3028	* The real 21143 requires that the transmitter be idle
3029	* in order to change the transmit threshold or store
3030	* and forward state.
3031	*/
3032	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3033
3034	for (i = 0; i < DC_TIMEOUT; i++) {
3035	isr = CSR_READ_4(sc, DC_ISR);
3036	if (isr & DC_ISR_TX_IDLE)
3037	break;
3038	DELAY(10);
3039	}
3040	if (i == DC_TIMEOUT) {
3041	printk("dc%d: failed to force tx to idle state\n",
3042	sc->dc_unit);
3043	dc_init(sc);
3044	}
3045	}
3046
3047	printk("dc%d: TX underrun -- ", sc->dc_unit);
3048	sc->dc_txthresh += DC_TXTHRESH_INC;
3049	if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3050	printk("using store and forward mode\n");
3051	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3052	} else {
3053	printk("increasing TX threshold\n");
3054	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3055	DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3056	}
3057
3058	if (DC_IS_INTEL(sc))
3059	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3060
3061	return;
3062	}
3063
3064	#ifdef DEVICE_POLLING
3065	static poll_handler_t dc_poll;
3066
3067	static void
3068	dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3069	{
3070	struct dc_softc *sc = ifp->if_softc;
3071
3072	if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
3073	/* Re-enable interrupts. */
3074	CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3075	return;
3076	}
3077	sc->rxcycles = count;
3078	dc_rxeof(sc);
3079	dc_txeof(sc);
3080	if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE))
3081	dc_start(ifp);
3082
3083	if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
3084	u_int32_t status;
3085
3086	status = CSR_READ_4(sc, DC_ISR);
3087	status &= (DC_ISR_RX_WATDOGTIMEO\|DC_ISR_RX_NOBUF\|
3088	DC_ISR_TX_NOBUF\|DC_ISR_TX_IDLE\|DC_ISR_TX_UNDERRUN\|
3089	DC_ISR_BUS_ERR);
3090	if (!status)
3091	return ;
3092	/* ack what we have */
3093	CSR_WRITE_4(sc, DC_ISR, status);
3094
3095	if (status & (DC_ISR_RX_WATDOGTIMEO\|DC_ISR_RX_NOBUF) ) {
3096	u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3097	ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
3098
3099	if (dc_rx_resync(sc))
3100	dc_rxeof(sc);
3101	}
3102	/* restart transmit unit if necessary */
3103	if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
3104	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3105
3106	if (status & DC_ISR_TX_UNDERRUN)
3107	dc_tx_underrun(sc);
3108
3109	if (status & DC_ISR_BUS_ERR) {
3110	printk("dc_poll: dc%d bus error\n", sc->dc_unit);
3111	dc_reset(sc);
3112	dc_init(sc);
3113	}
3114	}
3115	}
3116	#endif /* DEVICE_POLLING */
3117
3118	static void
3119	dc_intr(void* arg)
3120	{
3121	/* Need to make this work for multiple devices ... eventually */
3122	struct dc_softc sc = (struct dc_softc )arg;
3123
3124
3125	/* Disable interrupts. */
3126	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3127
3128	rtems_event_send(sc->daemontid, IRQ_EVENT);
3129	#if 0
3130	if (sc->suspended) {
3131	return;
3132	}
3133
3134	ifp = &sc->arpcom.ac_if;
3135
3136	#ifdef DEVICE_POLLING
3137	if (ifp->if_ipending & IFF_POLLING)
3138	return;
3139	if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */
3140	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3141	return;
3142	}
3143	#endif /* DEVICE_POLLING */
3144	if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
3145	return ;
3146
3147	/* Suppress unwanted interrupts */
3148	if (!(ifp->if_flags & IFF_UP)) {
3149	if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
3150	dc_stop(sc);
3151	return;
3152	}
3153	#endif
3154	}
3155
3156
3157	static void
3158	dc_daemon(void * arg)
3159	{
3160	struct dc_softc sc = (struct dc_softc )arg;
3161	struct ifnet *ifp;
3162	u_int32_t status;
3163	rtems_event_set events;
3164
3165
3166	for(;;) {
3167	rtems_bsdnet_event_receive(RTEMS_ALL_EVENTS, \
3168	RTEMS_WAIT \| RTEMS_EVENT_ANY, \
3169	RTEMS_NO_TIMEOUT,
3170	&events);
3171
3172
3173	ifp = &sc->arpcom.ac_if;
3174
3175	while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) {
3176
3177	CSR_WRITE_4(sc, DC_ISR, status);
3178
3179	if (status & DC_ISR_RX_OK) {
3180	int curpkts;
3181	curpkts = ifp->if_ipackets;
3182	dc_rxeof(sc);
3183	if (curpkts == ifp->if_ipackets) {
3184	while(dc_rx_resync(sc))
3185	dc_rxeof(sc);
3186	}
3187	}
3188
3189	if (status & (DC_ISR_TX_OK\|DC_ISR_TX_NOBUF))
3190	dc_txeof(sc);
3191
3192	if (status & DC_ISR_TX_IDLE) {
3193	dc_txeof(sc);
3194	if (sc->dc_cdata.dc_tx_cnt) {
3195	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3196	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3197	}
3198	}
3199
3200	if (status & DC_ISR_TX_UNDERRUN)
3201	dc_tx_underrun(sc);
3202
3203	if ((status & DC_ISR_RX_WATDOGTIMEO)
3204	\|\| (status & DC_ISR_RX_NOBUF)) {
3205	int curpkts;
3206	curpkts = ifp->if_ipackets;
3207	dc_rxeof(sc);
3208	if (curpkts == ifp->if_ipackets) {
3209	while(dc_rx_resync(sc))
3210	dc_rxeof(sc);
3211	}
3212	}
3213
3214	if (status & DC_ISR_BUS_ERR) {
3215	dc_reset(sc);
3216	dc_init(sc);
3217	}
3218	}
3219
3220	/* Make atomic !!! */
3221	/* Re-enable interrupts. */
3222	CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3223
3224	if (ifp->if_snd.ifq_head != NULL)
3225	dc_start(ifp);
3226	}
3227
3228	}
3229
3230
3231	/*
3232	* Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
3233	* pointers to the fragment pointers.
3234	*/
3235	static int dc_encap(sc, m_head, txidx)
3236	struct dc_softc *sc;
3237	struct mbuf *m_head;
3238	u_int32_t *txidx;
3239	{
3240	struct dc_desc *f = NULL;
3241	struct mbuf *m;
3242	int frag, cur, cnt = 0;
3243
3244	/*
3245	* Start packing the mbufs in this chain into
3246	* the fragment pointers. Stop when we run out
3247	* of fragments or hit the end of the mbuf chain.
3248	*/
3249	m = m_head;
3250	cur = frag = *txidx;
3251
3252	for (m = m_head; m != NULL; m = m->m_next) {
3253	if (m->m_len != 0) {
3254	if (sc->dc_flags & DC_TX_ADMTEK_WAR) {
3255	if (*txidx != sc->dc_cdata.dc_tx_prod &&
3256	frag == (DC_TX_LIST_CNT - 1))
3257	return(ENOBUFS);
3258	}
3259	if ((DC_TX_LIST_CNT -
3260	(sc->dc_cdata.dc_tx_cnt + cnt)) < 5)
3261	return(ENOBUFS);
3262
3263	f = &sc->dc_ldata->dc_tx_list[frag];
3264	f->dc_ctl = DC_TXCTL_TLINK \| m->m_len;
3265	if (cnt == 0) {
3266	f->dc_status = 0;
3267	f->dc_ctl \|= DC_TXCTL_FIRSTFRAG;
3268	} else
3269	f->dc_status = DC_TXSTAT_OWN;
3270	f->dc_data = vtophys(mtod(m, vm_offset_t));
3271	cur = frag;
3272	DC_INC(frag, DC_TX_LIST_CNT);
3273	cnt++;
3274	}
3275	}
3276
3277	if (m != NULL)
3278	return(ENOBUFS);
3279
3280	sc->dc_cdata.dc_tx_cnt += cnt;
3281	sc->dc_cdata.dc_tx_chain[cur] = m_head;
3282	sc->dc_ldata->dc_tx_list[cur].dc_ctl \|= DC_TXCTL_LASTFRAG;
3283	if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3284	sc->dc_ldata->dc_tx_list[*txidx].dc_ctl \|= DC_TXCTL_FINT;
3285	if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3286	sc->dc_ldata->dc_tx_list[cur].dc_ctl \|= DC_TXCTL_FINT;
3287	if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
3288	sc->dc_ldata->dc_tx_list[cur].dc_ctl \|= DC_TXCTL_FINT;
3289	sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN;
3290	*txidx = frag;
3291
3292	return(0);
3293	}
3294
3295	/*
3296	* Coalesce an mbuf chain into a single mbuf cluster buffer.
3297	* Needed for some really badly behaved chips that just can't
3298	* do scatter/gather correctly.
3299	*/
3300	static int dc_coal(sc, m_head)
3301	struct dc_softc *sc;
3302	struct mbuf **m_head;
3303	{
3304	struct mbuf m_new, m;
3305
3306	m = *m_head;
3307	MGETHDR(m_new, M_DONTWAIT, MT_DATA);
3308	if (m_new == NULL)
3309	return(ENOBUFS);
3310	if (m->m_pkthdr.len > MHLEN) {
3311	MCLGET(m_new, M_DONTWAIT);
3312	if (!(m_new->m_flags & M_EXT)) {
3313	m_freem(m_new);
3314	return(ENOBUFS);
3315	}
3316	}
3317	m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t));
3318	m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len;
3319	m_freem(m);
3320	*m_head = m_new;
3321
3322	return(0);
3323	}
3324
3325	/*
3326	* Main transmit routine. To avoid having to do mbuf copies, we put pointers
3327	* to the mbuf data regions directly in the transmit lists. We also save a
3328	* copy of the pointers since the transmit list fragment pointers are
3329	* physical addresses.
3330	*/
3331
3332	static void dc_start(ifp)
3333	struct ifnet *ifp;
3334	{
3335	struct dc_softc *sc;
3336	struct mbuf *m_head = NULL;
3337	u_int32_t idx;
3338
3339	sc = ifp->if_softc;
3340	#if 0
3341	if (!sc->dc_link && ifp->if_snd.ifq_len < 10)
3342	return;
3343	#endif
3344	if (ifp->if_flags & IFF_OACTIVE)
3345	return;
3346
3347	idx = sc->dc_cdata.dc_tx_prod;
3348
3349	while(sc->dc_cdata.dc_tx_chain[idx] == NULL) {
3350	IF_DEQUEUE(&ifp->if_snd, m_head);
3351	if (m_head == NULL)
3352	break;
3353
3354	if (sc->dc_flags & DC_TX_COALESCE &&
3355	m_head->m_next != NULL) {
3356	/* only coalesce if have >1 mbufs */
3357	if (dc_coal(sc, &m_head)) {
3358	IF_PREPEND(&ifp->if_snd, m_head);
3359	ifp->if_flags \|= IFF_OACTIVE;
3360	break;
3361	}
3362	}
3363
3364	if (dc_encap(sc, m_head, &idx)) {
3365	IF_PREPEND(&ifp->if_snd, m_head);
3366	ifp->if_flags \|= IFF_OACTIVE;
3367	break;
3368	}
3369	#if 0
3370	/*
3371	* If there's a BPF listener, bounce a copy of this frame
3372	* to him.
3373	*/
3374	if (ifp->if_bpf)
3375	bpf_mtap(ifp, m_head);
3376	#endif
3377	if (sc->dc_flags & DC_TX_ONE) {
3378	ifp->if_flags \|= IFF_OACTIVE;
3379	break;
3380	}
3381	}
3382
3383	/* Transmit */
3384	sc->dc_cdata.dc_tx_prod = idx;
3385	if (!(sc->dc_flags & DC_TX_POLL))
3386	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3387
3388	/*
3389	* Set a timeout in case the chip goes out to lunch.
3390	*/
3391	ifp->if_timer = 5;
3392
3393	return;
3394	}
3395
3396	static void dc_init(xsc)
3397	void *xsc;
3398	{
3399	struct dc_softc *sc = xsc;
3400	struct ifnet *ifp = &sc->arpcom.ac_if;
3401	/struct mii_data mii;*/
3402
3403
3404	/mii = device_get_softc(sc->dc_miibus);/
3405
3406	/*
3407	* Cancel pending I/O and free all RX/TX buffers.
3408	*/
3409	dc_stop(sc);
3410	dc_reset(sc);
3411
3412	/*
3413	* Set cache alignment and burst length.
3414	*/
3415	if (DC_IS_ASIX(sc) \|\| DC_IS_DAVICOM(sc))
3416	CSR_WRITE_4(sc, DC_BUSCTL, 0);
3417	else
3418	CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME\|DC_BUSCTL_MRLE);
3419	/*
3420	* Evenly share the bus between receive and transmit process.
3421	*/
3422	if (DC_IS_INTEL(sc))
3423	DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3424	if (DC_IS_DAVICOM(sc) \|\| DC_IS_INTEL(sc)) {
3425	DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3426	} else {
3427	DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3428	}
3429	if (sc->dc_flags & DC_TX_POLL)
3430	DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3431	switch(sc->dc_cachesize) {
3432	case 32:
3433	DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3434	break;
3435	case 16:
3436	DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3437	break;
3438	case 8:
3439	DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3440	break;
3441	case 0:
3442	default:
3443	DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3444	break;
3445	}
3446
3447	if (sc->dc_flags & DC_TX_STORENFWD)
3448	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3449	else {
3450	if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3451	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3452	} else {
3453	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3454	DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3455	}
3456	}
3457
3458	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3459	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3460
3461	if (DC_IS_MACRONIX(sc) \|\| DC_IS_PNICII(sc)) {
3462	/*
3463	* The app notes for the 98713 and 98715A say that
3464	* in order to have the chips operate properly, a magic
3465	* number must be written to CSR16. Macronix does not
3466	* document the meaning of these bits so there's no way
3467	* to know exactly what they do. The 98713 has a magic
3468	* number all its own; the rest all use a different one.
3469	*/
3470	DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3471	if (sc->dc_type == DC_TYPE_98713)
3472	DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3473	else
3474	DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3475	}
3476
3477	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3478	DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3479
3480	/* Init circular RX list. */
3481	if (dc_list_rx_init(sc) == ENOBUFS) {
3482	printk("dc%d: initialization failed: no "
3483	"memory for rx buffers\n", sc->dc_unit);
3484	dc_stop(sc);
3485	return;
3486	}
3487
3488	/*
3489	* Init tx descriptors.
3490	*/
3491	dc_list_tx_init(sc);
3492
3493	/*
3494	* Load the address of the RX list.
3495	*/
3496	CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0]));
3497	CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0]));
3498
3499	/*
3500	* Enable interrupts.
3501	*/
3502	#ifdef DEVICE_POLLING
3503	/*
3504	* ... but only if we are not polling, and make sure they are off in
3505	* the case of polling. Some cards (e.g. fxp) turn interrupts on
3506	* after a reset.
3507	*/
3508	if (ifp->if_ipending & IFF_POLLING)
3509	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3510	else
3511	#endif
3512	/* Enable interrupts */
3513	CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3514	CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3515
3516	/* Enable transmitter. */
3517	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3518
3519	/*
3520	* If this is an Intel 21143 and we're not using the
3521	* MII port, program the LED control pins so we get
3522	* link and activity indications.
3523	*/
3524	if (sc->dc_flags & DC_TULIP_LEDS) {
3525	CSR_WRITE_4(sc, DC_WATCHDOG,
3526	DC_WDOG_CTLWREN\|DC_WDOG_LINK\|DC_WDOG_ACTIVITY);
3527	CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3528	}
3529
3530	/*
3531	* Load the RX/multicast filter. We do this sort of late
3532	* because the filter programming scheme on the 21143 and
3533	* some clones requires DMAing a setup frame via the TX
3534	* engine, and we need the transmitter enabled for that.
3535	*/
3536	dc_setfilt(sc);
3537
3538	/* Enable receiver. */
3539	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3540	CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3541
3542	/mii_mediachg(mii);/
3543	dc_setcfg(sc, sc->dc_if_media);
3544
3545	ifp->if_flags \|= IFF_RUNNING;
3546	ifp->if_flags &= ~IFF_OACTIVE;
3547
3548
3549	#if 0
3550
3551	/* Don't start the ticker if this is a homePNA link. */
3552	if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_homePNA)
3553	sc->dc_link = 1;
3554	else {
3555	if (sc->dc_flags & DC_21143_NWAY)
3556	sc->dc_stat_ch = timeout(dc_tick, sc, hz/10);
3557	else
3558	sc->dc_stat_ch = timeout(dc_tick, sc, hz);
3559	}
3560
3561	#ifdef SRM_MEDIA
3562	if(sc->dc_srm_media) {
3563	struct ifreq ifr;
3564
3565	ifr.ifr_media = sc->dc_srm_media;
3566	ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA);
3567	sc->dc_srm_media = 0;
3568	}
3569	#endif
3570	#endif /* end if (0) */
3571	return;
3572	}
3573
3574
3575	#if 0
3576	/*
3577	* Set media options.
3578	*/
3579	static int dc_ifmedia_upd(ifp)
3580	struct ifnet *ifp;
3581	{
3582	struct dc_softc *sc;
3583	struct mii_data *mii;
3584	struct ifmedia *ifm;
3585
3586	sc = ifp->if_softc;
3587	mii = device_get_softc(sc->dc_miibus);
3588	mii_mediachg(mii);
3589	ifm = &mii->mii_media;
3590
3591	if (DC_IS_DAVICOM(sc) &&
3592	IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA)
3593	dc_setcfg(sc, ifm->ifm_media);
3594	else
3595	sc->dc_link = 0;
3596
3597	return(0);
3598	}
3599
3600	/*
3601	* Report current media status.
3602	*/
3603	static void dc_ifmedia_sts(ifp, ifmr)
3604	struct ifnet *ifp;
3605	struct ifmediareq *ifmr;
3606	{
3607	struct dc_softc *sc;
3608	struct mii_data *mii;
3609	struct ifmedia *ifm;
3610
3611	sc = ifp->if_softc;
3612	mii = device_get_softc(sc->dc_miibus);
3613	mii_pollstat(mii);
3614	ifm = &mii->mii_media;
3615	if (DC_IS_DAVICOM(sc)) {
3616	if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) {
3617	ifmr->ifm_active = ifm->ifm_media;
3618	ifmr->ifm_status = 0;
3619	return;
3620	}
3621	}
3622	ifmr->ifm_active = mii->mii_media_active;
3623	ifmr->ifm_status = mii->mii_media_status;
3624
3625	return;
3626	}
3627	#endif
3628
3629
3630	static int dc_ioctl(ifp, command, data)
3631	struct ifnet *ifp;
3632	ioctl_command_t command;
3633	caddr_t data;
3634	{
3635	struct dc_softc *sc = ifp->if_softc;
3636	/struct ifreq ifr = (struct ifreq *) data;
3637	struct mii_data mii;/
3638	int error = 0;
3639
3640
3641	switch(command) {
3642	case SIOCSIFADDR:
3643	case SIOCGIFADDR:
3644	case SIOCSIFMTU:
3645	error = ether_ioctl(ifp, command, data);
3646	break;
3647	case SIOCSIFFLAGS:
3648	if (ifp->if_flags & IFF_UP) {
3649	int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3650	(IFF_PROMISC \| IFF_ALLMULTI);
3651	if (ifp->if_flags & IFF_RUNNING) {
3652	if (need_setfilt)
3653	dc_setfilt(sc);
3654	} else {
3655	sc->dc_txthresh = 0;
3656	dc_init(sc);
3657	}
3658	} else {
3659	if (ifp->if_flags & IFF_RUNNING)
3660	dc_stop(sc);
3661	}
3662	sc->dc_if_flags = ifp->if_flags;
3663	error = 0;
3664	break;
3665	case SIOCADDMULTI:
3666	case SIOCDELMULTI:
3667	dc_setfilt(sc);
3668	error = 0;
3669	break;
3670	#if 0
3671	case SIOCGIFMEDIA:
3672	case SIOCSIFMEDIA:
3673	mii = device_get_softc(sc->dc_miibus);
3674	error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3675	#ifdef SRM_MEDIA
3676	if (sc->dc_srm_media)
3677	sc->dc_srm_media = 0;
3678	#endif
3679	break;
3680	#endif
3681	default:
3682	error = EINVAL;
3683	break;
3684	}
3685
3686
3687	return(error);
3688	}
3689
3690	static void dc_watchdog(ifp)
3691	struct ifnet *ifp;
3692	{
3693	struct dc_softc *sc;
3694
3695	sc = ifp->if_softc;
3696
3697	ifp->if_oerrors++;
3698	printk("dc%d: watchdog timeout\n", sc->dc_unit);
3699
3700	dc_stop(sc);
3701	dc_reset(sc);
3702	dc_init(sc);
3703
3704	if (ifp->if_snd.ifq_head != NULL)
3705	dc_start(ifp);
3706
3707	return;
3708	}
3709
3710	/*
3711	* Stop the adapter and free any mbufs allocated to the
3712	* RX and TX lists.
3713	*/
3714	static void dc_stop(sc)
3715	struct dc_softc *sc;
3716	{
3717	register int i;
3718	struct ifnet *ifp;
3719
3720	ifp = &sc->arpcom.ac_if;
3721	ifp->if_timer = 0;
3722
3723	/untimeout(dc_tick, sc, sc->dc_stat_ch);/
3724
3725	ifp->if_flags &= ~(IFF_RUNNING \| IFF_OACTIVE);
3726	#ifdef DEVICE_POLLING
3727	ether_poll_deregister(ifp);
3728	#endif
3729
3730	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON\|DC_NETCFG_TX_ON));
3731	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3732	CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3733	CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3734	sc->dc_link = 0;
3735
3736	/*
3737	* Free data in the RX lists.
3738	*/
3739	for (i = 0; i < DC_RX_LIST_CNT; i++) {
3740	if (sc->dc_cdata.dc_rx_chain[i] != NULL) {
3741	m_freem(sc->dc_cdata.dc_rx_chain[i]);
3742	sc->dc_cdata.dc_rx_chain[i] = NULL;
3743	}
3744	}
3745	bzero((char *)&sc->dc_ldata->dc_rx_list,
3746	sizeof(sc->dc_ldata->dc_rx_list));
3747
3748	/*
3749	* Free the TX list buffers.
3750	*/
3751	for (i = 0; i < DC_TX_LIST_CNT; i++) {
3752	if (sc->dc_cdata.dc_tx_chain[i] != NULL) {
3753	if (sc->dc_ldata->dc_tx_list[i].dc_ctl &
3754	DC_TXCTL_SETUP) {
3755	sc->dc_cdata.dc_tx_chain[i] = NULL;
3756	continue;
3757	}
3758	m_freem(sc->dc_cdata.dc_tx_chain[i]);
3759	sc->dc_cdata.dc_tx_chain[i] = NULL;
3760	}
3761	}
3762
3763	bzero((char *)&sc->dc_ldata->dc_tx_list,
3764	sizeof(sc->dc_ldata->dc_tx_list));
3765
3766	return;
3767	}
3768
3769
3770	#if 0
3771	/*
3772	* Stop all chip I/O so that the kernel's probe routines don't
3773	* get confused by errant DMAs when rebooting.
3774	*/
3775	static void dc_shutdown(dev)
3776	device_t dev;
3777	{
3778	struct dc_softc *sc;
3779
3780	sc = device_get_softc(dev);
3781
3782	dc_stop(sc);
3783
3784	return;
3785	}
3786
3787	/*
3788	* Device suspend routine. Stop the interface and save some PCI
3789	* settings in case the BIOS doesn't restore them properly on
3790	* resume.
3791	*/
3792	static int dc_suspend(dev)
3793	device_t dev;
3794	{
3795	register int i;
3796	int s;
3797	struct dc_softc *sc;
3798
3799
3800	sc = device_get_softc(dev);
3801
3802	dc_stop(sc);
3803
3804	for (i = 0; i < 5; i++)
3805	sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
3806	sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
3807	sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
3808	sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3809	sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3810
3811	sc->suspended = 1;
3812
3813	return (0);
3814	}
3815
3816	/*
3817	* Device resume routine. Restore some PCI settings in case the BIOS
3818	* doesn't, re-enable busmastering, and restart the interface if
3819	* appropriate.
3820	*/
3821	static int dc_resume(dev)
3822	device_t dev;
3823	{
3824	register int i;
3825	int s;
3826	struct dc_softc *sc;
3827	struct ifnet *ifp;
3828
3829
3830	sc = device_get_softc(dev);
3831	ifp = &sc->arpcom.ac_if;
3832
3833	dc_acpi(dev);
3834
3835	/* better way to do this? */
3836	for (i = 0; i < 5; i++)
3837	pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
3838	pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
3839	pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
3840	pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
3841	pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
3842
3843	/* reenable busmastering */
3844	pci_enable_busmaster(dev);
3845	pci_enable_io(dev, DC_RES);
3846
3847	/* reinitialize interface if necessary */
3848	if (ifp->if_flags & IFF_UP)
3849	dc_init(sc);
3850
3851	sc->suspended = 0;
3852
3853	return (0);
3854	}
3855	#endif
3856
3857	#endif /* end if supported */

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