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source: rtems/c/src/libchip/network/if_dc.c @ af28e68e

4.104.114.84.95

Last change on this file since af28e68e was af28e68e, checked in by Joel Sherrill <joel.sherrill@…>, on 06/16/05 at 20:09:36

2005-06-16 Daron Chabot <daron@…>

libchip/Makefile.am: Add driver for Tulip clones.
libchip/network/README.tulipclone, libchip/network/if_dc.c, libchip/network/if_dcreg.h: New files.

Property mode set to 100644

File size: 91.1 KB

Line
1	/* $Id$
2	*
3	* Ported from FreeBSD --> RTEMS, december 03.
4	* Daron Chabot <daron@nucleus.usask.ca>
5	* -- only tested with i386 bsp.
6	* -- supports one card (until the PCI & IRQ APIs get sorted out ;-))
7	*
8	*
9	* Copyright (c) 1997, 1998, 1999
10	* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
11	*
12	* Redistribution and use in source and binary forms, with or without
13	* modification, are permitted provided that the following conditions
14	* are met:
15	* 1. Redistributions of source code must retain the above copyright
16	* notice, this list of conditions and the following disclaimer.
17	* 2. Redistributions in binary form must reproduce the above copyright
18	* notice, this list of conditions and the following disclaimer in the
19	* documentation and/or other materials provided with the distribution.
20	* 3. All advertising materials mentioning features or use of this software
21	* must display the following acknowledgement:
22	* This product includes software developed by Bill Paul.
23	* 4. Neither the name of the author nor the names of any co-contributors
24	* may be used to endorse or promote products derived from this software
25	* without specific prior written permission.
26	*
27	* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
28	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30	* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
31	* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
37	* THE POSSIBILITY OF SUCH DAMAGE.
38	*
39	* $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.41 2003/03/05 18:42:33 njl Exp $
40	*/
41
42	/*
43	* DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
44	* series chips and several workalikes including the following:
45	*
46	* Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
47	* Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
48	* Lite-On 82c168/82c169 PNIC (www.litecom.com)
49	* ASIX Electronics AX88140A (www.asix.com.tw)
50	* ASIX Electronics AX88141 (www.asix.com.tw)
51	* ADMtek AL981 (www.admtek.com.tw)
52	* ADMtek AN985 (www.admtek.com.tw)
53	* Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
54	* Accton EN1217 (www.accton.com)
55	* Conexant LANfinity (www.conexant.com)
56	*
57	* Datasheets for the 21143 are available at developer.intel.com.
58	* Datasheets for the clone parts can be found at their respective sites.
59	* (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
60	* The PNIC II is essentially a Macronix 98715A chip; the only difference
61	* worth noting is that its multicast hash table is only 128 bits wide
62	* instead of 512.
63	*
64	* Written by Bill Paul <wpaul@ee.columbia.edu>
65	* Electrical Engineering Department
66	* Columbia University, New York City
67	*/
68
69	/*
70	* The Intel 21143 is the successor to the DEC 21140. It is basically
71	* the same as the 21140 but with a few new features. The 21143 supports
72	* three kinds of media attachments:
73	*
74	* o MII port, for 10Mbps and 100Mbps support and NWAY
75	* autonegotiation provided by an external PHY.
76	* o SYM port, for symbol mode 100Mbps support.
77	* o 10baseT port.
78	* o AUI/BNC port.
79	*
80	* The 100Mbps SYM port and 10baseT port can be used together in
81	* combination with the internal NWAY support to create a 10/100
82	* autosensing configuration.
83	*
84	* Note that not all tulip workalikes are handled in this driver: we only
85	* deal with those which are relatively well behaved. The Winbond is
86	* handled separately due to its different register offsets and the
87	* special handling needed for its various bugs. The PNIC is handled
88	* here, but I'm not thrilled about it.
89	*
90	* All of the workalike chips use some form of MII transceiver support
91	* with the exception of the Macronix chips, which also have a SYM port.
92	* The ASIX AX88140A is also documented to have a SYM port, but all
93	* the cards I've seen use an MII transceiver, probably because the
94	* AX88140A doesn't support internal NWAY.
95	*/
96
97	#include <rtems.h>
98	#include <rtems/error.h>
99	#include <rtems/rtems_bsdnet.h>
100
101
102
103	#include <net/if_types.h>
104
105	#include <sys/param.h>
106	#include <sys/sockio.h>
107	#include <sys/socket.h>
108	#include <sys/mbuf.h>
109	#include <net/if.h>
110	#include <netinet/in.h>
111	#include <netinet/if_ether.h>
112	#include <sys/malloc.h>
113	#include <sys/systm.h>
114	#include <bsp.h>
115
116	#include "if_media.h"
117	#include "pci.h"
118	/*#include <rtems/pci.h> moved to cpukit/include/rtems in CVS current !
119	#include <sys/kernel.h>
120	#include <sys/sysctl.h>
121	*/
122
123	#include <vm/vm.h> /* for vtophys */
124
125
126	#if defined(__i386__)
127	#define vtophys(p) (u_int32_t)(p)
128	#else
129	#define vtophys(p) vtophys(p)
130	#endif
131
132	/*
133	#include <net/if_arp.h>
134	#include <net/if_vlan_var.h>
135	#include <net/bpf.h>
136	*/
137
138	#if 0
139	#include <vm/pmap.h> /* for vtophys */
140	#include <machine/clock.h> /* for DELAY */
141	#include <machine/bus_pio.h>
142	#include <machine/bus_memio.h>
143	#include <machine/bus.h>
144	#include <machine/resource.h>
145	#include <sys/bus.h>
146	#include <sys/rman.h>
147
148	#include <dev/mii/mii.h>
149	#include <dev/mii/miivar.h>
150
151	#include <pci/pcireg.h>
152	#include <pci/pcivar.h>
153	#endif
154
155	/* NOTE: use mem space mapping (for now ...)
156	#define DC_USEIOSPACE
157	*/
158
159	#ifdef __alpha__
160	#define SRM_MEDIA
161	#endif
162
163	#if defined(__i386__)
164	#include <irq.h>
165	#include <pcibios.h>
166	#endif
167
168
169	#include "if_dcreg.h"
170
171
172	#define DRIVER_PREFIX "tl"
173	#define NDRIVER 1
174	#define IRQ_EVENT RTEMS_EVENT_13 /* Ha ... */
175	static struct dc_softc dc_softc_devs[NDRIVER];
176
177	#if 0
178	/* "controller miibus0" required. See GENERIC if you get errors here. */
179	#include "miibus_if.h"
180
181
182
183	#ifndef lint
184	static const char rcsid[] =
185	"$FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.41 2003/03/05 18:42:33 njl Exp $";
186	#endif
187
188	#endif
189
190
191	/*
192	* Various supported device vendors/types and their names.
193	* NOTE:
194	* -----
195	* Only the "ADMtek AN985" has been tested under RTEMS !!!
196	*/
197	static struct dc_type dc_devs[] = {
198	{ DC_VENDORID_DEC, DC_DEVICEID_21143,
199	"Intel 21143 10/100BaseTX", 0 },
200	{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009,
201	"Davicom DM9009 10/100BaseTX", 0 },
202	{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100,
203	"Davicom DM9100 10/100BaseTX", 0 },
204	{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
205	"Davicom DM9102 10/100BaseTX", 0 },
206	{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
207	"Davicom DM9102A 10/100BaseTX", 0 },
208	{ DC_VENDORID_ADMTEK, DC_DEVICEID_AL981,
209	"ADMtek AL981 10/100BaseTX", 0 },
210	{ DC_VENDORID_ADMTEK, DC_DEVICEID_AN985,
211	"ADMtek AN985 10/100BaseTX", 0 },
212	{ DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
213	"ASIX AX88140A 10/100BaseTX", 0 },
214	{ DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
215	"ASIX AX88141 10/100BaseTX", 0 },
216	{ DC_VENDORID_MX, DC_DEVICEID_98713,
217	"Macronix 98713 10/100BaseTX", 0 },
218	{ DC_VENDORID_MX, DC_DEVICEID_98713,
219	"Macronix 98713A 10/100BaseTX", 0 },
220	{ DC_VENDORID_CP, DC_DEVICEID_98713_CP,
221	"Compex RL100-TX 10/100BaseTX", 0 },
222	{ DC_VENDORID_CP, DC_DEVICEID_98713_CP,
223	"Compex RL100-TX 10/100BaseTX", 0 },
224	{ DC_VENDORID_MX, DC_DEVICEID_987x5,
225	"Macronix 98715/98715A 10/100BaseTX", 0 },
226	{ DC_VENDORID_MX, DC_DEVICEID_987x5,
227	"Macronix 98715AEC-C 10/100BaseTX", 0 },
228	{ DC_VENDORID_MX, DC_DEVICEID_987x5,
229	"Macronix 98725 10/100BaseTX", 0 },
230	{ DC_VENDORID_MX, DC_DEVICEID_98727,
231	"Macronix 98727/98732 10/100BaseTX", 0 },
232	{ DC_VENDORID_LO, DC_DEVICEID_82C115,
233	"LC82C115 PNIC II 10/100BaseTX", 0 },
234	{ DC_VENDORID_LO, DC_DEVICEID_82C168,
235	"82c168 PNIC 10/100BaseTX", 0 },
236	{ DC_VENDORID_LO, DC_DEVICEID_82C168,
237	"82c169 PNIC 10/100BaseTX", 0 },
238	{ DC_VENDORID_ACCTON, DC_DEVICEID_EN1217,
239	"Accton EN1217 10/100BaseTX", 0 },
240	{ DC_VENDORID_ACCTON, DC_DEVICEID_EN2242,
241	"Accton EN2242 MiniPCI 10/100BaseTX", 0 },
242	{ DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112,
243	"Conexant LANfinity MiniPCI 10/100BaseTX", 0 },
244	{ 0, 0, NULL, 0 }
245	};
246
247	#if 0
248	static int dc_probe __P((device_t));
249	static int dc_attach __P((device_t));
250	static int dc_detach __P((device_t));
251	static int dc_suspend __P((device_t));
252	static int dc_resume __P((device_t));
253	static void dc_shutdown __P((device_t));
254	static void dc_acpi __P((device_t));
255	#endif
256
257	static struct dc_type *dc_devtype(int);
258	static int dc_newbuf(struct dc_softc , int, struct mbuf );
259	static int dc_encap(struct dc_softc , struct mbuf ,
260	u_int32_t *);
261	static int dc_coal(struct dc_softc , struct mbuf *);
262	static void dc_pnic_rx_bug_war(struct dc_softc *, int);
263	static int dc_rx_resync(struct dc_softc *);
264	static void dc_rxeof(struct dc_softc *);
265	static void dc_txeof(struct dc_softc *);
266	/static void dc_tick((void ));*/
267	static void dc_tx_underrun(struct dc_softc *);
268	static rtems_isr dc_intr(rtems_vector_number);
269	static void dc_daemon(void *);
270	static void dc_start(struct ifnet *);
271	static int dc_ioctl(struct ifnet *, int, caddr_t);
272	static void dc_init(void *);
273	static void dc_stop(struct dc_softc *);
274	static void dc_watchdog(struct ifnet *);
275	#if 0
276	static int dc_ifmedia_upd __P((struct ifnet *));
277	static void dc_ifmedia_sts __P((struct ifnet , struct ifmediareq ));
278	#endif
279
280	static void dc_delay(struct dc_softc *);
281	static void dc_eeprom_idle(struct dc_softc *);
282	static void dc_eeprom_putbyte(struct dc_softc *, int);
283	static void dc_eeprom_getword(struct dc_softc , int, u_int16_t );
284	static void dc_eeprom_getword_pnic(struct dc_softc , int, u_int16_t );
285	static void dc_eeprom_width(struct dc_softc *);
286	static void dc_read_eeprom(struct dc_softc *, caddr_t, int,int, int);
287
288	#if 0
289	static void dc_mii_writebit __P((struct dc_softc *, int));
290	static int dc_mii_readbit __P((struct dc_softc *));
291	static void dc_mii_sync __P((struct dc_softc *));
292	static void dc_mii_send __P((struct dc_softc *, u_int32_t, int));
293	static int dc_mii_readreg __P((struct dc_softc , struct dc_mii_frame ));
294	static int dc_mii_writereg __P((struct dc_softc , struct dc_mii_frame ));
295	static int dc_miibus_readreg __P((device_t, int, int));
296	static int dc_miibus_writereg __P((device_t, int, int, int));
297	static void dc_miibus_statchg __P((device_t));
298	static void dc_miibus_mediainit __P((device_t));
299	#endif
300
301	static void dc_setcfg(struct dc_softc *, int);
302	static u_int32_t dc_crc_le(struct dc_softc *, caddr_t);
303	static u_int32_t dc_crc_be(caddr_t);
304	static void dc_setfilt_21143(struct dc_softc *);
305	static void dc_setfilt_asix(struct dc_softc *);
306	static void dc_setfilt_admtek(struct dc_softc *);
307	static void dc_setfilt(struct dc_softc *);
308	static void dc_reset(struct dc_softc *);
309	static int dc_list_rx_init(struct dc_softc *);
310	static int dc_list_tx_init(struct dc_softc *);
311	static void dc_read_srom(struct dc_softc *, int);
312	static void dc_parse_21143_srom(struct dc_softc *);
313	static void dc_apply_fixup(struct dc_softc *, int);
314
315	#if 0
316	static void dc_decode_leaf_sia __P((struct dc_softc *,
317	struct dc_eblock_sia *));
318	static void dc_decode_leaf_mii __P((struct dc_softc *,
319	struct dc_eblock_mii *));
320	static void dc_decode_leaf_sym __P((struct dc_softc *,
321	struct dc_eblock_sym *));
322	#endif
323
324
325	#ifdef DC_USEIOSPACE
326	#define DC_RES SYS_RES_IOPORT
327	#define DC_RID DC_PCI_CFBIO
328	#else
329	#define DC_RES SYS_RES_MEMORY
330	#define DC_RID DC_PCI_CFBMA
331	#endif
332
333	#if 0
334	static device_method_t dc_methods[] = {
335	/* Device interface */
336	DEVMETHOD(device_probe, dc_probe),
337	DEVMETHOD(device_attach, dc_attach),
338	DEVMETHOD(device_detach, dc_detach),
339	DEVMETHOD(device_suspend, dc_suspend),
340	DEVMETHOD(device_resume, dc_resume),
341	DEVMETHOD(device_shutdown, dc_shutdown),
342
343	/* bus interface */
344	DEVMETHOD(bus_print_child, bus_generic_print_child),
345	DEVMETHOD(bus_driver_added, bus_generic_driver_added),
346
347	/* MII interface */
348	DEVMETHOD(miibus_readreg, dc_miibus_readreg),
349	DEVMETHOD(miibus_writereg, dc_miibus_writereg),
350	DEVMETHOD(miibus_statchg, dc_miibus_statchg),
351	DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
352
353	{ 0, 0 }
354	};
355
356	static driver_t dc_driver = {
357	"dc",
358	dc_methods,
359	sizeof(struct dc_softc)
360	};
361
362	static devclass_t dc_devclass;
363	#endif
364
365
366	#ifdef __i386__
367	static int dc_quick=1;
368	#if 0
369	SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW,
370	&dc_quick,0,"do not mdevget in dc driver");
371	#endif
372	#endif
373
374	#if 0
375	DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0);
376	DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
377	#endif
378
379
380	#define DC_SETBIT(sc, reg, x) \
381	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) \| (x))
382
383	#define DC_CLRBIT(sc, reg, x) \
384	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
385
386	#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
387	#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
388
389
390	/* XXX Fixme: rtems_bsp_delay( ) for the pc386 BSP (at least)
391	* needs work... see pc386/include/bsp.h.
392	* I have "a" solution, utilizing the 2nd i8254 timer,
393	* if anyone is interested (first timer is used for clock_tick ISR)...
394	*/
395	#ifdef __i386__
396	extern void Wait_X_ms( unsigned int );
397	#define DELAY(n) Wait_X_ms( (unsigned int)((n)/100) )
398	#else
399	#define DELAY(n) rtems_bsp_delay(n)
400	#endif
401
402
403	static void dc_delay(sc)
404	struct dc_softc *sc;
405	{
406	int idx;
407
408	for (idx = (300 / 33) + 1; idx > 0; idx--)
409	CSR_READ_4(sc, DC_BUSCTL);
410	}
411
412	static void dc_eeprom_width(sc)
413	struct dc_softc *sc;
414	{
415	int i;
416
417	/* Force EEPROM to idle state. */
418	dc_eeprom_idle(sc);
419
420	/* Enter EEPROM access mode. */
421	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
422	dc_delay(sc);
423	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
424	dc_delay(sc);
425	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
426	dc_delay(sc);
427	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
428	dc_delay(sc);
429
430	for (i = 3; i--;) {
431	if (6 & (1 << i))
432	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
433	else
434	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
435	dc_delay(sc);
436	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
437	dc_delay(sc);
438	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
439	dc_delay(sc);
440	}
441
442	for (i = 1; i <= 12; i++) {
443	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
444	dc_delay(sc);
445	if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
446	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
447	dc_delay(sc);
448	break;
449	}
450	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
451	dc_delay(sc);
452	}
453
454	/* Turn off EEPROM access mode. */
455	dc_eeprom_idle(sc);
456
457	if (i < 4 \|\| i > 12)
458	sc->dc_romwidth = 6;
459	else
460	sc->dc_romwidth = i;
461
462	/* Enter EEPROM access mode. */
463	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
464	dc_delay(sc);
465	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
466	dc_delay(sc);
467	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
468	dc_delay(sc);
469	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
470	dc_delay(sc);
471
472	/* Turn off EEPROM access mode. */
473	dc_eeprom_idle(sc);
474	}
475
476	static void dc_eeprom_idle(sc)
477	struct dc_softc *sc;
478	{
479	register int i;
480
481	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
482	dc_delay(sc);
483	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
484	dc_delay(sc);
485	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
486	dc_delay(sc);
487	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
488	dc_delay(sc);
489
490	for (i = 0; i < 25; i++) {
491	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
492	dc_delay(sc);
493	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
494	dc_delay(sc);
495	}
496
497	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
498	dc_delay(sc);
499	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
500	dc_delay(sc);
501	CSR_WRITE_4(sc, DC_SIO, 0x00000000);
502
503	return;
504	}
505
506	/*
507	* Send a read command and address to the EEPROM, check for ACK.
508	*/
509	static void dc_eeprom_putbyte(sc, addr)
510	struct dc_softc *sc;
511	int addr;
512	{
513	register int d, i;
514
515	d = DC_EECMD_READ >> 6;
516	for (i = 3; i--; ) {
517	if (d & (1 << i))
518	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
519	else
520	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
521	dc_delay(sc);
522	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
523	dc_delay(sc);
524	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
525	dc_delay(sc);
526	}
527
528	/*
529	* Feed in each bit and strobe the clock.
530	*/
531	for (i = sc->dc_romwidth; i--;) {
532	if (addr & (1 << i)) {
533	SIO_SET(DC_SIO_EE_DATAIN);
534	} else {
535	SIO_CLR(DC_SIO_EE_DATAIN);
536	}
537	dc_delay(sc);
538	SIO_SET(DC_SIO_EE_CLK);
539	dc_delay(sc);
540	SIO_CLR(DC_SIO_EE_CLK);
541	dc_delay(sc);
542	}
543
544	return;
545	}
546
547	/*
548	* Read a word of data stored in the EEPROM at address 'addr.'
549	* The PNIC 82c168/82c169 has its own non-standard way to read
550	* the EEPROM.
551	*/
552	static void dc_eeprom_getword_pnic(sc, addr, dest)
553	struct dc_softc *sc;
554	int addr;
555	u_int16_t *dest;
556	{
557	register int i;
558	u_int32_t r;
559
560	CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ\|addr);
561
562	for (i = 0; i < DC_TIMEOUT; i++) {
563	DELAY(1);
564	r = CSR_READ_4(sc, DC_SIO);
565	if (!(r & DC_PN_SIOCTL_BUSY)) {
566	*dest = (u_int16_t)(r & 0xFFFF);
567	return;
568	}
569	}
570
571	return;
572	}
573
574	/*
575	* Read a word of data stored in the EEPROM at address 'addr.'
576	*/
577	static void dc_eeprom_getword(sc, addr, dest)
578	struct dc_softc *sc;
579	int addr;
580	u_int16_t *dest;
581	{
582	register int i;
583	u_int16_t word = 0;
584
585	/* Force EEPROM to idle state. */
586	dc_eeprom_idle(sc);
587
588	/* Enter EEPROM access mode. */
589	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
590	dc_delay(sc);
591	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
592	dc_delay(sc);
593	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
594	dc_delay(sc);
595	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
596	dc_delay(sc);
597
598	/*
599	* Send address of word we want to read.
600	*/
601	dc_eeprom_putbyte(sc, addr);
602
603	/*
604	* Start reading bits from EEPROM.
605	*/
606	for (i = 0x8000; i; i >>= 1) {
607	SIO_SET(DC_SIO_EE_CLK);
608	dc_delay(sc);
609	if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
610	word \|= i;
611	dc_delay(sc);
612	SIO_CLR(DC_SIO_EE_CLK);
613	dc_delay(sc);
614	}
615
616	/* Turn off EEPROM access mode. */
617	dc_eeprom_idle(sc);
618
619	*dest = word;
620
621	return;
622	}
623
624	/*
625	* Read a sequence of words from the EEPROM.
626	*/
627	static void dc_read_eeprom(sc, dest, off, cnt, swap)
628	struct dc_softc *sc;
629	caddr_t dest;
630	int off;
631	int cnt;
632	int swap;
633	{
634	int i;
635	u_int16_t word = 0, *ptr;
636
637	for (i = 0; i < cnt; i++) {
638	if (DC_IS_PNIC(sc))
639	dc_eeprom_getword_pnic(sc, off + i, &word);
640	else
641	dc_eeprom_getword(sc, off + i, &word);
642	ptr = (u_int16_t )(dest + (i 2));
643	if (swap)
644	*ptr = ntohs(word);
645	else
646	*ptr = word;
647	}
648
649	return;
650	}
651
652
653	#if 0
654	/*
655	* The following two routines are taken from the Macronix 98713
656	* Application Notes pp.19-21.
657	*/
658	/*
659	* Write a bit to the MII bus.
660	*/
661	static void dc_mii_writebit(sc, bit)
662	struct dc_softc *sc;
663	int bit;
664	{
665	if (bit)
666	CSR_WRITE_4(sc, DC_SIO,
667	DC_SIO_ROMCTL_WRITE\|DC_SIO_MII_DATAOUT);
668	else
669	CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
670
671	DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
672	DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
673
674	return;
675	}
676
677	/*
678	* Read a bit from the MII bus.
679	*/
680	static int dc_mii_readbit(sc)
681	struct dc_softc *sc;
682	{
683	CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ\|DC_SIO_MII_DIR);
684	CSR_READ_4(sc, DC_SIO);
685	DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
686	DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
687	if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
688	return(1);
689
690	return(0);
691	}
692
693	/*
694	* Sync the PHYs by setting data bit and strobing the clock 32 times.
695	*/
696	static void dc_mii_sync(sc)
697	struct dc_softc *sc;
698	{
699	register int i;
700
701	CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
702
703	for (i = 0; i < 32; i++)
704	dc_mii_writebit(sc, 1);
705
706	return;
707	}
708
709	/*
710	* Clock a series of bits through the MII.
711	*/
712	static void dc_mii_send(sc, bits, cnt)
713	struct dc_softc *sc;
714	u_int32_t bits;
715	int cnt;
716	{
717	int i;
718
719	for (i = (0x1 << (cnt - 1)); i; i >>= 1)
720	dc_mii_writebit(sc, bits & i);
721	}
722
723	/*
724	* Read an PHY register through the MII.
725	*/
726	static int dc_mii_readreg(sc, frame)
727	struct dc_softc *sc;
728	struct dc_mii_frame *frame;
729
730	{
731	int i, ack, s;
732
733
734	/*
735	* Set up frame for RX.
736	*/
737	frame->mii_stdelim = DC_MII_STARTDELIM;
738	frame->mii_opcode = DC_MII_READOP;
739	frame->mii_turnaround = 0;
740	frame->mii_data = 0;
741
742	/*
743	* Sync the PHYs.
744	*/
745	dc_mii_sync(sc);
746
747	/*
748	* Send command/address info.
749	*/
750	dc_mii_send(sc, frame->mii_stdelim, 2);
751	dc_mii_send(sc, frame->mii_opcode, 2);
752	dc_mii_send(sc, frame->mii_phyaddr, 5);
753	dc_mii_send(sc, frame->mii_regaddr, 5);
754
755	#ifdef notdef
756	/* Idle bit */
757	dc_mii_writebit(sc, 1);
758	dc_mii_writebit(sc, 0);
759	#endif
760
761	/* Check for ack */
762	ack = dc_mii_readbit(sc);
763
764	/*
765	* Now try reading data bits. If the ack failed, we still
766	* need to clock through 16 cycles to keep the PHY(s) in sync.
767	*/
768	if (ack) {
769	for(i = 0; i < 16; i++) {
770	dc_mii_readbit(sc);
771	}
772	goto fail;
773	}
774
775	for (i = 0x8000; i; i >>= 1) {
776	if (!ack) {
777	if (dc_mii_readbit(sc))
778	frame->mii_data \|= i;
779	}
780	}
781
782	fail:
783
784	dc_mii_writebit(sc, 0);
785	dc_mii_writebit(sc, 0);
786
787
788	if (ack)
789	return(1);
790	return(0);
791	}
792
793	/*
794	* Write to a PHY register through the MII.
795	*/
796	static int dc_mii_writereg(sc, frame)
797	struct dc_softc *sc;
798	struct dc_mii_frame *frame;
799
800	{
801	int s;
802
803	/*
804	* Set up frame for TX.
805	*/
806
807	frame->mii_stdelim = DC_MII_STARTDELIM;
808	frame->mii_opcode = DC_MII_WRITEOP;
809	frame->mii_turnaround = DC_MII_TURNAROUND;
810
811	/*
812	* Sync the PHYs.
813	*/
814	dc_mii_sync(sc);
815
816	dc_mii_send(sc, frame->mii_stdelim, 2);
817	dc_mii_send(sc, frame->mii_opcode, 2);
818	dc_mii_send(sc, frame->mii_phyaddr, 5);
819	dc_mii_send(sc, frame->mii_regaddr, 5);
820	dc_mii_send(sc, frame->mii_turnaround, 2);
821	dc_mii_send(sc, frame->mii_data, 16);
822
823	/* Idle bit. */
824	dc_mii_writebit(sc, 0);
825	dc_mii_writebit(sc, 0);
826
827
828	return(0);
829	}
830
831	static int dc_miibus_readreg(dev, phy, reg)
832	device_t dev;
833	int phy, reg;
834	{
835	struct dc_mii_frame frame;
836	struct dc_softc *sc;
837	int i, rval, phy_reg = 0;
838
839	sc = device_get_softc(dev);
840	bzero((char *)&frame, sizeof(frame));
841
842	/*
843	* Note: both the AL981 and AN985 have internal PHYs,
844	* however the AL981 provides direct access to the PHY
845	* registers while the AN985 uses a serial MII interface.
846	* The AN985's MII interface is also buggy in that you
847	* can read from any MII address (0 to 31), but only address 1
848	* behaves normally. To deal with both cases, we pretend
849	* that the PHY is at MII address 1.
850	*/
851	if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
852	return(0);
853
854	/*
855	* Note: the ukphy probes of the RS7112 report a PHY at
856	* MII address 0 (possibly HomePNA?) and 1 (ethernet)
857	* so we only respond to correct one.
858	*/
859	if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
860	return(0);
861
862	if (sc->dc_pmode != DC_PMODE_MII) {
863	if (phy == (MII_NPHY - 1)) {
864	switch(reg) {
865	case MII_BMSR:
866	/*
867	* Fake something to make the probe
868	* code think there's a PHY here.
869	*/
870	return(BMSR_MEDIAMASK);
871	break;
872	case MII_PHYIDR1:
873	if (DC_IS_PNIC(sc))
874	return(DC_VENDORID_LO);
875	return(DC_VENDORID_DEC);
876	break;
877	case MII_PHYIDR2:
878	if (DC_IS_PNIC(sc))
879	return(DC_DEVICEID_82C168);
880	return(DC_DEVICEID_21143);
881	break;
882	default:
883	return(0);
884	break;
885	}
886	} else
887	return(0);
888	}
889
890	if (DC_IS_PNIC(sc)) {
891	CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ \|
892	(phy << 23) \| (reg << 18));
893	for (i = 0; i < DC_TIMEOUT; i++) {
894	DELAY(1);
895	rval = CSR_READ_4(sc, DC_PN_MII);
896	if (!(rval & DC_PN_MII_BUSY)) {
897	rval &= 0xFFFF;
898	return(rval == 0xFFFF ? 0 : rval);
899	}
900	}
901	return(0);
902	}
903
904	if (DC_IS_COMET(sc)) {
905	switch(reg) {
906	case MII_BMCR:
907	phy_reg = DC_AL_BMCR;
908	break;
909	case MII_BMSR:
910	phy_reg = DC_AL_BMSR;
911	break;
912	case MII_PHYIDR1:
913	phy_reg = DC_AL_VENID;
914	break;
915	case MII_PHYIDR2:
916	phy_reg = DC_AL_DEVID;
917	break;
918	case MII_ANAR:
919	phy_reg = DC_AL_ANAR;
920	break;
921	case MII_ANLPAR:
922	phy_reg = DC_AL_LPAR;
923	break;
924	case MII_ANER:
925	phy_reg = DC_AL_ANER;
926	break;
927	default:
928	printk("dc%d: phy_read: bad phy register %x\n",
929	sc->dc_unit, reg);
930	return(0);
931	break;
932	}
933
934	rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
935
936	if (rval == 0xFFFF)
937	return(0);
938	return(rval);
939	}
940
941	frame.mii_phyaddr = phy;
942	frame.mii_regaddr = reg;
943	if (sc->dc_type == DC_TYPE_98713) {
944	phy_reg = CSR_READ_4(sc, DC_NETCFG);
945	CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
946	}
947	dc_mii_readreg(sc, &frame);
948	if (sc->dc_type == DC_TYPE_98713)
949	CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
950
951	return(frame.mii_data);
952	}
953
954	static int dc_miibus_writereg(dev, phy, reg, data)
955	device_t dev;
956	int phy, reg, data;
957	{
958	struct dc_softc *sc;
959	struct dc_mii_frame frame;
960	int i, phy_reg = 0;
961
962	sc = device_get_softc(dev);
963	bzero((char *)&frame, sizeof(frame));
964
965	if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
966	return(0);
967
968	if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
969	return(0);
970
971	if (DC_IS_PNIC(sc)) {
972	CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE \|
973	(phy << 23) \| (reg << 10) \| data);
974	for (i = 0; i < DC_TIMEOUT; i++) {
975	if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
976	break;
977	}
978	return(0);
979	}
980
981	if (DC_IS_COMET(sc)) {
982	switch(reg) {
983	case MII_BMCR:
984	phy_reg = DC_AL_BMCR;
985	break;
986	case MII_BMSR:
987	phy_reg = DC_AL_BMSR;
988	break;
989	case MII_PHYIDR1:
990	phy_reg = DC_AL_VENID;
991	break;
992	case MII_PHYIDR2:
993	phy_reg = DC_AL_DEVID;
994	break;
995	case MII_ANAR:
996	phy_reg = DC_AL_ANAR;
997	break;
998	case MII_ANLPAR:
999	phy_reg = DC_AL_LPAR;
1000	break;
1001	case MII_ANER:
1002	phy_reg = DC_AL_ANER;
1003	break;
1004	default:
1005	printk("dc%d: phy_write: bad phy register %x\n",
1006	sc->dc_unit, reg);
1007	return(0);
1008	break;
1009	}
1010
1011	CSR_WRITE_4(sc, phy_reg, data);
1012	return(0);
1013	}
1014
1015	frame.mii_phyaddr = phy;
1016	frame.mii_regaddr = reg;
1017	frame.mii_data = data;
1018
1019	if (sc->dc_type == DC_TYPE_98713) {
1020	phy_reg = CSR_READ_4(sc, DC_NETCFG);
1021	CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
1022	}
1023	dc_mii_writereg(sc, &frame);
1024	if (sc->dc_type == DC_TYPE_98713)
1025	CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
1026
1027	return(0);
1028	}
1029
1030	static void dc_miibus_statchg(dev)
1031	device_t dev;
1032	{
1033	struct dc_softc *sc;
1034	struct mii_data *mii;
1035	struct ifmedia *ifm;
1036
1037	sc = device_get_softc(dev);
1038	if (DC_IS_ADMTEK(sc))
1039	return;
1040
1041	mii = device_get_softc(sc->dc_miibus);
1042	ifm = &mii->mii_media;
1043	if (DC_IS_DAVICOM(sc) &&
1044	IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) {
1045	dc_setcfg(sc, ifm->ifm_media);
1046	sc->dc_if_media = ifm->ifm_media;
1047	} else {
1048	dc_setcfg(sc, mii->mii_media_active);
1049	sc->dc_if_media = mii->mii_media_active;
1050	}
1051
1052	return;
1053	}
1054
1055	/*
1056	* Special support for DM9102A cards with HomePNA PHYs. Note:
1057	* with the Davicom DM9102A/DM9801 eval board that I have, it seems
1058	* to be impossible to talk to the management interface of the DM9801
1059	* PHY (its MDIO pin is not connected to anything). Consequently,
1060	* the driver has to just 'know' about the additional mode and deal
1061	* with it itself. sigh
1062	*/
1063	static void dc_miibus_mediainit(dev)
1064	device_t dev;
1065	{
1066	struct dc_softc *sc;
1067	struct mii_data *mii;
1068	struct ifmedia *ifm;
1069	int rev;
1070
1071	rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF;
1072
1073	sc = device_get_softc(dev);
1074	mii = device_get_softc(sc->dc_miibus);
1075	ifm = &mii->mii_media;
1076
1077	if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
1078	ifmedia_add(ifm, IFM_ETHER\|IFM_homePNA, 0, NULL);
1079
1080	return;
1081	}
1082	#endif
1083
1084	#define DC_POLY 0xEDB88320
1085	#define DC_BITS_512 9
1086	#define DC_BITS_128 7
1087	#define DC_BITS_64 6
1088
1089	static u_int32_t dc_crc_le(sc, addr)
1090	struct dc_softc *sc;
1091	caddr_t addr;
1092	{
1093	u_int32_t idx, bit, data, crc;
1094
1095	/* Compute CRC for the address value. */
1096	crc = 0xFFFFFFFF; /* initial value */
1097
1098	for (idx = 0; idx < 6; idx++) {
1099	for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
1100	crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0);
1101	}
1102
1103	/*
1104	* The hash table on the PNIC II and the MX98715AEC-C/D/E
1105	* chips is only 128 bits wide.
1106	*/
1107	if (sc->dc_flags & DC_128BIT_HASH)
1108	return (crc & ((1 << DC_BITS_128) - 1));
1109
1110	/* The hash table on the MX98715BEC is only 64 bits wide. */
1111	if (sc->dc_flags & DC_64BIT_HASH)
1112	return (crc & ((1 << DC_BITS_64) - 1));
1113
1114	return (crc & ((1 << DC_BITS_512) - 1));
1115	}
1116
1117	/*
1118	* Calculate CRC of a multicast group address, return the lower 6 bits.
1119	*/
1120	static u_int32_t dc_crc_be(addr)
1121	caddr_t addr;
1122	{
1123	u_int32_t crc, carry;
1124	int i, j;
1125	u_int8_t c;
1126
1127	/* Compute CRC for the address value. */
1128	crc = 0xFFFFFFFF; /* initial value */
1129
1130	for (i = 0; i < 6; i++) {
1131	c = *(addr + i);
1132	for (j = 0; j < 8; j++) {
1133	carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
1134	crc <<= 1;
1135	c >>= 1;
1136	if (carry)
1137	crc = (crc ^ 0x04c11db6) \| carry;
1138	}
1139	}
1140
1141	/* return the filter bit position */
1142	return((crc >> 26) & 0x0000003F);
1143	}
1144
1145
1146	/*
1147	* 21143-style RX filter setup routine. Filter programming is done by
1148	* downloading a special setup frame into the TX engine. 21143, Macronix,
1149	* PNIC, PNIC II and Davicom chips are programmed this way.
1150	*
1151	* We always program the chip using 'hash perfect' mode, i.e. one perfect
1152	* address (our node address) and a 512-bit hash filter for multicast
1153	* frames. We also sneak the broadcast address into the hash filter since
1154	* we need that too.
1155	*/
1156	void dc_setfilt_21143(sc)
1157	struct dc_softc *sc;
1158	{
1159	struct dc_desc *sframe;
1160	u_int32_t h, *sp;
1161	/struct ifmultiaddr ifma;*/
1162	struct ifnet *ifp;
1163	int i;
1164
1165	ifp = &sc->arpcom.ac_if;
1166
1167	i = sc->dc_cdata.dc_tx_prod;
1168	DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1169	sc->dc_cdata.dc_tx_cnt++;
1170	sframe = &sc->dc_ldata->dc_tx_list[i];
1171	sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf;
1172	bzero((char *)sp, DC_SFRAME_LEN);
1173
1174	sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf);
1175	sframe->dc_ctl = DC_SFRAME_LEN \| DC_TXCTL_SETUP \| DC_TXCTL_TLINK \|
1176	DC_FILTER_HASHPERF \| DC_TXCTL_FINT;
1177
1178	sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf;
1179
1180	/* If we want promiscuous mode, set the allframes bit. */
1181	if (ifp->if_flags & IFF_PROMISC)
1182	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1183	else
1184	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1185
1186	if (ifp->if_flags & IFF_ALLMULTI)
1187	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1188	else
1189	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1190	#if 0
1191	for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1192	ifma = ifma->ifma_link.le_next) {
1193	if (ifma->ifma_addr->sa_family != AF_LINK)
1194	continue;
1195	h = dc_crc_le(sc,
1196	LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1197	sp[h >> 4] \|= 1 << (h & 0xF);
1198	}
1199	#endif
1200
1201	if (ifp->if_flags & IFF_BROADCAST) {
1202	h = dc_crc_le(sc, (caddr_t)&etherbroadcastaddr);
1203	sp[h >> 4] \|= 1 << (h & 0xF);
1204	}
1205
1206	/* Set our MAC address */
1207	sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0];
1208	sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1];
1209	sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2];
1210
1211	sframe->dc_status = DC_TXSTAT_OWN;
1212	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1213
1214	/*
1215	* The PNIC takes an exceedingly long time to process its
1216	* setup frame; wait 10ms after posting the setup frame
1217	* before proceeding, just so it has time to swallow its
1218	* medicine.
1219	*/
1220	DELAY(10000);
1221
1222	ifp->if_timer = 5;
1223
1224	return;
1225	}
1226
1227	void dc_setfilt_admtek(sc)
1228	struct dc_softc *sc;
1229	{
1230	struct ifnet *ifp;
1231	#if 0
1232	int h = 0;
1233	u_int32_t hashes[2] = { 0, 0 };
1234	struct ifmultiaddr *ifma;
1235	#endif
1236
1237	ifp = &sc->arpcom.ac_if;
1238
1239	/* Init our MAC address */
1240	CSR_WRITE_4(sc, DC_AL_PAR0, (u_int32_t )(&sc->arpcom.ac_enaddr[0]));
1241	CSR_WRITE_4(sc, DC_AL_PAR1, (u_int32_t )(&sc->arpcom.ac_enaddr[4]));
1242
1243	/* If we want promiscuous mode, set the allframes bit. */
1244	if (ifp->if_flags & IFF_PROMISC)
1245	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1246	else
1247	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1248
1249	if (ifp->if_flags & IFF_ALLMULTI)
1250	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1251	else
1252	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1253
1254	/* first, zot all the existing hash bits */
1255	CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1256	CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1257
1258	#if 0
1259	/*
1260	* If we're already in promisc or allmulti mode, we
1261	* don't have to bother programming the multicast filter.
1262	*/
1263	if (ifp->if_flags & (IFF_PROMISC\|IFF_ALLMULTI))
1264	return;
1265
1266	/* now program new ones */
1267	for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1268	ifma = ifma->ifma_link.le_next) {
1269	if (ifma->ifma_addr->sa_family != AF_LINK)
1270	continue;
1271	h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1272	if (h < 32)
1273	hashes[0] \|= (1 << h);
1274	else
1275	hashes[1] \|= (1 << (h - 32));
1276	}
1277
1278	CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1279	CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1280	#endif
1281	return;
1282	}
1283
1284	void dc_setfilt_asix(sc)
1285	struct dc_softc *sc;
1286	{
1287	struct ifnet *ifp;
1288	#if 0
1289	int h = 0;
1290	u_int32_t hashes[2] = { 0, 0 };
1291	struct ifmultiaddr *ifma;
1292	#endif
1293
1294	ifp = &sc->arpcom.ac_if;
1295
1296	/* Init our MAC address */
1297	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1298	CSR_WRITE_4(sc, DC_AX_FILTDATA,
1299	(u_int32_t )(&sc->arpcom.ac_enaddr[0]));
1300	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1301	CSR_WRITE_4(sc, DC_AX_FILTDATA,
1302	(u_int32_t )(&sc->arpcom.ac_enaddr[4]));
1303
1304	/* If we want promiscuous mode, set the allframes bit. */
1305	if (ifp->if_flags & IFF_PROMISC)
1306	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1307	else
1308	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1309
1310	if (ifp->if_flags & IFF_ALLMULTI)
1311	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1312	else
1313	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1314
1315	/*
1316	* The ASIX chip has a special bit to enable reception
1317	* of broadcast frames.
1318	*/
1319	if (ifp->if_flags & IFF_BROADCAST)
1320	DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1321	else
1322	DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1323
1324	/* first, zot all the existing hash bits */
1325	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1326	CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1327	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1328	CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1329
1330	#if 0
1331	/*
1332	* If we're already in promisc or allmulti mode, we
1333	* don't have to bother programming the multicast filter.
1334	*/
1335	if (ifp->if_flags & (IFF_PROMISC\|IFF_ALLMULTI))
1336	return;
1337
1338	/* now program new ones */
1339	for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1340	ifma = ifma->ifma_link.le_next) {
1341	if (ifma->ifma_addr->sa_family != AF_LINK)
1342	continue;
1343	h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1344	if (h < 32)
1345	hashes[0] \|= (1 << h);
1346	else
1347	hashes[1] \|= (1 << (h - 32));
1348	}
1349
1350	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1351	CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1352	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1353	CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1354	#endif
1355	return;
1356	}
1357
1358	static void dc_setfilt(sc)
1359	struct dc_softc *sc;
1360	{
1361	if (DC_IS_INTEL(sc) \|\| DC_IS_MACRONIX(sc) \|\| DC_IS_PNIC(sc) \|\|
1362	DC_IS_PNICII(sc) \|\| DC_IS_DAVICOM(sc) \|\| DC_IS_CONEXANT(sc))
1363	dc_setfilt_21143(sc);
1364
1365	if (DC_IS_ASIX(sc))
1366	dc_setfilt_asix(sc);
1367
1368	if (DC_IS_ADMTEK(sc))
1369	dc_setfilt_admtek(sc);
1370
1371	return;
1372	}
1373
1374	/*
1375	* In order to fiddle with the
1376	* 'full-duplex' and '100Mbps' bits in the netconfig register, we
1377	* first have to put the transmit and/or receive logic in the idle state.
1378	*/
1379	static void dc_setcfg(sc, media)
1380	struct dc_softc *sc;
1381	int media;
1382	{
1383	int i, restart = 0;
1384	u_int32_t isr;
1385
1386	if (IFM_SUBTYPE(media) == IFM_NONE)
1387	return;
1388
1389	if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON\|DC_NETCFG_RX_ON)) {
1390	restart = 1;
1391	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON\|DC_NETCFG_RX_ON));
1392
1393	for (i = 0; i < DC_TIMEOUT; i++) {
1394	isr = CSR_READ_4(sc, DC_ISR);
1395	if (isr & DC_ISR_TX_IDLE \|\|
1396	(isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED)
1397	break;
1398	DELAY(10);
1399	}
1400
1401	if (i == DC_TIMEOUT)
1402	printk("dc%d: failed to force tx and "
1403	"rx to idle state\n", sc->dc_unit);
1404	}
1405
1406	if (IFM_SUBTYPE(media) == IFM_100_TX) {
1407	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1408	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1409	if (sc->dc_pmode == DC_PMODE_MII) {
1410	int watchdogreg;
1411
1412	if (DC_IS_INTEL(sc)) {
1413	/* there's a write enable bit here that reads as 1 */
1414	watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1415	watchdogreg &= ~DC_WDOG_CTLWREN;
1416	watchdogreg \|= DC_WDOG_JABBERDIS;
1417	CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1418	} else {
1419	DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1420	}
1421	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS\|
1422	DC_NETCFG_PORTSEL\|DC_NETCFG_SCRAMBLER));
1423	if (sc->dc_type == DC_TYPE_98713)
1424	DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS\|
1425	DC_NETCFG_SCRAMBLER));
1426	if (!DC_IS_DAVICOM(sc))
1427	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1428	DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1429	if (DC_IS_INTEL(sc))
1430	dc_apply_fixup(sc, IFM_AUTO);
1431	} else {
1432	if (DC_IS_PNIC(sc)) {
1433	DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1434	DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1435	DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1436	}
1437	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1438	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1439	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1440	if (DC_IS_INTEL(sc))
1441	dc_apply_fixup(sc,
1442	(media & IFM_GMASK) == IFM_FDX ?
1443	IFM_100_TX\|IFM_FDX : IFM_100_TX);
1444	}
1445	}
1446
1447	if (IFM_SUBTYPE(media) == IFM_10_T) {
1448	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1449	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1450	if (sc->dc_pmode == DC_PMODE_MII) {
1451	int watchdogreg;
1452
1453	/* there's a write enable bit here that reads as 1 */
1454	if (DC_IS_INTEL(sc)) {
1455	watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1456	watchdogreg &= ~DC_WDOG_CTLWREN;
1457	watchdogreg \|= DC_WDOG_JABBERDIS;
1458	CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1459	} else {
1460	DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1461	}
1462	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS\|
1463	DC_NETCFG_PORTSEL\|DC_NETCFG_SCRAMBLER));
1464	if (sc->dc_type == DC_TYPE_98713)
1465	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1466	if (!DC_IS_DAVICOM(sc))
1467	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1468	DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1469	if (DC_IS_INTEL(sc))
1470	dc_apply_fixup(sc, IFM_AUTO);
1471	} else {
1472	if (DC_IS_PNIC(sc)) {
1473	DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1474	DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1475	DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1476	}
1477	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1478	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1479	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1480	if (DC_IS_INTEL(sc)) {
1481	DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1482	DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1483	if ((media & IFM_GMASK) == IFM_FDX)
1484	DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1485	else
1486	DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1487	DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1488	DC_CLRBIT(sc, DC_10BTCTRL,
1489	DC_TCTL_AUTONEGENBL);
1490	dc_apply_fixup(sc,
1491	(media & IFM_GMASK) == IFM_FDX ?
1492	IFM_10_T\|IFM_FDX : IFM_10_T);
1493	DELAY(20000);
1494	}
1495	}
1496	}
1497
1498	#if 0
1499	/*
1500	* If this is a Davicom DM9102A card with a DM9801 HomePNA
1501	* PHY and we want HomePNA mode, set the portsel bit to turn
1502	* on the external MII port.
1503	*/
1504	if (DC_IS_DAVICOM(sc)) {
1505	if (IFM_SUBTYPE(media) == IFM_homePNA) {
1506	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1507	sc->dc_link = 1;
1508	} else {
1509	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1510	}
1511	}
1512	#endif
1513
1514	if ((media & IFM_GMASK) == IFM_FDX) {
1515	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1516	if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1517	DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1518	} else {
1519	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1520	if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1521	DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1522	}
1523
1524	if (restart)
1525	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON\|DC_NETCFG_RX_ON);
1526
1527	return;
1528	}
1529
1530	static void dc_reset(sc)
1531	struct dc_softc *sc;
1532	{
1533	register int i;
1534
1535	DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1536
1537	for (i = 0; i < DC_TIMEOUT; i++) {
1538	DELAY(10);
1539	if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1540	break;
1541	}
1542
1543	if (DC_IS_ASIX(sc) \|\| DC_IS_ADMTEK(sc) \|\| DC_IS_CONEXANT(sc)) {
1544	DELAY(10000);
1545	DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1546	i = 0;
1547	}
1548
1549	if (i == DC_TIMEOUT)
1550	printk("dc%d: reset never completed!\n", sc->dc_unit);
1551
1552	/* Wait a little while for the chip to get its brains in order. */
1553	DELAY(1000);
1554
1555	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1556	CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1557	CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1558
1559	/*
1560	* Bring the SIA out of reset. In some cases, it looks
1561	* like failing to unreset the SIA soon enough gets it
1562	* into a state where it will never come out of reset
1563	* until we reset the whole chip again.
1564	*/
1565	if (DC_IS_INTEL(sc)) {
1566	DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1567	CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1568	CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1569	}
1570
1571	return;
1572	}
1573
1574	static
1575	struct dc_type *dc_devtype( int unitnum )
1576	{
1577	struct dc_type *t;
1578	u_int32_t rev;
1579	int rc;
1580
1581
1582	t = dc_devs;
1583
1584	while(t->dc_name != NULL) {
1585	rc = pcib_find_by_devid(t->dc_vid, t->dc_did, \
1586	(unitnum - 1), &t->dc_devsig);
1587	if (rc == PCIB_ERR_SUCCESS) {
1588	/* Check the PCI revision */
1589	pcib_conf_read32(t->dc_devsig, DC_PCI_CFRV, &rev);
1590	rev &= 0xFF;
1591	if (t->dc_did == DC_DEVICEID_98713 &&
1592	rev >= DC_REVISION_98713A)
1593	t++;
1594	if (t->dc_did == DC_DEVICEID_98713_CP &&
1595	rev >= DC_REVISION_98713A)
1596	t++;
1597	if (t->dc_did == DC_DEVICEID_987x5 &&
1598	rev >= DC_REVISION_98715AEC_C)
1599	t++;
1600	if (t->dc_did == DC_DEVICEID_987x5 &&
1601	rev >= DC_REVISION_98725)
1602	t++;
1603	if (t->dc_did == DC_DEVICEID_AX88140A &&
1604	rev >= DC_REVISION_88141)
1605	t++;
1606	if (t->dc_did == DC_DEVICEID_82C168 &&
1607	rev >= DC_REVISION_82C169)
1608	t++;
1609	if (t->dc_did == DC_DEVICEID_DM9102 &&
1610	rev >= DC_REVISION_DM9102A)
1611	t++;
1612	return(t);
1613	}
1614	t++;
1615	}
1616
1617	return(NULL);
1618	}
1619
1620	#if 0
1621	/*
1622	* Probe for a 21143 or clone chip. Check the PCI vendor and device
1623	* IDs against our list and return a device name if we find a match.
1624	* We do a little bit of extra work to identify the exact type of
1625	* chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1626	* but different revision IDs. The same is true for 98715/98715A
1627	* chips and the 98725, as well as the ASIX and ADMtek chips. In some
1628	* cases, the exact chip revision affects driver behavior.
1629	*/
1630	static int dc_probe(dev)
1631	device_t dev;
1632	{
1633	struct dc_type *t;
1634
1635	t = dc_devtype(dev);
1636
1637	if (t != NULL) {
1638	device_set_desc(dev, t->dc_name);
1639	return(0);
1640	}
1641
1642	return(ENXIO);
1643	}
1644
1645
1646	static void dc_acpi(dev)
1647	device_t dev;
1648	{
1649	u_int32_t r, cptr;
1650	int unit;
1651
1652	unit = device_get_unit(dev);
1653
1654	/* Find the location of the capabilities block */
1655	cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF;
1656
1657	r = pci_read_config(dev, cptr, 4) & 0xFF;
1658	if (r == 0x01) {
1659
1660	r = pci_read_config(dev, cptr + 4, 4);
1661	if (r & DC_PSTATE_D3) {
1662	u_int32_t iobase, membase, irq;
1663
1664	/* Save important PCI config data. */
1665	iobase = pci_read_config(dev, DC_PCI_CFBIO, 4);
1666	membase = pci_read_config(dev, DC_PCI_CFBMA, 4);
1667	irq = pci_read_config(dev, DC_PCI_CFIT, 4);
1668
1669	/* Reset the power state. */
1670	printk("dc%d: chip is in D%d power mode "
1671	"-- setting to D0\n", unit, r & DC_PSTATE_D3);
1672	r &= 0xFFFFFFFC;
1673	pci_write_config(dev, cptr + 4, r, 4);
1674
1675	/* Restore PCI config data. */
1676	pci_write_config(dev, DC_PCI_CFBIO, iobase, 4);
1677	pci_write_config(dev, DC_PCI_CFBMA, membase, 4);
1678	pci_write_config(dev, DC_PCI_CFIT, irq, 4);
1679	}
1680	}
1681	return;
1682	}
1683	#endif
1684
1685
1686	static void dc_apply_fixup(sc, media)
1687	struct dc_softc *sc;
1688	int media;
1689	{
1690	struct dc_mediainfo *m;
1691	u_int8_t *p;
1692	int i;
1693	u_int32_t reg;
1694
1695	m = sc->dc_mi;
1696
1697	while (m != NULL) {
1698	if (m->dc_media == media)
1699	break;
1700	m = m->dc_next;
1701	}
1702
1703	if (m == NULL)
1704	return;
1705
1706	for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1707	reg = (p[0] \| (p[1] << 8)) << 16;
1708	CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1709	}
1710
1711	for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1712	reg = (p[0] \| (p[1] << 8)) << 16;
1713	CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1714	}
1715
1716	return;
1717	}
1718
1719	#if 0
1720	static void dc_decode_leaf_sia(sc, l)
1721	struct dc_softc *sc;
1722	struct dc_eblock_sia *l;
1723	{
1724	struct dc_mediainfo *m;
1725
1726	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1727	bzero(m, sizeof(struct dc_mediainfo));
1728	if (l->dc_sia_code == DC_SIA_CODE_10BT)
1729	m->dc_media = IFM_10_T;
1730
1731	if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX)
1732	m->dc_media = IFM_10_T\|IFM_FDX;
1733
1734	if (l->dc_sia_code == DC_SIA_CODE_10B2)
1735	m->dc_media = IFM_10_2;
1736
1737	if (l->dc_sia_code == DC_SIA_CODE_10B5)
1738	m->dc_media = IFM_10_5;
1739
1740	m->dc_gp_len = 2;
1741	m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl;
1742
1743	m->dc_next = sc->dc_mi;
1744	sc->dc_mi = m;
1745
1746	sc->dc_pmode = DC_PMODE_SIA;
1747
1748	return;
1749	}
1750
1751	static void dc_decode_leaf_sym(sc, l)
1752	struct dc_softc *sc;
1753	struct dc_eblock_sym *l;
1754	{
1755	struct dc_mediainfo *m;
1756
1757	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1758	bzero(m, sizeof(struct dc_mediainfo));
1759	if (l->dc_sym_code == DC_SYM_CODE_100BT)
1760	m->dc_media = IFM_100_TX;
1761
1762	if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1763	m->dc_media = IFM_100_TX\|IFM_FDX;
1764
1765	m->dc_gp_len = 2;
1766	m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
1767
1768	m->dc_next = sc->dc_mi;
1769	sc->dc_mi = m;
1770
1771	sc->dc_pmode = DC_PMODE_SYM;
1772
1773	return;
1774	}
1775
1776	static void dc_decode_leaf_mii(sc, l)
1777	struct dc_softc *sc;
1778	struct dc_eblock_mii *l;
1779	{
1780	u_int8_t *p;
1781	struct dc_mediainfo *m;
1782
1783	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1784	bzero(m, sizeof(struct dc_mediainfo));
1785	/* We abuse IFM_AUTO to represent MII. */
1786	m->dc_media = IFM_AUTO;
1787	m->dc_gp_len = l->dc_gpr_len;
1788
1789	p = (u_int8_t *)l;
1790	p += sizeof(struct dc_eblock_mii);
1791	m->dc_gp_ptr = p;
1792	p += 2 * l->dc_gpr_len;
1793	m->dc_reset_len = *p;
1794	p++;
1795	m->dc_reset_ptr = p;
1796
1797	m->dc_next = sc->dc_mi;
1798	sc->dc_mi = m;
1799
1800	return;
1801	}
1802	#endif
1803
1804	static void dc_read_srom(sc, bits)
1805	struct dc_softc *sc;
1806	int bits;
1807	{
1808	int size;
1809
1810	size = 2 << bits;
1811	sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT);
1812	dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1813	}
1814
1815	static void dc_parse_21143_srom(sc)
1816	struct dc_softc *sc;
1817	{
1818	struct dc_leaf_hdr *lhdr;
1819	struct dc_eblock_hdr *hdr;
1820	int i, loff;
1821	char *ptr;
1822
1823	loff = sc->dc_srom[27];
1824	lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1825
1826	ptr = (char *)lhdr;
1827	ptr += sizeof(struct dc_leaf_hdr) - 1;
1828	for (i = 0; i < lhdr->dc_mcnt; i++) {
1829	hdr = (struct dc_eblock_hdr *)ptr;
1830	switch(hdr->dc_type) {
1831	#if 0
1832	case DC_EBLOCK_MII:
1833	dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1834	break;
1835	case DC_EBLOCK_SIA:
1836	dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr);
1837	break;
1838	case DC_EBLOCK_SYM:
1839	dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr);
1840	break;
1841	#endif
1842	default:
1843	/* Don't care. Yet. */
1844	break;
1845	}
1846	ptr += (hdr->dc_len & 0x7F);
1847	ptr++;
1848	}
1849
1850	return;
1851	}
1852
1853
1854	static void
1855	nop(const rtems_irq_connect_data* unused)
1856	{
1857	}
1858
1859	static int
1860	decISON(const rtems_irq_connect_data* irq)
1861	{
1862	return (BSP_irq_enabled_at_i8259s(irq->name));
1863	}
1864
1865
1866	/*
1867	* Attach the interface. Allocate softc structures, do ifmedia
1868	* setup and ethernet/BPF attach.
1869	*/
1870	int
1871	rtems_dc_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching)
1872	{
1873	/int s, tmp = 0;/
1874	u_char eaddr[ETHER_ADDR_LEN];
1875
1876	char *unitName;
1877	int unitNumber;
1878
1879	u_int32_t command;
1880	struct dc_softc *sc;
1881	struct ifnet *ifp;
1882	u_int32_t revision;
1883	int error = 0, mac_offset;
1884	#if defined(__i386__)
1885	int sig;
1886	int value;
1887	#endif
1888
1889	/*
1890	* Get the instance number for the board we're going to configure
1891	* from the user.
1892	*/
1893	unitNumber = rtems_bsdnet_parse_driver_name(config, &unitName);
1894	if( unitNumber < 0) {
1895	return 0;
1896	}
1897	if( strcmp(unitName, DRIVER_PREFIX) ) {
1898	printk("dec2114x : unit name '%s' not %s\n", \
1899	unitName, DRIVER_PREFIX );
1900	return 0;
1901	}
1902
1903
1904	/*
1905	* First, find a DEC board
1906	*/
1907	if (pcib_init() == PCIB_ERR_NOTPRESENT) {
1908	rtems_panic("PCI BIOS not found !!");
1909	}
1910
1911	sc = &dc_softc_devs[unitNumber - 1];
1912	ifp = &sc->arpcom.ac_if;
1913
1914	if(ifp->if_softc != NULL) {
1915	printk("dec2114x[%d]: unit number already in use.\n", \
1916	unitNumber);
1917	return (0);
1918	}
1919	memset(sc, 0, sizeof(struct dc_softc));
1920
1921	/unit = device_get_unit(dev);/
1922	sc->dc_unit = unitNumber;
1923	sc->dc_name = unitName;
1924
1925	/*
1926	* Handle power management nonsense.
1927	*
1928	dc_acpi(dev);
1929	*/
1930
1931	/* Scan for dec2114x cards in pci config space */
1932	if( (sc->dc_info = dc_devtype(unitNumber)) == NULL) {
1933	printk("Can't find any dec2114x NICs in PCI space.\n");
1934	return 0;
1935	}
1936
1937
1938	/*
1939	* Map control/status registers.
1940	*/
1941	sig = sc->dc_info->dc_devsig;
1942	pcib_conf_read32(sig, PCI_COMMAND, &command);
1943	command \|= (PCI_COMMAND_IO \| PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
1944	pcib_conf_write32(sig, PCI_COMMAND, command);
1945	pcib_conf_read32(sig, PCI_COMMAND, &command);
1946
1947	#ifdef DC_USEIOSPACE
1948	if (!(command & PCI_COMMAND_IO)) {
1949	printk("dc%d: failed to enable I/O ports!\n", sc->dc_unit);
1950	error = ENXIO;
1951	goto fail;
1952	}
1953	#else
1954	if (!(command & PCI_COMMAND_MEMORY)) {
1955	printk("dc%d: failed to enable memory mapping!\n", sc->dc_unit);
1956	error = ENXIO;
1957	goto fail;
1958	}
1959	#endif
1960
1961	#if 0
1962	rid = DC_RID;
1963	sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid,
1964	0, ~0, 1, RF_ACTIVE);
1965
1966	if (sc->dc_res == NULL) {
1967	printk("dc%d: couldn't map ports/memory\n", unit);
1968	error = ENXIO;
1969	goto fail;
1970	}
1971	sc->dc_btag = rman_get_bustag(sc->dc_res);
1972	sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
1973	#endif
1974
1975	/* sc->membase is the address of the card's CSRs !!! */
1976	pcib_conf_read32(sig, DC_PCI_CFBMA, &value);
1977	sc->membase = value;
1978
1979	/* Allocate interrupt */
1980	memset(&sc->irqInfo, 0, sizeof(rtems_irq_connect_data));
1981	pcib_conf_read32(sig, DC_PCI_CFIT, &value);
1982	sc->irqInfo.name = value & 0xFF;
1983
1984	sc->irqInfo.hdl = (rtems_irq_hdl)dc_intr;
1985	sc->irqInfo.on = nop;
1986	sc->irqInfo.off = nop;
1987	sc->irqInfo.isOn = decISON;
1988
1989	if(!(BSP_install_rtems_irq_handler( &sc->irqInfo ))) {
1990	rtems_panic("Can't install dec2114x irq handler.\n");
1991	}
1992
1993
1994	#if 0
1995	rid = 0;
1996	sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1997	RF_SHAREABLE \| RF_ACTIVE);
1998
1999	if (sc->dc_irq == NULL) {
2000	printk("dc%d: couldn't map interrupt\n", unit);
2001	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2002	error = ENXIO;
2003	goto fail;
2004	}
2005
2006	error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET,
2007	dc_intr, sc, &sc->dc_intrhand);
2008
2009	if (error) {
2010	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2011	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2012	printk("dc%d: couldn't set up irq\n", unit);
2013	goto fail;
2014	}
2015	#endif
2016
2017
2018	/* Need this info to decide on a chip type.
2019	sc->dc_info = dc_devtype(dev);
2020	*/
2021	pcib_conf_read32(sig, DC_PCI_CFRV, &revision);
2022	revision &= 0x000000FF;
2023
2024	/* Get the eeprom width, but PNIC has diff eeprom */
2025	if (sc->dc_info->dc_did != DC_DEVICEID_82C168)
2026	dc_eeprom_width(sc);
2027
2028	switch(sc->dc_info->dc_did) {
2029	case DC_DEVICEID_21143:
2030	sc->dc_type = DC_TYPE_21143;
2031	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR;
2032	sc->dc_flags \|= DC_REDUCED_MII_POLL;
2033	/* Save EEPROM contents so we can parse them later. */
2034	dc_read_srom(sc, sc->dc_romwidth);
2035	break;
2036	case DC_DEVICEID_DM9009:
2037	case DC_DEVICEID_DM9100:
2038	case DC_DEVICEID_DM9102:
2039	sc->dc_type = DC_TYPE_DM9102;
2040	sc->dc_flags \|= DC_TX_COALESCE\|DC_TX_INTR_ALWAYS;
2041	sc->dc_flags \|= DC_REDUCED_MII_POLL\|DC_TX_STORENFWD;
2042	sc->dc_pmode = DC_PMODE_MII;
2043	/* Increase the latency timer value. */
2044	pcib_conf_read32(sig, DC_PCI_CFLT, &command);
2045	command &= 0xFFFF00FF;
2046	command \|= 0x00008000;
2047	pcib_conf_write32(sig, DC_PCI_CFLT, command);
2048	break;
2049	case DC_DEVICEID_AL981:
2050	sc->dc_type = DC_TYPE_AL981;
2051	sc->dc_flags \|= DC_TX_USE_TX_INTR;
2052	sc->dc_flags \|= DC_TX_ADMTEK_WAR;
2053	sc->dc_pmode = DC_PMODE_MII;
2054	dc_read_srom(sc, sc->dc_romwidth);
2055	break;
2056	case DC_DEVICEID_AN985:
2057	case DC_DEVICEID_EN2242:
2058	sc->dc_type = DC_TYPE_AN985;
2059	sc->dc_flags \|= DC_TX_USE_TX_INTR;
2060	sc->dc_flags \|= DC_TX_ADMTEK_WAR;
2061	sc->dc_pmode = DC_PMODE_MII;
2062	dc_read_srom(sc, sc->dc_romwidth);
2063	break;
2064	case DC_DEVICEID_98713:
2065	case DC_DEVICEID_98713_CP:
2066	if (revision < DC_REVISION_98713A) {
2067	sc->dc_type = DC_TYPE_98713;
2068	}
2069	if (revision >= DC_REVISION_98713A) {
2070	sc->dc_type = DC_TYPE_98713A;
2071	sc->dc_flags \|= DC_21143_NWAY;
2072	}
2073	sc->dc_flags \|= DC_REDUCED_MII_POLL;
2074	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR;
2075	break;
2076	case DC_DEVICEID_987x5:
2077	case DC_DEVICEID_EN1217:
2078	/*
2079	* Macronix MX98715AEC-C/D/E parts have only a
2080	* 128-bit hash table. We need to deal with these
2081	* in the same manner as the PNIC II so that we
2082	* get the right number of bits out of the
2083	* CRC routine.
2084	*/
2085	if (revision >= DC_REVISION_98715AEC_C &&
2086	revision < DC_REVISION_98725)
2087	sc->dc_flags \|= DC_128BIT_HASH;
2088	sc->dc_type = DC_TYPE_987x5;
2089	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR;
2090	sc->dc_flags \|= DC_REDUCED_MII_POLL\|DC_21143_NWAY;
2091	break;
2092	case DC_DEVICEID_98727:
2093	sc->dc_type = DC_TYPE_987x5;
2094	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR;
2095	sc->dc_flags \|= DC_REDUCED_MII_POLL\|DC_21143_NWAY;
2096	break;
2097	case DC_DEVICEID_82C115:
2098	sc->dc_type = DC_TYPE_PNICII;
2099	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR\|DC_128BIT_HASH;
2100	sc->dc_flags \|= DC_REDUCED_MII_POLL\|DC_21143_NWAY;
2101	break;
2102	case DC_DEVICEID_82C168:
2103	sc->dc_type = DC_TYPE_PNIC;
2104	sc->dc_flags \|= DC_TX_STORENFWD\|DC_TX_INTR_ALWAYS;
2105	sc->dc_flags \|= DC_PNIC_RX_BUG_WAR;
2106	sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT);
2107	if (revision < DC_REVISION_82C169)
2108	sc->dc_pmode = DC_PMODE_SYM;
2109	break;
2110	case DC_DEVICEID_AX88140A:
2111	sc->dc_type = DC_TYPE_ASIX;
2112	sc->dc_flags \|= DC_TX_USE_TX_INTR\|DC_TX_INTR_FIRSTFRAG;
2113	sc->dc_flags \|= DC_REDUCED_MII_POLL;
2114	sc->dc_pmode = DC_PMODE_MII;
2115	break;
2116	case DC_DEVICEID_RS7112:
2117	sc->dc_type = DC_TYPE_CONEXANT;
2118	sc->dc_flags \|= DC_TX_INTR_ALWAYS;
2119	sc->dc_flags \|= DC_REDUCED_MII_POLL;
2120	sc->dc_pmode = DC_PMODE_MII;
2121	dc_read_srom(sc, sc->dc_romwidth);
2122	break;
2123	default:
2124	printk("dc%d: unknown device: %x\n", sc->dc_unit,
2125	sc->dc_info->dc_did);
2126	break;
2127	}
2128
2129	/* Save the cache line size. */
2130	if (DC_IS_DAVICOM(sc)) {
2131	sc->dc_cachesize = 0;
2132	}
2133	else {
2134	pcib_conf_read32(sig, DC_PCI_CFLT, &value);
2135	sc->dc_cachesize = (u_int8_t)(value & 0xFF);
2136	}
2137
2138	/* Reset the adapter. */
2139	dc_reset(sc);
2140
2141	/* Take 21143 out of snooze mode */
2142	if (DC_IS_INTEL(sc)) {
2143	pcib_conf_read32(sig, DC_PCI_CFDD, &command);
2144	command &= ~(DC_CFDD_SNOOZE_MODE\|DC_CFDD_SLEEP_MODE);
2145	pcib_conf_write32(sig, DC_PCI_CFDD, command);
2146	}
2147
2148
2149	/*
2150	* Try to learn something about the supported media.
2151	* We know that ASIX and ADMtek and Davicom devices
2152	* will always be using MII media, so that's a no-brainer.
2153	* The tricky ones are the Macronix/PNIC II and the
2154	* Intel 21143.
2155	*/
2156	if (DC_IS_INTEL(sc))
2157	dc_parse_21143_srom(sc);
2158	else if (DC_IS_MACRONIX(sc) \|\| DC_IS_PNICII(sc)) {
2159	if (sc->dc_type == DC_TYPE_98713)
2160	sc->dc_pmode = DC_PMODE_MII;
2161	else
2162	sc->dc_pmode = DC_PMODE_SYM;
2163	} else if (!sc->dc_pmode)
2164	sc->dc_pmode = DC_PMODE_MII;
2165
2166	/*
2167	* Get station address from the EEPROM.
2168	*/
2169	switch(sc->dc_type) {
2170	case DC_TYPE_98713:
2171	case DC_TYPE_98713A:
2172	case DC_TYPE_987x5:
2173	case DC_TYPE_PNICII:
2174	dc_read_eeprom(sc, (caddr_t)&mac_offset,
2175	(DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2176	dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2177	break;
2178	case DC_TYPE_PNIC:
2179	dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2180	break;
2181	case DC_TYPE_DM9102:
2182	case DC_TYPE_21143:
2183	case DC_TYPE_ASIX:
2184	dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2185	break;
2186	case DC_TYPE_AL981:
2187	case DC_TYPE_AN985:
2188	bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr,
2189	ETHER_ADDR_LEN);
2190	dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0);
2191	break;
2192	case DC_TYPE_CONEXANT:
2193	bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6);
2194	break;
2195	default:
2196	dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2197	break;
2198	}
2199
2200	/*
2201	* A 21143 or clone chip was detected. Inform the world.
2202	*/
2203	bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
2204	printk("dc%d: MAC address -- %02x:%02x:%02x:%02x:%02x:%02x\n", \
2205	sc->dc_unit,sc->arpcom.ac_enaddr[0], \
2206	sc->arpcom.ac_enaddr[1], sc->arpcom.ac_enaddr[2], \
2207	sc->arpcom.ac_enaddr[3], sc->arpcom.ac_enaddr[4], \
2208	sc->arpcom.ac_enaddr[5]);
2209
2210
2211	sc->dc_ldata = malloc(sizeof(struct dc_list_data), M_DEVBUF, M_NOWAIT);
2212
2213	if (sc->dc_ldata == NULL) {
2214	printk("dc%d: no memory for list buffers!\n", sc->dc_unit);
2215	if (sc->dc_pnic_rx_buf != NULL)
2216	free(sc->dc_pnic_rx_buf, M_DEVBUF);
2217	#if 0
2218	bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2219	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2220	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2221	#endif
2222	error = ENXIO;
2223	goto fail;
2224	}
2225
2226	bzero(sc->dc_ldata, sizeof(struct dc_list_data));
2227
2228	ifp = &sc->arpcom.ac_if;
2229	ifp->if_softc = sc;
2230	ifp->if_unit = unitNumber; /sc->dc_unit;/
2231	ifp->if_name = unitName; /sc->dc_name;/
2232	ifp->if_mtu = ETHERMTU;
2233	ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX;/* \| IFF_MULTICAST;*/
2234	ifp->if_ioctl = dc_ioctl;
2235	ifp->if_output = ether_output;
2236	ifp->if_start = dc_start;
2237	ifp->if_watchdog = dc_watchdog;
2238	ifp->if_init = dc_init;
2239	ifp->if_baudrate = 100000000;
2240	ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1;
2241
2242	#if 0
2243	/*
2244	* Do MII setup. If this is a 21143, check for a PHY on the
2245	* MII bus after applying any necessary fixups to twiddle the
2246	* GPIO bits. If we don't end up finding a PHY, restore the
2247	* old selection (SIA only or SIA/SYM) and attach the dcphy
2248	* driver instead.
2249	*/
2250	if (DC_IS_INTEL(sc)) {
2251	dc_apply_fixup(sc, IFM_AUTO);
2252	tmp = sc->dc_pmode;
2253	sc->dc_pmode = DC_PMODE_MII;
2254	}
2255
2256	error = mii_phy_probe(dev, &sc->dc_miibus,
2257	dc_ifmedia_upd, dc_ifmedia_sts);
2258
2259	if (error && DC_IS_INTEL(sc)) {
2260	sc->dc_pmode = tmp;
2261	if (sc->dc_pmode != DC_PMODE_SIA)
2262	sc->dc_pmode = DC_PMODE_SYM;
2263	sc->dc_flags \|= DC_21143_NWAY;
2264	mii_phy_probe(dev, &sc->dc_miibus,
2265	dc_ifmedia_upd, dc_ifmedia_sts);
2266	/*
2267	* For non-MII cards, we need to have the 21143
2268	* drive the LEDs. Except there are some systems
2269	* like the NEC VersaPro NoteBook PC which have no
2270	* LEDs, and twiddling these bits has adverse effects
2271	* on them. (I.e. you suddenly can't get a link.)
2272	*/
2273	if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033)
2274	sc->dc_flags \|= DC_TULIP_LEDS;
2275	error = 0;
2276	}
2277
2278	if (error) {
2279	printk("dc%d: MII without any PHY!\n", sc->dc_unit);
2280	contigfree(sc->dc_ldata, sizeof(struct dc_list_data),
2281	M_DEVBUF);
2282	if (sc->dc_pnic_rx_buf != NULL)
2283	free(sc->dc_pnic_rx_buf, M_DEVBUF);
2284	bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2285	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2286	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2287	error = ENXIO;
2288	goto fail;
2289	}
2290	#endif
2291
2292	/*
2293	* Call MI attach routine.
2294	*/
2295	if_attach(ifp);
2296	ether_ifattach(ifp);
2297	/callout_handle_init(&sc->dc_stat_ch);/
2298
2299	if (DC_IS_ADMTEK(sc)) {
2300	/*
2301	* Set automatic TX underrun recovery for the ADMtek chips
2302	*/
2303	DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2304	}
2305
2306	if(sc->daemontid == 0) {
2307	sc->daemontid = rtems_bsdnet_newproc("decD",4096, \
2308	dc_daemon,(void *)sc);
2309	printk("dec[%d]: daemon process started\n", sc->dc_unit);
2310	}
2311
2312	/*
2313	* Tell the upper layer(s) we support long frames.
2314	*
2315	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2316	*/
2317
2318	#ifdef SRM_MEDIA
2319	sc->dc_srm_media = 0;
2320
2321	/* Remember the SRM console media setting */
2322	if (DC_IS_INTEL(sc)) {
2323	command = pci_read_config(dev, DC_PCI_CFDD, 4);
2324	command &= ~(DC_CFDD_SNOOZE_MODE\|DC_CFDD_SLEEP_MODE);
2325	switch ((command >> 8) & 0xff) {
2326	case 3:
2327	sc->dc_srm_media = IFM_10_T;
2328	break;
2329	case 4:
2330	sc->dc_srm_media = IFM_10_T \| IFM_FDX;
2331	break;
2332	case 5:
2333	sc->dc_srm_media = IFM_100_TX;
2334	break;
2335	case 6:
2336	sc->dc_srm_media = IFM_100_TX \| IFM_FDX;
2337	break;
2338	}
2339	if (sc->dc_srm_media)
2340	sc->dc_srm_media \|= IFM_ACTIVE \| IFM_ETHER;
2341	}
2342	#endif
2343
2344
2345	fail:
2346
2347	return (1); /(error);/
2348	}
2349
2350	#if 0
2351	static int dc_detach(dev)
2352	device_t dev;
2353	{
2354	struct dc_softc *sc;
2355	struct ifnet *ifp;
2356	int s;
2357	struct dc_mediainfo *m;
2358
2359
2360	sc = device_get_softc(dev);
2361	ifp = &sc->arpcom.ac_if;
2362
2363	dc_stop(sc);
2364	ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
2365
2366	bus_generic_detach(dev);
2367	device_delete_child(dev, sc->dc_miibus);
2368
2369	bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2370	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2371	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2372
2373	contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF);
2374	if (sc->dc_pnic_rx_buf != NULL)
2375	free(sc->dc_pnic_rx_buf, M_DEVBUF);
2376
2377	while(sc->dc_mi != NULL) {
2378	m = sc->dc_mi->dc_next;
2379	free(sc->dc_mi, M_DEVBUF);
2380	sc->dc_mi = m;
2381	}
2382	free(sc->dc_srom, M_DEVBUF);
2383
2384
2385	return(0);
2386	}
2387	#endif
2388
2389
2390	/*
2391	* Initialize the transmit descriptors.
2392	*/
2393	static int dc_list_tx_init(sc)
2394	struct dc_softc *sc;
2395	{
2396	struct dc_chain_data *cd;
2397	struct dc_list_data *ld;
2398	int i;
2399
2400	cd = &sc->dc_cdata;
2401	ld = sc->dc_ldata;
2402	for (i = 0; i < DC_TX_LIST_CNT; i++) {
2403	if (i == (DC_TX_LIST_CNT - 1)) {
2404	ld->dc_tx_list[i].dc_next =
2405	vtophys(&ld->dc_tx_list[0]);
2406	} else {
2407	ld->dc_tx_list[i].dc_next =
2408	vtophys(&ld->dc_tx_list[i + 1]);
2409	}
2410	cd->dc_tx_chain[i] = NULL;
2411	ld->dc_tx_list[i].dc_data = 0;
2412	ld->dc_tx_list[i].dc_ctl = 0;
2413	}
2414
2415	cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2416
2417	return(0);
2418	}
2419
2420
2421	/*
2422	* Initialize the RX descriptors and allocate mbufs for them. Note that
2423	* we arrange the descriptors in a closed ring, so that the last descriptor
2424	* points back to the first.
2425	*/
2426	static int dc_list_rx_init(sc)
2427	struct dc_softc *sc;
2428	{
2429	struct dc_chain_data *cd;
2430	struct dc_list_data *ld;
2431	int i;
2432
2433	cd = &sc->dc_cdata;
2434	ld = sc->dc_ldata;
2435
2436	for (i = 0; i < DC_RX_LIST_CNT; i++) {
2437	if (dc_newbuf(sc, i, NULL) == ENOBUFS)
2438	return(ENOBUFS);
2439	if (i == (DC_RX_LIST_CNT - 1)) {
2440	ld->dc_rx_list[i].dc_next =
2441	vtophys(&ld->dc_rx_list[0]);
2442	} else {
2443	ld->dc_rx_list[i].dc_next =
2444	vtophys(&ld->dc_rx_list[i + 1]);
2445	}
2446	}
2447
2448	cd->dc_rx_prod = 0;
2449
2450	return(0);
2451	}
2452
2453	/*
2454	* Initialize an RX descriptor and attach an MBUF cluster.
2455	*/
2456	static int dc_newbuf(sc, i, m)
2457	struct dc_softc *sc;
2458	int i;
2459	struct mbuf *m;
2460	{
2461	struct mbuf *m_new = NULL;
2462	struct dc_desc *c;
2463
2464	c = &sc->dc_ldata->dc_rx_list[i];
2465
2466	if (m == NULL) {
2467	MGETHDR(m_new, M_DONTWAIT, MT_DATA);
2468	if (m_new == NULL)
2469	return(ENOBUFS);
2470
2471	MCLGET(m_new, M_DONTWAIT);
2472	if (!(m_new->m_flags & M_EXT)) {
2473	m_freem(m_new);
2474	return(ENOBUFS);
2475	}
2476	m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2477	} else {
2478	m_new = m;
2479	m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2480	m_new->m_data = m_new->m_ext.ext_buf;
2481	}
2482
2483	m_adj(m_new, sizeof(u_int64_t));
2484
2485	/*
2486	* If this is a PNIC chip, zero the buffer. This is part
2487	* of the workaround for the receive bug in the 82c168 and
2488	* 82c169 chips.
2489	*/
2490	if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2491	bzero((char )mtod(m_new, char ), m_new->m_len);
2492
2493	sc->dc_cdata.dc_rx_chain[i] = m_new;
2494	c->dc_data = vtophys(mtod(m_new, caddr_t));
2495	c->dc_ctl = DC_RXCTL_RLINK \| DC_RXLEN;
2496	c->dc_status = DC_RXSTAT_OWN;
2497
2498	return(0);
2499	}
2500
2501	/*
2502	* Grrrrr.
2503	* The PNIC chip has a terrible bug in it that manifests itself during
2504	* periods of heavy activity. The exact mode of failure if difficult to
2505	* pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2506	* will happen on slow machines. The bug is that sometimes instead of
2507	* uploading one complete frame during reception, it uploads what looks
2508	* like the entire contents of its FIFO memory. The frame we want is at
2509	* the end of the whole mess, but we never know exactly how much data has
2510	* been uploaded, so salvaging the frame is hard.
2511	*
2512	* There is only one way to do it reliably, and it's disgusting.
2513	* Here's what we know:
2514	*
2515	* - We know there will always be somewhere between one and three extra
2516	* descriptors uploaded.
2517	*
2518	* - We know the desired received frame will always be at the end of the
2519	* total data upload.
2520	*
2521	* - We know the size of the desired received frame because it will be
2522	* provided in the length field of the status word in the last descriptor.
2523	*
2524	* Here's what we do:
2525	*
2526	* - When we allocate buffers for the receive ring, we bzero() them.
2527	* This means that we know that the buffer contents should be all
2528	* zeros, except for data uploaded by the chip.
2529	*
2530	* - We also force the PNIC chip to upload frames that include the
2531	* ethernet CRC at the end.
2532	*
2533	* - We gather all of the bogus frame data into a single buffer.
2534	*
2535	* - We then position a pointer at the end of this buffer and scan
2536	* backwards until we encounter the first non-zero byte of data.
2537	* This is the end of the received frame. We know we will encounter
2538	* some data at the end of the frame because the CRC will always be
2539	* there, so even if the sender transmits a packet of all zeros,
2540	* we won't be fooled.
2541	*
2542	* - We know the size of the actual received frame, so we subtract
2543	* that value from the current pointer location. This brings us
2544	* to the start of the actual received packet.
2545	*
2546	* - We copy this into an mbuf and pass it on, along with the actual
2547	* frame length.
2548	*
2549	* The performance hit is tremendous, but it beats dropping frames all
2550	* the time.
2551	*/
2552
2553	#define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG\|DC_RXSTAT_LASTFRAG)
2554	static void dc_pnic_rx_bug_war(sc, idx)
2555	struct dc_softc *sc;
2556	int idx;
2557	{
2558	struct dc_desc *cur_rx;
2559	struct dc_desc *c = NULL;
2560	struct mbuf *m = NULL;
2561	unsigned char *ptr;
2562	int i, total_len;
2563	u_int32_t rxstat = 0;
2564
2565	i = sc->dc_pnic_rx_bug_save;
2566	cur_rx = &sc->dc_ldata->dc_rx_list[idx];
2567	ptr = sc->dc_pnic_rx_buf;
2568	bzero(ptr, sizeof(DC_RXLEN * 5));
2569
2570	/* Copy all the bytes from the bogus buffers. */
2571	while (1) {
2572	c = &sc->dc_ldata->dc_rx_list[i];
2573	rxstat = c->dc_status;
2574	m = sc->dc_cdata.dc_rx_chain[i];
2575	bcopy(mtod(m, char *), ptr, DC_RXLEN);
2576	ptr += DC_RXLEN;
2577	/* If this is the last buffer, break out. */
2578	if (i == idx \|\| rxstat & DC_RXSTAT_LASTFRAG)
2579	break;
2580	dc_newbuf(sc, i, m);
2581	DC_INC(i, DC_RX_LIST_CNT);
2582	}
2583
2584	/* Find the length of the actual receive frame. */
2585	total_len = DC_RXBYTES(rxstat);
2586
2587	/* Scan backwards until we hit a non-zero byte. */
2588	while(*ptr == 0x00)
2589	ptr--;
2590	#if 0
2591	/* Round off. */
2592	if ((uintptr_t)(ptr) & 0x3)
2593	ptr -= 1;
2594	#endif
2595
2596	/* Now find the start of the frame. */
2597	ptr -= total_len;
2598	if (ptr < sc->dc_pnic_rx_buf)
2599	ptr = sc->dc_pnic_rx_buf;
2600
2601	/*
2602	* Now copy the salvaged frame to the last mbuf and fake up
2603	* the status word to make it look like a successful
2604	* frame reception.
2605	*/
2606	dc_newbuf(sc, i, m);
2607	bcopy(ptr, mtod(m, char *), total_len);
2608	cur_rx->dc_status = rxstat \| DC_RXSTAT_FIRSTFRAG;
2609
2610	return;
2611	}
2612
2613	/*
2614	* This routine searches the RX ring for dirty descriptors in the
2615	* event that the rxeof routine falls out of sync with the chip's
2616	* current descriptor pointer. This may happen sometimes as a result
2617	* of a "no RX buffer available" condition that happens when the chip
2618	* consumes all of the RX buffers before the driver has a chance to
2619	* process the RX ring. This routine may need to be called more than
2620	* once to bring the driver back in sync with the chip, however we
2621	* should still be getting RX DONE interrupts to drive the search
2622	* for new packets in the RX ring, so we should catch up eventually.
2623	*/
2624	static int dc_rx_resync(sc)
2625	struct dc_softc *sc;
2626	{
2627	int i, pos;
2628	struct dc_desc *cur_rx;
2629
2630	pos = sc->dc_cdata.dc_rx_prod;
2631
2632	for (i = 0; i < DC_RX_LIST_CNT; i++) {
2633	cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2634	if (!(cur_rx->dc_status & DC_RXSTAT_OWN))
2635	break;
2636	DC_INC(pos, DC_RX_LIST_CNT);
2637	}
2638
2639	/* If the ring really is empty, then just return. */
2640	if (i == DC_RX_LIST_CNT)
2641	return(0);
2642
2643	/* We've fallen behing the chip: catch it. */
2644	sc->dc_cdata.dc_rx_prod = pos;
2645
2646	return(EAGAIN);
2647	}
2648
2649	/*
2650	* A frame has been uploaded: pass the resulting mbuf chain up to
2651	* the higher level protocols.
2652	*/
2653	static void dc_rxeof(sc)
2654	struct dc_softc *sc;
2655	{
2656	struct ether_header *eh;
2657	struct mbuf *m;
2658	struct ifnet *ifp;
2659	struct dc_desc *cur_rx;
2660	int i, total_len = 0;
2661	u_int32_t rxstat;
2662
2663	ifp = &sc->arpcom.ac_if;
2664	i = sc->dc_cdata.dc_rx_prod;
2665
2666	while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) {
2667
2668	#ifdef DEVICE_POLLING
2669	if (ifp->if_ipending & IFF_POLLING) {
2670	if (sc->rxcycles <= 0)
2671	break;
2672	sc->rxcycles--;
2673	}
2674	#endif /* DEVICE_POLLING */
2675	cur_rx = &sc->dc_ldata->dc_rx_list[i];
2676	rxstat = cur_rx->dc_status;
2677	m = sc->dc_cdata.dc_rx_chain[i];
2678	total_len = DC_RXBYTES(rxstat);
2679
2680	if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2681	if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2682	if (rxstat & DC_RXSTAT_FIRSTFRAG)
2683	sc->dc_pnic_rx_bug_save = i;
2684	if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
2685	DC_INC(i, DC_RX_LIST_CNT);
2686	continue;
2687	}
2688	dc_pnic_rx_bug_war(sc, i);
2689	rxstat = cur_rx->dc_status;
2690	total_len = DC_RXBYTES(rxstat);
2691	}
2692	}
2693
2694	sc->dc_cdata.dc_rx_chain[i] = NULL;
2695
2696	/*
2697	* If an error occurs, update stats, clear the
2698	* status word and leave the mbuf cluster in place:
2699	* it should simply get re-used next time this descriptor
2700	* comes up in the ring. However, don't report long
2701	* frames as errors since they could be vlans
2702	*/
2703	if ((rxstat & DC_RXSTAT_RXERR)){
2704	if (!(rxstat & DC_RXSTAT_GIANT) \|\|
2705	(rxstat & (DC_RXSTAT_CRCERR \| DC_RXSTAT_DRIBBLE \|
2706	DC_RXSTAT_MIIERE \| DC_RXSTAT_COLLSEEN \|
2707	DC_RXSTAT_RUNT \| DC_RXSTAT_DE))) {
2708	ifp->if_ierrors++;
2709	if (rxstat & DC_RXSTAT_COLLSEEN)
2710	ifp->if_collisions++;
2711	dc_newbuf(sc, i, m);
2712	if (rxstat & DC_RXSTAT_CRCERR) {
2713	DC_INC(i, DC_RX_LIST_CNT);
2714	continue;
2715	} else {
2716	dc_init(sc);
2717	return;
2718	}
2719	}
2720	}
2721
2722	/* No errors; receive the packet. */
2723	total_len -= ETHER_CRC_LEN;
2724
2725	#ifdef __i386__
2726	/*
2727	* On the x86 we do not have alignment problems, so try to
2728	* allocate a new buffer for the receive ring, and pass up
2729	* the one where the packet is already, saving the expensive
2730	* copy done in m_devget().
2731	* If we are on an architecture with alignment problems, or
2732	* if the allocation fails, then use m_devget and leave the
2733	* existing buffer in the receive ring.
2734	*/
2735	if (dc_quick && dc_newbuf(sc, i, NULL) == 0) {
2736	m->m_pkthdr.rcvif = ifp;
2737	m->m_pkthdr.len = m->m_len = total_len;
2738	DC_INC(i, DC_RX_LIST_CNT);
2739	} else
2740	#endif
2741	{
2742	struct mbuf *m0;
2743
2744	m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
2745	total_len + ETHER_ALIGN, 0, ifp, NULL);
2746	dc_newbuf(sc, i, m);
2747	DC_INC(i, DC_RX_LIST_CNT);
2748	if (m0 == NULL) {
2749	ifp->if_ierrors++;
2750	continue;
2751	}
2752	m_adj(m0, ETHER_ALIGN);
2753	m = m0;
2754	}
2755
2756	ifp->if_ipackets++;
2757	eh = mtod(m, struct ether_header *);
2758
2759	/* Remove header from mbuf and pass it on. */
2760	m_adj(m, sizeof(struct ether_header));
2761	ether_input(ifp, eh, m);
2762	}
2763
2764	sc->dc_cdata.dc_rx_prod = i;
2765	}
2766
2767	/*
2768	* A frame was downloaded to the chip. It's safe for us to clean up
2769	* the list buffers.
2770	*/
2771
2772	static void
2773	dc_txeof(sc)
2774	struct dc_softc *sc;
2775	{
2776	struct dc_desc *cur_tx = NULL;
2777	struct ifnet *ifp;
2778	int idx;
2779
2780	ifp = &sc->arpcom.ac_if;
2781
2782	/*
2783	* Go through our tx list and free mbufs for those
2784	* frames that have been transmitted.
2785	*/
2786	idx = sc->dc_cdata.dc_tx_cons;
2787	while(idx != sc->dc_cdata.dc_tx_prod) {
2788	u_int32_t txstat;
2789
2790	cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2791	txstat = cur_tx->dc_status;
2792
2793	if (txstat & DC_TXSTAT_OWN)
2794	break;
2795
2796	if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) \|\|
2797	cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2798	if (cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2799	/*
2800	* Yes, the PNIC is so brain damaged
2801	* that it will sometimes generate a TX
2802	* underrun error while DMAing the RX
2803	* filter setup frame. If we detect this,
2804	* we have to send the setup frame again,
2805	* or else the filter won't be programmed
2806	* correctly.
2807	*/
2808	if (DC_IS_PNIC(sc)) {
2809	if (txstat & DC_TXSTAT_ERRSUM)
2810	dc_setfilt(sc);
2811	}
2812	sc->dc_cdata.dc_tx_chain[idx] = NULL;
2813	}
2814	sc->dc_cdata.dc_tx_cnt--;
2815	DC_INC(idx, DC_TX_LIST_CNT);
2816	continue;
2817	}
2818
2819	if (DC_IS_CONEXANT(sc)) {
2820	/*
2821	* For some reason Conexant chips like
2822	* setting the CARRLOST flag even when
2823	* the carrier is there. In CURRENT we
2824	* have the same problem for Xircom
2825	* cards !
2826	*/
2827	if (/sc->dc_type == DC_TYPE_21143 &&/
2828	sc->dc_pmode == DC_PMODE_MII &&
2829	((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM\|
2830	DC_TXSTAT_NOCARRIER)))
2831	txstat &= ~DC_TXSTAT_ERRSUM;
2832	} else {
2833	if (/sc->dc_type == DC_TYPE_21143 &&/
2834	sc->dc_pmode == DC_PMODE_MII &&
2835	((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM\|
2836	DC_TXSTAT_NOCARRIER\|DC_TXSTAT_CARRLOST)))
2837	txstat &= ~DC_TXSTAT_ERRSUM;
2838	}
2839
2840	if (txstat & DC_TXSTAT_ERRSUM) {
2841	ifp->if_oerrors++;
2842	if (txstat & DC_TXSTAT_EXCESSCOLL)
2843	ifp->if_collisions++;
2844	if (txstat & DC_TXSTAT_LATECOLL)
2845	ifp->if_collisions++;
2846	if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2847	dc_init(sc);
2848	return;
2849	}
2850	}
2851
2852	ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2853
2854	ifp->if_opackets++;
2855	if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
2856	m_freem(sc->dc_cdata.dc_tx_chain[idx]);
2857	sc->dc_cdata.dc_tx_chain[idx] = NULL;
2858	}
2859
2860	sc->dc_cdata.dc_tx_cnt--;
2861	DC_INC(idx, DC_TX_LIST_CNT);
2862	}
2863
2864	if (idx != sc->dc_cdata.dc_tx_cons) {
2865	/* some buffers have been freed */
2866	sc->dc_cdata.dc_tx_cons = idx;
2867	ifp->if_flags &= ~IFF_OACTIVE;
2868	}
2869	ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5;
2870
2871	return;
2872	}
2873
2874
2875	#if 0
2876	static void dc_tick(xsc)
2877	void *xsc;
2878	{
2879	struct dc_softc *sc;
2880	/struct mii_data mii;*/
2881	struct ifnet *ifp;
2882	int s;
2883	u_int32_t r;
2884
2885
2886	sc = xsc;
2887	ifp = &sc->arpcom.ac_if;
2888	mii = device_get_softc(sc->dc_miibus);
2889
2890	if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2891	if (sc->dc_flags & DC_21143_NWAY) {
2892	r = CSR_READ_4(sc, DC_10BTSTAT);
2893	if (IFM_SUBTYPE(mii->mii_media_active) ==
2894	IFM_100_TX && (r & DC_TSTAT_LS100)) {
2895	sc->dc_link = 0;
2896	mii_mediachg(mii);
2897	}
2898	if (IFM_SUBTYPE(mii->mii_media_active) ==
2899	IFM_10_T && (r & DC_TSTAT_LS10)) {
2900	sc->dc_link = 0;
2901	mii_mediachg(mii);
2902	}
2903	if (sc->dc_link == 0)
2904	mii_tick(mii);
2905	} else {
2906	r = CSR_READ_4(sc, DC_ISR);
2907	if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT &&
2908	sc->dc_cdata.dc_tx_cnt == 0)
2909	mii_tick(mii);
2910	if (!(mii->mii_media_status & IFM_ACTIVE))
2911	sc->dc_link = 0;
2912	}
2913	} else
2914	mii_tick(mii);
2915
2916	/*
2917	* When the init routine completes, we expect to be able to send
2918	* packets right away, and in fact the network code will send a
2919	* gratuitous ARP the moment the init routine marks the interface
2920	* as running. However, even though the MAC may have been initialized,
2921	* there may be a delay of a few seconds before the PHY completes
2922	* autonegotiation and the link is brought up. Any transmissions
2923	* made during that delay will be lost. Dealing with this is tricky:
2924	* we can't just pause in the init routine while waiting for the
2925	* PHY to come ready since that would bring the whole system to
2926	* a screeching halt for several seconds.
2927	*
2928	* What we do here is prevent the TX start routine from sending
2929	* any packets until a link has been established. After the
2930	* interface has been initialized, the tick routine will poll
2931	* the state of the PHY until the IFM_ACTIVE flag is set. Until
2932	* that time, packets will stay in the send queue, and once the
2933	* link comes up, they will be flushed out to the wire.
2934	*/
2935	if (!sc->dc_link) {
2936	mii_pollstat(mii);
2937	if (mii->mii_media_status & IFM_ACTIVE &&
2938	IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2939	sc->dc_link++;
2940	if (ifp->if_snd.ifq_head != NULL)
2941	dc_start(ifp);
2942	}
2943	}
2944
2945	if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2946	sc->dc_stat_ch = timeout(dc_tick, sc, hz/10);
2947	else
2948	sc->dc_stat_ch = timeout(dc_tick, sc, hz);
2949
2950	return;
2951	}
2952	#endif
2953
2954	/*
2955	* A transmit underrun has occurred. Back off the transmit threshold,
2956	* or switch to store and forward mode if we have to.
2957	*/
2958	static void dc_tx_underrun(sc)
2959	struct dc_softc *sc;
2960	{
2961	u_int32_t isr;
2962	int i;
2963
2964	if (DC_IS_DAVICOM(sc))
2965	dc_init(sc);
2966
2967	if (DC_IS_INTEL(sc)) {
2968	/*
2969	* The real 21143 requires that the transmitter be idle
2970	* in order to change the transmit threshold or store
2971	* and forward state.
2972	*/
2973	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2974
2975	for (i = 0; i < DC_TIMEOUT; i++) {
2976	isr = CSR_READ_4(sc, DC_ISR);
2977	if (isr & DC_ISR_TX_IDLE)
2978	break;
2979	DELAY(10);
2980	}
2981	if (i == DC_TIMEOUT) {
2982	printk("dc%d: failed to force tx to idle state\n",
2983	sc->dc_unit);
2984	dc_init(sc);
2985	}
2986	}
2987
2988	printk("dc%d: TX underrun -- ", sc->dc_unit);
2989	sc->dc_txthresh += DC_TXTHRESH_INC;
2990	if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
2991	printk("using store and forward mode\n");
2992	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
2993	} else {
2994	printk("increasing TX threshold\n");
2995	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
2996	DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
2997	}
2998
2999	if (DC_IS_INTEL(sc))
3000	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3001
3002	return;
3003	}
3004
3005	#ifdef DEVICE_POLLING
3006	static poll_handler_t dc_poll;
3007
3008	static void
3009	dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3010	{
3011	struct dc_softc *sc = ifp->if_softc;
3012
3013	if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
3014	/* Re-enable interrupts. */
3015	CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3016	return;
3017	}
3018	sc->rxcycles = count;
3019	dc_rxeof(sc);
3020	dc_txeof(sc);
3021	if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE))
3022	dc_start(ifp);
3023
3024	if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
3025	u_int32_t status;
3026
3027	status = CSR_READ_4(sc, DC_ISR);
3028	status &= (DC_ISR_RX_WATDOGTIMEO\|DC_ISR_RX_NOBUF\|
3029	DC_ISR_TX_NOBUF\|DC_ISR_TX_IDLE\|DC_ISR_TX_UNDERRUN\|
3030	DC_ISR_BUS_ERR);
3031	if (!status)
3032	return ;
3033	/* ack what we have */
3034	CSR_WRITE_4(sc, DC_ISR, status);
3035
3036	if (status & (DC_ISR_RX_WATDOGTIMEO\|DC_ISR_RX_NOBUF) ) {
3037	u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3038	ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
3039
3040	if (dc_rx_resync(sc))
3041	dc_rxeof(sc);
3042	}
3043	/* restart transmit unit if necessary */
3044	if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
3045	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3046
3047	if (status & DC_ISR_TX_UNDERRUN)
3048	dc_tx_underrun(sc);
3049
3050	if (status & DC_ISR_BUS_ERR) {
3051	printk("dc_poll: dc%d bus error\n", sc->dc_unit);
3052	dc_reset(sc);
3053	dc_init(sc);
3054	}
3055	}
3056	}
3057	#endif /* DEVICE_POLLING */
3058
3059	static void
3060	dc_intr(rtems_vector_number v)
3061	{
3062	/* Need to make this work for multiple devices ... eventually */
3063	struct dc_softc *sc = &dc_softc_devs[0];
3064
3065
3066	/* Disable interrupts. */
3067	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3068
3069	rtems_event_send(sc->daemontid, IRQ_EVENT);
3070	#if 0
3071	if (sc->suspended) {
3072	return;
3073	}
3074
3075	ifp = &sc->arpcom.ac_if;
3076
3077	#ifdef DEVICE_POLLING
3078	if (ifp->if_ipending & IFF_POLLING)
3079	return;
3080	if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */
3081	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3082	return;
3083	}
3084	#endif /* DEVICE_POLLING */
3085	if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
3086	return ;
3087
3088	/* Suppress unwanted interrupts */
3089	if (!(ifp->if_flags & IFF_UP)) {
3090	if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
3091	dc_stop(sc);
3092	return;
3093	}
3094	#endif
3095	}
3096
3097
3098	static void
3099	dc_daemon(void * arg)
3100	{
3101	struct dc_softc sc = (struct dc_softc )arg;
3102	struct ifnet *ifp;
3103	u_int32_t status;
3104	rtems_event_set events;
3105
3106
3107	for(;;) {
3108	rtems_bsdnet_event_receive(RTEMS_ALL_EVENTS, \
3109	RTEMS_WAIT \| RTEMS_EVENT_ANY, \
3110	RTEMS_NO_TIMEOUT,
3111	&events);
3112
3113
3114	ifp = &sc->arpcom.ac_if;
3115
3116	while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) {
3117
3118	CSR_WRITE_4(sc, DC_ISR, status);
3119
3120	if (status & DC_ISR_RX_OK) {
3121	int curpkts;
3122	curpkts = ifp->if_ipackets;
3123	dc_rxeof(sc);
3124	if (curpkts == ifp->if_ipackets) {
3125	while(dc_rx_resync(sc))
3126	dc_rxeof(sc);
3127	}
3128	}
3129
3130	if (status & (DC_ISR_TX_OK\|DC_ISR_TX_NOBUF))
3131	dc_txeof(sc);
3132
3133	if (status & DC_ISR_TX_IDLE) {
3134	dc_txeof(sc);
3135	if (sc->dc_cdata.dc_tx_cnt) {
3136	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3137	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3138	}
3139	}
3140
3141	if (status & DC_ISR_TX_UNDERRUN)
3142	dc_tx_underrun(sc);
3143
3144	if ((status & DC_ISR_RX_WATDOGTIMEO)
3145	\|\| (status & DC_ISR_RX_NOBUF)) {
3146	int curpkts;
3147	curpkts = ifp->if_ipackets;
3148	dc_rxeof(sc);
3149	if (curpkts == ifp->if_ipackets) {
3150	while(dc_rx_resync(sc))
3151	dc_rxeof(sc);
3152	}
3153	}
3154
3155	if (status & DC_ISR_BUS_ERR) {
3156	dc_reset(sc);
3157	dc_init(sc);
3158	}
3159	}
3160
3161	/* Make atomic !!! */
3162	/* Re-enable interrupts. */
3163	CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3164
3165	if (ifp->if_snd.ifq_head != NULL)
3166	dc_start(ifp);
3167	}
3168
3169	}
3170
3171
3172	/*
3173	* Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
3174	* pointers to the fragment pointers.
3175	*/
3176	static int dc_encap(sc, m_head, txidx)
3177	struct dc_softc *sc;
3178	struct mbuf *m_head;
3179	u_int32_t *txidx;
3180	{
3181	struct dc_desc *f = NULL;
3182	struct mbuf *m;
3183	int frag, cur, cnt = 0;
3184
3185	/*
3186	* Start packing the mbufs in this chain into
3187	* the fragment pointers. Stop when we run out
3188	* of fragments or hit the end of the mbuf chain.
3189	*/
3190	m = m_head;
3191	cur = frag = *txidx;
3192
3193	for (m = m_head; m != NULL; m = m->m_next) {
3194	if (m->m_len != 0) {
3195	if (sc->dc_flags & DC_TX_ADMTEK_WAR) {
3196	if (*txidx != sc->dc_cdata.dc_tx_prod &&
3197	frag == (DC_TX_LIST_CNT - 1))
3198	return(ENOBUFS);
3199	}
3200	if ((DC_TX_LIST_CNT -
3201	(sc->dc_cdata.dc_tx_cnt + cnt)) < 5)
3202	return(ENOBUFS);
3203
3204	f = &sc->dc_ldata->dc_tx_list[frag];
3205	f->dc_ctl = DC_TXCTL_TLINK \| m->m_len;
3206	if (cnt == 0) {
3207	f->dc_status = 0;
3208	f->dc_ctl \|= DC_TXCTL_FIRSTFRAG;
3209	} else
3210	f->dc_status = DC_TXSTAT_OWN;
3211	f->dc_data = vtophys(mtod(m, vm_offset_t));
3212	cur = frag;
3213	DC_INC(frag, DC_TX_LIST_CNT);
3214	cnt++;
3215	}
3216	}
3217
3218	if (m != NULL)
3219	return(ENOBUFS);
3220
3221	sc->dc_cdata.dc_tx_cnt += cnt;
3222	sc->dc_cdata.dc_tx_chain[cur] = m_head;
3223	sc->dc_ldata->dc_tx_list[cur].dc_ctl \|= DC_TXCTL_LASTFRAG;
3224	if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3225	sc->dc_ldata->dc_tx_list[*txidx].dc_ctl \|= DC_TXCTL_FINT;
3226	if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3227	sc->dc_ldata->dc_tx_list[cur].dc_ctl \|= DC_TXCTL_FINT;
3228	if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
3229	sc->dc_ldata->dc_tx_list[cur].dc_ctl \|= DC_TXCTL_FINT;
3230	sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN;
3231	*txidx = frag;
3232
3233	return(0);
3234	}
3235
3236	/*
3237	* Coalesce an mbuf chain into a single mbuf cluster buffer.
3238	* Needed for some really badly behaved chips that just can't
3239	* do scatter/gather correctly.
3240	*/
3241	static int dc_coal(sc, m_head)
3242	struct dc_softc *sc;
3243	struct mbuf **m_head;
3244	{
3245	struct mbuf m_new, m;
3246
3247	m = *m_head;
3248	MGETHDR(m_new, M_DONTWAIT, MT_DATA);
3249	if (m_new == NULL)
3250	return(ENOBUFS);
3251	if (m->m_pkthdr.len > MHLEN) {
3252	MCLGET(m_new, M_DONTWAIT);
3253	if (!(m_new->m_flags & M_EXT)) {
3254	m_freem(m_new);
3255	return(ENOBUFS);
3256	}
3257	}
3258	m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t));
3259	m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len;
3260	m_freem(m);
3261	*m_head = m_new;
3262
3263	return(0);
3264	}
3265
3266	/*
3267	* Main transmit routine. To avoid having to do mbuf copies, we put pointers
3268	* to the mbuf data regions directly in the transmit lists. We also save a
3269	* copy of the pointers since the transmit list fragment pointers are
3270	* physical addresses.
3271	*/
3272
3273	static void dc_start(ifp)
3274	struct ifnet *ifp;
3275	{
3276	struct dc_softc *sc;
3277	struct mbuf *m_head = NULL;
3278	int idx;
3279
3280	sc = ifp->if_softc;
3281	#if 0
3282	if (!sc->dc_link && ifp->if_snd.ifq_len < 10)
3283	return;
3284	#endif
3285	if (ifp->if_flags & IFF_OACTIVE)
3286	return;
3287
3288	idx = sc->dc_cdata.dc_tx_prod;
3289
3290	while(sc->dc_cdata.dc_tx_chain[idx] == NULL) {
3291	IF_DEQUEUE(&ifp->if_snd, m_head);
3292	if (m_head == NULL)
3293	break;
3294
3295	if (sc->dc_flags & DC_TX_COALESCE &&
3296	m_head->m_next != NULL) {
3297	/* only coalesce if have >1 mbufs */
3298	if (dc_coal(sc, &m_head)) {
3299	IF_PREPEND(&ifp->if_snd, m_head);
3300	ifp->if_flags \|= IFF_OACTIVE;
3301	break;
3302	}
3303	}
3304
3305	if (dc_encap(sc, m_head, &idx)) {
3306	IF_PREPEND(&ifp->if_snd, m_head);
3307	ifp->if_flags \|= IFF_OACTIVE;
3308	break;
3309	}
3310	#if 0
3311	/*
3312	* If there's a BPF listener, bounce a copy of this frame
3313	* to him.
3314	*/
3315	if (ifp->if_bpf)
3316	bpf_mtap(ifp, m_head);
3317	#endif
3318	if (sc->dc_flags & DC_TX_ONE) {
3319	ifp->if_flags \|= IFF_OACTIVE;
3320	break;
3321	}
3322	}
3323
3324	/* Transmit */
3325	sc->dc_cdata.dc_tx_prod = idx;
3326	if (!(sc->dc_flags & DC_TX_POLL))
3327	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3328
3329	/*
3330	* Set a timeout in case the chip goes out to lunch.
3331	*/
3332	ifp->if_timer = 5;
3333
3334	return;
3335	}
3336
3337	static void dc_init(xsc)
3338	void *xsc;
3339	{
3340	struct dc_softc *sc = xsc;
3341	struct ifnet *ifp = &sc->arpcom.ac_if;
3342	/struct mii_data mii;*/
3343
3344
3345	/mii = device_get_softc(sc->dc_miibus);/
3346
3347	/*
3348	* Cancel pending I/O and free all RX/TX buffers.
3349	*/
3350	dc_stop(sc);
3351	dc_reset(sc);
3352
3353	/*
3354	* Set cache alignment and burst length.
3355	*/
3356	if (DC_IS_ASIX(sc) \|\| DC_IS_DAVICOM(sc))
3357	CSR_WRITE_4(sc, DC_BUSCTL, 0);
3358	else
3359	CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME\|DC_BUSCTL_MRLE);
3360	/*
3361	* Evenly share the bus between receive and transmit process.
3362	*/
3363	if (DC_IS_INTEL(sc))
3364	DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3365	if (DC_IS_DAVICOM(sc) \|\| DC_IS_INTEL(sc)) {
3366	DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3367	} else {
3368	DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3369	}
3370	if (sc->dc_flags & DC_TX_POLL)
3371	DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3372	switch(sc->dc_cachesize) {
3373	case 32:
3374	DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3375	break;
3376	case 16:
3377	DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3378	break;
3379	case 8:
3380	DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3381	break;
3382	case 0:
3383	default:
3384	DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3385	break;
3386	}
3387
3388	if (sc->dc_flags & DC_TX_STORENFWD)
3389	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3390	else {
3391	if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3392	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3393	} else {
3394	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3395	DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3396	}
3397	}
3398
3399	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3400	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3401
3402	if (DC_IS_MACRONIX(sc) \|\| DC_IS_PNICII(sc)) {
3403	/*
3404	* The app notes for the 98713 and 98715A say that
3405	* in order to have the chips operate properly, a magic
3406	* number must be written to CSR16. Macronix does not
3407	* document the meaning of these bits so there's no way
3408	* to know exactly what they do. The 98713 has a magic
3409	* number all its own; the rest all use a different one.
3410	*/
3411	DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3412	if (sc->dc_type == DC_TYPE_98713)
3413	DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3414	else
3415	DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3416	}
3417
3418	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3419	DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3420
3421	/* Init circular RX list. */
3422	if (dc_list_rx_init(sc) == ENOBUFS) {
3423	printk("dc%d: initialization failed: no "
3424	"memory for rx buffers\n", sc->dc_unit);
3425	dc_stop(sc);
3426	return;
3427	}
3428
3429	/*
3430	* Init tx descriptors.
3431	*/
3432	dc_list_tx_init(sc);
3433
3434	/*
3435	* Load the address of the RX list.
3436	*/
3437	CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0]));
3438	CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0]));
3439
3440	/*
3441	* Enable interrupts.
3442	*/
3443	#ifdef DEVICE_POLLING
3444	/*
3445	* ... but only if we are not polling, and make sure they are off in
3446	* the case of polling. Some cards (e.g. fxp) turn interrupts on
3447	* after a reset.
3448	*/
3449	if (ifp->if_ipending & IFF_POLLING)
3450	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3451	else
3452	#endif
3453	/* Enable interrupts */
3454	CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3455	CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3456
3457	/* Enable transmitter. */
3458	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3459
3460	/*
3461	* If this is an Intel 21143 and we're not using the
3462	* MII port, program the LED control pins so we get
3463	* link and activity indications.
3464	*/
3465	if (sc->dc_flags & DC_TULIP_LEDS) {
3466	CSR_WRITE_4(sc, DC_WATCHDOG,
3467	DC_WDOG_CTLWREN\|DC_WDOG_LINK\|DC_WDOG_ACTIVITY);
3468	CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3469	}
3470
3471	/*
3472	* Load the RX/multicast filter. We do this sort of late
3473	* because the filter programming scheme on the 21143 and
3474	* some clones requires DMAing a setup frame via the TX
3475	* engine, and we need the transmitter enabled for that.
3476	*/
3477	dc_setfilt(sc);
3478
3479	/* Enable receiver. */
3480	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3481	CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3482
3483	/mii_mediachg(mii);/
3484	dc_setcfg(sc, sc->dc_if_media);
3485
3486	ifp->if_flags \|= IFF_RUNNING;
3487	ifp->if_flags &= ~IFF_OACTIVE;
3488
3489
3490	#if 0
3491
3492	/* Don't start the ticker if this is a homePNA link. */
3493	if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_homePNA)
3494	sc->dc_link = 1;
3495	else {
3496	if (sc->dc_flags & DC_21143_NWAY)
3497	sc->dc_stat_ch = timeout(dc_tick, sc, hz/10);
3498	else
3499	sc->dc_stat_ch = timeout(dc_tick, sc, hz);
3500	}
3501
3502	#ifdef SRM_MEDIA
3503	if(sc->dc_srm_media) {
3504	struct ifreq ifr;
3505
3506	ifr.ifr_media = sc->dc_srm_media;
3507	ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA);
3508	sc->dc_srm_media = 0;
3509	}
3510	#endif
3511	#endif /* end if (0) */
3512	return;
3513	}
3514
3515
3516	#if 0
3517	/*
3518	* Set media options.
3519	*/
3520	static int dc_ifmedia_upd(ifp)
3521	struct ifnet *ifp;
3522	{
3523	struct dc_softc *sc;
3524	struct mii_data *mii;
3525	struct ifmedia *ifm;
3526
3527	sc = ifp->if_softc;
3528	mii = device_get_softc(sc->dc_miibus);
3529	mii_mediachg(mii);
3530	ifm = &mii->mii_media;
3531
3532	if (DC_IS_DAVICOM(sc) &&
3533	IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA)
3534	dc_setcfg(sc, ifm->ifm_media);
3535	else
3536	sc->dc_link = 0;
3537
3538	return(0);
3539	}
3540
3541	/*
3542	* Report current media status.
3543	*/
3544	static void dc_ifmedia_sts(ifp, ifmr)
3545	struct ifnet *ifp;
3546	struct ifmediareq *ifmr;
3547	{
3548	struct dc_softc *sc;
3549	struct mii_data *mii;
3550	struct ifmedia *ifm;
3551
3552	sc = ifp->if_softc;
3553	mii = device_get_softc(sc->dc_miibus);
3554	mii_pollstat(mii);
3555	ifm = &mii->mii_media;
3556	if (DC_IS_DAVICOM(sc)) {
3557	if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) {
3558	ifmr->ifm_active = ifm->ifm_media;
3559	ifmr->ifm_status = 0;
3560	return;
3561	}
3562	}
3563	ifmr->ifm_active = mii->mii_media_active;
3564	ifmr->ifm_status = mii->mii_media_status;
3565
3566	return;
3567	}
3568	#endif
3569
3570
3571	static int dc_ioctl(ifp, command, data)
3572	struct ifnet *ifp;
3573	int command;
3574	caddr_t data;
3575	{
3576	struct dc_softc *sc = ifp->if_softc;
3577	/struct ifreq ifr = (struct ifreq *) data;
3578	struct mii_data mii;/
3579	int error = 0;
3580
3581
3582	switch(command) {
3583	case SIOCSIFADDR:
3584	case SIOCGIFADDR:
3585	case SIOCSIFMTU:
3586	error = ether_ioctl(ifp, command, data);
3587	break;
3588	case SIOCSIFFLAGS:
3589	if (ifp->if_flags & IFF_UP) {
3590	int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3591	(IFF_PROMISC \| IFF_ALLMULTI);
3592	if (ifp->if_flags & IFF_RUNNING) {
3593	if (need_setfilt)
3594	dc_setfilt(sc);
3595	} else {
3596	sc->dc_txthresh = 0;
3597	dc_init(sc);
3598	}
3599	} else {
3600	if (ifp->if_flags & IFF_RUNNING)
3601	dc_stop(sc);
3602	}
3603	sc->dc_if_flags = ifp->if_flags;
3604	error = 0;
3605	break;
3606	case SIOCADDMULTI:
3607	case SIOCDELMULTI:
3608	dc_setfilt(sc);
3609	error = 0;
3610	break;
3611	#if 0
3612	case SIOCGIFMEDIA:
3613	case SIOCSIFMEDIA:
3614	mii = device_get_softc(sc->dc_miibus);
3615	error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3616	#ifdef SRM_MEDIA
3617	if (sc->dc_srm_media)
3618	sc->dc_srm_media = 0;
3619	#endif
3620	break;
3621	#endif
3622	default:
3623	error = EINVAL;
3624	break;
3625	}
3626
3627
3628	return(error);
3629	}
3630
3631	static void dc_watchdog(ifp)
3632	struct ifnet *ifp;
3633	{
3634	struct dc_softc *sc;
3635
3636	sc = ifp->if_softc;
3637
3638	ifp->if_oerrors++;
3639	printk("dc%d: watchdog timeout\n", sc->dc_unit);
3640
3641	dc_stop(sc);
3642	dc_reset(sc);
3643	dc_init(sc);
3644
3645	if (ifp->if_snd.ifq_head != NULL)
3646	dc_start(ifp);
3647
3648	return;
3649	}
3650
3651	/*
3652	* Stop the adapter and free any mbufs allocated to the
3653	* RX and TX lists.
3654	*/
3655	static void dc_stop(sc)
3656	struct dc_softc *sc;
3657	{
3658	register int i;
3659	struct ifnet *ifp;
3660
3661	ifp = &sc->arpcom.ac_if;
3662	ifp->if_timer = 0;
3663
3664	/untimeout(dc_tick, sc, sc->dc_stat_ch);/
3665
3666	ifp->if_flags &= ~(IFF_RUNNING \| IFF_OACTIVE);
3667	#ifdef DEVICE_POLLING
3668	ether_poll_deregister(ifp);
3669	#endif
3670
3671	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON\|DC_NETCFG_TX_ON));
3672	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3673	CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3674	CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3675	sc->dc_link = 0;
3676
3677	/*
3678	* Free data in the RX lists.
3679	*/
3680	for (i = 0; i < DC_RX_LIST_CNT; i++) {
3681	if (sc->dc_cdata.dc_rx_chain[i] != NULL) {
3682	m_freem(sc->dc_cdata.dc_rx_chain[i]);
3683	sc->dc_cdata.dc_rx_chain[i] = NULL;
3684	}
3685	}
3686	bzero((char *)&sc->dc_ldata->dc_rx_list,
3687	sizeof(sc->dc_ldata->dc_rx_list));
3688
3689	/*
3690	* Free the TX list buffers.
3691	*/
3692	for (i = 0; i < DC_TX_LIST_CNT; i++) {
3693	if (sc->dc_cdata.dc_tx_chain[i] != NULL) {
3694	if (sc->dc_ldata->dc_tx_list[i].dc_ctl &
3695	DC_TXCTL_SETUP) {
3696	sc->dc_cdata.dc_tx_chain[i] = NULL;
3697	continue;
3698	}
3699	m_freem(sc->dc_cdata.dc_tx_chain[i]);
3700	sc->dc_cdata.dc_tx_chain[i] = NULL;
3701	}
3702	}
3703
3704	bzero((char *)&sc->dc_ldata->dc_tx_list,
3705	sizeof(sc->dc_ldata->dc_tx_list));
3706
3707	return;
3708	}
3709
3710
3711	#if 0
3712	/*
3713	* Stop all chip I/O so that the kernel's probe routines don't
3714	* get confused by errant DMAs when rebooting.
3715	*/
3716	static void dc_shutdown(dev)
3717	device_t dev;
3718	{
3719	struct dc_softc *sc;
3720
3721	sc = device_get_softc(dev);
3722
3723	dc_stop(sc);
3724
3725	return;
3726	}
3727
3728	/*
3729	* Device suspend routine. Stop the interface and save some PCI
3730	* settings in case the BIOS doesn't restore them properly on
3731	* resume.
3732	*/
3733	static int dc_suspend(dev)
3734	device_t dev;
3735	{
3736	register int i;
3737	int s;
3738	struct dc_softc *sc;
3739
3740
3741	sc = device_get_softc(dev);
3742
3743	dc_stop(sc);
3744
3745	for (i = 0; i < 5; i++)
3746	sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
3747	sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
3748	sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
3749	sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3750	sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3751
3752	sc->suspended = 1;
3753
3754	return (0);
3755	}
3756
3757	/*
3758	* Device resume routine. Restore some PCI settings in case the BIOS
3759	* doesn't, re-enable busmastering, and restart the interface if
3760	* appropriate.
3761	*/
3762	static int dc_resume(dev)
3763	device_t dev;
3764	{
3765	register int i;
3766	int s;
3767	struct dc_softc *sc;
3768	struct ifnet *ifp;
3769
3770
3771	sc = device_get_softc(dev);
3772	ifp = &sc->arpcom.ac_if;
3773
3774	dc_acpi(dev);
3775
3776	/* better way to do this? */
3777	for (i = 0; i < 5; i++)
3778	pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
3779	pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
3780	pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
3781	pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
3782	pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
3783
3784	/* reenable busmastering */
3785	pci_enable_busmaster(dev);
3786	pci_enable_io(dev, DC_RES);
3787
3788	/* reinitialize interface if necessary */
3789	if (ifp->if_flags & IFF_UP)
3790	dc_init(sc);
3791
3792	sc->suspended = 0;
3793
3794	return (0);
3795	}
3796	#endif
3797
3798

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