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source: rtems/c/src/libchip/network/if_dc.c @ a5b5b50

4.104.115

Last change on this file since a5b5b50 was a5b5b50, checked in by Joel Sherrill <joel.sherrill@…>, on 12/08/09 at 16:54:20

2009-12-08 Joel Sherrill <joel.sherrill@…>

libchip/network/dec21140.c, libchip/network/elnk.c, libchip/network/if_dc.c: Ensure PCI drivers are built on all supported configurations. PowerPC conditionals were not current and code was not being built on supported BSPs.

Property mode set to 100644

File size: 93.0 KB

Line
1	/* $Id$
2	*
3	* Ported from FreeBSD --> RTEMS, december 03.
4	* Daron Chabot <daron@nucleus.usask.ca>
5	* -- only tested with i386 bsp.
6	* -- supports one card (until the PCI & IRQ APIs get sorted out ;-))
7	*
8	*
9	* Copyright (c) 1997, 1998, 1999
10	* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
11	*
12	* Redistribution and use in source and binary forms, with or without
13	* modification, are permitted provided that the following conditions
14	* are met:
15	* 1. Redistributions of source code must retain the above copyright
16	* notice, this list of conditions and the following disclaimer.
17	* 2. Redistributions in binary form must reproduce the above copyright
18	* notice, this list of conditions and the following disclaimer in the
19	* documentation and/or other materials provided with the distribution.
20	* 3. All advertising materials mentioning features or use of this software
21	* must display the following acknowledgement:
22	* This product includes software developed by Bill Paul.
23	* 4. Neither the name of the author nor the names of any co-contributors
24	* may be used to endorse or promote products derived from this software
25	* without specific prior written permission.
26	*
27	* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
28	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30	* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
31	* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
37	* THE POSSIBILITY OF SUCH DAMAGE.
38	*
39	* $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.41 2003/03/05 18:42:33 njl Exp $
40	*/
41
42	/*
43	* DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
44	* series chips and several workalikes including the following:
45	*
46	* Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
47	* Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
48	* Lite-On 82c168/82c169 PNIC (www.litecom.com)
49	* ASIX Electronics AX88140A (www.asix.com.tw)
50	* ASIX Electronics AX88141 (www.asix.com.tw)
51	* ADMtek AL981 (www.admtek.com.tw)
52	* ADMtek AN985 (www.admtek.com.tw)
53	* Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
54	* Accton EN1217 (www.accton.com)
55	* Conexant LANfinity (www.conexant.com)
56	*
57	* Datasheets for the 21143 are available at developer.intel.com.
58	* Datasheets for the clone parts can be found at their respective sites.
59	* (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
60	* The PNIC II is essentially a Macronix 98715A chip; the only difference
61	* worth noting is that its multicast hash table is only 128 bits wide
62	* instead of 512.
63	*
64	* Written by Bill Paul <wpaul@ee.columbia.edu>
65	* Electrical Engineering Department
66	* Columbia University, New York City
67	*/
68
69	/*
70	* The Intel 21143 is the successor to the DEC 21140. It is basically
71	* the same as the 21140 but with a few new features. The 21143 supports
72	* three kinds of media attachments:
73	*
74	* o MII port, for 10Mbps and 100Mbps support and NWAY
75	* autonegotiation provided by an external PHY.
76	* o SYM port, for symbol mode 100Mbps support.
77	* o 10baseT port.
78	* o AUI/BNC port.
79	*
80	* The 100Mbps SYM port and 10baseT port can be used together in
81	* combination with the internal NWAY support to create a 10/100
82	* autosensing configuration.
83	*
84	* Note that not all tulip workalikes are handled in this driver: we only
85	* deal with those which are relatively well behaved. The Winbond is
86	* handled separately due to its different register offsets and the
87	* special handling needed for its various bugs. The PNIC is handled
88	* here, but I'm not thrilled about it.
89	*
90	* All of the workalike chips use some form of MII transceiver support
91	* with the exception of the Macronix chips, which also have a SYM port.
92	* The ASIX AX88140A is also documented to have a SYM port, but all
93	* the cards I've seen use an MII transceiver, probably because the
94	* AX88140A doesn't support internal NWAY.
95	*/
96
97	/*
98	* This driver only supports architectures with the new style
99	* exception processing. The following checks try to keep this
100	* from being compiled on systems which can't support this driver.
101	*/
102
103	#if defined(DRIVER_SUPPORTED)
104	#undef DRIVER_SUPPORTED
105	#endif
106
107	#if defined(__i386__)
108	#define DRIVER_SUPPORTED
109	#endif
110
111	#if defined(__PPC__)
112	#define DRIVER_SUPPORTED
113	#warning The if_dc driver is untested on the PPC platform !!!
114	#endif
115
116	#include <bsp.h>
117	#include <rtems/pci.h>
118
119	#if !defined(PCI_DRAM_OFFSET)
120	#undef DRIVER_SUPPORTED
121	#endif
122
123	#if defined(DRIVER_SUPPORTED) /* this covers the file "globally"... */
124
125	#include <rtems/error.h>
126	#include <errno.h>
127	#include <rtems/rtems_bsdnet.h>
128
129	#include <net/if_types.h>
130
131	#include <sys/param.h>
132	#include <sys/sockio.h>
133	#include <sys/socket.h>
134	#include <sys/mbuf.h>
135	#include <net/if.h>
136	#include <netinet/in.h>
137	#include <netinet/if_ether.h>
138	#include <sys/malloc.h>
139	#include <sys/systm.h>
140	#include <bsp.h>
141
142	/* moved to cpukit/include/rtems in CVS current ! */
143	/#include "if_media.h" /
144	/#include "pci.h" /
145	#include <net/if_media.h>
146	#include <rtems/pci.h>
147	/*
148	#include <sys/kernel.h>
149	#include <sys/sysctl.h>
150	*/
151
152	#include <vm/vm.h> /* for vtophys */
153
154
155	#if defined(__i386__)
156	#define vtophys(p) (u_int32_t)(p)
157	#else
158	#define vtophys(p) vtophys(p)
159	#endif
160
161	/*
162	#include <net/if_arp.h>
163	#include <net/if_vlan_var.h>
164	#include <net/bpf.h>
165	*/
166
167	#if 0
168	#include <vm/pmap.h> /* for vtophys */
169	#include <machine/clock.h> /* for DELAY */
170	#include <machine/bus_pio.h>
171	#include <machine/bus_memio.h>
172	#include <machine/bus.h>
173	#include <machine/resource.h>
174	#include <sys/bus.h>
175	#include <sys/rman.h>
176	#endif
177	#include <dev/mii/mii.h>
178	#if 0
179	#include <dev/mii/miivar.h>
180
181	#include <pci/pcireg.h>
182	#include <pci/pcivar.h>
183	#endif
184
185	/* NOTE: use mem space mapping (for now ...)
186	#define DC_USEIOSPACE
187	*/
188
189	#ifdef __alpha__
190	#define SRM_MEDIA
191	#endif
192
193	#include <bsp/irq.h>
194
195
196	#include "if_dcreg.h"
197
198
199	#define DRIVER_PREFIX "tl"
200	#define NDRIVER 1
201	#define IRQ_EVENT RTEMS_EVENT_13 /* Ha ... */
202	static struct dc_softc dc_softc_devs[NDRIVER];
203
204	#define UNUSED
205
206	#if 0
207	/* "controller miibus0" required. See GENERIC if you get errors here. */
208	#include "miibus_if.h"
209
210
211
212	#ifndef lint
213	static const char rcsid[] =
214	"$FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.41 2003/03/05 18:42:33 njl Exp $";
215	#endif
216
217	#endif
218
219
220	/*
221	* Various supported device vendors/types and their names.
222	* NOTE:
223	* -----
224	* Only the "ADMtek AN985" has been tested under RTEMS !!!
225	*/
226	static struct dc_type dc_devs[] = {
227	{ DC_VENDORID_DEC, DC_DEVICEID_21143,
228	"Intel 21143 10/100BaseTX", 0 },
229	{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009,
230	"Davicom DM9009 10/100BaseTX", 0 },
231	{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100,
232	"Davicom DM9100 10/100BaseTX", 0 },
233	{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
234	"Davicom DM9102 10/100BaseTX", 0 },
235	{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
236	"Davicom DM9102A 10/100BaseTX", 0 },
237	{ DC_VENDORID_ADMTEK, DC_DEVICEID_AL981,
238	"ADMtek AL981 10/100BaseTX", 0 },
239	{ DC_VENDORID_ADMTEK, DC_DEVICEID_AN985,
240	"ADMtek AN985 10/100BaseTX", 0 },
241	{ DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
242	"ASIX AX88140A 10/100BaseTX", 0 },
243	{ DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
244	"ASIX AX88141 10/100BaseTX", 0 },
245	{ DC_VENDORID_MX, DC_DEVICEID_98713,
246	"Macronix 98713 10/100BaseTX", 0 },
247	{ DC_VENDORID_MX, DC_DEVICEID_98713,
248	"Macronix 98713A 10/100BaseTX", 0 },
249	{ DC_VENDORID_CP, DC_DEVICEID_98713_CP,
250	"Compex RL100-TX 10/100BaseTX", 0 },
251	{ DC_VENDORID_CP, DC_DEVICEID_98713_CP,
252	"Compex RL100-TX 10/100BaseTX", 0 },
253	{ DC_VENDORID_MX, DC_DEVICEID_987x5,
254	"Macronix 98715/98715A 10/100BaseTX", 0 },
255	{ DC_VENDORID_MX, DC_DEVICEID_987x5,
256	"Macronix 98715AEC-C 10/100BaseTX", 0 },
257	{ DC_VENDORID_MX, DC_DEVICEID_987x5,
258	"Macronix 98725 10/100BaseTX", 0 },
259	{ DC_VENDORID_MX, DC_DEVICEID_98727,
260	"Macronix 98727/98732 10/100BaseTX", 0 },
261	{ DC_VENDORID_LO, DC_DEVICEID_82C115,
262	"LC82C115 PNIC II 10/100BaseTX", 0 },
263	{ DC_VENDORID_LO, DC_DEVICEID_82C168,
264	"82c168 PNIC 10/100BaseTX", 0 },
265	{ DC_VENDORID_LO, DC_DEVICEID_82C168,
266	"82c169 PNIC 10/100BaseTX", 0 },
267	{ DC_VENDORID_ACCTON, DC_DEVICEID_EN1217,
268	"Accton EN1217 10/100BaseTX", 0 },
269	{ DC_VENDORID_ACCTON, DC_DEVICEID_EN2242,
270	"Accton EN2242 MiniPCI 10/100BaseTX", 0 },
271	{ DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112,
272	"Conexant LANfinity MiniPCI 10/100BaseTX", 0 },
273	{ 0, 0, NULL, 0 }
274	};
275
276	#if 0
277	static int dc_probe __P((device_t));
278	static int dc_attach __P((device_t));
279	static int dc_detach __P((device_t));
280	static int dc_suspend __P((device_t));
281	static int dc_resume __P((device_t));
282	static void dc_shutdown __P((device_t));
283	static void dc_acpi __P((device_t));
284	#endif
285
286	static struct dc_type *dc_devtype(int);
287	static int dc_newbuf(struct dc_softc , int, struct mbuf );
288	static int dc_encap(struct dc_softc , struct mbuf ,
289	u_int32_t *);
290	static int dc_coal(struct dc_softc , struct mbuf *);
291	static void dc_pnic_rx_bug_war(struct dc_softc *, int);
292	static int dc_rx_resync(struct dc_softc *);
293	static void dc_rxeof(struct dc_softc *);
294	static void dc_txeof(struct dc_softc *);
295	/static void dc_tick((void ));*/
296	static void dc_tx_underrun(struct dc_softc *);
297	static void dc_intr(void *);
298	static void dc_daemon(void *);
299	static void dc_start(struct ifnet *);
300	static int dc_ioctl(struct ifnet *, ioctl_command_t, caddr_t);
301	static void dc_init(void *);
302	static void dc_stop(struct dc_softc *);
303	static void dc_watchdog(struct ifnet *);
304	#if 0
305	static int dc_ifmedia_upd __P((struct ifnet *));
306	static void dc_ifmedia_sts __P((struct ifnet , struct ifmediareq ));
307	#endif
308
309	static void dc_delay(struct dc_softc *);
310	static void dc_eeprom_idle(struct dc_softc *);
311	static void dc_eeprom_putbyte(struct dc_softc *, int);
312	static void dc_eeprom_getword(struct dc_softc , int, u_int16_t );
313	static void dc_eeprom_getword_pnic(struct dc_softc , int, u_int16_t );
314	static void dc_eeprom_width(struct dc_softc *);
315	static void dc_read_eeprom(struct dc_softc *, caddr_t, int,int, int);
316
317	#if 0
318	static void dc_mii_writebit __P((struct dc_softc *, int));
319	static int dc_mii_readbit __P((struct dc_softc *));
320	static void dc_mii_sync __P((struct dc_softc *));
321	static void dc_mii_send __P((struct dc_softc *, u_int32_t, int));
322	static int dc_mii_readreg __P((struct dc_softc , struct dc_mii_frame ));
323	static int dc_mii_writereg __P((struct dc_softc , struct dc_mii_frame ));
324	static int dc_miibus_readreg __P((device_t, int, int));
325	static int dc_miibus_writereg __P((device_t, int, int, int));
326	static void dc_miibus_statchg __P((device_t));
327	static void dc_miibus_mediainit __P((device_t));
328	#endif
329
330	static void dc_setcfg(struct dc_softc *, int);
331	static u_int32_t dc_crc_le(struct dc_softc *, caddr_t);
332	#ifndef UNUSED
333	static u_int32_t dc_crc_be(caddr_t);
334	#endif
335	static void dc_setfilt_21143(struct dc_softc *);
336	static void dc_setfilt_asix(struct dc_softc *);
337	static void dc_setfilt_admtek(struct dc_softc *);
338	static void dc_setfilt(struct dc_softc *);
339	static void dc_reset(struct dc_softc *);
340	static int dc_list_rx_init(struct dc_softc *);
341	static int dc_list_tx_init(struct dc_softc *);
342	static void dc_read_srom(struct dc_softc *, int);
343	static void dc_parse_21143_srom(struct dc_softc *);
344	static void dc_apply_fixup(struct dc_softc *, int);
345
346	#if 0
347	static void dc_decode_leaf_sia __P((struct dc_softc *,
348	struct dc_eblock_sia *));
349	static void dc_decode_leaf_mii __P((struct dc_softc *,
350	struct dc_eblock_mii *));
351	static void dc_decode_leaf_sym __P((struct dc_softc *,
352	struct dc_eblock_sym *));
353	#endif
354
355
356	#ifdef DC_USEIOSPACE
357	#define DC_RES SYS_RES_IOPORT
358	#define DC_RID DC_PCI_CFBIO
359	#else
360	#define DC_RES SYS_RES_MEMORY
361	#define DC_RID DC_PCI_CFBMA
362	#endif
363
364	#if 0
365	static device_method_t dc_methods[] = {
366	/* Device interface */
367	DEVMETHOD(device_probe, dc_probe),
368	DEVMETHOD(device_attach, dc_attach),
369	DEVMETHOD(device_detach, dc_detach),
370	DEVMETHOD(device_suspend, dc_suspend),
371	DEVMETHOD(device_resume, dc_resume),
372	DEVMETHOD(device_shutdown, dc_shutdown),
373
374	/* bus interface */
375	DEVMETHOD(bus_print_child, bus_generic_print_child),
376	DEVMETHOD(bus_driver_added, bus_generic_driver_added),
377
378	/* MII interface */
379	DEVMETHOD(miibus_readreg, dc_miibus_readreg),
380	DEVMETHOD(miibus_writereg, dc_miibus_writereg),
381	DEVMETHOD(miibus_statchg, dc_miibus_statchg),
382	DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
383
384	{ 0, 0 }
385	};
386
387	static driver_t dc_driver = {
388	"dc",
389	dc_methods,
390	sizeof(struct dc_softc)
391	};
392
393	static devclass_t dc_devclass;
394	#endif
395
396
397	#ifdef __i386__
398	static int dc_quick=1;
399	#if 0
400	SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW,
401	&dc_quick,0,"do not mdevget in dc driver");
402	#endif
403	#endif
404
405	#if 0
406	DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0);
407	DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
408	#endif
409
410
411	#define DC_SETBIT(sc, reg, x) \
412	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) \| (x))
413
414	#define DC_CLRBIT(sc, reg, x) \
415	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
416
417	#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
418	#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
419
420
421	/* XXX Fixme: rtems_bsp_delay( ) for the pc386 BSP (at least)
422	* needs work... see pc386/include/bsp.h.
423	* I have "a" solution, utilizing the 2nd i8254 timer,
424	* if anyone is interested (first timer is used for clock_tick ISR)...
425	*/
426	#ifdef __i386__
427	extern void Wait_X_ms( unsigned int );
428	#define DELAY(n) Wait_X_ms( (unsigned int)((n)/100) )
429	#else
430	#define DELAY(n) rtems_bsp_delay(n)
431	#endif
432
433
434	static void dc_delay(sc)
435	struct dc_softc *sc;
436	{
437	int idx;
438
439	for (idx = (300 / 33) + 1; idx > 0; idx--)
440	CSR_READ_4(sc, DC_BUSCTL);
441	}
442
443	static void dc_eeprom_width(sc)
444	struct dc_softc *sc;
445	{
446	int i;
447
448	/* Force EEPROM to idle state. */
449	dc_eeprom_idle(sc);
450
451	/* Enter EEPROM access mode. */
452	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
453	dc_delay(sc);
454	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
455	dc_delay(sc);
456	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
457	dc_delay(sc);
458	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
459	dc_delay(sc);
460
461	for (i = 3; i--;) {
462	if (6 & (1 << i))
463	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
464	else
465	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
466	dc_delay(sc);
467	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
468	dc_delay(sc);
469	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
470	dc_delay(sc);
471	}
472
473	for (i = 1; i <= 12; i++) {
474	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
475	dc_delay(sc);
476	if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
477	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
478	dc_delay(sc);
479	break;
480	}
481	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
482	dc_delay(sc);
483	}
484
485	/* Turn off EEPROM access mode. */
486	dc_eeprom_idle(sc);
487
488	if (i < 4 \|\| i > 12)
489	sc->dc_romwidth = 6;
490	else
491	sc->dc_romwidth = i;
492
493	/* Enter EEPROM access mode. */
494	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
495	dc_delay(sc);
496	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
497	dc_delay(sc);
498	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
499	dc_delay(sc);
500	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
501	dc_delay(sc);
502
503	/* Turn off EEPROM access mode. */
504	dc_eeprom_idle(sc);
505	}
506
507	static void dc_eeprom_idle(sc)
508	struct dc_softc *sc;
509	{
510	register int i;
511
512	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
513	dc_delay(sc);
514	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
515	dc_delay(sc);
516	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
517	dc_delay(sc);
518	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
519	dc_delay(sc);
520
521	for (i = 0; i < 25; i++) {
522	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
523	dc_delay(sc);
524	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
525	dc_delay(sc);
526	}
527
528	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
529	dc_delay(sc);
530	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
531	dc_delay(sc);
532	CSR_WRITE_4(sc, DC_SIO, 0x00000000);
533
534	return;
535	}
536
537	/*
538	* Send a read command and address to the EEPROM, check for ACK.
539	*/
540	static void dc_eeprom_putbyte(sc, addr)
541	struct dc_softc *sc;
542	int addr;
543	{
544	register int d, i;
545
546	d = DC_EECMD_READ >> 6;
547	for (i = 3; i--; ) {
548	if (d & (1 << i))
549	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
550	else
551	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
552	dc_delay(sc);
553	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
554	dc_delay(sc);
555	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
556	dc_delay(sc);
557	}
558
559	/*
560	* Feed in each bit and strobe the clock.
561	*/
562	for (i = sc->dc_romwidth; i--;) {
563	if (addr & (1 << i)) {
564	SIO_SET(DC_SIO_EE_DATAIN);
565	} else {
566	SIO_CLR(DC_SIO_EE_DATAIN);
567	}
568	dc_delay(sc);
569	SIO_SET(DC_SIO_EE_CLK);
570	dc_delay(sc);
571	SIO_CLR(DC_SIO_EE_CLK);
572	dc_delay(sc);
573	}
574
575	return;
576	}
577
578	/*
579	* Read a word of data stored in the EEPROM at address 'addr.'
580	* The PNIC 82c168/82c169 has its own non-standard way to read
581	* the EEPROM.
582	*/
583	static void dc_eeprom_getword_pnic(sc, addr, dest)
584	struct dc_softc *sc;
585	int addr;
586	u_int16_t *dest;
587	{
588	register int i;
589	u_int32_t r;
590
591	CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ\|addr);
592
593	for (i = 0; i < DC_TIMEOUT; i++) {
594	DELAY(1);
595	r = CSR_READ_4(sc, DC_SIO);
596	if (!(r & DC_PN_SIOCTL_BUSY)) {
597	*dest = (u_int16_t)(r & 0xFFFF);
598	return;
599	}
600	}
601
602	return;
603	}
604
605	/*
606	* Read a word of data stored in the EEPROM at address 'addr.'
607	*/
608	static void dc_eeprom_getword(sc, addr, dest)
609	struct dc_softc *sc;
610	int addr;
611	u_int16_t *dest;
612	{
613	register int i;
614	u_int16_t word = 0;
615
616	/* Force EEPROM to idle state. */
617	dc_eeprom_idle(sc);
618
619	/* Enter EEPROM access mode. */
620	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
621	dc_delay(sc);
622	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
623	dc_delay(sc);
624	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
625	dc_delay(sc);
626	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
627	dc_delay(sc);
628
629	/*
630	* Send address of word we want to read.
631	*/
632	dc_eeprom_putbyte(sc, addr);
633
634	/*
635	* Start reading bits from EEPROM.
636	*/
637	for (i = 0x8000; i; i >>= 1) {
638	SIO_SET(DC_SIO_EE_CLK);
639	dc_delay(sc);
640	if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
641	word \|= i;
642	dc_delay(sc);
643	SIO_CLR(DC_SIO_EE_CLK);
644	dc_delay(sc);
645	}
646
647	/* Turn off EEPROM access mode. */
648	dc_eeprom_idle(sc);
649
650	*dest = word;
651
652	return;
653	}
654
655	/*
656	* Read a sequence of words from the EEPROM.
657	*/
658	static void dc_read_eeprom(sc, dest, off, cnt, swap)
659	struct dc_softc *sc;
660	caddr_t dest;
661	int off;
662	int cnt;
663	int swap;
664	{
665	int i;
666	u_int16_t word = 0, *ptr;
667
668	for (i = 0; i < cnt; i++) {
669	if (DC_IS_PNIC(sc))
670	dc_eeprom_getword_pnic(sc, off + i, &word);
671	else
672	dc_eeprom_getword(sc, off + i, &word);
673	ptr = (u_int16_t )(dest + (i 2));
674	if (swap)
675	*ptr = ntohs(word);
676	else
677	*ptr = word;
678	}
679
680	return;
681	}
682
683
684	#if 0
685	/*
686	* The following two routines are taken from the Macronix 98713
687	* Application Notes pp.19-21.
688	*/
689	/*
690	* Write a bit to the MII bus.
691	*/
692	static void dc_mii_writebit(sc, bit)
693	struct dc_softc *sc;
694	int bit;
695	{
696	if (bit)
697	CSR_WRITE_4(sc, DC_SIO,
698	DC_SIO_ROMCTL_WRITE\|DC_SIO_MII_DATAOUT);
699	else
700	CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
701
702	DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
703	DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
704
705	return;
706	}
707
708	/*
709	* Read a bit from the MII bus.
710	*/
711	static int dc_mii_readbit(sc)
712	struct dc_softc *sc;
713	{
714	CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ\|DC_SIO_MII_DIR);
715	CSR_READ_4(sc, DC_SIO);
716	DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
717	DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
718	if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
719	return(1);
720
721	return(0);
722	}
723
724	/*
725	* Sync the PHYs by setting data bit and strobing the clock 32 times.
726	*/
727	static void dc_mii_sync(sc)
728	struct dc_softc *sc;
729	{
730	register int i;
731
732	CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
733
734	for (i = 0; i < 32; i++)
735	dc_mii_writebit(sc, 1);
736
737	return;
738	}
739
740	/*
741	* Clock a series of bits through the MII.
742	*/
743	static void dc_mii_send(sc, bits, cnt)
744	struct dc_softc *sc;
745	u_int32_t bits;
746	int cnt;
747	{
748	int i;
749
750	for (i = (0x1 << (cnt - 1)); i; i >>= 1)
751	dc_mii_writebit(sc, bits & i);
752	}
753
754	/*
755	* Read an PHY register through the MII.
756	*/
757	static int dc_mii_readreg(sc, frame)
758	struct dc_softc *sc;
759	struct dc_mii_frame *frame;
760
761	{
762	int i, ack, s;
763
764
765	/*
766	* Set up frame for RX.
767	*/
768	frame->mii_stdelim = DC_MII_STARTDELIM;
769	frame->mii_opcode = DC_MII_READOP;
770	frame->mii_turnaround = 0;
771	frame->mii_data = 0;
772
773	/*
774	* Sync the PHYs.
775	*/
776	dc_mii_sync(sc);
777
778	/*
779	* Send command/address info.
780	*/
781	dc_mii_send(sc, frame->mii_stdelim, 2);
782	dc_mii_send(sc, frame->mii_opcode, 2);
783	dc_mii_send(sc, frame->mii_phyaddr, 5);
784	dc_mii_send(sc, frame->mii_regaddr, 5);
785
786	#ifdef notdef
787	/* Idle bit */
788	dc_mii_writebit(sc, 1);
789	dc_mii_writebit(sc, 0);
790	#endif
791
792	/* Check for ack */
793	ack = dc_mii_readbit(sc);
794
795	/*
796	* Now try reading data bits. If the ack failed, we still
797	* need to clock through 16 cycles to keep the PHY(s) in sync.
798	*/
799	if (ack) {
800	for(i = 0; i < 16; i++) {
801	dc_mii_readbit(sc);
802	}
803	goto fail;
804	}
805
806	for (i = 0x8000; i; i >>= 1) {
807	if (!ack) {
808	if (dc_mii_readbit(sc))
809	frame->mii_data \|= i;
810	}
811	}
812
813	fail:
814
815	dc_mii_writebit(sc, 0);
816	dc_mii_writebit(sc, 0);
817
818
819	if (ack)
820	return(1);
821	return(0);
822	}
823
824	/*
825	* Write to a PHY register through the MII.
826	*/
827	static int dc_mii_writereg(sc, frame)
828	struct dc_softc *sc;
829	struct dc_mii_frame *frame;
830
831	{
832	int s;
833
834	/*
835	* Set up frame for TX.
836	*/
837
838	frame->mii_stdelim = DC_MII_STARTDELIM;
839	frame->mii_opcode = DC_MII_WRITEOP;
840	frame->mii_turnaround = DC_MII_TURNAROUND;
841
842	/*
843	* Sync the PHYs.
844	*/
845	dc_mii_sync(sc);
846
847	dc_mii_send(sc, frame->mii_stdelim, 2);
848	dc_mii_send(sc, frame->mii_opcode, 2);
849	dc_mii_send(sc, frame->mii_phyaddr, 5);
850	dc_mii_send(sc, frame->mii_regaddr, 5);
851	dc_mii_send(sc, frame->mii_turnaround, 2);
852	dc_mii_send(sc, frame->mii_data, 16);
853
854	/* Idle bit. */
855	dc_mii_writebit(sc, 0);
856	dc_mii_writebit(sc, 0);
857
858
859	return(0);
860	}
861
862	static int dc_miibus_readreg(dev, phy, reg)
863	device_t dev;
864	int phy, reg;
865	{
866	struct dc_mii_frame frame;
867	struct dc_softc *sc;
868	int i, rval, phy_reg = 0;
869
870	sc = device_get_softc(dev);
871	bzero((char *)&frame, sizeof(frame));
872
873	/*
874	* Note: both the AL981 and AN985 have internal PHYs,
875	* however the AL981 provides direct access to the PHY
876	* registers while the AN985 uses a serial MII interface.
877	* The AN985's MII interface is also buggy in that you
878	* can read from any MII address (0 to 31), but only address 1
879	* behaves normally. To deal with both cases, we pretend
880	* that the PHY is at MII address 1.
881	*/
882	if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
883	return(0);
884
885	/*
886	* Note: the ukphy probes of the RS7112 report a PHY at
887	* MII address 0 (possibly HomePNA?) and 1 (ethernet)
888	* so we only respond to correct one.
889	*/
890	if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
891	return(0);
892
893	if (sc->dc_pmode != DC_PMODE_MII) {
894	if (phy == (MII_NPHY - 1)) {
895	switch(reg) {
896	case MII_BMSR:
897	/*
898	* Fake something to make the probe
899	* code think there's a PHY here.
900	*/
901	return(BMSR_MEDIAMASK);
902	break;
903	case MII_PHYIDR1:
904	if (DC_IS_PNIC(sc))
905	return(DC_VENDORID_LO);
906	return(DC_VENDORID_DEC);
907	break;
908	case MII_PHYIDR2:
909	if (DC_IS_PNIC(sc))
910	return(DC_DEVICEID_82C168);
911	return(DC_DEVICEID_21143);
912	break;
913	default:
914	return(0);
915	break;
916	}
917	} else
918	return(0);
919	}
920
921	if (DC_IS_PNIC(sc)) {
922	CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ \|
923	(phy << 23) \| (reg << 18));
924	for (i = 0; i < DC_TIMEOUT; i++) {
925	DELAY(1);
926	rval = CSR_READ_4(sc, DC_PN_MII);
927	if (!(rval & DC_PN_MII_BUSY)) {
928	rval &= 0xFFFF;
929	return(rval == 0xFFFF ? 0 : rval);
930	}
931	}
932	return(0);
933	}
934
935	if (DC_IS_COMET(sc)) {
936	switch(reg) {
937	case MII_BMCR:
938	phy_reg = DC_AL_BMCR;
939	break;
940	case MII_BMSR:
941	phy_reg = DC_AL_BMSR;
942	break;
943	case MII_PHYIDR1:
944	phy_reg = DC_AL_VENID;
945	break;
946	case MII_PHYIDR2:
947	phy_reg = DC_AL_DEVID;
948	break;
949	case MII_ANAR:
950	phy_reg = DC_AL_ANAR;
951	break;
952	case MII_ANLPAR:
953	phy_reg = DC_AL_LPAR;
954	break;
955	case MII_ANER:
956	phy_reg = DC_AL_ANER;
957	break;
958	default:
959	printk("dc%d: phy_read: bad phy register %x\n",
960	sc->dc_unit, reg);
961	return(0);
962	break;
963	}
964
965	rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
966
967	if (rval == 0xFFFF)
968	return(0);
969	return(rval);
970	}
971
972	frame.mii_phyaddr = phy;
973	frame.mii_regaddr = reg;
974	if (sc->dc_type == DC_TYPE_98713) {
975	phy_reg = CSR_READ_4(sc, DC_NETCFG);
976	CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
977	}
978	dc_mii_readreg(sc, &frame);
979	if (sc->dc_type == DC_TYPE_98713)
980	CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
981
982	return(frame.mii_data);
983	}
984
985	static int dc_miibus_writereg(dev, phy, reg, data)
986	device_t dev;
987	int phy, reg, data;
988	{
989	struct dc_softc *sc;
990	struct dc_mii_frame frame;
991	int i, phy_reg = 0;
992
993	sc = device_get_softc(dev);
994	bzero((char *)&frame, sizeof(frame));
995
996	if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
997	return(0);
998
999	if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
1000	return(0);
1001
1002	if (DC_IS_PNIC(sc)) {
1003	CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE \|
1004	(phy << 23) \| (reg << 10) \| data);
1005	for (i = 0; i < DC_TIMEOUT; i++) {
1006	if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
1007	break;
1008	}
1009	return(0);
1010	}
1011
1012	if (DC_IS_COMET(sc)) {
1013	switch(reg) {
1014	case MII_BMCR:
1015	phy_reg = DC_AL_BMCR;
1016	break;
1017	case MII_BMSR:
1018	phy_reg = DC_AL_BMSR;
1019	break;
1020	case MII_PHYIDR1:
1021	phy_reg = DC_AL_VENID;
1022	break;
1023	case MII_PHYIDR2:
1024	phy_reg = DC_AL_DEVID;
1025	break;
1026	case MII_ANAR:
1027	phy_reg = DC_AL_ANAR;
1028	break;
1029	case MII_ANLPAR:
1030	phy_reg = DC_AL_LPAR;
1031	break;
1032	case MII_ANER:
1033	phy_reg = DC_AL_ANER;
1034	break;
1035	default:
1036	printk("dc%d: phy_write: bad phy register %x\n",
1037	sc->dc_unit, reg);
1038	return(0);
1039	break;
1040	}
1041
1042	CSR_WRITE_4(sc, phy_reg, data);
1043	return(0);
1044	}
1045
1046	frame.mii_phyaddr = phy;
1047	frame.mii_regaddr = reg;
1048	frame.mii_data = data;
1049
1050	if (sc->dc_type == DC_TYPE_98713) {
1051	phy_reg = CSR_READ_4(sc, DC_NETCFG);
1052	CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
1053	}
1054	dc_mii_writereg(sc, &frame);
1055	if (sc->dc_type == DC_TYPE_98713)
1056	CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
1057
1058	return(0);
1059	}
1060
1061	static void dc_miibus_statchg(dev)
1062	device_t dev;
1063	{
1064	struct dc_softc *sc;
1065	struct mii_data *mii;
1066	struct ifmedia *ifm;
1067
1068	sc = device_get_softc(dev);
1069	if (DC_IS_ADMTEK(sc))
1070	return;
1071
1072	mii = device_get_softc(sc->dc_miibus);
1073	ifm = &mii->mii_media;
1074	if (DC_IS_DAVICOM(sc) &&
1075	IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) {
1076	dc_setcfg(sc, ifm->ifm_media);
1077	sc->dc_if_media = ifm->ifm_media;
1078	} else {
1079	dc_setcfg(sc, mii->mii_media_active);
1080	sc->dc_if_media = mii->mii_media_active;
1081	}
1082
1083	return;
1084	}
1085
1086	/*
1087	* Special support for DM9102A cards with HomePNA PHYs. Note:
1088	* with the Davicom DM9102A/DM9801 eval board that I have, it seems
1089	* to be impossible to talk to the management interface of the DM9801
1090	* PHY (its MDIO pin is not connected to anything). Consequently,
1091	* the driver has to just 'know' about the additional mode and deal
1092	* with it itself. sigh
1093	*/
1094	static void dc_miibus_mediainit(dev)
1095	device_t dev;
1096	{
1097	struct dc_softc *sc;
1098	struct mii_data *mii;
1099	struct ifmedia *ifm;
1100	int rev;
1101
1102	rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF;
1103
1104	sc = device_get_softc(dev);
1105	mii = device_get_softc(sc->dc_miibus);
1106	ifm = &mii->mii_media;
1107
1108	if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
1109	ifmedia_add(ifm, IFM_ETHER\|IFM_homePNA, 0, NULL);
1110
1111	return;
1112	}
1113	#endif
1114
1115	#define DC_POLY 0xEDB88320
1116	#define DC_BITS_512 9
1117	#define DC_BITS_128 7
1118	#define DC_BITS_64 6
1119
1120	static u_int32_t dc_crc_le(sc, addr)
1121	struct dc_softc *sc;
1122	caddr_t addr;
1123	{
1124	u_int32_t idx, bit, data, crc;
1125
1126	/* Compute CRC for the address value. */
1127	crc = 0xFFFFFFFF; /* initial value */
1128
1129	for (idx = 0; idx < 6; idx++) {
1130	for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
1131	crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0);
1132	}
1133
1134	/*
1135	* The hash table on the PNIC II and the MX98715AEC-C/D/E
1136	* chips is only 128 bits wide.
1137	*/
1138	if (sc->dc_flags & DC_128BIT_HASH)
1139	return (crc & ((1 << DC_BITS_128) - 1));
1140
1141	/* The hash table on the MX98715BEC is only 64 bits wide. */
1142	if (sc->dc_flags & DC_64BIT_HASH)
1143	return (crc & ((1 << DC_BITS_64) - 1));
1144
1145	return (crc & ((1 << DC_BITS_512) - 1));
1146	}
1147
1148	#ifndef UNUSED
1149	/*
1150	* Calculate CRC of a multicast group address, return the lower 6 bits.
1151	*/
1152	static u_int32_t dc_crc_be(addr)
1153	caddr_t addr;
1154	{
1155	u_int32_t crc, carry;
1156	int i, j;
1157	u_int8_t c;
1158
1159	/* Compute CRC for the address value. */
1160	crc = 0xFFFFFFFF; /* initial value */
1161
1162	for (i = 0; i < 6; i++) {
1163	c = *(addr + i);
1164	for (j = 0; j < 8; j++) {
1165	carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
1166	crc <<= 1;
1167	c >>= 1;
1168	if (carry)
1169	crc = (crc ^ 0x04c11db6) \| carry;
1170	}
1171	}
1172
1173	/* return the filter bit position */
1174	return((crc >> 26) & 0x0000003F);
1175	}
1176	#endif
1177
1178	/*
1179	* 21143-style RX filter setup routine. Filter programming is done by
1180	* downloading a special setup frame into the TX engine. 21143, Macronix,
1181	* PNIC, PNIC II and Davicom chips are programmed this way.
1182	*
1183	* We always program the chip using 'hash perfect' mode, i.e. one perfect
1184	* address (our node address) and a 512-bit hash filter for multicast
1185	* frames. We also sneak the broadcast address into the hash filter since
1186	* we need that too.
1187	*/
1188	void dc_setfilt_21143(sc)
1189	struct dc_softc *sc;
1190	{
1191	struct dc_desc *sframe;
1192	u_int32_t h, *sp;
1193	/struct ifmultiaddr ifma;*/
1194	struct ifnet *ifp;
1195	int i;
1196	u_int16_t *ac_enaddr;
1197
1198	ifp = &sc->arpcom.ac_if;
1199
1200	i = sc->dc_cdata.dc_tx_prod;
1201	DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1202	sc->dc_cdata.dc_tx_cnt++;
1203	sframe = &sc->dc_ldata->dc_tx_list[i];
1204	sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf;
1205	bzero((char *)sp, DC_SFRAME_LEN);
1206
1207	sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf);
1208	sframe->dc_ctl = DC_SFRAME_LEN \| DC_TXCTL_SETUP \| DC_TXCTL_TLINK \|
1209	DC_FILTER_HASHPERF \| DC_TXCTL_FINT;
1210
1211	sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf;
1212
1213	/* If we want promiscuous mode, set the allframes bit. */
1214	if (ifp->if_flags & IFF_PROMISC)
1215	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1216	else
1217	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1218
1219	if (ifp->if_flags & IFF_ALLMULTI)
1220	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1221	else
1222	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1223	#if 0
1224	for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1225	ifma = ifma->ifma_link.le_next) {
1226	if (ifma->ifma_addr->sa_family != AF_LINK)
1227	continue;
1228	h = dc_crc_le(sc,
1229	LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1230	sp[h >> 4] \|= 1 << (h & 0xF);
1231	}
1232	#endif
1233
1234	if (ifp->if_flags & IFF_BROADCAST) {
1235	h = dc_crc_le(sc, (caddr_t)&etherbroadcastaddr);
1236	sp[h >> 4] \|= 1 << (h & 0xF);
1237	}
1238
1239	/* Set our MAC address */
1240	ac_enaddr = (u_int16_t *)sc->arpcom.ac_enaddr;
1241	sp[39] = ac_enaddr[0];
1242	sp[40] = ac_enaddr[1];
1243	sp[41] = ac_enaddr[2];
1244
1245	sframe->dc_status = DC_TXSTAT_OWN;
1246	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1247
1248	/*
1249	* The PNIC takes an exceedingly long time to process its
1250	* setup frame; wait 10ms after posting the setup frame
1251	* before proceeding, just so it has time to swallow its
1252	* medicine.
1253	*/
1254	DELAY(10000);
1255
1256	ifp->if_timer = 5;
1257
1258	return;
1259	}
1260
1261	void dc_setfilt_admtek(sc)
1262	struct dc_softc *sc;
1263	{
1264	struct ifnet *ifp;
1265	#if 0
1266	int h = 0;
1267	u_int32_t hashes[2] = { 0, 0 };
1268	struct ifmultiaddr *ifma;
1269	#endif
1270	u_int32_t *ac_enaddr;
1271
1272	ifp = &sc->arpcom.ac_if;
1273
1274	/* Init our MAC address */
1275	ac_enaddr = (u_int32_t *)&sc->arpcom.ac_enaddr[0];
1276	CSR_WRITE_4(sc, DC_AL_PAR0, *ac_enaddr);
1277	ac_enaddr = (u_int32_t *)&sc->arpcom.ac_enaddr[4];
1278	CSR_WRITE_4(sc, DC_AL_PAR1, *ac_enaddr);
1279
1280	/* If we want promiscuous mode, set the allframes bit. */
1281	if (ifp->if_flags & IFF_PROMISC)
1282	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1283	else
1284	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1285
1286	if (ifp->if_flags & IFF_ALLMULTI)
1287	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1288	else
1289	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1290
1291	/* first, zot all the existing hash bits */
1292	CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1293	CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1294
1295	#if 0
1296	/*
1297	* If we're already in promisc or allmulti mode, we
1298	* don't have to bother programming the multicast filter.
1299	*/
1300	if (ifp->if_flags & (IFF_PROMISC\|IFF_ALLMULTI))
1301	return;
1302
1303	/* now program new ones */
1304	for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1305	ifma = ifma->ifma_link.le_next) {
1306	if (ifma->ifma_addr->sa_family != AF_LINK)
1307	continue;
1308	h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1309	if (h < 32)
1310	hashes[0] \|= (1 << h);
1311	else
1312	hashes[1] \|= (1 << (h - 32));
1313	}
1314
1315	CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1316	CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1317	#endif
1318	return;
1319	}
1320
1321	void dc_setfilt_asix(sc)
1322	struct dc_softc *sc;
1323	{
1324	struct ifnet *ifp;
1325	#if 0
1326	int h = 0;
1327	u_int32_t hashes[2] = { 0, 0 };
1328	struct ifmultiaddr *ifma;
1329	#endif
1330	u_int32_t *ac_enaddr;
1331
1332	ifp = &sc->arpcom.ac_if;
1333
1334	/* Init our MAC address */
1335	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1336	ac_enaddr = (u_int32_t *)&sc->arpcom.ac_enaddr[0];
1337	CSR_WRITE_4(sc, DC_AX_FILTDATA, *ac_enaddr);
1338
1339	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1340
1341	ac_enaddr = (u_int32_t *)&sc->arpcom.ac_enaddr[4];
1342	CSR_WRITE_4(sc, DC_AX_FILTDATA, *ac_enaddr);
1343
1344	/* If we want promiscuous mode, set the allframes bit. */
1345	if (ifp->if_flags & IFF_PROMISC)
1346	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1347	else
1348	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1349
1350	if (ifp->if_flags & IFF_ALLMULTI)
1351	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1352	else
1353	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1354
1355	/*
1356	* The ASIX chip has a special bit to enable reception
1357	* of broadcast frames.
1358	*/
1359	if (ifp->if_flags & IFF_BROADCAST)
1360	DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1361	else
1362	DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1363
1364	/* first, zot all the existing hash bits */
1365	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1366	CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1367	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1368	CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1369
1370	#if 0
1371	/*
1372	* If we're already in promisc or allmulti mode, we
1373	* don't have to bother programming the multicast filter.
1374	*/
1375	if (ifp->if_flags & (IFF_PROMISC\|IFF_ALLMULTI))
1376	return;
1377
1378	/* now program new ones */
1379	for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1380	ifma = ifma->ifma_link.le_next) {
1381	if (ifma->ifma_addr->sa_family != AF_LINK)
1382	continue;
1383	h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1384	if (h < 32)
1385	hashes[0] \|= (1 << h);
1386	else
1387	hashes[1] \|= (1 << (h - 32));
1388	}
1389
1390	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1391	CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1392	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1393	CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1394	#endif
1395	return;
1396	}
1397
1398	static void dc_setfilt(sc)
1399	struct dc_softc *sc;
1400	{
1401	if (DC_IS_INTEL(sc) \|\| DC_IS_MACRONIX(sc) \|\| DC_IS_PNIC(sc) \|\|
1402	DC_IS_PNICII(sc) \|\| DC_IS_DAVICOM(sc) \|\| DC_IS_CONEXANT(sc))
1403	dc_setfilt_21143(sc);
1404
1405	if (DC_IS_ASIX(sc))
1406	dc_setfilt_asix(sc);
1407
1408	if (DC_IS_ADMTEK(sc))
1409	dc_setfilt_admtek(sc);
1410
1411	return;
1412	}
1413
1414	/*
1415	* In order to fiddle with the
1416	* 'full-duplex' and '100Mbps' bits in the netconfig register, we
1417	* first have to put the transmit and/or receive logic in the idle state.
1418	*/
1419	static void dc_setcfg(sc, media)
1420	struct dc_softc *sc;
1421	int media;
1422	{
1423	int i, restart = 0;
1424	u_int32_t isr;
1425
1426	if (IFM_SUBTYPE(media) == IFM_NONE)
1427	return;
1428
1429	if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON\|DC_NETCFG_RX_ON)) {
1430	restart = 1;
1431	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON\|DC_NETCFG_RX_ON));
1432
1433	for (i = 0; i < DC_TIMEOUT; i++) {
1434	isr = CSR_READ_4(sc, DC_ISR);
1435	if (isr & DC_ISR_TX_IDLE \|\|
1436	(isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED)
1437	break;
1438	DELAY(10);
1439	}
1440
1441	if (i == DC_TIMEOUT)
1442	printk("dc%d: failed to force tx and "
1443	"rx to idle state\n", sc->dc_unit);
1444	}
1445
1446	if (IFM_SUBTYPE(media) == IFM_100_TX) {
1447	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1448	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1449	if (sc->dc_pmode == DC_PMODE_MII) {
1450	int watchdogreg;
1451
1452	if (DC_IS_INTEL(sc)) {
1453	/* there's a write enable bit here that reads as 1 */
1454	watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1455	watchdogreg &= ~DC_WDOG_CTLWREN;
1456	watchdogreg \|= DC_WDOG_JABBERDIS;
1457	CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1458	} else {
1459	DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1460	}
1461	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS\|
1462	DC_NETCFG_PORTSEL\|DC_NETCFG_SCRAMBLER));
1463	if (sc->dc_type == DC_TYPE_98713)
1464	DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS\|
1465	DC_NETCFG_SCRAMBLER));
1466	if (!DC_IS_DAVICOM(sc))
1467	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1468	DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1469	if (DC_IS_INTEL(sc))
1470	dc_apply_fixup(sc, IFM_AUTO);
1471	} else {
1472	if (DC_IS_PNIC(sc)) {
1473	DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1474	DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1475	DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1476	}
1477	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1478	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1479	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1480	if (DC_IS_INTEL(sc))
1481	dc_apply_fixup(sc,
1482	(media & IFM_GMASK) == IFM_FDX ?
1483	IFM_100_TX\|IFM_FDX : IFM_100_TX);
1484	}
1485	}
1486
1487	if (IFM_SUBTYPE(media) == IFM_10_T) {
1488	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1489	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1490	if (sc->dc_pmode == DC_PMODE_MII) {
1491	int watchdogreg;
1492
1493	/* there's a write enable bit here that reads as 1 */
1494	if (DC_IS_INTEL(sc)) {
1495	watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1496	watchdogreg &= ~DC_WDOG_CTLWREN;
1497	watchdogreg \|= DC_WDOG_JABBERDIS;
1498	CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1499	} else {
1500	DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1501	}
1502	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS\|
1503	DC_NETCFG_PORTSEL\|DC_NETCFG_SCRAMBLER));
1504	if (sc->dc_type == DC_TYPE_98713)
1505	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1506	if (!DC_IS_DAVICOM(sc))
1507	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1508	DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1509	if (DC_IS_INTEL(sc))
1510	dc_apply_fixup(sc, IFM_AUTO);
1511	} else {
1512	if (DC_IS_PNIC(sc)) {
1513	DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1514	DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1515	DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1516	}
1517	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1518	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1519	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1520	if (DC_IS_INTEL(sc)) {
1521	DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1522	DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1523	if ((media & IFM_GMASK) == IFM_FDX)
1524	DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1525	else
1526	DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1527	DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1528	DC_CLRBIT(sc, DC_10BTCTRL,
1529	DC_TCTL_AUTONEGENBL);
1530	dc_apply_fixup(sc,
1531	(media & IFM_GMASK) == IFM_FDX ?
1532	IFM_10_T\|IFM_FDX : IFM_10_T);
1533	DELAY(20000);
1534	}
1535	}
1536	}
1537
1538	#if 0
1539	/*
1540	* If this is a Davicom DM9102A card with a DM9801 HomePNA
1541	* PHY and we want HomePNA mode, set the portsel bit to turn
1542	* on the external MII port.
1543	*/
1544	if (DC_IS_DAVICOM(sc)) {
1545	if (IFM_SUBTYPE(media) == IFM_homePNA) {
1546	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1547	sc->dc_link = 1;
1548	} else {
1549	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1550	}
1551	}
1552	#endif
1553
1554	if ((media & IFM_GMASK) == IFM_FDX) {
1555	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1556	if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1557	DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1558	} else {
1559	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1560	if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1561	DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1562	}
1563
1564	if (restart)
1565	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON\|DC_NETCFG_RX_ON);
1566
1567	return;
1568	}
1569
1570	static void dc_reset(sc)
1571	struct dc_softc *sc;
1572	{
1573	register int i;
1574
1575	DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1576
1577	for (i = 0; i < DC_TIMEOUT; i++) {
1578	DELAY(10);
1579	if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1580	break;
1581	}
1582
1583	if (DC_IS_ASIX(sc) \|\| DC_IS_ADMTEK(sc) \|\| DC_IS_CONEXANT(sc)) {
1584	DELAY(10000);
1585	DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1586	i = 0;
1587	}
1588
1589	if (i == DC_TIMEOUT)
1590	printk("dc%d: reset never completed!\n", sc->dc_unit);
1591
1592	/* Wait a little while for the chip to get its brains in order. */
1593	DELAY(1000);
1594
1595	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1596	CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1597	CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1598
1599	/*
1600	* Bring the SIA out of reset. In some cases, it looks
1601	* like failing to unreset the SIA soon enough gets it
1602	* into a state where it will never come out of reset
1603	* until we reset the whole chip again.
1604	*/
1605	if (DC_IS_INTEL(sc)) {
1606	DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1607	CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1608	CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1609	}
1610
1611	return;
1612	}
1613
1614	static
1615	struct dc_type *dc_devtype( int unitnum )
1616	{
1617	struct dc_type *t;
1618	uint32_t rev;
1619	int rc;
1620
1621
1622	t = dc_devs;
1623
1624	while(t->dc_name != NULL) {
1625	rc = pci_find_device(t->dc_vid, t->dc_did, \
1626	(unitnum - 1), &t->dc_bus, &t->dc_dev, &t->dc_fun);
1627	if (rc == PCIB_ERR_SUCCESS) {
1628	/* Check the PCI revision */
1629	/pcib_conf_read32(t->dc_devsig, DC_PCI_CFRV, &rev); /
1630	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
1631	DC_PCI_CFRV, &rev);
1632	rev &= 0xFF;
1633
1634	if (t->dc_did == DC_DEVICEID_98713 &&
1635	rev >= DC_REVISION_98713A)
1636	t++;
1637	if (t->dc_did == DC_DEVICEID_98713_CP &&
1638	rev >= DC_REVISION_98713A)
1639	t++;
1640	if (t->dc_did == DC_DEVICEID_987x5 &&
1641	rev >= DC_REVISION_98715AEC_C)
1642	t++;
1643	if (t->dc_did == DC_DEVICEID_987x5 &&
1644	rev >= DC_REVISION_98725)
1645	t++;
1646	if (t->dc_did == DC_DEVICEID_AX88140A &&
1647	rev >= DC_REVISION_88141)
1648	t++;
1649	if (t->dc_did == DC_DEVICEID_82C168 &&
1650	rev >= DC_REVISION_82C169)
1651	t++;
1652	if (t->dc_did == DC_DEVICEID_DM9102 &&
1653	rev >= DC_REVISION_DM9102A)
1654	t++;
1655	return(t);
1656	}
1657	t++;
1658	}
1659
1660	return(NULL);
1661	}
1662
1663	#if 0
1664	/*
1665	* Probe for a 21143 or clone chip. Check the PCI vendor and device
1666	* IDs against our list and return a device name if we find a match.
1667	* We do a little bit of extra work to identify the exact type of
1668	* chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1669	* but different revision IDs. The same is true for 98715/98715A
1670	* chips and the 98725, as well as the ASIX and ADMtek chips. In some
1671	* cases, the exact chip revision affects driver behavior.
1672	*/
1673	static int dc_probe(dev)
1674	device_t dev;
1675	{
1676	struct dc_type *t;
1677
1678	t = dc_devtype(dev);
1679
1680	if (t != NULL) {
1681	device_set_desc(dev, t->dc_name);
1682	return(0);
1683	}
1684
1685	return(ENXIO);
1686	}
1687
1688
1689	static void dc_acpi(dev)
1690	device_t dev;
1691	{
1692	u_int32_t r, cptr;
1693	int unit;
1694
1695	unit = device_get_unit(dev);
1696
1697	/* Find the location of the capabilities block */
1698	cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF;
1699
1700	r = pci_read_config(dev, cptr, 4) & 0xFF;
1701	if (r == 0x01) {
1702
1703	r = pci_read_config(dev, cptr + 4, 4);
1704	if (r & DC_PSTATE_D3) {
1705	u_int32_t iobase, membase, irq;
1706
1707	/* Save important PCI config data. */
1708	iobase = pci_read_config(dev, DC_PCI_CFBIO, 4);
1709	membase = pci_read_config(dev, DC_PCI_CFBMA, 4);
1710	irq = pci_read_config(dev, DC_PCI_CFIT, 4);
1711
1712	/* Reset the power state. */
1713	printk("dc%d: chip is in D%d power mode "
1714	"-- setting to D0\n", unit, r & DC_PSTATE_D3);
1715	r &= 0xFFFFFFFC;
1716	pci_write_config(dev, cptr + 4, r, 4);
1717
1718	/* Restore PCI config data. */
1719	pci_write_config(dev, DC_PCI_CFBIO, iobase, 4);
1720	pci_write_config(dev, DC_PCI_CFBMA, membase, 4);
1721	pci_write_config(dev, DC_PCI_CFIT, irq, 4);
1722	}
1723	}
1724	return;
1725	}
1726	#endif
1727
1728
1729	static void dc_apply_fixup(sc, media)
1730	struct dc_softc *sc;
1731	int media;
1732	{
1733	struct dc_mediainfo *m;
1734	u_int8_t *p;
1735	int i;
1736	u_int32_t reg;
1737
1738	m = sc->dc_mi;
1739
1740	while (m != NULL) {
1741	if (m->dc_media == media)
1742	break;
1743	m = m->dc_next;
1744	}
1745
1746	if (m == NULL)
1747	return;
1748
1749	for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1750	reg = (p[0] \| (p[1] << 8)) << 16;
1751	CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1752	}
1753
1754	for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1755	reg = (p[0] \| (p[1] << 8)) << 16;
1756	CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1757	}
1758
1759	return;
1760	}
1761
1762	#if 0
1763	static void dc_decode_leaf_sia(sc, l)
1764	struct dc_softc *sc;
1765	struct dc_eblock_sia *l;
1766	{
1767	struct dc_mediainfo *m;
1768
1769	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1770	bzero(m, sizeof(struct dc_mediainfo));
1771	if (l->dc_sia_code == DC_SIA_CODE_10BT)
1772	m->dc_media = IFM_10_T;
1773
1774	if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX)
1775	m->dc_media = IFM_10_T\|IFM_FDX;
1776
1777	if (l->dc_sia_code == DC_SIA_CODE_10B2)
1778	m->dc_media = IFM_10_2;
1779
1780	if (l->dc_sia_code == DC_SIA_CODE_10B5)
1781	m->dc_media = IFM_10_5;
1782
1783	m->dc_gp_len = 2;
1784	m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl;
1785
1786	m->dc_next = sc->dc_mi;
1787	sc->dc_mi = m;
1788
1789	sc->dc_pmode = DC_PMODE_SIA;
1790
1791	return;
1792	}
1793
1794	static void dc_decode_leaf_sym(sc, l)
1795	struct dc_softc *sc;
1796	struct dc_eblock_sym *l;
1797	{
1798	struct dc_mediainfo *m;
1799
1800	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1801	bzero(m, sizeof(struct dc_mediainfo));
1802	if (l->dc_sym_code == DC_SYM_CODE_100BT)
1803	m->dc_media = IFM_100_TX;
1804
1805	if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1806	m->dc_media = IFM_100_TX\|IFM_FDX;
1807
1808	m->dc_gp_len = 2;
1809	m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
1810
1811	m->dc_next = sc->dc_mi;
1812	sc->dc_mi = m;
1813
1814	sc->dc_pmode = DC_PMODE_SYM;
1815
1816	return;
1817	}
1818
1819	static void dc_decode_leaf_mii(sc, l)
1820	struct dc_softc *sc;
1821	struct dc_eblock_mii *l;
1822	{
1823	u_int8_t *p;
1824	struct dc_mediainfo *m;
1825
1826	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1827	bzero(m, sizeof(struct dc_mediainfo));
1828	/* We abuse IFM_AUTO to represent MII. */
1829	m->dc_media = IFM_AUTO;
1830	m->dc_gp_len = l->dc_gpr_len;
1831
1832	p = (u_int8_t *)l;
1833	p += sizeof(struct dc_eblock_mii);
1834	m->dc_gp_ptr = p;
1835	p += 2 * l->dc_gpr_len;
1836	m->dc_reset_len = *p;
1837	p++;
1838	m->dc_reset_ptr = p;
1839
1840	m->dc_next = sc->dc_mi;
1841	sc->dc_mi = m;
1842
1843	return;
1844	}
1845	#endif
1846
1847	static void dc_read_srom(sc, bits)
1848	struct dc_softc *sc;
1849	int bits;
1850	{
1851	int size;
1852
1853	size = 2 << bits;
1854	sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT);
1855	dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1856	}
1857
1858	static void dc_parse_21143_srom(sc)
1859	struct dc_softc *sc;
1860	{
1861	struct dc_leaf_hdr *lhdr;
1862	struct dc_eblock_hdr *hdr;
1863	int i, loff;
1864	char *ptr;
1865
1866	loff = sc->dc_srom[27];
1867	lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1868
1869	ptr = (char *)lhdr;
1870	ptr += sizeof(struct dc_leaf_hdr) - 1;
1871	for (i = 0; i < lhdr->dc_mcnt; i++) {
1872	hdr = (struct dc_eblock_hdr *)ptr;
1873	switch(hdr->dc_type) {
1874	#if 0
1875	case DC_EBLOCK_MII:
1876	dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1877	break;
1878	case DC_EBLOCK_SIA:
1879	dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr);
1880	break;
1881	case DC_EBLOCK_SYM:
1882	dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr);
1883	break;
1884	#endif
1885	default:
1886	/* Don't care. Yet. */
1887	break;
1888	}
1889	ptr += (hdr->dc_len & 0x7F);
1890	ptr++;
1891	}
1892
1893	return;
1894	}
1895
1896
1897	static void
1898	nop(const rtems_irq_connect_data* unused)
1899	{
1900	}
1901
1902	static int
1903	decISON(const rtems_irq_connect_data* irq)
1904	{
1905	return (BSP_irq_enabled_at_i8259s(irq->name));
1906	}
1907
1908
1909	/*
1910	* Attach the interface. Allocate softc structures, do ifmedia
1911	* setup and ethernet/BPF attach.
1912	*/
1913	int
1914	rtems_dc_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching)
1915	{
1916	int rc;
1917	u_char eaddr[ETHER_ADDR_LEN];
1918
1919	char *unitName;
1920	int unitNumber;
1921
1922	uint32_t command;
1923	struct dc_softc *sc;
1924	struct ifnet *ifp;
1925	struct dc_type *t;
1926	uint32_t revision;
1927	int error = 0, mac_offset;
1928	uint32_t value;
1929
1930	/*
1931	* Get the instance number for the board we're going to configure
1932	* from the user.
1933	*/
1934	unitNumber = rtems_bsdnet_parse_driver_name(config, &unitName);
1935	if( unitNumber < 0) {
1936	return 0;
1937	}
1938	if( strcmp(unitName, DRIVER_PREFIX) ) {
1939	printk("dec2114x : unit name '%s' not %s\n", \
1940	unitName, DRIVER_PREFIX );
1941	return 0;
1942	}
1943
1944	sc = &dc_softc_devs[unitNumber - 1];
1945	ifp = &sc->arpcom.ac_if;
1946
1947	if(ifp->if_softc != NULL) {
1948	printk("dec2114x[%d]: unit number already in use.\n", \
1949	unitNumber);
1950	return (0);
1951	}
1952	memset(sc, 0, sizeof(struct dc_softc));
1953
1954	/unit = device_get_unit(dev);/
1955	sc->dc_unit = unitNumber;
1956	sc->dc_name = unitName;
1957
1958	/*
1959	* Handle power management nonsense.
1960	*
1961	dc_acpi(dev);
1962	*/
1963
1964	/* Scan for dec2114x cards in pci config space */
1965	if( (sc->dc_info = dc_devtype(unitNumber)) == NULL) {
1966	printk("Can't find any dec2114x NICs in PCI space.\n");
1967	return 0;
1968	}
1969	t = sc->dc_info;
1970
1971
1972	/*
1973	* Map control/status registers.
1974	*/
1975	/sig = sc->dc_info->dc_devsig; /
1976	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
1977	PCI_COMMAND, &command);
1978	/pcib_conf_read32(sig, PCI_COMMAND, &command); /
1979	command \|= (PCI_COMMAND_IO \| PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
1980	pci_write_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
1981	PCI_COMMAND, command);
1982	/pcib_conf_write32(sig, PCI_COMMAND, command); /
1983	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
1984	PCI_COMMAND, &command);
1985	/pcib_conf_read32(sig, PCI_COMMAND, &command); /
1986
1987	#ifdef DC_USEIOSPACE
1988	if (!(command & PCI_COMMAND_IO)) {
1989	printk("dc%d: failed to enable I/O ports!\n", sc->dc_unit);
1990	error = ENXIO;
1991	goto fail;
1992	}
1993	#else
1994	if (!(command & PCI_COMMAND_MEMORY)) {
1995	printk("dc%d: failed to enable memory mapping!\n", sc->dc_unit);
1996	error = ENXIO;
1997	goto fail;
1998	}
1999	#endif
2000
2001	#if 0
2002	rid = DC_RID;
2003	sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid,
2004	0, ~0, 1, RF_ACTIVE);
2005
2006	if (sc->dc_res == NULL) {
2007	printk("dc%d: couldn't map ports/memory\n", unit);
2008	error = ENXIO;
2009	goto fail;
2010	}
2011	sc->dc_btag = rman_get_bustag(sc->dc_res);
2012	sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
2013	#endif
2014
2015	/* sc->membase is the address of the card's CSRs !!! */
2016	/pcib_conf_read32(sig, DC_PCI_CFBMA, &value); /
2017	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2018	DC_PCI_CFBMA, &value);
2019	sc->membase = value;
2020
2021	/* Allocate interrupt */
2022	memset(&sc->irqInfo, 0, sizeof(rtems_irq_connect_data));
2023	/pcib_conf_read32(sig, DC_PCI_CFIT, &value); /
2024	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2025	DC_PCI_CFIT, &value);
2026
2027	sc->irqInfo.name = value & 0xFF;
2028	sc->irqInfo.hdl = (rtems_irq_hdl)dc_intr;
2029	sc->irqInfo.handle = (void )sc; / new parameter */
2030	sc->irqInfo.on = nop;
2031	sc->irqInfo.off = nop;
2032	sc->irqInfo.isOn = decISON;
2033
2034	#ifdef BSP_SHARED_HANDLER_SUPPORT
2035	rc = BSP_install_rtems_shared_irq_handler( &sc->irqInfo );
2036	#else
2037	rc = BSP_install_rtems_irq_handler( &sc->irqInfo );
2038	#endif
2039	if(!rc) {
2040	rtems_panic("Can't install dec2114x irq handler.\n");
2041	}
2042
2043
2044	#if 0
2045	rid = 0;
2046	sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
2047	RF_SHAREABLE \| RF_ACTIVE);
2048
2049	if (sc->dc_irq == NULL) {
2050	printk("dc%d: couldn't map interrupt\n", unit);
2051	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2052	error = ENXIO;
2053	goto fail;
2054	}
2055
2056	error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET,
2057	dc_intr, sc, &sc->dc_intrhand);
2058
2059	if (error) {
2060	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2061	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2062	printk("dc%d: couldn't set up irq\n", unit);
2063	goto fail;
2064	}
2065	#endif
2066
2067
2068	/* Need this info to decide on a chip type.
2069	sc->dc_info = dc_devtype(dev);
2070	*/
2071	/pcib_conf_read32(sig, DC_PCI_CFRV, &revision); /
2072	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2073	DC_PCI_CFRV, &revision);
2074	revision &= 0x000000FF;
2075
2076	/* Get the eeprom width, but PNIC has diff eeprom */
2077	if (sc->dc_info->dc_did != DC_DEVICEID_82C168)
2078	dc_eeprom_width(sc);
2079
2080	switch(sc->dc_info->dc_did) {
2081	case DC_DEVICEID_21143:
2082	sc->dc_type = DC_TYPE_21143;
2083	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR;
2084	sc->dc_flags \|= DC_REDUCED_MII_POLL;
2085	/* Save EEPROM contents so we can parse them later. */
2086	dc_read_srom(sc, sc->dc_romwidth);
2087	break;
2088	case DC_DEVICEID_DM9009:
2089	case DC_DEVICEID_DM9100:
2090	case DC_DEVICEID_DM9102:
2091	sc->dc_type = DC_TYPE_DM9102;
2092	sc->dc_flags \|= DC_TX_COALESCE\|DC_TX_INTR_ALWAYS;
2093	sc->dc_flags \|= DC_REDUCED_MII_POLL\|DC_TX_STORENFWD;
2094	sc->dc_pmode = DC_PMODE_MII;
2095	/* Increase the latency timer value. */
2096	/pcib_conf_read32(sig, DC_PCI_CFLT, &command); /
2097	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2098	DC_PCI_CFLT, &command);
2099	command &= 0xFFFF00FF;
2100	command \|= 0x00008000;
2101	/pcib_conf_write32(sig, DC_PCI_CFLT, command); /
2102	pci_write_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2103	DC_PCI_CFLT, command);
2104	break;
2105	case DC_DEVICEID_AL981:
2106	sc->dc_type = DC_TYPE_AL981;
2107	sc->dc_flags \|= DC_TX_USE_TX_INTR;
2108	sc->dc_flags \|= DC_TX_ADMTEK_WAR;
2109	sc->dc_pmode = DC_PMODE_MII;
2110	dc_read_srom(sc, sc->dc_romwidth);
2111	break;
2112	case DC_DEVICEID_AN985:
2113	case DC_DEVICEID_EN2242:
2114	sc->dc_type = DC_TYPE_AN985;
2115	sc->dc_flags \|= DC_TX_USE_TX_INTR;
2116	sc->dc_flags \|= DC_TX_ADMTEK_WAR;
2117	sc->dc_pmode = DC_PMODE_MII;
2118	dc_read_srom(sc, sc->dc_romwidth);
2119	break;
2120	case DC_DEVICEID_98713:
2121	case DC_DEVICEID_98713_CP:
2122	if (revision < DC_REVISION_98713A) {
2123	sc->dc_type = DC_TYPE_98713;
2124	}
2125	if (revision >= DC_REVISION_98713A) {
2126	sc->dc_type = DC_TYPE_98713A;
2127	sc->dc_flags \|= DC_21143_NWAY;
2128	}
2129	sc->dc_flags \|= DC_REDUCED_MII_POLL;
2130	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR;
2131	break;
2132	case DC_DEVICEID_987x5:
2133	case DC_DEVICEID_EN1217:
2134	/*
2135	* Macronix MX98715AEC-C/D/E parts have only a
2136	* 128-bit hash table. We need to deal with these
2137	* in the same manner as the PNIC II so that we
2138	* get the right number of bits out of the
2139	* CRC routine.
2140	*/
2141	if (revision >= DC_REVISION_98715AEC_C &&
2142	revision < DC_REVISION_98725)
2143	sc->dc_flags \|= DC_128BIT_HASH;
2144	sc->dc_type = DC_TYPE_987x5;
2145	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR;
2146	sc->dc_flags \|= DC_REDUCED_MII_POLL\|DC_21143_NWAY;
2147	break;
2148	case DC_DEVICEID_98727:
2149	sc->dc_type = DC_TYPE_987x5;
2150	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR;
2151	sc->dc_flags \|= DC_REDUCED_MII_POLL\|DC_21143_NWAY;
2152	break;
2153	case DC_DEVICEID_82C115:
2154	sc->dc_type = DC_TYPE_PNICII;
2155	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR\|DC_128BIT_HASH;
2156	sc->dc_flags \|= DC_REDUCED_MII_POLL\|DC_21143_NWAY;
2157	break;
2158	case DC_DEVICEID_82C168:
2159	sc->dc_type = DC_TYPE_PNIC;
2160	sc->dc_flags \|= DC_TX_STORENFWD\|DC_TX_INTR_ALWAYS;
2161	sc->dc_flags \|= DC_PNIC_RX_BUG_WAR;
2162	sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT);
2163	if (revision < DC_REVISION_82C169)
2164	sc->dc_pmode = DC_PMODE_SYM;
2165	break;
2166	case DC_DEVICEID_AX88140A:
2167	sc->dc_type = DC_TYPE_ASIX;
2168	sc->dc_flags \|= DC_TX_USE_TX_INTR\|DC_TX_INTR_FIRSTFRAG;
2169	sc->dc_flags \|= DC_REDUCED_MII_POLL;
2170	sc->dc_pmode = DC_PMODE_MII;
2171	break;
2172	case DC_DEVICEID_RS7112:
2173	sc->dc_type = DC_TYPE_CONEXANT;
2174	sc->dc_flags \|= DC_TX_INTR_ALWAYS;
2175	sc->dc_flags \|= DC_REDUCED_MII_POLL;
2176	sc->dc_pmode = DC_PMODE_MII;
2177	dc_read_srom(sc, sc->dc_romwidth);
2178	break;
2179	default:
2180	printk("dc%d: unknown device: %x\n", sc->dc_unit,
2181	sc->dc_info->dc_did);
2182	break;
2183	}
2184
2185	/* Save the cache line size. */
2186	if (DC_IS_DAVICOM(sc)) {
2187	sc->dc_cachesize = 0;
2188	}
2189	else {
2190	/pcib_conf_read32(sig, DC_PCI_CFLT, &value); /
2191	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2192	DC_PCI_CFLT, &value);
2193	sc->dc_cachesize = (u_int8_t)(value & 0xFF);
2194	}
2195
2196	/* Reset the adapter. */
2197	dc_reset(sc);
2198
2199	/* Take 21143 out of snooze mode */
2200	if (DC_IS_INTEL(sc)) {
2201	/pcib_conf_read32(sig, DC_PCI_CFDD, &command); /
2202	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2203	DC_PCI_CFDD, &command);
2204	command &= ~(DC_CFDD_SNOOZE_MODE\|DC_CFDD_SLEEP_MODE);
2205	/pcib_conf_write32(sig, DC_PCI_CFDD, command); /
2206	pci_write_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2207	DC_PCI_CFDD, command);
2208	}
2209
2210
2211	/*
2212	* Try to learn something about the supported media.
2213	* We know that ASIX and ADMtek and Davicom devices
2214	* will always be using MII media, so that's a no-brainer.
2215	* The tricky ones are the Macronix/PNIC II and the
2216	* Intel 21143.
2217	*/
2218	if (DC_IS_INTEL(sc))
2219	dc_parse_21143_srom(sc);
2220	else if (DC_IS_MACRONIX(sc) \|\| DC_IS_PNICII(sc)) {
2221	if (sc->dc_type == DC_TYPE_98713)
2222	sc->dc_pmode = DC_PMODE_MII;
2223	else
2224	sc->dc_pmode = DC_PMODE_SYM;
2225	} else if (!sc->dc_pmode)
2226	sc->dc_pmode = DC_PMODE_MII;
2227
2228	/*
2229	* Get station address from the EEPROM.
2230	*/
2231	switch(sc->dc_type) {
2232	case DC_TYPE_98713:
2233	case DC_TYPE_98713A:
2234	case DC_TYPE_987x5:
2235	case DC_TYPE_PNICII:
2236	dc_read_eeprom(sc, (caddr_t)&mac_offset,
2237	(DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2238	dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2239	break;
2240	case DC_TYPE_PNIC:
2241	dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2242	break;
2243	case DC_TYPE_DM9102:
2244	case DC_TYPE_21143:
2245	case DC_TYPE_ASIX:
2246	dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2247	break;
2248	case DC_TYPE_AL981:
2249	case DC_TYPE_AN985:
2250	bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr,
2251	ETHER_ADDR_LEN);
2252	dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0);
2253	break;
2254	case DC_TYPE_CONEXANT:
2255	bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6);
2256	break;
2257	default:
2258	dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2259	break;
2260	}
2261
2262	/*
2263	* A 21143 or clone chip was detected. Inform the world.
2264	*/
2265	bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
2266	printk("dc%d: MAC address -- %02x:%02x:%02x:%02x:%02x:%02x\n", \
2267	sc->dc_unit,sc->arpcom.ac_enaddr[0], \
2268	sc->arpcom.ac_enaddr[1], sc->arpcom.ac_enaddr[2], \
2269	sc->arpcom.ac_enaddr[3], sc->arpcom.ac_enaddr[4], \
2270	sc->arpcom.ac_enaddr[5]);
2271
2272
2273	sc->dc_ldata = malloc(sizeof(struct dc_list_data), M_DEVBUF, M_NOWAIT);
2274
2275	if (sc->dc_ldata == NULL) {
2276	printk("dc%d: no memory for list buffers!\n", sc->dc_unit);
2277	if (sc->dc_pnic_rx_buf != NULL)
2278	free(sc->dc_pnic_rx_buf, M_DEVBUF);
2279	#if 0
2280	bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2281	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2282	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2283	#endif
2284	error = ENXIO;
2285	goto fail;
2286	}
2287
2288	bzero(sc->dc_ldata, sizeof(struct dc_list_data));
2289
2290	ifp = &sc->arpcom.ac_if;
2291	ifp->if_softc = sc;
2292	ifp->if_unit = unitNumber; /sc->dc_unit;/
2293	ifp->if_name = unitName; /sc->dc_name;/
2294	ifp->if_mtu = ETHERMTU;
2295	ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX; /* \| IFF_MULTICAST;*/
2296	ifp->if_ioctl = dc_ioctl;
2297	ifp->if_output = ether_output;
2298	ifp->if_start = dc_start;
2299	ifp->if_watchdog = dc_watchdog;
2300	ifp->if_init = dc_init;
2301	ifp->if_baudrate = 100000000;
2302	ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1;
2303
2304	#if 0
2305	/*
2306	* Do MII setup. If this is a 21143, check for a PHY on the
2307	* MII bus after applying any necessary fixups to twiddle the
2308	* GPIO bits. If we don't end up finding a PHY, restore the
2309	* old selection (SIA only or SIA/SYM) and attach the dcphy
2310	* driver instead.
2311	*/
2312	if (DC_IS_INTEL(sc)) {
2313	dc_apply_fixup(sc, IFM_AUTO);
2314	tmp = sc->dc_pmode;
2315	sc->dc_pmode = DC_PMODE_MII;
2316	}
2317
2318	error = mii_phy_probe(dev, &sc->dc_miibus,
2319	dc_ifmedia_upd, dc_ifmedia_sts);
2320
2321	if (error && DC_IS_INTEL(sc)) {
2322	sc->dc_pmode = tmp;
2323	if (sc->dc_pmode != DC_PMODE_SIA)
2324	sc->dc_pmode = DC_PMODE_SYM;
2325	sc->dc_flags \|= DC_21143_NWAY;
2326	mii_phy_probe(dev, &sc->dc_miibus,
2327	dc_ifmedia_upd, dc_ifmedia_sts);
2328	/*
2329	* For non-MII cards, we need to have the 21143
2330	* drive the LEDs. Except there are some systems
2331	* like the NEC VersaPro NoteBook PC which have no
2332	* LEDs, and twiddling these bits has adverse effects
2333	* on them. (I.e. you suddenly can't get a link.)
2334	*/
2335	if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033)
2336	sc->dc_flags \|= DC_TULIP_LEDS;
2337	error = 0;
2338	}
2339
2340	if (error) {
2341	printk("dc%d: MII without any PHY!\n", sc->dc_unit);
2342	contigfree(sc->dc_ldata, sizeof(struct dc_list_data),
2343	M_DEVBUF);
2344	if (sc->dc_pnic_rx_buf != NULL)
2345	free(sc->dc_pnic_rx_buf, M_DEVBUF);
2346	bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2347	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2348	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2349	error = ENXIO;
2350	goto fail;
2351	}
2352	#endif
2353
2354	/*
2355	* Call MI attach routine.
2356	*/
2357	if_attach(ifp);
2358	ether_ifattach(ifp);
2359	/callout_handle_init(&sc->dc_stat_ch);/
2360
2361	if (DC_IS_ADMTEK(sc)) {
2362	/*
2363	* Set automatic TX underrun recovery for the ADMtek chips
2364	*/
2365	DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2366	}
2367
2368	if(sc->daemontid == 0) {
2369	sc->daemontid = rtems_bsdnet_newproc("decD",4096, \
2370	dc_daemon,(void *)sc);
2371	printk("dec[%d]: daemon process started\n", sc->dc_unit);
2372	}
2373
2374	/*
2375	* Tell the upper layer(s) we support long frames.
2376	*
2377	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2378	*/
2379
2380	#ifdef SRM_MEDIA /* only defined if __alpha__ is defined... */
2381	sc->dc_srm_media = 0;
2382
2383	/* Remember the SRM console media setting */
2384	if (DC_IS_INTEL(sc)) {
2385	command = pci_read_config(dev, DC_PCI_CFDD, 4);
2386	command &= ~(DC_CFDD_SNOOZE_MODE\|DC_CFDD_SLEEP_MODE);
2387	switch ((command >> 8) & 0xff) {
2388	case 3:
2389	sc->dc_srm_media = IFM_10_T;
2390	break;
2391	case 4:
2392	sc->dc_srm_media = IFM_10_T \| IFM_FDX;
2393	break;
2394	case 5:
2395	sc->dc_srm_media = IFM_100_TX;
2396	break;
2397	case 6:
2398	sc->dc_srm_media = IFM_100_TX \| IFM_FDX;
2399	break;
2400	}
2401	if (sc->dc_srm_media)
2402	sc->dc_srm_media \|= IFM_ACTIVE \| IFM_ETHER;
2403	}
2404	#endif
2405
2406
2407	fail:
2408
2409	return (1); /(error);/
2410	}
2411
2412	#if 0
2413	static int dc_detach(dev)
2414	device_t dev;
2415	{
2416	struct dc_softc *sc;
2417	struct ifnet *ifp;
2418	int s;
2419	struct dc_mediainfo *m;
2420
2421
2422	sc = device_get_softc(dev);
2423	ifp = &sc->arpcom.ac_if;
2424
2425	dc_stop(sc);
2426	ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
2427
2428	bus_generic_detach(dev);
2429	device_delete_child(dev, sc->dc_miibus);
2430
2431	bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2432	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2433	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2434
2435	contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF);
2436	if (sc->dc_pnic_rx_buf != NULL)
2437	free(sc->dc_pnic_rx_buf, M_DEVBUF);
2438
2439	while(sc->dc_mi != NULL) {
2440	m = sc->dc_mi->dc_next;
2441	free(sc->dc_mi, M_DEVBUF);
2442	sc->dc_mi = m;
2443	}
2444	free(sc->dc_srom, M_DEVBUF);
2445
2446
2447	return(0);
2448	}
2449	#endif
2450
2451
2452	/*
2453	* Initialize the transmit descriptors.
2454	*/
2455	static int dc_list_tx_init(sc)
2456	struct dc_softc *sc;
2457	{
2458	struct dc_chain_data *cd;
2459	struct dc_list_data *ld;
2460	int i;
2461
2462	cd = &sc->dc_cdata;
2463	ld = sc->dc_ldata;
2464	for (i = 0; i < DC_TX_LIST_CNT; i++) {
2465	if (i == (DC_TX_LIST_CNT - 1)) {
2466	ld->dc_tx_list[i].dc_next =
2467	vtophys(&ld->dc_tx_list[0]);
2468	} else {
2469	ld->dc_tx_list[i].dc_next =
2470	vtophys(&ld->dc_tx_list[i + 1]);
2471	}
2472	cd->dc_tx_chain[i] = NULL;
2473	ld->dc_tx_list[i].dc_data = 0;
2474	ld->dc_tx_list[i].dc_ctl = 0;
2475	}
2476
2477	cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2478
2479	return(0);
2480	}
2481
2482
2483	/*
2484	* Initialize the RX descriptors and allocate mbufs for them. Note that
2485	* we arrange the descriptors in a closed ring, so that the last descriptor
2486	* points back to the first.
2487	*/
2488	static int dc_list_rx_init(sc)
2489	struct dc_softc *sc;
2490	{
2491	struct dc_chain_data *cd;
2492	struct dc_list_data *ld;
2493	int i;
2494
2495	cd = &sc->dc_cdata;
2496	ld = sc->dc_ldata;
2497
2498	for (i = 0; i < DC_RX_LIST_CNT; i++) {
2499	if (dc_newbuf(sc, i, NULL) == ENOBUFS)
2500	return(ENOBUFS);
2501	if (i == (DC_RX_LIST_CNT - 1)) {
2502	ld->dc_rx_list[i].dc_next =
2503	vtophys(&ld->dc_rx_list[0]);
2504	} else {
2505	ld->dc_rx_list[i].dc_next =
2506	vtophys(&ld->dc_rx_list[i + 1]);
2507	}
2508	}
2509
2510	cd->dc_rx_prod = 0;
2511
2512	return(0);
2513	}
2514
2515	/*
2516	* Initialize an RX descriptor and attach an MBUF cluster.
2517	*/
2518	static int dc_newbuf(sc, i, m)
2519	struct dc_softc *sc;
2520	int i;
2521	struct mbuf *m;
2522	{
2523	struct mbuf *m_new = NULL;
2524	struct dc_desc *c;
2525
2526	c = &sc->dc_ldata->dc_rx_list[i];
2527
2528	if (m == NULL) {
2529	MGETHDR(m_new, M_DONTWAIT, MT_DATA);
2530	if (m_new == NULL)
2531	return(ENOBUFS);
2532
2533	MCLGET(m_new, M_DONTWAIT);
2534	if (!(m_new->m_flags & M_EXT)) {
2535	m_freem(m_new);
2536	return(ENOBUFS);
2537	}
2538	m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2539	} else {
2540	m_new = m;
2541	m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2542	m_new->m_data = m_new->m_ext.ext_buf;
2543	}
2544
2545	m_adj(m_new, sizeof(u_int64_t));
2546
2547	/*
2548	* If this is a PNIC chip, zero the buffer. This is part
2549	* of the workaround for the receive bug in the 82c168 and
2550	* 82c169 chips.
2551	*/
2552	if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2553	bzero((char )mtod(m_new, char ), m_new->m_len);
2554
2555	sc->dc_cdata.dc_rx_chain[i] = m_new;
2556	c->dc_data = vtophys(mtod(m_new, caddr_t));
2557	c->dc_ctl = DC_RXCTL_RLINK \| DC_RXLEN;
2558	c->dc_status = DC_RXSTAT_OWN;
2559
2560	return(0);
2561	}
2562
2563	/*
2564	* Grrrrr.
2565	* The PNIC chip has a terrible bug in it that manifests itself during
2566	* periods of heavy activity. The exact mode of failure if difficult to
2567	* pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2568	* will happen on slow machines. The bug is that sometimes instead of
2569	* uploading one complete frame during reception, it uploads what looks
2570	* like the entire contents of its FIFO memory. The frame we want is at
2571	* the end of the whole mess, but we never know exactly how much data has
2572	* been uploaded, so salvaging the frame is hard.
2573	*
2574	* There is only one way to do it reliably, and it's disgusting.
2575	* Here's what we know:
2576	*
2577	* - We know there will always be somewhere between one and three extra
2578	* descriptors uploaded.
2579	*
2580	* - We know the desired received frame will always be at the end of the
2581	* total data upload.
2582	*
2583	* - We know the size of the desired received frame because it will be
2584	* provided in the length field of the status word in the last descriptor.
2585	*
2586	* Here's what we do:
2587	*
2588	* - When we allocate buffers for the receive ring, we bzero() them.
2589	* This means that we know that the buffer contents should be all
2590	* zeros, except for data uploaded by the chip.
2591	*
2592	* - We also force the PNIC chip to upload frames that include the
2593	* ethernet CRC at the end.
2594	*
2595	* - We gather all of the bogus frame data into a single buffer.
2596	*
2597	* - We then position a pointer at the end of this buffer and scan
2598	* backwards until we encounter the first non-zero byte of data.
2599	* This is the end of the received frame. We know we will encounter
2600	* some data at the end of the frame because the CRC will always be
2601	* there, so even if the sender transmits a packet of all zeros,
2602	* we won't be fooled.
2603	*
2604	* - We know the size of the actual received frame, so we subtract
2605	* that value from the current pointer location. This brings us
2606	* to the start of the actual received packet.
2607	*
2608	* - We copy this into an mbuf and pass it on, along with the actual
2609	* frame length.
2610	*
2611	* The performance hit is tremendous, but it beats dropping frames all
2612	* the time.
2613	*/
2614
2615	#define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG\|DC_RXSTAT_LASTFRAG)
2616	static void dc_pnic_rx_bug_war(sc, idx)
2617	struct dc_softc *sc;
2618	int idx;
2619	{
2620	struct dc_desc *cur_rx;
2621	struct dc_desc *c = NULL;
2622	struct mbuf *m = NULL;
2623	unsigned char *ptr;
2624	int i, total_len;
2625	u_int32_t rxstat = 0;
2626
2627	i = sc->dc_pnic_rx_bug_save;
2628	cur_rx = &sc->dc_ldata->dc_rx_list[idx];
2629	ptr = sc->dc_pnic_rx_buf;
2630	bzero(ptr, sizeof(DC_RXLEN * 5));
2631
2632	/* Copy all the bytes from the bogus buffers. */
2633	while (1) {
2634	c = &sc->dc_ldata->dc_rx_list[i];
2635	rxstat = c->dc_status;
2636	m = sc->dc_cdata.dc_rx_chain[i];
2637	bcopy(mtod(m, char *), ptr, DC_RXLEN);
2638	ptr += DC_RXLEN;
2639	/* If this is the last buffer, break out. */
2640	if (i == idx \|\| rxstat & DC_RXSTAT_LASTFRAG)
2641	break;
2642	dc_newbuf(sc, i, m);
2643	DC_INC(i, DC_RX_LIST_CNT);
2644	}
2645
2646	/* Find the length of the actual receive frame. */
2647	total_len = DC_RXBYTES(rxstat);
2648
2649	/* Scan backwards until we hit a non-zero byte. */
2650	while(*ptr == 0x00)
2651	ptr--;
2652	#if 0
2653	/* Round off. */
2654	if ((uintptr_t)(ptr) & 0x3)
2655	ptr -= 1;
2656	#endif
2657
2658	/* Now find the start of the frame. */
2659	ptr -= total_len;
2660	if (ptr < sc->dc_pnic_rx_buf)
2661	ptr = sc->dc_pnic_rx_buf;
2662
2663	/*
2664	* Now copy the salvaged frame to the last mbuf and fake up
2665	* the status word to make it look like a successful
2666	* frame reception.
2667	*/
2668	dc_newbuf(sc, i, m);
2669	bcopy(ptr, mtod(m, char *), total_len);
2670	cur_rx->dc_status = rxstat \| DC_RXSTAT_FIRSTFRAG;
2671
2672	return;
2673	}
2674
2675	/*
2676	* This routine searches the RX ring for dirty descriptors in the
2677	* event that the rxeof routine falls out of sync with the chip's
2678	* current descriptor pointer. This may happen sometimes as a result
2679	* of a "no RX buffer available" condition that happens when the chip
2680	* consumes all of the RX buffers before the driver has a chance to
2681	* process the RX ring. This routine may need to be called more than
2682	* once to bring the driver back in sync with the chip, however we
2683	* should still be getting RX DONE interrupts to drive the search
2684	* for new packets in the RX ring, so we should catch up eventually.
2685	*/
2686	static int dc_rx_resync(sc)
2687	struct dc_softc *sc;
2688	{
2689	int i, pos;
2690	struct dc_desc *cur_rx;
2691
2692	pos = sc->dc_cdata.dc_rx_prod;
2693
2694	for (i = 0; i < DC_RX_LIST_CNT; i++) {
2695	cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2696	if (!(cur_rx->dc_status & DC_RXSTAT_OWN))
2697	break;
2698	DC_INC(pos, DC_RX_LIST_CNT);
2699	}
2700
2701	/* If the ring really is empty, then just return. */
2702	if (i == DC_RX_LIST_CNT)
2703	return(0);
2704
2705	/* We've fallen behing the chip: catch it. */
2706	sc->dc_cdata.dc_rx_prod = pos;
2707
2708	return(EAGAIN);
2709	}
2710
2711	/*
2712	* A frame has been uploaded: pass the resulting mbuf chain up to
2713	* the higher level protocols.
2714	*/
2715	static void dc_rxeof(sc)
2716	struct dc_softc *sc;
2717	{
2718	struct ether_header *eh;
2719	struct mbuf *m;
2720	struct ifnet *ifp;
2721	struct dc_desc *cur_rx;
2722	int i, total_len = 0;
2723	u_int32_t rxstat;
2724
2725	ifp = &sc->arpcom.ac_if;
2726	i = sc->dc_cdata.dc_rx_prod;
2727
2728	while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) {
2729
2730	#ifdef DEVICE_POLLING
2731	if (ifp->if_ipending & IFF_POLLING) {
2732	if (sc->rxcycles <= 0)
2733	break;
2734	sc->rxcycles--;
2735	}
2736	#endif /* DEVICE_POLLING */
2737	cur_rx = &sc->dc_ldata->dc_rx_list[i];
2738	rxstat = cur_rx->dc_status;
2739	m = sc->dc_cdata.dc_rx_chain[i];
2740	total_len = DC_RXBYTES(rxstat);
2741
2742	if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2743	if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2744	if (rxstat & DC_RXSTAT_FIRSTFRAG)
2745	sc->dc_pnic_rx_bug_save = i;
2746	if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
2747	DC_INC(i, DC_RX_LIST_CNT);
2748	continue;
2749	}
2750	dc_pnic_rx_bug_war(sc, i);
2751	rxstat = cur_rx->dc_status;
2752	total_len = DC_RXBYTES(rxstat);
2753	}
2754	}
2755
2756	sc->dc_cdata.dc_rx_chain[i] = NULL;
2757
2758	/*
2759	* If an error occurs, update stats, clear the
2760	* status word and leave the mbuf cluster in place:
2761	* it should simply get re-used next time this descriptor
2762	* comes up in the ring. However, don't report long
2763	* frames as errors since they could be vlans
2764	*/
2765	if ((rxstat & DC_RXSTAT_RXERR)){
2766	if (!(rxstat & DC_RXSTAT_GIANT) \|\|
2767	(rxstat & (DC_RXSTAT_CRCERR \| DC_RXSTAT_DRIBBLE \|
2768	DC_RXSTAT_MIIERE \| DC_RXSTAT_COLLSEEN \|
2769	DC_RXSTAT_RUNT \| DC_RXSTAT_DE))) {
2770	ifp->if_ierrors++;
2771	if (rxstat & DC_RXSTAT_COLLSEEN)
2772	ifp->if_collisions++;
2773	dc_newbuf(sc, i, m);
2774	if (rxstat & DC_RXSTAT_CRCERR) {
2775	DC_INC(i, DC_RX_LIST_CNT);
2776	continue;
2777	} else {
2778	dc_init(sc);
2779	return;
2780	}
2781	}
2782	}
2783
2784	/* No errors; receive the packet. */
2785	total_len -= ETHER_CRC_LEN;
2786
2787	#ifdef __i386__
2788	/*
2789	* On the x86 we do not have alignment problems, so try to
2790	* allocate a new buffer for the receive ring, and pass up
2791	* the one where the packet is already, saving the expensive
2792	* copy done in m_devget().
2793	* If we are on an architecture with alignment problems, or
2794	* if the allocation fails, then use m_devget and leave the
2795	* existing buffer in the receive ring.
2796	*/
2797	if (dc_quick && dc_newbuf(sc, i, NULL) == 0) {
2798	m->m_pkthdr.rcvif = ifp;
2799	m->m_pkthdr.len = m->m_len = total_len;
2800	DC_INC(i, DC_RX_LIST_CNT);
2801	} else
2802	#endif
2803	{
2804	struct mbuf *m0;
2805
2806	m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
2807	total_len + ETHER_ALIGN, 0, ifp, NULL);
2808	dc_newbuf(sc, i, m);
2809	DC_INC(i, DC_RX_LIST_CNT);
2810	if (m0 == NULL) {
2811	ifp->if_ierrors++;
2812	continue;
2813	}
2814	m_adj(m0, ETHER_ALIGN);
2815	m = m0;
2816	}
2817
2818	ifp->if_ipackets++;
2819	eh = mtod(m, struct ether_header *);
2820
2821	/* Remove header from mbuf and pass it on. */
2822	m_adj(m, sizeof(struct ether_header));
2823	ether_input(ifp, eh, m);
2824	}
2825
2826	sc->dc_cdata.dc_rx_prod = i;
2827	}
2828
2829	/*
2830	* A frame was downloaded to the chip. It's safe for us to clean up
2831	* the list buffers.
2832	*/
2833
2834	static void
2835	dc_txeof(sc)
2836	struct dc_softc *sc;
2837	{
2838	struct dc_desc *cur_tx = NULL;
2839	struct ifnet *ifp;
2840	int idx;
2841
2842	ifp = &sc->arpcom.ac_if;
2843
2844	/*
2845	* Go through our tx list and free mbufs for those
2846	* frames that have been transmitted.
2847	*/
2848	idx = sc->dc_cdata.dc_tx_cons;
2849	while(idx != sc->dc_cdata.dc_tx_prod) {
2850	u_int32_t txstat;
2851
2852	cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2853	txstat = cur_tx->dc_status;
2854
2855	if (txstat & DC_TXSTAT_OWN)
2856	break;
2857
2858	if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) \|\|
2859	cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2860	if (cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2861	/*
2862	* Yes, the PNIC is so brain damaged
2863	* that it will sometimes generate a TX
2864	* underrun error while DMAing the RX
2865	* filter setup frame. If we detect this,
2866	* we have to send the setup frame again,
2867	* or else the filter won't be programmed
2868	* correctly.
2869	*/
2870	if (DC_IS_PNIC(sc)) {
2871	if (txstat & DC_TXSTAT_ERRSUM)
2872	dc_setfilt(sc);
2873	}
2874	sc->dc_cdata.dc_tx_chain[idx] = NULL;
2875	}
2876	sc->dc_cdata.dc_tx_cnt--;
2877	DC_INC(idx, DC_TX_LIST_CNT);
2878	continue;
2879	}
2880
2881	if (DC_IS_CONEXANT(sc)) {
2882	/*
2883	* For some reason Conexant chips like
2884	* setting the CARRLOST flag even when
2885	* the carrier is there. In CURRENT we
2886	* have the same problem for Xircom
2887	* cards !
2888	*/
2889	if (/sc->dc_type == DC_TYPE_21143 &&/
2890	sc->dc_pmode == DC_PMODE_MII &&
2891	((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM\|
2892	DC_TXSTAT_NOCARRIER)))
2893	txstat &= ~DC_TXSTAT_ERRSUM;
2894	} else {
2895	if (/sc->dc_type == DC_TYPE_21143 &&/
2896	sc->dc_pmode == DC_PMODE_MII &&
2897	((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM\|
2898	DC_TXSTAT_NOCARRIER\|DC_TXSTAT_CARRLOST)))
2899	txstat &= ~DC_TXSTAT_ERRSUM;
2900	}
2901
2902	if (txstat & DC_TXSTAT_ERRSUM) {
2903	ifp->if_oerrors++;
2904	if (txstat & DC_TXSTAT_EXCESSCOLL)
2905	ifp->if_collisions++;
2906	if (txstat & DC_TXSTAT_LATECOLL)
2907	ifp->if_collisions++;
2908	if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2909	dc_init(sc);
2910	return;
2911	}
2912	}
2913
2914	ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2915
2916	ifp->if_opackets++;
2917	if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
2918	m_freem(sc->dc_cdata.dc_tx_chain[idx]);
2919	sc->dc_cdata.dc_tx_chain[idx] = NULL;
2920	}
2921
2922	sc->dc_cdata.dc_tx_cnt--;
2923	DC_INC(idx, DC_TX_LIST_CNT);
2924	}
2925
2926	if (idx != sc->dc_cdata.dc_tx_cons) {
2927	/* some buffers have been freed */
2928	sc->dc_cdata.dc_tx_cons = idx;
2929	ifp->if_flags &= ~IFF_OACTIVE;
2930	}
2931	ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5;
2932
2933	return;
2934	}
2935
2936
2937	#if 0
2938	static void dc_tick(xsc)
2939	void *xsc;
2940	{
2941	struct dc_softc *sc;
2942	/struct mii_data mii;*/
2943	struct ifnet *ifp;
2944	int s;
2945	u_int32_t r;
2946
2947
2948	sc = xsc;
2949	ifp = &sc->arpcom.ac_if;
2950	mii = device_get_softc(sc->dc_miibus);
2951
2952	if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2953	if (sc->dc_flags & DC_21143_NWAY) {
2954	r = CSR_READ_4(sc, DC_10BTSTAT);
2955	if (IFM_SUBTYPE(mii->mii_media_active) ==
2956	IFM_100_TX && (r & DC_TSTAT_LS100)) {
2957	sc->dc_link = 0;
2958	mii_mediachg(mii);
2959	}
2960	if (IFM_SUBTYPE(mii->mii_media_active) ==
2961	IFM_10_T && (r & DC_TSTAT_LS10)) {
2962	sc->dc_link = 0;
2963	mii_mediachg(mii);
2964	}
2965	if (sc->dc_link == 0)
2966	mii_tick(mii);
2967	} else {
2968	r = CSR_READ_4(sc, DC_ISR);
2969	if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT &&
2970	sc->dc_cdata.dc_tx_cnt == 0)
2971	mii_tick(mii);
2972	if (!(mii->mii_media_status & IFM_ACTIVE))
2973	sc->dc_link = 0;
2974	}
2975	} else
2976	mii_tick(mii);
2977
2978	/*
2979	* When the init routine completes, we expect to be able to send
2980	* packets right away, and in fact the network code will send a
2981	* gratuitous ARP the moment the init routine marks the interface
2982	* as running. However, even though the MAC may have been initialized,
2983	* there may be a delay of a few seconds before the PHY completes
2984	* autonegotiation and the link is brought up. Any transmissions
2985	* made during that delay will be lost. Dealing with this is tricky:
2986	* we can't just pause in the init routine while waiting for the
2987	* PHY to come ready since that would bring the whole system to
2988	* a screeching halt for several seconds.
2989	*
2990	* What we do here is prevent the TX start routine from sending
2991	* any packets until a link has been established. After the
2992	* interface has been initialized, the tick routine will poll
2993	* the state of the PHY until the IFM_ACTIVE flag is set. Until
2994	* that time, packets will stay in the send queue, and once the
2995	* link comes up, they will be flushed out to the wire.
2996	*/
2997	if (!sc->dc_link) {
2998	mii_pollstat(mii);
2999	if (mii->mii_media_status & IFM_ACTIVE &&
3000	IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3001	sc->dc_link++;
3002	if (ifp->if_snd.ifq_head != NULL)
3003	dc_start(ifp);
3004	}
3005	}
3006
3007	if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
3008	sc->dc_stat_ch = timeout(dc_tick, sc, hz/10);
3009	else
3010	sc->dc_stat_ch = timeout(dc_tick, sc, hz);
3011
3012	return;
3013	}
3014	#endif
3015
3016	/*
3017	* A transmit underrun has occurred. Back off the transmit threshold,
3018	* or switch to store and forward mode if we have to.
3019	*/
3020	static void dc_tx_underrun(sc)
3021	struct dc_softc *sc;
3022	{
3023	u_int32_t isr;
3024	int i;
3025
3026	if (DC_IS_DAVICOM(sc))
3027	dc_init(sc);
3028
3029	if (DC_IS_INTEL(sc)) {
3030	/*
3031	* The real 21143 requires that the transmitter be idle
3032	* in order to change the transmit threshold or store
3033	* and forward state.
3034	*/
3035	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3036
3037	for (i = 0; i < DC_TIMEOUT; i++) {
3038	isr = CSR_READ_4(sc, DC_ISR);
3039	if (isr & DC_ISR_TX_IDLE)
3040	break;
3041	DELAY(10);
3042	}
3043	if (i == DC_TIMEOUT) {
3044	printk("dc%d: failed to force tx to idle state\n",
3045	sc->dc_unit);
3046	dc_init(sc);
3047	}
3048	}
3049
3050	printk("dc%d: TX underrun -- ", sc->dc_unit);
3051	sc->dc_txthresh += DC_TXTHRESH_INC;
3052	if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3053	printk("using store and forward mode\n");
3054	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3055	} else {
3056	printk("increasing TX threshold\n");
3057	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3058	DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3059	}
3060
3061	if (DC_IS_INTEL(sc))
3062	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3063
3064	return;
3065	}
3066
3067	#ifdef DEVICE_POLLING
3068	static poll_handler_t dc_poll;
3069
3070	static void
3071	dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3072	{
3073	struct dc_softc *sc = ifp->if_softc;
3074
3075	if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
3076	/* Re-enable interrupts. */
3077	CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3078	return;
3079	}
3080	sc->rxcycles = count;
3081	dc_rxeof(sc);
3082	dc_txeof(sc);
3083	if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE))
3084	dc_start(ifp);
3085
3086	if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
3087	u_int32_t status;
3088
3089	status = CSR_READ_4(sc, DC_ISR);
3090	status &= (DC_ISR_RX_WATDOGTIMEO\|DC_ISR_RX_NOBUF\|
3091	DC_ISR_TX_NOBUF\|DC_ISR_TX_IDLE\|DC_ISR_TX_UNDERRUN\|
3092	DC_ISR_BUS_ERR);
3093	if (!status)
3094	return ;
3095	/* ack what we have */
3096	CSR_WRITE_4(sc, DC_ISR, status);
3097
3098	if (status & (DC_ISR_RX_WATDOGTIMEO\|DC_ISR_RX_NOBUF) ) {
3099	u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3100	ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
3101
3102	if (dc_rx_resync(sc))
3103	dc_rxeof(sc);
3104	}
3105	/* restart transmit unit if necessary */
3106	if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
3107	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3108
3109	if (status & DC_ISR_TX_UNDERRUN)
3110	dc_tx_underrun(sc);
3111
3112	if (status & DC_ISR_BUS_ERR) {
3113	printk("dc_poll: dc%d bus error\n", sc->dc_unit);
3114	dc_reset(sc);
3115	dc_init(sc);
3116	}
3117	}
3118	}
3119	#endif /* DEVICE_POLLING */
3120
3121	static void
3122	dc_intr(void* arg)
3123	{
3124	/* Need to make this work for multiple devices ... eventually */
3125	struct dc_softc sc = (struct dc_softc )arg;
3126
3127
3128	/* Disable interrupts. */
3129	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3130
3131	rtems_event_send(sc->daemontid, IRQ_EVENT);
3132	#if 0
3133	if (sc->suspended) {
3134	return;
3135	}
3136
3137	ifp = &sc->arpcom.ac_if;
3138
3139	#ifdef DEVICE_POLLING
3140	if (ifp->if_ipending & IFF_POLLING)
3141	return;
3142	if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */
3143	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3144	return;
3145	}
3146	#endif /* DEVICE_POLLING */
3147	if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
3148	return ;
3149
3150	/* Suppress unwanted interrupts */
3151	if (!(ifp->if_flags & IFF_UP)) {
3152	if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
3153	dc_stop(sc);
3154	return;
3155	}
3156	#endif
3157	}
3158
3159
3160	static void
3161	dc_daemon(void * arg)
3162	{
3163	struct dc_softc sc = (struct dc_softc )arg;
3164	struct ifnet *ifp;
3165	u_int32_t status;
3166	rtems_event_set events;
3167
3168
3169	for(;;) {
3170	rtems_bsdnet_event_receive(RTEMS_ALL_EVENTS, \
3171	RTEMS_WAIT \| RTEMS_EVENT_ANY, \
3172	RTEMS_NO_TIMEOUT,
3173	&events);
3174
3175
3176	ifp = &sc->arpcom.ac_if;
3177
3178	while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) {
3179
3180	CSR_WRITE_4(sc, DC_ISR, status);
3181
3182	if (status & DC_ISR_RX_OK) {
3183	int curpkts;
3184	curpkts = ifp->if_ipackets;
3185	dc_rxeof(sc);
3186	if (curpkts == ifp->if_ipackets) {
3187	while(dc_rx_resync(sc))
3188	dc_rxeof(sc);
3189	}
3190	}
3191
3192	if (status & (DC_ISR_TX_OK\|DC_ISR_TX_NOBUF))
3193	dc_txeof(sc);
3194
3195	if (status & DC_ISR_TX_IDLE) {
3196	dc_txeof(sc);
3197	if (sc->dc_cdata.dc_tx_cnt) {
3198	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3199	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3200	}
3201	}
3202
3203	if (status & DC_ISR_TX_UNDERRUN)
3204	dc_tx_underrun(sc);
3205
3206	if ((status & DC_ISR_RX_WATDOGTIMEO)
3207	\|\| (status & DC_ISR_RX_NOBUF)) {
3208	int curpkts;
3209	curpkts = ifp->if_ipackets;
3210	dc_rxeof(sc);
3211	if (curpkts == ifp->if_ipackets) {
3212	while(dc_rx_resync(sc))
3213	dc_rxeof(sc);
3214	}
3215	}
3216
3217	if (status & DC_ISR_BUS_ERR) {
3218	dc_reset(sc);
3219	dc_init(sc);
3220	}
3221	}
3222
3223	/* Make atomic !!! */
3224	/* Re-enable interrupts. */
3225	CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3226
3227	if (ifp->if_snd.ifq_head != NULL)
3228	dc_start(ifp);
3229	}
3230
3231	}
3232
3233
3234	/*
3235	* Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
3236	* pointers to the fragment pointers.
3237	*/
3238	static int dc_encap(sc, m_head, txidx)
3239	struct dc_softc *sc;
3240	struct mbuf *m_head;
3241	u_int32_t *txidx;
3242	{
3243	struct dc_desc *f = NULL;
3244	struct mbuf *m;
3245	int frag, cur, cnt = 0;
3246
3247	/*
3248	* Start packing the mbufs in this chain into
3249	* the fragment pointers. Stop when we run out
3250	* of fragments or hit the end of the mbuf chain.
3251	*/
3252	m = m_head;
3253	cur = frag = *txidx;
3254
3255	for (m = m_head; m != NULL; m = m->m_next) {
3256	if (m->m_len != 0) {
3257	if (sc->dc_flags & DC_TX_ADMTEK_WAR) {
3258	if (*txidx != sc->dc_cdata.dc_tx_prod &&
3259	frag == (DC_TX_LIST_CNT - 1))
3260	return(ENOBUFS);
3261	}
3262	if ((DC_TX_LIST_CNT -
3263	(sc->dc_cdata.dc_tx_cnt + cnt)) < 5)
3264	return(ENOBUFS);
3265
3266	f = &sc->dc_ldata->dc_tx_list[frag];
3267	f->dc_ctl = DC_TXCTL_TLINK \| m->m_len;
3268	if (cnt == 0) {
3269	f->dc_status = 0;
3270	f->dc_ctl \|= DC_TXCTL_FIRSTFRAG;
3271	} else
3272	f->dc_status = DC_TXSTAT_OWN;
3273	f->dc_data = vtophys(mtod(m, vm_offset_t));
3274	cur = frag;
3275	DC_INC(frag, DC_TX_LIST_CNT);
3276	cnt++;
3277	}
3278	}
3279
3280	if (m != NULL)
3281	return(ENOBUFS);
3282
3283	sc->dc_cdata.dc_tx_cnt += cnt;
3284	sc->dc_cdata.dc_tx_chain[cur] = m_head;
3285	sc->dc_ldata->dc_tx_list[cur].dc_ctl \|= DC_TXCTL_LASTFRAG;
3286	if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3287	sc->dc_ldata->dc_tx_list[*txidx].dc_ctl \|= DC_TXCTL_FINT;
3288	if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3289	sc->dc_ldata->dc_tx_list[cur].dc_ctl \|= DC_TXCTL_FINT;
3290	if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
3291	sc->dc_ldata->dc_tx_list[cur].dc_ctl \|= DC_TXCTL_FINT;
3292	sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN;
3293	*txidx = frag;
3294
3295	return(0);
3296	}
3297
3298	/*
3299	* Coalesce an mbuf chain into a single mbuf cluster buffer.
3300	* Needed for some really badly behaved chips that just can't
3301	* do scatter/gather correctly.
3302	*/
3303	static int dc_coal(sc, m_head)
3304	struct dc_softc *sc;
3305	struct mbuf **m_head;
3306	{
3307	struct mbuf m_new, m;
3308
3309	m = *m_head;
3310	MGETHDR(m_new, M_DONTWAIT, MT_DATA);
3311	if (m_new == NULL)
3312	return(ENOBUFS);
3313	if (m->m_pkthdr.len > MHLEN) {
3314	MCLGET(m_new, M_DONTWAIT);
3315	if (!(m_new->m_flags & M_EXT)) {
3316	m_freem(m_new);
3317	return(ENOBUFS);
3318	}
3319	}
3320	m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t));
3321	m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len;
3322	m_freem(m);
3323	*m_head = m_new;
3324
3325	return(0);
3326	}
3327
3328	/*
3329	* Main transmit routine. To avoid having to do mbuf copies, we put pointers
3330	* to the mbuf data regions directly in the transmit lists. We also save a
3331	* copy of the pointers since the transmit list fragment pointers are
3332	* physical addresses.
3333	*/
3334
3335	static void dc_start(ifp)
3336	struct ifnet *ifp;
3337	{
3338	struct dc_softc *sc;
3339	struct mbuf *m_head = NULL;
3340	u_int32_t idx;
3341
3342	sc = ifp->if_softc;
3343	#if 0
3344	if (!sc->dc_link && ifp->if_snd.ifq_len < 10)
3345	return;
3346	#endif
3347	if (ifp->if_flags & IFF_OACTIVE)
3348	return;
3349
3350	idx = sc->dc_cdata.dc_tx_prod;
3351
3352	while(sc->dc_cdata.dc_tx_chain[idx] == NULL) {
3353	IF_DEQUEUE(&ifp->if_snd, m_head);
3354	if (m_head == NULL)
3355	break;
3356
3357	if (sc->dc_flags & DC_TX_COALESCE &&
3358	m_head->m_next != NULL) {
3359	/* only coalesce if have >1 mbufs */
3360	if (dc_coal(sc, &m_head)) {
3361	IF_PREPEND(&ifp->if_snd, m_head);
3362	ifp->if_flags \|= IFF_OACTIVE;
3363	break;
3364	}
3365	}
3366
3367	if (dc_encap(sc, m_head, &idx)) {
3368	IF_PREPEND(&ifp->if_snd, m_head);
3369	ifp->if_flags \|= IFF_OACTIVE;
3370	break;
3371	}
3372	#if 0
3373	/*
3374	* If there's a BPF listener, bounce a copy of this frame
3375	* to him.
3376	*/
3377	if (ifp->if_bpf)
3378	bpf_mtap(ifp, m_head);
3379	#endif
3380	if (sc->dc_flags & DC_TX_ONE) {
3381	ifp->if_flags \|= IFF_OACTIVE;
3382	break;
3383	}
3384	}
3385
3386	/* Transmit */
3387	sc->dc_cdata.dc_tx_prod = idx;
3388	if (!(sc->dc_flags & DC_TX_POLL))
3389	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3390
3391	/*
3392	* Set a timeout in case the chip goes out to lunch.
3393	*/
3394	ifp->if_timer = 5;
3395
3396	return;
3397	}
3398
3399	static void dc_init(xsc)
3400	void *xsc;
3401	{
3402	struct dc_softc *sc = xsc;
3403	struct ifnet *ifp = &sc->arpcom.ac_if;
3404	/struct mii_data mii;*/
3405
3406
3407	/mii = device_get_softc(sc->dc_miibus);/
3408
3409	/*
3410	* Cancel pending I/O and free all RX/TX buffers.
3411	*/
3412	dc_stop(sc);
3413	dc_reset(sc);
3414
3415	/*
3416	* Set cache alignment and burst length.
3417	*/
3418	if (DC_IS_ASIX(sc) \|\| DC_IS_DAVICOM(sc))
3419	CSR_WRITE_4(sc, DC_BUSCTL, 0);
3420	else
3421	CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME\|DC_BUSCTL_MRLE);
3422	/*
3423	* Evenly share the bus between receive and transmit process.
3424	*/
3425	if (DC_IS_INTEL(sc))
3426	DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3427	if (DC_IS_DAVICOM(sc) \|\| DC_IS_INTEL(sc)) {
3428	DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3429	} else {
3430	DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3431	}
3432	if (sc->dc_flags & DC_TX_POLL)
3433	DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3434	switch(sc->dc_cachesize) {
3435	case 32:
3436	DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3437	break;
3438	case 16:
3439	DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3440	break;
3441	case 8:
3442	DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3443	break;
3444	case 0:
3445	default:
3446	DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3447	break;
3448	}
3449
3450	if (sc->dc_flags & DC_TX_STORENFWD)
3451	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3452	else {
3453	if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3454	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3455	} else {
3456	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3457	DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3458	}
3459	}
3460
3461	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3462	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3463
3464	if (DC_IS_MACRONIX(sc) \|\| DC_IS_PNICII(sc)) {
3465	/*
3466	* The app notes for the 98713 and 98715A say that
3467	* in order to have the chips operate properly, a magic
3468	* number must be written to CSR16. Macronix does not
3469	* document the meaning of these bits so there's no way
3470	* to know exactly what they do. The 98713 has a magic
3471	* number all its own; the rest all use a different one.
3472	*/
3473	DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3474	if (sc->dc_type == DC_TYPE_98713)
3475	DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3476	else
3477	DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3478	}
3479
3480	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3481	DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3482
3483	/* Init circular RX list. */
3484	if (dc_list_rx_init(sc) == ENOBUFS) {
3485	printk("dc%d: initialization failed: no "
3486	"memory for rx buffers\n", sc->dc_unit);
3487	dc_stop(sc);
3488	return;
3489	}
3490
3491	/*
3492	* Init tx descriptors.
3493	*/
3494	dc_list_tx_init(sc);
3495
3496	/*
3497	* Load the address of the RX list.
3498	*/
3499	CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0]));
3500	CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0]));
3501
3502	/*
3503	* Enable interrupts.
3504	*/
3505	#ifdef DEVICE_POLLING
3506	/*
3507	* ... but only if we are not polling, and make sure they are off in
3508	* the case of polling. Some cards (e.g. fxp) turn interrupts on
3509	* after a reset.
3510	*/
3511	if (ifp->if_ipending & IFF_POLLING)
3512	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3513	else
3514	#endif
3515	/* Enable interrupts */
3516	CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3517	CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3518
3519	/* Enable transmitter. */
3520	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3521
3522	/*
3523	* If this is an Intel 21143 and we're not using the
3524	* MII port, program the LED control pins so we get
3525	* link and activity indications.
3526	*/
3527	if (sc->dc_flags & DC_TULIP_LEDS) {
3528	CSR_WRITE_4(sc, DC_WATCHDOG,
3529	DC_WDOG_CTLWREN\|DC_WDOG_LINK\|DC_WDOG_ACTIVITY);
3530	CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3531	}
3532
3533	/*
3534	* Load the RX/multicast filter. We do this sort of late
3535	* because the filter programming scheme on the 21143 and
3536	* some clones requires DMAing a setup frame via the TX
3537	* engine, and we need the transmitter enabled for that.
3538	*/
3539	dc_setfilt(sc);
3540
3541	/* Enable receiver. */
3542	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3543	CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3544
3545	/mii_mediachg(mii);/
3546	dc_setcfg(sc, sc->dc_if_media);
3547
3548	ifp->if_flags \|= IFF_RUNNING;
3549	ifp->if_flags &= ~IFF_OACTIVE;
3550
3551
3552	#if 0
3553
3554	/* Don't start the ticker if this is a homePNA link. */
3555	if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_homePNA)
3556	sc->dc_link = 1;
3557	else {
3558	if (sc->dc_flags & DC_21143_NWAY)
3559	sc->dc_stat_ch = timeout(dc_tick, sc, hz/10);
3560	else
3561	sc->dc_stat_ch = timeout(dc_tick, sc, hz);
3562	}
3563
3564	#ifdef SRM_MEDIA
3565	if(sc->dc_srm_media) {
3566	struct ifreq ifr;
3567
3568	ifr.ifr_media = sc->dc_srm_media;
3569	ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA);
3570	sc->dc_srm_media = 0;
3571	}
3572	#endif
3573	#endif /* end if (0) */
3574	return;
3575	}
3576
3577
3578	#if 0
3579	/*
3580	* Set media options.
3581	*/
3582	static int dc_ifmedia_upd(ifp)
3583	struct ifnet *ifp;
3584	{
3585	struct dc_softc *sc;
3586	struct mii_data *mii;
3587	struct ifmedia *ifm;
3588
3589	sc = ifp->if_softc;
3590	mii = device_get_softc(sc->dc_miibus);
3591	mii_mediachg(mii);
3592	ifm = &mii->mii_media;
3593
3594	if (DC_IS_DAVICOM(sc) &&
3595	IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA)
3596	dc_setcfg(sc, ifm->ifm_media);
3597	else
3598	sc->dc_link = 0;
3599
3600	return(0);
3601	}
3602
3603	/*
3604	* Report current media status.
3605	*/
3606	static void dc_ifmedia_sts(ifp, ifmr)
3607	struct ifnet *ifp;
3608	struct ifmediareq *ifmr;
3609	{
3610	struct dc_softc *sc;
3611	struct mii_data *mii;
3612	struct ifmedia *ifm;
3613
3614	sc = ifp->if_softc;
3615	mii = device_get_softc(sc->dc_miibus);
3616	mii_pollstat(mii);
3617	ifm = &mii->mii_media;
3618	if (DC_IS_DAVICOM(sc)) {
3619	if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) {
3620	ifmr->ifm_active = ifm->ifm_media;
3621	ifmr->ifm_status = 0;
3622	return;
3623	}
3624	}
3625	ifmr->ifm_active = mii->mii_media_active;
3626	ifmr->ifm_status = mii->mii_media_status;
3627
3628	return;
3629	}
3630	#endif
3631
3632
3633	static int dc_ioctl(ifp, command, data)
3634	struct ifnet *ifp;
3635	ioctl_command_t command;
3636	caddr_t data;
3637	{
3638	struct dc_softc *sc = ifp->if_softc;
3639	/struct ifreq ifr = (struct ifreq *) data;
3640	struct mii_data mii;/
3641	int error = 0;
3642
3643
3644	switch(command) {
3645	case SIOCSIFADDR:
3646	case SIOCGIFADDR:
3647	case SIOCSIFMTU:
3648	error = ether_ioctl(ifp, command, data);
3649	break;
3650	case SIOCSIFFLAGS:
3651	if (ifp->if_flags & IFF_UP) {
3652	int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3653	(IFF_PROMISC \| IFF_ALLMULTI);
3654	if (ifp->if_flags & IFF_RUNNING) {
3655	if (need_setfilt)
3656	dc_setfilt(sc);
3657	} else {
3658	sc->dc_txthresh = 0;
3659	dc_init(sc);
3660	}
3661	} else {
3662	if (ifp->if_flags & IFF_RUNNING)
3663	dc_stop(sc);
3664	}
3665	sc->dc_if_flags = ifp->if_flags;
3666	error = 0;
3667	break;
3668	case SIOCADDMULTI:
3669	case SIOCDELMULTI:
3670	dc_setfilt(sc);
3671	error = 0;
3672	break;
3673	#if 0
3674	case SIOCGIFMEDIA:
3675	case SIOCSIFMEDIA:
3676	mii = device_get_softc(sc->dc_miibus);
3677	error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3678	#ifdef SRM_MEDIA
3679	if (sc->dc_srm_media)
3680	sc->dc_srm_media = 0;
3681	#endif
3682	break;
3683	#endif
3684	default:
3685	error = EINVAL;
3686	break;
3687	}
3688
3689
3690	return(error);
3691	}
3692
3693	static void dc_watchdog(ifp)
3694	struct ifnet *ifp;
3695	{
3696	struct dc_softc *sc;
3697
3698	sc = ifp->if_softc;
3699
3700	ifp->if_oerrors++;
3701	printk("dc%d: watchdog timeout\n", sc->dc_unit);
3702
3703	dc_stop(sc);
3704	dc_reset(sc);
3705	dc_init(sc);
3706
3707	if (ifp->if_snd.ifq_head != NULL)
3708	dc_start(ifp);
3709
3710	return;
3711	}
3712
3713	/*
3714	* Stop the adapter and free any mbufs allocated to the
3715	* RX and TX lists.
3716	*/
3717	static void dc_stop(sc)
3718	struct dc_softc *sc;
3719	{
3720	register int i;
3721	struct ifnet *ifp;
3722
3723	ifp = &sc->arpcom.ac_if;
3724	ifp->if_timer = 0;
3725
3726	/untimeout(dc_tick, sc, sc->dc_stat_ch);/
3727
3728	ifp->if_flags &= ~(IFF_RUNNING \| IFF_OACTIVE);
3729	#ifdef DEVICE_POLLING
3730	ether_poll_deregister(ifp);
3731	#endif
3732
3733	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON\|DC_NETCFG_TX_ON));
3734	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3735	CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3736	CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3737	sc->dc_link = 0;
3738
3739	/*
3740	* Free data in the RX lists.
3741	*/
3742	for (i = 0; i < DC_RX_LIST_CNT; i++) {
3743	if (sc->dc_cdata.dc_rx_chain[i] != NULL) {
3744	m_freem(sc->dc_cdata.dc_rx_chain[i]);
3745	sc->dc_cdata.dc_rx_chain[i] = NULL;
3746	}
3747	}
3748	bzero((char *)&sc->dc_ldata->dc_rx_list,
3749	sizeof(sc->dc_ldata->dc_rx_list));
3750
3751	/*
3752	* Free the TX list buffers.
3753	*/
3754	for (i = 0; i < DC_TX_LIST_CNT; i++) {
3755	if (sc->dc_cdata.dc_tx_chain[i] != NULL) {
3756	if (sc->dc_ldata->dc_tx_list[i].dc_ctl &
3757	DC_TXCTL_SETUP) {
3758	sc->dc_cdata.dc_tx_chain[i] = NULL;
3759	continue;
3760	}
3761	m_freem(sc->dc_cdata.dc_tx_chain[i]);
3762	sc->dc_cdata.dc_tx_chain[i] = NULL;
3763	}
3764	}
3765
3766	bzero((char *)&sc->dc_ldata->dc_tx_list,
3767	sizeof(sc->dc_ldata->dc_tx_list));
3768
3769	return;
3770	}
3771
3772
3773	#if 0
3774	/*
3775	* Stop all chip I/O so that the kernel's probe routines don't
3776	* get confused by errant DMAs when rebooting.
3777	*/
3778	static void dc_shutdown(dev)
3779	device_t dev;
3780	{
3781	struct dc_softc *sc;
3782
3783	sc = device_get_softc(dev);
3784
3785	dc_stop(sc);
3786
3787	return;
3788	}
3789
3790	/*
3791	* Device suspend routine. Stop the interface and save some PCI
3792	* settings in case the BIOS doesn't restore them properly on
3793	* resume.
3794	*/
3795	static int dc_suspend(dev)
3796	device_t dev;
3797	{
3798	register int i;
3799	int s;
3800	struct dc_softc *sc;
3801
3802
3803	sc = device_get_softc(dev);
3804
3805	dc_stop(sc);
3806
3807	for (i = 0; i < 5; i++)
3808	sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
3809	sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
3810	sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
3811	sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3812	sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3813
3814	sc->suspended = 1;
3815
3816	return (0);
3817	}
3818
3819	/*
3820	* Device resume routine. Restore some PCI settings in case the BIOS
3821	* doesn't, re-enable busmastering, and restart the interface if
3822	* appropriate.
3823	*/
3824	static int dc_resume(dev)
3825	device_t dev;
3826	{
3827	register int i;
3828	int s;
3829	struct dc_softc *sc;
3830	struct ifnet *ifp;
3831
3832
3833	sc = device_get_softc(dev);
3834	ifp = &sc->arpcom.ac_if;
3835
3836	dc_acpi(dev);
3837
3838	/* better way to do this? */
3839	for (i = 0; i < 5; i++)
3840	pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
3841	pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
3842	pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
3843	pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
3844	pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
3845
3846	/* reenable busmastering */
3847	pci_enable_busmaster(dev);
3848	pci_enable_io(dev, DC_RES);
3849
3850	/* reinitialize interface if necessary */
3851	if (ifp->if_flags & IFF_UP)
3852	dc_init(sc);
3853
3854	sc->suspended = 0;
3855
3856	return (0);
3857	}
3858	#endif
3859
3860	#endif /* end if supported */

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