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source: rtems/c/src/libchip/network/if_dc.c @ 9c5873b7

4.104.114.84.95

Last change on this file since 9c5873b7 was 9c5873b7, checked in by Joel Sherrill <joel.sherrill@…>, on 06/17/05 at 14:32:23

2005-06-17 Joel Sherrill <joel@…>

libchip/network/if_dc.c: Begin to convert to new PCI and IRQ interface. Also correct attempting to build on other than PowerPC and x86.

Property mode set to 100644

File size: 91.5 KB

Line
1	/* $Id$
2	*
3	* Ported from FreeBSD --> RTEMS, december 03.
4	* Daron Chabot <daron@nucleus.usask.ca>
5	* -- only tested with i386 bsp.
6	* -- supports one card (until the PCI & IRQ APIs get sorted out ;-))
7	*
8	*
9	* Copyright (c) 1997, 1998, 1999
10	* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
11	*
12	* Redistribution and use in source and binary forms, with or without
13	* modification, are permitted provided that the following conditions
14	* are met:
15	* 1. Redistributions of source code must retain the above copyright
16	* notice, this list of conditions and the following disclaimer.
17	* 2. Redistributions in binary form must reproduce the above copyright
18	* notice, this list of conditions and the following disclaimer in the
19	* documentation and/or other materials provided with the distribution.
20	* 3. All advertising materials mentioning features or use of this software
21	* must display the following acknowledgement:
22	* This product includes software developed by Bill Paul.
23	* 4. Neither the name of the author nor the names of any co-contributors
24	* may be used to endorse or promote products derived from this software
25	* without specific prior written permission.
26	*
27	* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
28	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30	* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
31	* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
37	* THE POSSIBILITY OF SUCH DAMAGE.
38	*
39	* $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.41 2003/03/05 18:42:33 njl Exp $
40	*/
41
42	/*
43	* DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
44	* series chips and several workalikes including the following:
45	*
46	* Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
47	* Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
48	* Lite-On 82c168/82c169 PNIC (www.litecom.com)
49	* ASIX Electronics AX88140A (www.asix.com.tw)
50	* ASIX Electronics AX88141 (www.asix.com.tw)
51	* ADMtek AL981 (www.admtek.com.tw)
52	* ADMtek AN985 (www.admtek.com.tw)
53	* Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
54	* Accton EN1217 (www.accton.com)
55	* Conexant LANfinity (www.conexant.com)
56	*
57	* Datasheets for the 21143 are available at developer.intel.com.
58	* Datasheets for the clone parts can be found at their respective sites.
59	* (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
60	* The PNIC II is essentially a Macronix 98715A chip; the only difference
61	* worth noting is that its multicast hash table is only 128 bits wide
62	* instead of 512.
63	*
64	* Written by Bill Paul <wpaul@ee.columbia.edu>
65	* Electrical Engineering Department
66	* Columbia University, New York City
67	*/
68
69	/*
70	* The Intel 21143 is the successor to the DEC 21140. It is basically
71	* the same as the 21140 but with a few new features. The 21143 supports
72	* three kinds of media attachments:
73	*
74	* o MII port, for 10Mbps and 100Mbps support and NWAY
75	* autonegotiation provided by an external PHY.
76	* o SYM port, for symbol mode 100Mbps support.
77	* o 10baseT port.
78	* o AUI/BNC port.
79	*
80	* The 100Mbps SYM port and 10baseT port can be used together in
81	* combination with the internal NWAY support to create a 10/100
82	* autosensing configuration.
83	*
84	* Note that not all tulip workalikes are handled in this driver: we only
85	* deal with those which are relatively well behaved. The Winbond is
86	* handled separately due to its different register offsets and the
87	* special handling needed for its various bugs. The PNIC is handled
88	* here, but I'm not thrilled about it.
89	*
90	* All of the workalike chips use some form of MII transceiver support
91	* with the exception of the Macronix chips, which also have a SYM port.
92	* The ASIX AX88140A is also documented to have a SYM port, but all
93	* the cards I've seen use an MII transceiver, probably because the
94	* AX88140A doesn't support internal NWAY.
95	*/
96
97	/*
98	* This driver only supports architectures with the new style
99	* exception processing. The following checks try to keep this
100	* from being compiled on systems which can't support this driver.
101	*/
102
103	#if defined(__i386__)
104	#define DRIVER_SUPPORTED
105	#endif
106
107	#if defined(__PPC__) && (defined(mpc604) \|\| defined(mpc750) \|\| defined(mpc603e))
108	#define DRIVER_SUPPORTED
109	#endif
110
111	#undef DRIVER_SUPPORTED
112
113	#if defined(DRIVER_SUPPORTED)
114	#include <rtems.h>
115	#include <rtems/error.h>
116	#include <rtems/rtems_bsdnet.h>
117
118
119
120	#include <net/if_types.h>
121
122	#include <sys/param.h>
123	#include <sys/sockio.h>
124	#include <sys/socket.h>
125	#include <sys/mbuf.h>
126	#include <net/if.h>
127	#include <netinet/in.h>
128	#include <netinet/if_ether.h>
129	#include <sys/malloc.h>
130	#include <sys/systm.h>
131	#include <bsp.h>
132
133	#include "if_media.h"
134	#include <rtems/pci.h>
135	/*
136	#include <sys/kernel.h>
137	#include <sys/sysctl.h>
138	*/
139
140	#include <vm/vm.h> /* for vtophys */
141
142
143	#if defined(__i386__)
144	#define vtophys(p) (u_int32_t)(p)
145	#else
146	#define vtophys(p) vtophys(p)
147	#endif
148
149	/*
150	#include <net/if_arp.h>
151	#include <net/if_vlan_var.h>
152	#include <net/bpf.h>
153	*/
154
155	#if 0
156	#include <vm/pmap.h> /* for vtophys */
157	#include <machine/clock.h> /* for DELAY */
158	#include <machine/bus_pio.h>
159	#include <machine/bus_memio.h>
160	#include <machine/bus.h>
161	#include <machine/resource.h>
162	#include <sys/bus.h>
163	#include <sys/rman.h>
164
165	#include <dev/mii/mii.h>
166	#include <dev/mii/miivar.h>
167
168	#include <pci/pcireg.h>
169	#include <pci/pcivar.h>
170	#endif
171
172	/* NOTE: use mem space mapping (for now ...)
173	#define DC_USEIOSPACE
174	*/
175
176	#ifdef __alpha__
177	#define SRM_MEDIA
178	#endif
179
180	#include <bsp/irq.h>
181
182
183	#include "if_dcreg.h"
184
185
186	#define DRIVER_PREFIX "tl"
187	#define NDRIVER 1
188	#define IRQ_EVENT RTEMS_EVENT_13 /* Ha ... */
189	static struct dc_softc dc_softc_devs[NDRIVER];
190
191	#if 0
192	/* "controller miibus0" required. See GENERIC if you get errors here. */
193	#include "miibus_if.h"
194
195
196
197	#ifndef lint
198	static const char rcsid[] =
199	"$FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.41 2003/03/05 18:42:33 njl Exp $";
200	#endif
201
202	#endif
203
204
205	/*
206	* Various supported device vendors/types and their names.
207	* NOTE:
208	* -----
209	* Only the "ADMtek AN985" has been tested under RTEMS !!!
210	*/
211	static struct dc_type dc_devs[] = {
212	{ DC_VENDORID_DEC, DC_DEVICEID_21143,
213	"Intel 21143 10/100BaseTX", 0 },
214	{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009,
215	"Davicom DM9009 10/100BaseTX", 0 },
216	{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100,
217	"Davicom DM9100 10/100BaseTX", 0 },
218	{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
219	"Davicom DM9102 10/100BaseTX", 0 },
220	{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
221	"Davicom DM9102A 10/100BaseTX", 0 },
222	{ DC_VENDORID_ADMTEK, DC_DEVICEID_AL981,
223	"ADMtek AL981 10/100BaseTX", 0 },
224	{ DC_VENDORID_ADMTEK, DC_DEVICEID_AN985,
225	"ADMtek AN985 10/100BaseTX", 0 },
226	{ DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
227	"ASIX AX88140A 10/100BaseTX", 0 },
228	{ DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
229	"ASIX AX88141 10/100BaseTX", 0 },
230	{ DC_VENDORID_MX, DC_DEVICEID_98713,
231	"Macronix 98713 10/100BaseTX", 0 },
232	{ DC_VENDORID_MX, DC_DEVICEID_98713,
233	"Macronix 98713A 10/100BaseTX", 0 },
234	{ DC_VENDORID_CP, DC_DEVICEID_98713_CP,
235	"Compex RL100-TX 10/100BaseTX", 0 },
236	{ DC_VENDORID_CP, DC_DEVICEID_98713_CP,
237	"Compex RL100-TX 10/100BaseTX", 0 },
238	{ DC_VENDORID_MX, DC_DEVICEID_987x5,
239	"Macronix 98715/98715A 10/100BaseTX", 0 },
240	{ DC_VENDORID_MX, DC_DEVICEID_987x5,
241	"Macronix 98715AEC-C 10/100BaseTX", 0 },
242	{ DC_VENDORID_MX, DC_DEVICEID_987x5,
243	"Macronix 98725 10/100BaseTX", 0 },
244	{ DC_VENDORID_MX, DC_DEVICEID_98727,
245	"Macronix 98727/98732 10/100BaseTX", 0 },
246	{ DC_VENDORID_LO, DC_DEVICEID_82C115,
247	"LC82C115 PNIC II 10/100BaseTX", 0 },
248	{ DC_VENDORID_LO, DC_DEVICEID_82C168,
249	"82c168 PNIC 10/100BaseTX", 0 },
250	{ DC_VENDORID_LO, DC_DEVICEID_82C168,
251	"82c169 PNIC 10/100BaseTX", 0 },
252	{ DC_VENDORID_ACCTON, DC_DEVICEID_EN1217,
253	"Accton EN1217 10/100BaseTX", 0 },
254	{ DC_VENDORID_ACCTON, DC_DEVICEID_EN2242,
255	"Accton EN2242 MiniPCI 10/100BaseTX", 0 },
256	{ DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112,
257	"Conexant LANfinity MiniPCI 10/100BaseTX", 0 },
258	{ 0, 0, NULL, 0 }
259	};
260
261	#if 0
262	static int dc_probe __P((device_t));
263	static int dc_attach __P((device_t));
264	static int dc_detach __P((device_t));
265	static int dc_suspend __P((device_t));
266	static int dc_resume __P((device_t));
267	static void dc_shutdown __P((device_t));
268	static void dc_acpi __P((device_t));
269	#endif
270
271	static struct dc_type *dc_devtype(int);
272	static int dc_newbuf(struct dc_softc , int, struct mbuf );
273	static int dc_encap(struct dc_softc , struct mbuf ,
274	u_int32_t *);
275	static int dc_coal(struct dc_softc , struct mbuf *);
276	static void dc_pnic_rx_bug_war(struct dc_softc *, int);
277	static int dc_rx_resync(struct dc_softc *);
278	static void dc_rxeof(struct dc_softc *);
279	static void dc_txeof(struct dc_softc *);
280	/static void dc_tick((void ));*/
281	static void dc_tx_underrun(struct dc_softc *);
282	static rtems_isr dc_intr(rtems_vector_number);
283	static void dc_daemon(void *);
284	static void dc_start(struct ifnet *);
285	static int dc_ioctl(struct ifnet *, int, caddr_t);
286	static void dc_init(void *);
287	static void dc_stop(struct dc_softc *);
288	static void dc_watchdog(struct ifnet *);
289	#if 0
290	static int dc_ifmedia_upd __P((struct ifnet *));
291	static void dc_ifmedia_sts __P((struct ifnet , struct ifmediareq ));
292	#endif
293
294	static void dc_delay(struct dc_softc *);
295	static void dc_eeprom_idle(struct dc_softc *);
296	static void dc_eeprom_putbyte(struct dc_softc *, int);
297	static void dc_eeprom_getword(struct dc_softc , int, u_int16_t );
298	static void dc_eeprom_getword_pnic(struct dc_softc , int, u_int16_t );
299	static void dc_eeprom_width(struct dc_softc *);
300	static void dc_read_eeprom(struct dc_softc *, caddr_t, int,int, int);
301
302	#if 0
303	static void dc_mii_writebit __P((struct dc_softc *, int));
304	static int dc_mii_readbit __P((struct dc_softc *));
305	static void dc_mii_sync __P((struct dc_softc *));
306	static void dc_mii_send __P((struct dc_softc *, u_int32_t, int));
307	static int dc_mii_readreg __P((struct dc_softc , struct dc_mii_frame ));
308	static int dc_mii_writereg __P((struct dc_softc , struct dc_mii_frame ));
309	static int dc_miibus_readreg __P((device_t, int, int));
310	static int dc_miibus_writereg __P((device_t, int, int, int));
311	static void dc_miibus_statchg __P((device_t));
312	static void dc_miibus_mediainit __P((device_t));
313	#endif
314
315	static void dc_setcfg(struct dc_softc *, int);
316	static u_int32_t dc_crc_le(struct dc_softc *, caddr_t);
317	static u_int32_t dc_crc_be(caddr_t);
318	static void dc_setfilt_21143(struct dc_softc *);
319	static void dc_setfilt_asix(struct dc_softc *);
320	static void dc_setfilt_admtek(struct dc_softc *);
321	static void dc_setfilt(struct dc_softc *);
322	static void dc_reset(struct dc_softc *);
323	static int dc_list_rx_init(struct dc_softc *);
324	static int dc_list_tx_init(struct dc_softc *);
325	static void dc_read_srom(struct dc_softc *, int);
326	static void dc_parse_21143_srom(struct dc_softc *);
327	static void dc_apply_fixup(struct dc_softc *, int);
328
329	#if 0
330	static void dc_decode_leaf_sia __P((struct dc_softc *,
331	struct dc_eblock_sia *));
332	static void dc_decode_leaf_mii __P((struct dc_softc *,
333	struct dc_eblock_mii *));
334	static void dc_decode_leaf_sym __P((struct dc_softc *,
335	struct dc_eblock_sym *));
336	#endif
337
338
339	#ifdef DC_USEIOSPACE
340	#define DC_RES SYS_RES_IOPORT
341	#define DC_RID DC_PCI_CFBIO
342	#else
343	#define DC_RES SYS_RES_MEMORY
344	#define DC_RID DC_PCI_CFBMA
345	#endif
346
347	#if 0
348	static device_method_t dc_methods[] = {
349	/* Device interface */
350	DEVMETHOD(device_probe, dc_probe),
351	DEVMETHOD(device_attach, dc_attach),
352	DEVMETHOD(device_detach, dc_detach),
353	DEVMETHOD(device_suspend, dc_suspend),
354	DEVMETHOD(device_resume, dc_resume),
355	DEVMETHOD(device_shutdown, dc_shutdown),
356
357	/* bus interface */
358	DEVMETHOD(bus_print_child, bus_generic_print_child),
359	DEVMETHOD(bus_driver_added, bus_generic_driver_added),
360
361	/* MII interface */
362	DEVMETHOD(miibus_readreg, dc_miibus_readreg),
363	DEVMETHOD(miibus_writereg, dc_miibus_writereg),
364	DEVMETHOD(miibus_statchg, dc_miibus_statchg),
365	DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
366
367	{ 0, 0 }
368	};
369
370	static driver_t dc_driver = {
371	"dc",
372	dc_methods,
373	sizeof(struct dc_softc)
374	};
375
376	static devclass_t dc_devclass;
377	#endif
378
379
380	#ifdef __i386__
381	static int dc_quick=1;
382	#if 0
383	SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW,
384	&dc_quick,0,"do not mdevget in dc driver");
385	#endif
386	#endif
387
388	#if 0
389	DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0);
390	DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
391	#endif
392
393
394	#define DC_SETBIT(sc, reg, x) \
395	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) \| (x))
396
397	#define DC_CLRBIT(sc, reg, x) \
398	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
399
400	#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
401	#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
402
403
404	/* XXX Fixme: rtems_bsp_delay( ) for the pc386 BSP (at least)
405	* needs work... see pc386/include/bsp.h.
406	* I have "a" solution, utilizing the 2nd i8254 timer,
407	* if anyone is interested (first timer is used for clock_tick ISR)...
408	*/
409	#ifdef __i386__
410	extern void Wait_X_ms( unsigned int );
411	#define DELAY(n) Wait_X_ms( (unsigned int)((n)/100) )
412	#else
413	#define DELAY(n) rtems_bsp_delay(n)
414	#endif
415
416
417	static void dc_delay(sc)
418	struct dc_softc *sc;
419	{
420	int idx;
421
422	for (idx = (300 / 33) + 1; idx > 0; idx--)
423	CSR_READ_4(sc, DC_BUSCTL);
424	}
425
426	static void dc_eeprom_width(sc)
427	struct dc_softc *sc;
428	{
429	int i;
430
431	/* Force EEPROM to idle state. */
432	dc_eeprom_idle(sc);
433
434	/* Enter EEPROM access mode. */
435	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
436	dc_delay(sc);
437	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
438	dc_delay(sc);
439	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
440	dc_delay(sc);
441	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
442	dc_delay(sc);
443
444	for (i = 3; i--;) {
445	if (6 & (1 << i))
446	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
447	else
448	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
449	dc_delay(sc);
450	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
451	dc_delay(sc);
452	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
453	dc_delay(sc);
454	}
455
456	for (i = 1; i <= 12; i++) {
457	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
458	dc_delay(sc);
459	if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
460	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
461	dc_delay(sc);
462	break;
463	}
464	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
465	dc_delay(sc);
466	}
467
468	/* Turn off EEPROM access mode. */
469	dc_eeprom_idle(sc);
470
471	if (i < 4 \|\| i > 12)
472	sc->dc_romwidth = 6;
473	else
474	sc->dc_romwidth = i;
475
476	/* Enter EEPROM access mode. */
477	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
478	dc_delay(sc);
479	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
480	dc_delay(sc);
481	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
482	dc_delay(sc);
483	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
484	dc_delay(sc);
485
486	/* Turn off EEPROM access mode. */
487	dc_eeprom_idle(sc);
488	}
489
490	static void dc_eeprom_idle(sc)
491	struct dc_softc *sc;
492	{
493	register int i;
494
495	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
496	dc_delay(sc);
497	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
498	dc_delay(sc);
499	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
500	dc_delay(sc);
501	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
502	dc_delay(sc);
503
504	for (i = 0; i < 25; i++) {
505	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
506	dc_delay(sc);
507	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
508	dc_delay(sc);
509	}
510
511	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
512	dc_delay(sc);
513	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
514	dc_delay(sc);
515	CSR_WRITE_4(sc, DC_SIO, 0x00000000);
516
517	return;
518	}
519
520	/*
521	* Send a read command and address to the EEPROM, check for ACK.
522	*/
523	static void dc_eeprom_putbyte(sc, addr)
524	struct dc_softc *sc;
525	int addr;
526	{
527	register int d, i;
528
529	d = DC_EECMD_READ >> 6;
530	for (i = 3; i--; ) {
531	if (d & (1 << i))
532	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
533	else
534	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
535	dc_delay(sc);
536	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
537	dc_delay(sc);
538	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
539	dc_delay(sc);
540	}
541
542	/*
543	* Feed in each bit and strobe the clock.
544	*/
545	for (i = sc->dc_romwidth; i--;) {
546	if (addr & (1 << i)) {
547	SIO_SET(DC_SIO_EE_DATAIN);
548	} else {
549	SIO_CLR(DC_SIO_EE_DATAIN);
550	}
551	dc_delay(sc);
552	SIO_SET(DC_SIO_EE_CLK);
553	dc_delay(sc);
554	SIO_CLR(DC_SIO_EE_CLK);
555	dc_delay(sc);
556	}
557
558	return;
559	}
560
561	/*
562	* Read a word of data stored in the EEPROM at address 'addr.'
563	* The PNIC 82c168/82c169 has its own non-standard way to read
564	* the EEPROM.
565	*/
566	static void dc_eeprom_getword_pnic(sc, addr, dest)
567	struct dc_softc *sc;
568	int addr;
569	u_int16_t *dest;
570	{
571	register int i;
572	u_int32_t r;
573
574	CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ\|addr);
575
576	for (i = 0; i < DC_TIMEOUT; i++) {
577	DELAY(1);
578	r = CSR_READ_4(sc, DC_SIO);
579	if (!(r & DC_PN_SIOCTL_BUSY)) {
580	*dest = (u_int16_t)(r & 0xFFFF);
581	return;
582	}
583	}
584
585	return;
586	}
587
588	/*
589	* Read a word of data stored in the EEPROM at address 'addr.'
590	*/
591	static void dc_eeprom_getword(sc, addr, dest)
592	struct dc_softc *sc;
593	int addr;
594	u_int16_t *dest;
595	{
596	register int i;
597	u_int16_t word = 0;
598
599	/* Force EEPROM to idle state. */
600	dc_eeprom_idle(sc);
601
602	/* Enter EEPROM access mode. */
603	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
604	dc_delay(sc);
605	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
606	dc_delay(sc);
607	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
608	dc_delay(sc);
609	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
610	dc_delay(sc);
611
612	/*
613	* Send address of word we want to read.
614	*/
615	dc_eeprom_putbyte(sc, addr);
616
617	/*
618	* Start reading bits from EEPROM.
619	*/
620	for (i = 0x8000; i; i >>= 1) {
621	SIO_SET(DC_SIO_EE_CLK);
622	dc_delay(sc);
623	if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
624	word \|= i;
625	dc_delay(sc);
626	SIO_CLR(DC_SIO_EE_CLK);
627	dc_delay(sc);
628	}
629
630	/* Turn off EEPROM access mode. */
631	dc_eeprom_idle(sc);
632
633	*dest = word;
634
635	return;
636	}
637
638	/*
639	* Read a sequence of words from the EEPROM.
640	*/
641	static void dc_read_eeprom(sc, dest, off, cnt, swap)
642	struct dc_softc *sc;
643	caddr_t dest;
644	int off;
645	int cnt;
646	int swap;
647	{
648	int i;
649	u_int16_t word = 0, *ptr;
650
651	for (i = 0; i < cnt; i++) {
652	if (DC_IS_PNIC(sc))
653	dc_eeprom_getword_pnic(sc, off + i, &word);
654	else
655	dc_eeprom_getword(sc, off + i, &word);
656	ptr = (u_int16_t )(dest + (i 2));
657	if (swap)
658	*ptr = ntohs(word);
659	else
660	*ptr = word;
661	}
662
663	return;
664	}
665
666
667	#if 0
668	/*
669	* The following two routines are taken from the Macronix 98713
670	* Application Notes pp.19-21.
671	*/
672	/*
673	* Write a bit to the MII bus.
674	*/
675	static void dc_mii_writebit(sc, bit)
676	struct dc_softc *sc;
677	int bit;
678	{
679	if (bit)
680	CSR_WRITE_4(sc, DC_SIO,
681	DC_SIO_ROMCTL_WRITE\|DC_SIO_MII_DATAOUT);
682	else
683	CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
684
685	DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
686	DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
687
688	return;
689	}
690
691	/*
692	* Read a bit from the MII bus.
693	*/
694	static int dc_mii_readbit(sc)
695	struct dc_softc *sc;
696	{
697	CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ\|DC_SIO_MII_DIR);
698	CSR_READ_4(sc, DC_SIO);
699	DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
700	DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
701	if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
702	return(1);
703
704	return(0);
705	}
706
707	/*
708	* Sync the PHYs by setting data bit and strobing the clock 32 times.
709	*/
710	static void dc_mii_sync(sc)
711	struct dc_softc *sc;
712	{
713	register int i;
714
715	CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
716
717	for (i = 0; i < 32; i++)
718	dc_mii_writebit(sc, 1);
719
720	return;
721	}
722
723	/*
724	* Clock a series of bits through the MII.
725	*/
726	static void dc_mii_send(sc, bits, cnt)
727	struct dc_softc *sc;
728	u_int32_t bits;
729	int cnt;
730	{
731	int i;
732
733	for (i = (0x1 << (cnt - 1)); i; i >>= 1)
734	dc_mii_writebit(sc, bits & i);
735	}
736
737	/*
738	* Read an PHY register through the MII.
739	*/
740	static int dc_mii_readreg(sc, frame)
741	struct dc_softc *sc;
742	struct dc_mii_frame *frame;
743
744	{
745	int i, ack, s;
746
747
748	/*
749	* Set up frame for RX.
750	*/
751	frame->mii_stdelim = DC_MII_STARTDELIM;
752	frame->mii_opcode = DC_MII_READOP;
753	frame->mii_turnaround = 0;
754	frame->mii_data = 0;
755
756	/*
757	* Sync the PHYs.
758	*/
759	dc_mii_sync(sc);
760
761	/*
762	* Send command/address info.
763	*/
764	dc_mii_send(sc, frame->mii_stdelim, 2);
765	dc_mii_send(sc, frame->mii_opcode, 2);
766	dc_mii_send(sc, frame->mii_phyaddr, 5);
767	dc_mii_send(sc, frame->mii_regaddr, 5);
768
769	#ifdef notdef
770	/* Idle bit */
771	dc_mii_writebit(sc, 1);
772	dc_mii_writebit(sc, 0);
773	#endif
774
775	/* Check for ack */
776	ack = dc_mii_readbit(sc);
777
778	/*
779	* Now try reading data bits. If the ack failed, we still
780	* need to clock through 16 cycles to keep the PHY(s) in sync.
781	*/
782	if (ack) {
783	for(i = 0; i < 16; i++) {
784	dc_mii_readbit(sc);
785	}
786	goto fail;
787	}
788
789	for (i = 0x8000; i; i >>= 1) {
790	if (!ack) {
791	if (dc_mii_readbit(sc))
792	frame->mii_data \|= i;
793	}
794	}
795
796	fail:
797
798	dc_mii_writebit(sc, 0);
799	dc_mii_writebit(sc, 0);
800
801
802	if (ack)
803	return(1);
804	return(0);
805	}
806
807	/*
808	* Write to a PHY register through the MII.
809	*/
810	static int dc_mii_writereg(sc, frame)
811	struct dc_softc *sc;
812	struct dc_mii_frame *frame;
813
814	{
815	int s;
816
817	/*
818	* Set up frame for TX.
819	*/
820
821	frame->mii_stdelim = DC_MII_STARTDELIM;
822	frame->mii_opcode = DC_MII_WRITEOP;
823	frame->mii_turnaround = DC_MII_TURNAROUND;
824
825	/*
826	* Sync the PHYs.
827	*/
828	dc_mii_sync(sc);
829
830	dc_mii_send(sc, frame->mii_stdelim, 2);
831	dc_mii_send(sc, frame->mii_opcode, 2);
832	dc_mii_send(sc, frame->mii_phyaddr, 5);
833	dc_mii_send(sc, frame->mii_regaddr, 5);
834	dc_mii_send(sc, frame->mii_turnaround, 2);
835	dc_mii_send(sc, frame->mii_data, 16);
836
837	/* Idle bit. */
838	dc_mii_writebit(sc, 0);
839	dc_mii_writebit(sc, 0);
840
841
842	return(0);
843	}
844
845	static int dc_miibus_readreg(dev, phy, reg)
846	device_t dev;
847	int phy, reg;
848	{
849	struct dc_mii_frame frame;
850	struct dc_softc *sc;
851	int i, rval, phy_reg = 0;
852
853	sc = device_get_softc(dev);
854	bzero((char *)&frame, sizeof(frame));
855
856	/*
857	* Note: both the AL981 and AN985 have internal PHYs,
858	* however the AL981 provides direct access to the PHY
859	* registers while the AN985 uses a serial MII interface.
860	* The AN985's MII interface is also buggy in that you
861	* can read from any MII address (0 to 31), but only address 1
862	* behaves normally. To deal with both cases, we pretend
863	* that the PHY is at MII address 1.
864	*/
865	if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
866	return(0);
867
868	/*
869	* Note: the ukphy probes of the RS7112 report a PHY at
870	* MII address 0 (possibly HomePNA?) and 1 (ethernet)
871	* so we only respond to correct one.
872	*/
873	if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
874	return(0);
875
876	if (sc->dc_pmode != DC_PMODE_MII) {
877	if (phy == (MII_NPHY - 1)) {
878	switch(reg) {
879	case MII_BMSR:
880	/*
881	* Fake something to make the probe
882	* code think there's a PHY here.
883	*/
884	return(BMSR_MEDIAMASK);
885	break;
886	case MII_PHYIDR1:
887	if (DC_IS_PNIC(sc))
888	return(DC_VENDORID_LO);
889	return(DC_VENDORID_DEC);
890	break;
891	case MII_PHYIDR2:
892	if (DC_IS_PNIC(sc))
893	return(DC_DEVICEID_82C168);
894	return(DC_DEVICEID_21143);
895	break;
896	default:
897	return(0);
898	break;
899	}
900	} else
901	return(0);
902	}
903
904	if (DC_IS_PNIC(sc)) {
905	CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ \|
906	(phy << 23) \| (reg << 18));
907	for (i = 0; i < DC_TIMEOUT; i++) {
908	DELAY(1);
909	rval = CSR_READ_4(sc, DC_PN_MII);
910	if (!(rval & DC_PN_MII_BUSY)) {
911	rval &= 0xFFFF;
912	return(rval == 0xFFFF ? 0 : rval);
913	}
914	}
915	return(0);
916	}
917
918	if (DC_IS_COMET(sc)) {
919	switch(reg) {
920	case MII_BMCR:
921	phy_reg = DC_AL_BMCR;
922	break;
923	case MII_BMSR:
924	phy_reg = DC_AL_BMSR;
925	break;
926	case MII_PHYIDR1:
927	phy_reg = DC_AL_VENID;
928	break;
929	case MII_PHYIDR2:
930	phy_reg = DC_AL_DEVID;
931	break;
932	case MII_ANAR:
933	phy_reg = DC_AL_ANAR;
934	break;
935	case MII_ANLPAR:
936	phy_reg = DC_AL_LPAR;
937	break;
938	case MII_ANER:
939	phy_reg = DC_AL_ANER;
940	break;
941	default:
942	printk("dc%d: phy_read: bad phy register %x\n",
943	sc->dc_unit, reg);
944	return(0);
945	break;
946	}
947
948	rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
949
950	if (rval == 0xFFFF)
951	return(0);
952	return(rval);
953	}
954
955	frame.mii_phyaddr = phy;
956	frame.mii_regaddr = reg;
957	if (sc->dc_type == DC_TYPE_98713) {
958	phy_reg = CSR_READ_4(sc, DC_NETCFG);
959	CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
960	}
961	dc_mii_readreg(sc, &frame);
962	if (sc->dc_type == DC_TYPE_98713)
963	CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
964
965	return(frame.mii_data);
966	}
967
968	static int dc_miibus_writereg(dev, phy, reg, data)
969	device_t dev;
970	int phy, reg, data;
971	{
972	struct dc_softc *sc;
973	struct dc_mii_frame frame;
974	int i, phy_reg = 0;
975
976	sc = device_get_softc(dev);
977	bzero((char *)&frame, sizeof(frame));
978
979	if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
980	return(0);
981
982	if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
983	return(0);
984
985	if (DC_IS_PNIC(sc)) {
986	CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE \|
987	(phy << 23) \| (reg << 10) \| data);
988	for (i = 0; i < DC_TIMEOUT; i++) {
989	if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
990	break;
991	}
992	return(0);
993	}
994
995	if (DC_IS_COMET(sc)) {
996	switch(reg) {
997	case MII_BMCR:
998	phy_reg = DC_AL_BMCR;
999	break;
1000	case MII_BMSR:
1001	phy_reg = DC_AL_BMSR;
1002	break;
1003	case MII_PHYIDR1:
1004	phy_reg = DC_AL_VENID;
1005	break;
1006	case MII_PHYIDR2:
1007	phy_reg = DC_AL_DEVID;
1008	break;
1009	case MII_ANAR:
1010	phy_reg = DC_AL_ANAR;
1011	break;
1012	case MII_ANLPAR:
1013	phy_reg = DC_AL_LPAR;
1014	break;
1015	case MII_ANER:
1016	phy_reg = DC_AL_ANER;
1017	break;
1018	default:
1019	printk("dc%d: phy_write: bad phy register %x\n",
1020	sc->dc_unit, reg);
1021	return(0);
1022	break;
1023	}
1024
1025	CSR_WRITE_4(sc, phy_reg, data);
1026	return(0);
1027	}
1028
1029	frame.mii_phyaddr = phy;
1030	frame.mii_regaddr = reg;
1031	frame.mii_data = data;
1032
1033	if (sc->dc_type == DC_TYPE_98713) {
1034	phy_reg = CSR_READ_4(sc, DC_NETCFG);
1035	CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
1036	}
1037	dc_mii_writereg(sc, &frame);
1038	if (sc->dc_type == DC_TYPE_98713)
1039	CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
1040
1041	return(0);
1042	}
1043
1044	static void dc_miibus_statchg(dev)
1045	device_t dev;
1046	{
1047	struct dc_softc *sc;
1048	struct mii_data *mii;
1049	struct ifmedia *ifm;
1050
1051	sc = device_get_softc(dev);
1052	if (DC_IS_ADMTEK(sc))
1053	return;
1054
1055	mii = device_get_softc(sc->dc_miibus);
1056	ifm = &mii->mii_media;
1057	if (DC_IS_DAVICOM(sc) &&
1058	IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) {
1059	dc_setcfg(sc, ifm->ifm_media);
1060	sc->dc_if_media = ifm->ifm_media;
1061	} else {
1062	dc_setcfg(sc, mii->mii_media_active);
1063	sc->dc_if_media = mii->mii_media_active;
1064	}
1065
1066	return;
1067	}
1068
1069	/*
1070	* Special support for DM9102A cards with HomePNA PHYs. Note:
1071	* with the Davicom DM9102A/DM9801 eval board that I have, it seems
1072	* to be impossible to talk to the management interface of the DM9801
1073	* PHY (its MDIO pin is not connected to anything). Consequently,
1074	* the driver has to just 'know' about the additional mode and deal
1075	* with it itself. sigh
1076	*/
1077	static void dc_miibus_mediainit(dev)
1078	device_t dev;
1079	{
1080	struct dc_softc *sc;
1081	struct mii_data *mii;
1082	struct ifmedia *ifm;
1083	int rev;
1084
1085	rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF;
1086
1087	sc = device_get_softc(dev);
1088	mii = device_get_softc(sc->dc_miibus);
1089	ifm = &mii->mii_media;
1090
1091	if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
1092	ifmedia_add(ifm, IFM_ETHER\|IFM_homePNA, 0, NULL);
1093
1094	return;
1095	}
1096	#endif
1097
1098	#define DC_POLY 0xEDB88320
1099	#define DC_BITS_512 9
1100	#define DC_BITS_128 7
1101	#define DC_BITS_64 6
1102
1103	static u_int32_t dc_crc_le(sc, addr)
1104	struct dc_softc *sc;
1105	caddr_t addr;
1106	{
1107	u_int32_t idx, bit, data, crc;
1108
1109	/* Compute CRC for the address value. */
1110	crc = 0xFFFFFFFF; /* initial value */
1111
1112	for (idx = 0; idx < 6; idx++) {
1113	for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
1114	crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0);
1115	}
1116
1117	/*
1118	* The hash table on the PNIC II and the MX98715AEC-C/D/E
1119	* chips is only 128 bits wide.
1120	*/
1121	if (sc->dc_flags & DC_128BIT_HASH)
1122	return (crc & ((1 << DC_BITS_128) - 1));
1123
1124	/* The hash table on the MX98715BEC is only 64 bits wide. */
1125	if (sc->dc_flags & DC_64BIT_HASH)
1126	return (crc & ((1 << DC_BITS_64) - 1));
1127
1128	return (crc & ((1 << DC_BITS_512) - 1));
1129	}
1130
1131	/*
1132	* Calculate CRC of a multicast group address, return the lower 6 bits.
1133	*/
1134	static u_int32_t dc_crc_be(addr)
1135	caddr_t addr;
1136	{
1137	u_int32_t crc, carry;
1138	int i, j;
1139	u_int8_t c;
1140
1141	/* Compute CRC for the address value. */
1142	crc = 0xFFFFFFFF; /* initial value */
1143
1144	for (i = 0; i < 6; i++) {
1145	c = *(addr + i);
1146	for (j = 0; j < 8; j++) {
1147	carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
1148	crc <<= 1;
1149	c >>= 1;
1150	if (carry)
1151	crc = (crc ^ 0x04c11db6) \| carry;
1152	}
1153	}
1154
1155	/* return the filter bit position */
1156	return((crc >> 26) & 0x0000003F);
1157	}
1158
1159
1160	/*
1161	* 21143-style RX filter setup routine. Filter programming is done by
1162	* downloading a special setup frame into the TX engine. 21143, Macronix,
1163	* PNIC, PNIC II and Davicom chips are programmed this way.
1164	*
1165	* We always program the chip using 'hash perfect' mode, i.e. one perfect
1166	* address (our node address) and a 512-bit hash filter for multicast
1167	* frames. We also sneak the broadcast address into the hash filter since
1168	* we need that too.
1169	*/
1170	void dc_setfilt_21143(sc)
1171	struct dc_softc *sc;
1172	{
1173	struct dc_desc *sframe;
1174	u_int32_t h, *sp;
1175	/struct ifmultiaddr ifma;*/
1176	struct ifnet *ifp;
1177	int i;
1178
1179	ifp = &sc->arpcom.ac_if;
1180
1181	i = sc->dc_cdata.dc_tx_prod;
1182	DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1183	sc->dc_cdata.dc_tx_cnt++;
1184	sframe = &sc->dc_ldata->dc_tx_list[i];
1185	sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf;
1186	bzero((char *)sp, DC_SFRAME_LEN);
1187
1188	sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf);
1189	sframe->dc_ctl = DC_SFRAME_LEN \| DC_TXCTL_SETUP \| DC_TXCTL_TLINK \|
1190	DC_FILTER_HASHPERF \| DC_TXCTL_FINT;
1191
1192	sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf;
1193
1194	/* If we want promiscuous mode, set the allframes bit. */
1195	if (ifp->if_flags & IFF_PROMISC)
1196	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1197	else
1198	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1199
1200	if (ifp->if_flags & IFF_ALLMULTI)
1201	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1202	else
1203	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1204	#if 0
1205	for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1206	ifma = ifma->ifma_link.le_next) {
1207	if (ifma->ifma_addr->sa_family != AF_LINK)
1208	continue;
1209	h = dc_crc_le(sc,
1210	LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1211	sp[h >> 4] \|= 1 << (h & 0xF);
1212	}
1213	#endif
1214
1215	if (ifp->if_flags & IFF_BROADCAST) {
1216	h = dc_crc_le(sc, (caddr_t)&etherbroadcastaddr);
1217	sp[h >> 4] \|= 1 << (h & 0xF);
1218	}
1219
1220	/* Set our MAC address */
1221	sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0];
1222	sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1];
1223	sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2];
1224
1225	sframe->dc_status = DC_TXSTAT_OWN;
1226	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1227
1228	/*
1229	* The PNIC takes an exceedingly long time to process its
1230	* setup frame; wait 10ms after posting the setup frame
1231	* before proceeding, just so it has time to swallow its
1232	* medicine.
1233	*/
1234	DELAY(10000);
1235
1236	ifp->if_timer = 5;
1237
1238	return;
1239	}
1240
1241	void dc_setfilt_admtek(sc)
1242	struct dc_softc *sc;
1243	{
1244	struct ifnet *ifp;
1245	#if 0
1246	int h = 0;
1247	u_int32_t hashes[2] = { 0, 0 };
1248	struct ifmultiaddr *ifma;
1249	#endif
1250
1251	ifp = &sc->arpcom.ac_if;
1252
1253	/* Init our MAC address */
1254	CSR_WRITE_4(sc, DC_AL_PAR0, (u_int32_t )(&sc->arpcom.ac_enaddr[0]));
1255	CSR_WRITE_4(sc, DC_AL_PAR1, (u_int32_t )(&sc->arpcom.ac_enaddr[4]));
1256
1257	/* If we want promiscuous mode, set the allframes bit. */
1258	if (ifp->if_flags & IFF_PROMISC)
1259	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1260	else
1261	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1262
1263	if (ifp->if_flags & IFF_ALLMULTI)
1264	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1265	else
1266	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1267
1268	/* first, zot all the existing hash bits */
1269	CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1270	CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1271
1272	#if 0
1273	/*
1274	* If we're already in promisc or allmulti mode, we
1275	* don't have to bother programming the multicast filter.
1276	*/
1277	if (ifp->if_flags & (IFF_PROMISC\|IFF_ALLMULTI))
1278	return;
1279
1280	/* now program new ones */
1281	for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1282	ifma = ifma->ifma_link.le_next) {
1283	if (ifma->ifma_addr->sa_family != AF_LINK)
1284	continue;
1285	h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1286	if (h < 32)
1287	hashes[0] \|= (1 << h);
1288	else
1289	hashes[1] \|= (1 << (h - 32));
1290	}
1291
1292	CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1293	CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1294	#endif
1295	return;
1296	}
1297
1298	void dc_setfilt_asix(sc)
1299	struct dc_softc *sc;
1300	{
1301	struct ifnet *ifp;
1302	#if 0
1303	int h = 0;
1304	u_int32_t hashes[2] = { 0, 0 };
1305	struct ifmultiaddr *ifma;
1306	#endif
1307
1308	ifp = &sc->arpcom.ac_if;
1309
1310	/* Init our MAC address */
1311	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1312	CSR_WRITE_4(sc, DC_AX_FILTDATA,
1313	(u_int32_t )(&sc->arpcom.ac_enaddr[0]));
1314	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1315	CSR_WRITE_4(sc, DC_AX_FILTDATA,
1316	(u_int32_t )(&sc->arpcom.ac_enaddr[4]));
1317
1318	/* If we want promiscuous mode, set the allframes bit. */
1319	if (ifp->if_flags & IFF_PROMISC)
1320	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1321	else
1322	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1323
1324	if (ifp->if_flags & IFF_ALLMULTI)
1325	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1326	else
1327	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1328
1329	/*
1330	* The ASIX chip has a special bit to enable reception
1331	* of broadcast frames.
1332	*/
1333	if (ifp->if_flags & IFF_BROADCAST)
1334	DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1335	else
1336	DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1337
1338	/* first, zot all the existing hash bits */
1339	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1340	CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1341	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1342	CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1343
1344	#if 0
1345	/*
1346	* If we're already in promisc or allmulti mode, we
1347	* don't have to bother programming the multicast filter.
1348	*/
1349	if (ifp->if_flags & (IFF_PROMISC\|IFF_ALLMULTI))
1350	return;
1351
1352	/* now program new ones */
1353	for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1354	ifma = ifma->ifma_link.le_next) {
1355	if (ifma->ifma_addr->sa_family != AF_LINK)
1356	continue;
1357	h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1358	if (h < 32)
1359	hashes[0] \|= (1 << h);
1360	else
1361	hashes[1] \|= (1 << (h - 32));
1362	}
1363
1364	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1365	CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1366	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1367	CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1368	#endif
1369	return;
1370	}
1371
1372	static void dc_setfilt(sc)
1373	struct dc_softc *sc;
1374	{
1375	if (DC_IS_INTEL(sc) \|\| DC_IS_MACRONIX(sc) \|\| DC_IS_PNIC(sc) \|\|
1376	DC_IS_PNICII(sc) \|\| DC_IS_DAVICOM(sc) \|\| DC_IS_CONEXANT(sc))
1377	dc_setfilt_21143(sc);
1378
1379	if (DC_IS_ASIX(sc))
1380	dc_setfilt_asix(sc);
1381
1382	if (DC_IS_ADMTEK(sc))
1383	dc_setfilt_admtek(sc);
1384
1385	return;
1386	}
1387
1388	/*
1389	* In order to fiddle with the
1390	* 'full-duplex' and '100Mbps' bits in the netconfig register, we
1391	* first have to put the transmit and/or receive logic in the idle state.
1392	*/
1393	static void dc_setcfg(sc, media)
1394	struct dc_softc *sc;
1395	int media;
1396	{
1397	int i, restart = 0;
1398	u_int32_t isr;
1399
1400	if (IFM_SUBTYPE(media) == IFM_NONE)
1401	return;
1402
1403	if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON\|DC_NETCFG_RX_ON)) {
1404	restart = 1;
1405	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON\|DC_NETCFG_RX_ON));
1406
1407	for (i = 0; i < DC_TIMEOUT; i++) {
1408	isr = CSR_READ_4(sc, DC_ISR);
1409	if (isr & DC_ISR_TX_IDLE \|\|
1410	(isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED)
1411	break;
1412	DELAY(10);
1413	}
1414
1415	if (i == DC_TIMEOUT)
1416	printk("dc%d: failed to force tx and "
1417	"rx to idle state\n", sc->dc_unit);
1418	}
1419
1420	if (IFM_SUBTYPE(media) == IFM_100_TX) {
1421	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1422	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1423	if (sc->dc_pmode == DC_PMODE_MII) {
1424	int watchdogreg;
1425
1426	if (DC_IS_INTEL(sc)) {
1427	/* there's a write enable bit here that reads as 1 */
1428	watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1429	watchdogreg &= ~DC_WDOG_CTLWREN;
1430	watchdogreg \|= DC_WDOG_JABBERDIS;
1431	CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1432	} else {
1433	DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1434	}
1435	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS\|
1436	DC_NETCFG_PORTSEL\|DC_NETCFG_SCRAMBLER));
1437	if (sc->dc_type == DC_TYPE_98713)
1438	DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS\|
1439	DC_NETCFG_SCRAMBLER));
1440	if (!DC_IS_DAVICOM(sc))
1441	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1442	DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1443	if (DC_IS_INTEL(sc))
1444	dc_apply_fixup(sc, IFM_AUTO);
1445	} else {
1446	if (DC_IS_PNIC(sc)) {
1447	DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1448	DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1449	DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1450	}
1451	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1452	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1453	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1454	if (DC_IS_INTEL(sc))
1455	dc_apply_fixup(sc,
1456	(media & IFM_GMASK) == IFM_FDX ?
1457	IFM_100_TX\|IFM_FDX : IFM_100_TX);
1458	}
1459	}
1460
1461	if (IFM_SUBTYPE(media) == IFM_10_T) {
1462	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1463	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1464	if (sc->dc_pmode == DC_PMODE_MII) {
1465	int watchdogreg;
1466
1467	/* there's a write enable bit here that reads as 1 */
1468	if (DC_IS_INTEL(sc)) {
1469	watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1470	watchdogreg &= ~DC_WDOG_CTLWREN;
1471	watchdogreg \|= DC_WDOG_JABBERDIS;
1472	CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1473	} else {
1474	DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1475	}
1476	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS\|
1477	DC_NETCFG_PORTSEL\|DC_NETCFG_SCRAMBLER));
1478	if (sc->dc_type == DC_TYPE_98713)
1479	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1480	if (!DC_IS_DAVICOM(sc))
1481	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1482	DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1483	if (DC_IS_INTEL(sc))
1484	dc_apply_fixup(sc, IFM_AUTO);
1485	} else {
1486	if (DC_IS_PNIC(sc)) {
1487	DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1488	DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1489	DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1490	}
1491	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1492	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1493	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1494	if (DC_IS_INTEL(sc)) {
1495	DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1496	DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1497	if ((media & IFM_GMASK) == IFM_FDX)
1498	DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1499	else
1500	DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1501	DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1502	DC_CLRBIT(sc, DC_10BTCTRL,
1503	DC_TCTL_AUTONEGENBL);
1504	dc_apply_fixup(sc,
1505	(media & IFM_GMASK) == IFM_FDX ?
1506	IFM_10_T\|IFM_FDX : IFM_10_T);
1507	DELAY(20000);
1508	}
1509	}
1510	}
1511
1512	#if 0
1513	/*
1514	* If this is a Davicom DM9102A card with a DM9801 HomePNA
1515	* PHY and we want HomePNA mode, set the portsel bit to turn
1516	* on the external MII port.
1517	*/
1518	if (DC_IS_DAVICOM(sc)) {
1519	if (IFM_SUBTYPE(media) == IFM_homePNA) {
1520	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1521	sc->dc_link = 1;
1522	} else {
1523	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1524	}
1525	}
1526	#endif
1527
1528	if ((media & IFM_GMASK) == IFM_FDX) {
1529	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1530	if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1531	DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1532	} else {
1533	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1534	if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1535	DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1536	}
1537
1538	if (restart)
1539	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON\|DC_NETCFG_RX_ON);
1540
1541	return;
1542	}
1543
1544	static void dc_reset(sc)
1545	struct dc_softc *sc;
1546	{
1547	register int i;
1548
1549	DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1550
1551	for (i = 0; i < DC_TIMEOUT; i++) {
1552	DELAY(10);
1553	if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1554	break;
1555	}
1556
1557	if (DC_IS_ASIX(sc) \|\| DC_IS_ADMTEK(sc) \|\| DC_IS_CONEXANT(sc)) {
1558	DELAY(10000);
1559	DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1560	i = 0;
1561	}
1562
1563	if (i == DC_TIMEOUT)
1564	printk("dc%d: reset never completed!\n", sc->dc_unit);
1565
1566	/* Wait a little while for the chip to get its brains in order. */
1567	DELAY(1000);
1568
1569	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1570	CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1571	CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1572
1573	/*
1574	* Bring the SIA out of reset. In some cases, it looks
1575	* like failing to unreset the SIA soon enough gets it
1576	* into a state where it will never come out of reset
1577	* until we reset the whole chip again.
1578	*/
1579	if (DC_IS_INTEL(sc)) {
1580	DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1581	CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1582	CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1583	}
1584
1585	return;
1586	}
1587
1588	static
1589	struct dc_type *dc_devtype( int unitnum )
1590	{
1591	struct dc_type *t;
1592	u_int32_t rev;
1593	int rc;
1594
1595
1596	t = dc_devs;
1597
1598	while(t->dc_name != NULL) {
1599	rc = pcib_find_by_devid(t->dc_vid, t->dc_did, \
1600	(unitnum - 1), &t->dc_devsig);
1601	if (rc == PCIB_ERR_SUCCESS) {
1602	/* Check the PCI revision */
1603	pcib_conf_read32(t->dc_devsig, DC_PCI_CFRV, &rev);
1604	rev &= 0xFF;
1605	if (t->dc_did == DC_DEVICEID_98713 &&
1606	rev >= DC_REVISION_98713A)
1607	t++;
1608	if (t->dc_did == DC_DEVICEID_98713_CP &&
1609	rev >= DC_REVISION_98713A)
1610	t++;
1611	if (t->dc_did == DC_DEVICEID_987x5 &&
1612	rev >= DC_REVISION_98715AEC_C)
1613	t++;
1614	if (t->dc_did == DC_DEVICEID_987x5 &&
1615	rev >= DC_REVISION_98725)
1616	t++;
1617	if (t->dc_did == DC_DEVICEID_AX88140A &&
1618	rev >= DC_REVISION_88141)
1619	t++;
1620	if (t->dc_did == DC_DEVICEID_82C168 &&
1621	rev >= DC_REVISION_82C169)
1622	t++;
1623	if (t->dc_did == DC_DEVICEID_DM9102 &&
1624	rev >= DC_REVISION_DM9102A)
1625	t++;
1626	return(t);
1627	}
1628	t++;
1629	}
1630
1631	return(NULL);
1632	}
1633
1634	#if 0
1635	/*
1636	* Probe for a 21143 or clone chip. Check the PCI vendor and device
1637	* IDs against our list and return a device name if we find a match.
1638	* We do a little bit of extra work to identify the exact type of
1639	* chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1640	* but different revision IDs. The same is true for 98715/98715A
1641	* chips and the 98725, as well as the ASIX and ADMtek chips. In some
1642	* cases, the exact chip revision affects driver behavior.
1643	*/
1644	static int dc_probe(dev)
1645	device_t dev;
1646	{
1647	struct dc_type *t;
1648
1649	t = dc_devtype(dev);
1650
1651	if (t != NULL) {
1652	device_set_desc(dev, t->dc_name);
1653	return(0);
1654	}
1655
1656	return(ENXIO);
1657	}
1658
1659
1660	static void dc_acpi(dev)
1661	device_t dev;
1662	{
1663	u_int32_t r, cptr;
1664	int unit;
1665
1666	unit = device_get_unit(dev);
1667
1668	/* Find the location of the capabilities block */
1669	cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF;
1670
1671	r = pci_read_config(dev, cptr, 4) & 0xFF;
1672	if (r == 0x01) {
1673
1674	r = pci_read_config(dev, cptr + 4, 4);
1675	if (r & DC_PSTATE_D3) {
1676	u_int32_t iobase, membase, irq;
1677
1678	/* Save important PCI config data. */
1679	iobase = pci_read_config(dev, DC_PCI_CFBIO, 4);
1680	membase = pci_read_config(dev, DC_PCI_CFBMA, 4);
1681	irq = pci_read_config(dev, DC_PCI_CFIT, 4);
1682
1683	/* Reset the power state. */
1684	printk("dc%d: chip is in D%d power mode "
1685	"-- setting to D0\n", unit, r & DC_PSTATE_D3);
1686	r &= 0xFFFFFFFC;
1687	pci_write_config(dev, cptr + 4, r, 4);
1688
1689	/* Restore PCI config data. */
1690	pci_write_config(dev, DC_PCI_CFBIO, iobase, 4);
1691	pci_write_config(dev, DC_PCI_CFBMA, membase, 4);
1692	pci_write_config(dev, DC_PCI_CFIT, irq, 4);
1693	}
1694	}
1695	return;
1696	}
1697	#endif
1698
1699
1700	static void dc_apply_fixup(sc, media)
1701	struct dc_softc *sc;
1702	int media;
1703	{
1704	struct dc_mediainfo *m;
1705	u_int8_t *p;
1706	int i;
1707	u_int32_t reg;
1708
1709	m = sc->dc_mi;
1710
1711	while (m != NULL) {
1712	if (m->dc_media == media)
1713	break;
1714	m = m->dc_next;
1715	}
1716
1717	if (m == NULL)
1718	return;
1719
1720	for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1721	reg = (p[0] \| (p[1] << 8)) << 16;
1722	CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1723	}
1724
1725	for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1726	reg = (p[0] \| (p[1] << 8)) << 16;
1727	CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1728	}
1729
1730	return;
1731	}
1732
1733	#if 0
1734	static void dc_decode_leaf_sia(sc, l)
1735	struct dc_softc *sc;
1736	struct dc_eblock_sia *l;
1737	{
1738	struct dc_mediainfo *m;
1739
1740	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1741	bzero(m, sizeof(struct dc_mediainfo));
1742	if (l->dc_sia_code == DC_SIA_CODE_10BT)
1743	m->dc_media = IFM_10_T;
1744
1745	if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX)
1746	m->dc_media = IFM_10_T\|IFM_FDX;
1747
1748	if (l->dc_sia_code == DC_SIA_CODE_10B2)
1749	m->dc_media = IFM_10_2;
1750
1751	if (l->dc_sia_code == DC_SIA_CODE_10B5)
1752	m->dc_media = IFM_10_5;
1753
1754	m->dc_gp_len = 2;
1755	m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl;
1756
1757	m->dc_next = sc->dc_mi;
1758	sc->dc_mi = m;
1759
1760	sc->dc_pmode = DC_PMODE_SIA;
1761
1762	return;
1763	}
1764
1765	static void dc_decode_leaf_sym(sc, l)
1766	struct dc_softc *sc;
1767	struct dc_eblock_sym *l;
1768	{
1769	struct dc_mediainfo *m;
1770
1771	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1772	bzero(m, sizeof(struct dc_mediainfo));
1773	if (l->dc_sym_code == DC_SYM_CODE_100BT)
1774	m->dc_media = IFM_100_TX;
1775
1776	if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1777	m->dc_media = IFM_100_TX\|IFM_FDX;
1778
1779	m->dc_gp_len = 2;
1780	m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
1781
1782	m->dc_next = sc->dc_mi;
1783	sc->dc_mi = m;
1784
1785	sc->dc_pmode = DC_PMODE_SYM;
1786
1787	return;
1788	}
1789
1790	static void dc_decode_leaf_mii(sc, l)
1791	struct dc_softc *sc;
1792	struct dc_eblock_mii *l;
1793	{
1794	u_int8_t *p;
1795	struct dc_mediainfo *m;
1796
1797	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1798	bzero(m, sizeof(struct dc_mediainfo));
1799	/* We abuse IFM_AUTO to represent MII. */
1800	m->dc_media = IFM_AUTO;
1801	m->dc_gp_len = l->dc_gpr_len;
1802
1803	p = (u_int8_t *)l;
1804	p += sizeof(struct dc_eblock_mii);
1805	m->dc_gp_ptr = p;
1806	p += 2 * l->dc_gpr_len;
1807	m->dc_reset_len = *p;
1808	p++;
1809	m->dc_reset_ptr = p;
1810
1811	m->dc_next = sc->dc_mi;
1812	sc->dc_mi = m;
1813
1814	return;
1815	}
1816	#endif
1817
1818	static void dc_read_srom(sc, bits)
1819	struct dc_softc *sc;
1820	int bits;
1821	{
1822	int size;
1823
1824	size = 2 << bits;
1825	sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT);
1826	dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1827	}
1828
1829	static void dc_parse_21143_srom(sc)
1830	struct dc_softc *sc;
1831	{
1832	struct dc_leaf_hdr *lhdr;
1833	struct dc_eblock_hdr *hdr;
1834	int i, loff;
1835	char *ptr;
1836
1837	loff = sc->dc_srom[27];
1838	lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1839
1840	ptr = (char *)lhdr;
1841	ptr += sizeof(struct dc_leaf_hdr) - 1;
1842	for (i = 0; i < lhdr->dc_mcnt; i++) {
1843	hdr = (struct dc_eblock_hdr *)ptr;
1844	switch(hdr->dc_type) {
1845	#if 0
1846	case DC_EBLOCK_MII:
1847	dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1848	break;
1849	case DC_EBLOCK_SIA:
1850	dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr);
1851	break;
1852	case DC_EBLOCK_SYM:
1853	dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr);
1854	break;
1855	#endif
1856	default:
1857	/* Don't care. Yet. */
1858	break;
1859	}
1860	ptr += (hdr->dc_len & 0x7F);
1861	ptr++;
1862	}
1863
1864	return;
1865	}
1866
1867
1868	static void
1869	nop(const rtems_irq_connect_data* unused)
1870	{
1871	}
1872
1873	static int
1874	decISON(const rtems_irq_connect_data* irq)
1875	{
1876	return (BSP_irq_enabled_at_i8259s(irq->name));
1877	}
1878
1879
1880	/*
1881	* Attach the interface. Allocate softc structures, do ifmedia
1882	* setup and ethernet/BPF attach.
1883	*/
1884	int
1885	rtems_dc_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching)
1886	{
1887	/int s, tmp = 0;/
1888	u_char eaddr[ETHER_ADDR_LEN];
1889
1890	char *unitName;
1891	int unitNumber;
1892
1893	u_int32_t command;
1894	struct dc_softc *sc;
1895	struct ifnet *ifp;
1896	u_int32_t revision;
1897	int error = 0, mac_offset;
1898	#if defined(__i386__)
1899	int sig;
1900	int value;
1901	#endif
1902
1903	/*
1904	* Get the instance number for the board we're going to configure
1905	* from the user.
1906	*/
1907	unitNumber = rtems_bsdnet_parse_driver_name(config, &unitName);
1908	if( unitNumber < 0) {
1909	return 0;
1910	}
1911	if( strcmp(unitName, DRIVER_PREFIX) ) {
1912	printk("dec2114x : unit name '%s' not %s\n", \
1913	unitName, DRIVER_PREFIX );
1914	return 0;
1915	}
1916
1917
1918	/*
1919	* First, find a DEC board
1920	*/
1921	if (pci_initialize() == PCIB_ERR_NOTPRESENT) {
1922	rtems_panic("PCI BIOS not found !!");
1923	}
1924
1925	sc = &dc_softc_devs[unitNumber - 1];
1926	ifp = &sc->arpcom.ac_if;
1927
1928	if(ifp->if_softc != NULL) {
1929	printk("dec2114x[%d]: unit number already in use.\n", \
1930	unitNumber);
1931	return (0);
1932	}
1933	memset(sc, 0, sizeof(struct dc_softc));
1934
1935	/unit = device_get_unit(dev);/
1936	sc->dc_unit = unitNumber;
1937	sc->dc_name = unitName;
1938
1939	/*
1940	* Handle power management nonsense.
1941	*
1942	dc_acpi(dev);
1943	*/
1944
1945	/* Scan for dec2114x cards in pci config space */
1946	if( (sc->dc_info = dc_devtype(unitNumber)) == NULL) {
1947	printk("Can't find any dec2114x NICs in PCI space.\n");
1948	return 0;
1949	}
1950
1951
1952	/*
1953	* Map control/status registers.
1954	*/
1955	sig = sc->dc_info->dc_devsig;
1956	pcib_conf_read32(sig, PCI_COMMAND, &command);
1957	command \|= (PCI_COMMAND_IO \| PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
1958	pcib_conf_write32(sig, PCI_COMMAND, command);
1959	pcib_conf_read32(sig, PCI_COMMAND, &command);
1960
1961	#ifdef DC_USEIOSPACE
1962	if (!(command & PCI_COMMAND_IO)) {
1963	printk("dc%d: failed to enable I/O ports!\n", sc->dc_unit);
1964	error = ENXIO;
1965	goto fail;
1966	}
1967	#else
1968	if (!(command & PCI_COMMAND_MEMORY)) {
1969	printk("dc%d: failed to enable memory mapping!\n", sc->dc_unit);
1970	error = ENXIO;
1971	goto fail;
1972	}
1973	#endif
1974
1975	#if 0
1976	rid = DC_RID;
1977	sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid,
1978	0, ~0, 1, RF_ACTIVE);
1979
1980	if (sc->dc_res == NULL) {
1981	printk("dc%d: couldn't map ports/memory\n", unit);
1982	error = ENXIO;
1983	goto fail;
1984	}
1985	sc->dc_btag = rman_get_bustag(sc->dc_res);
1986	sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
1987	#endif
1988
1989	/* sc->membase is the address of the card's CSRs !!! */
1990	pcib_conf_read32(sig, DC_PCI_CFBMA, &value);
1991	sc->membase = value;
1992
1993	/* Allocate interrupt */
1994	memset(&sc->irqInfo, 0, sizeof(rtems_irq_connect_data));
1995	pcib_conf_read32(sig, DC_PCI_CFIT, &value);
1996	sc->irqInfo.name = value & 0xFF;
1997
1998	sc->irqInfo.hdl = (rtems_irq_hdl)dc_intr;
1999	sc->irqInfo.on = nop;
2000	sc->irqInfo.off = nop;
2001	sc->irqInfo.isOn = decISON;
2002
2003	if(!(BSP_install_rtems_irq_handler( &sc->irqInfo ))) {
2004	rtems_panic("Can't install dec2114x irq handler.\n");
2005	}
2006
2007
2008	#if 0
2009	rid = 0;
2010	sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
2011	RF_SHAREABLE \| RF_ACTIVE);
2012
2013	if (sc->dc_irq == NULL) {
2014	printk("dc%d: couldn't map interrupt\n", unit);
2015	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2016	error = ENXIO;
2017	goto fail;
2018	}
2019
2020	error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET,
2021	dc_intr, sc, &sc->dc_intrhand);
2022
2023	if (error) {
2024	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2025	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2026	printk("dc%d: couldn't set up irq\n", unit);
2027	goto fail;
2028	}
2029	#endif
2030
2031
2032	/* Need this info to decide on a chip type.
2033	sc->dc_info = dc_devtype(dev);
2034	*/
2035	pcib_conf_read32(sig, DC_PCI_CFRV, &revision);
2036	revision &= 0x000000FF;
2037
2038	/* Get the eeprom width, but PNIC has diff eeprom */
2039	if (sc->dc_info->dc_did != DC_DEVICEID_82C168)
2040	dc_eeprom_width(sc);
2041
2042	switch(sc->dc_info->dc_did) {
2043	case DC_DEVICEID_21143:
2044	sc->dc_type = DC_TYPE_21143;
2045	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR;
2046	sc->dc_flags \|= DC_REDUCED_MII_POLL;
2047	/* Save EEPROM contents so we can parse them later. */
2048	dc_read_srom(sc, sc->dc_romwidth);
2049	break;
2050	case DC_DEVICEID_DM9009:
2051	case DC_DEVICEID_DM9100:
2052	case DC_DEVICEID_DM9102:
2053	sc->dc_type = DC_TYPE_DM9102;
2054	sc->dc_flags \|= DC_TX_COALESCE\|DC_TX_INTR_ALWAYS;
2055	sc->dc_flags \|= DC_REDUCED_MII_POLL\|DC_TX_STORENFWD;
2056	sc->dc_pmode = DC_PMODE_MII;
2057	/* Increase the latency timer value. */
2058	pcib_conf_read32(sig, DC_PCI_CFLT, &command);
2059	command &= 0xFFFF00FF;
2060	command \|= 0x00008000;
2061	pcib_conf_write32(sig, DC_PCI_CFLT, command);
2062	break;
2063	case DC_DEVICEID_AL981:
2064	sc->dc_type = DC_TYPE_AL981;
2065	sc->dc_flags \|= DC_TX_USE_TX_INTR;
2066	sc->dc_flags \|= DC_TX_ADMTEK_WAR;
2067	sc->dc_pmode = DC_PMODE_MII;
2068	dc_read_srom(sc, sc->dc_romwidth);
2069	break;
2070	case DC_DEVICEID_AN985:
2071	case DC_DEVICEID_EN2242:
2072	sc->dc_type = DC_TYPE_AN985;
2073	sc->dc_flags \|= DC_TX_USE_TX_INTR;
2074	sc->dc_flags \|= DC_TX_ADMTEK_WAR;
2075	sc->dc_pmode = DC_PMODE_MII;
2076	dc_read_srom(sc, sc->dc_romwidth);
2077	break;
2078	case DC_DEVICEID_98713:
2079	case DC_DEVICEID_98713_CP:
2080	if (revision < DC_REVISION_98713A) {
2081	sc->dc_type = DC_TYPE_98713;
2082	}
2083	if (revision >= DC_REVISION_98713A) {
2084	sc->dc_type = DC_TYPE_98713A;
2085	sc->dc_flags \|= DC_21143_NWAY;
2086	}
2087	sc->dc_flags \|= DC_REDUCED_MII_POLL;
2088	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR;
2089	break;
2090	case DC_DEVICEID_987x5:
2091	case DC_DEVICEID_EN1217:
2092	/*
2093	* Macronix MX98715AEC-C/D/E parts have only a
2094	* 128-bit hash table. We need to deal with these
2095	* in the same manner as the PNIC II so that we
2096	* get the right number of bits out of the
2097	* CRC routine.
2098	*/
2099	if (revision >= DC_REVISION_98715AEC_C &&
2100	revision < DC_REVISION_98725)
2101	sc->dc_flags \|= DC_128BIT_HASH;
2102	sc->dc_type = DC_TYPE_987x5;
2103	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR;
2104	sc->dc_flags \|= DC_REDUCED_MII_POLL\|DC_21143_NWAY;
2105	break;
2106	case DC_DEVICEID_98727:
2107	sc->dc_type = DC_TYPE_987x5;
2108	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR;
2109	sc->dc_flags \|= DC_REDUCED_MII_POLL\|DC_21143_NWAY;
2110	break;
2111	case DC_DEVICEID_82C115:
2112	sc->dc_type = DC_TYPE_PNICII;
2113	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR\|DC_128BIT_HASH;
2114	sc->dc_flags \|= DC_REDUCED_MII_POLL\|DC_21143_NWAY;
2115	break;
2116	case DC_DEVICEID_82C168:
2117	sc->dc_type = DC_TYPE_PNIC;
2118	sc->dc_flags \|= DC_TX_STORENFWD\|DC_TX_INTR_ALWAYS;
2119	sc->dc_flags \|= DC_PNIC_RX_BUG_WAR;
2120	sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT);
2121	if (revision < DC_REVISION_82C169)
2122	sc->dc_pmode = DC_PMODE_SYM;
2123	break;
2124	case DC_DEVICEID_AX88140A:
2125	sc->dc_type = DC_TYPE_ASIX;
2126	sc->dc_flags \|= DC_TX_USE_TX_INTR\|DC_TX_INTR_FIRSTFRAG;
2127	sc->dc_flags \|= DC_REDUCED_MII_POLL;
2128	sc->dc_pmode = DC_PMODE_MII;
2129	break;
2130	case DC_DEVICEID_RS7112:
2131	sc->dc_type = DC_TYPE_CONEXANT;
2132	sc->dc_flags \|= DC_TX_INTR_ALWAYS;
2133	sc->dc_flags \|= DC_REDUCED_MII_POLL;
2134	sc->dc_pmode = DC_PMODE_MII;
2135	dc_read_srom(sc, sc->dc_romwidth);
2136	break;
2137	default:
2138	printk("dc%d: unknown device: %x\n", sc->dc_unit,
2139	sc->dc_info->dc_did);
2140	break;
2141	}
2142
2143	/* Save the cache line size. */
2144	if (DC_IS_DAVICOM(sc)) {
2145	sc->dc_cachesize = 0;
2146	}
2147	else {
2148	pcib_conf_read32(sig, DC_PCI_CFLT, &value);
2149	sc->dc_cachesize = (u_int8_t)(value & 0xFF);
2150	}
2151
2152	/* Reset the adapter. */
2153	dc_reset(sc);
2154
2155	/* Take 21143 out of snooze mode */
2156	if (DC_IS_INTEL(sc)) {
2157	pcib_conf_read32(sig, DC_PCI_CFDD, &command);
2158	command &= ~(DC_CFDD_SNOOZE_MODE\|DC_CFDD_SLEEP_MODE);
2159	pcib_conf_write32(sig, DC_PCI_CFDD, command);
2160	}
2161
2162
2163	/*
2164	* Try to learn something about the supported media.
2165	* We know that ASIX and ADMtek and Davicom devices
2166	* will always be using MII media, so that's a no-brainer.
2167	* The tricky ones are the Macronix/PNIC II and the
2168	* Intel 21143.
2169	*/
2170	if (DC_IS_INTEL(sc))
2171	dc_parse_21143_srom(sc);
2172	else if (DC_IS_MACRONIX(sc) \|\| DC_IS_PNICII(sc)) {
2173	if (sc->dc_type == DC_TYPE_98713)
2174	sc->dc_pmode = DC_PMODE_MII;
2175	else
2176	sc->dc_pmode = DC_PMODE_SYM;
2177	} else if (!sc->dc_pmode)
2178	sc->dc_pmode = DC_PMODE_MII;
2179
2180	/*
2181	* Get station address from the EEPROM.
2182	*/
2183	switch(sc->dc_type) {
2184	case DC_TYPE_98713:
2185	case DC_TYPE_98713A:
2186	case DC_TYPE_987x5:
2187	case DC_TYPE_PNICII:
2188	dc_read_eeprom(sc, (caddr_t)&mac_offset,
2189	(DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2190	dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2191	break;
2192	case DC_TYPE_PNIC:
2193	dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2194	break;
2195	case DC_TYPE_DM9102:
2196	case DC_TYPE_21143:
2197	case DC_TYPE_ASIX:
2198	dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2199	break;
2200	case DC_TYPE_AL981:
2201	case DC_TYPE_AN985:
2202	bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr,
2203	ETHER_ADDR_LEN);
2204	dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0);
2205	break;
2206	case DC_TYPE_CONEXANT:
2207	bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6);
2208	break;
2209	default:
2210	dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2211	break;
2212	}
2213
2214	/*
2215	* A 21143 or clone chip was detected. Inform the world.
2216	*/
2217	bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
2218	printk("dc%d: MAC address -- %02x:%02x:%02x:%02x:%02x:%02x\n", \
2219	sc->dc_unit,sc->arpcom.ac_enaddr[0], \
2220	sc->arpcom.ac_enaddr[1], sc->arpcom.ac_enaddr[2], \
2221	sc->arpcom.ac_enaddr[3], sc->arpcom.ac_enaddr[4], \
2222	sc->arpcom.ac_enaddr[5]);
2223
2224
2225	sc->dc_ldata = malloc(sizeof(struct dc_list_data), M_DEVBUF, M_NOWAIT);
2226
2227	if (sc->dc_ldata == NULL) {
2228	printk("dc%d: no memory for list buffers!\n", sc->dc_unit);
2229	if (sc->dc_pnic_rx_buf != NULL)
2230	free(sc->dc_pnic_rx_buf, M_DEVBUF);
2231	#if 0
2232	bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2233	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2234	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2235	#endif
2236	error = ENXIO;
2237	goto fail;
2238	}
2239
2240	bzero(sc->dc_ldata, sizeof(struct dc_list_data));
2241
2242	ifp = &sc->arpcom.ac_if;
2243	ifp->if_softc = sc;
2244	ifp->if_unit = unitNumber; /sc->dc_unit;/
2245	ifp->if_name = unitName; /sc->dc_name;/
2246	ifp->if_mtu = ETHERMTU;
2247	ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX;/* \| IFF_MULTICAST;*/
2248	ifp->if_ioctl = dc_ioctl;
2249	ifp->if_output = ether_output;
2250	ifp->if_start = dc_start;
2251	ifp->if_watchdog = dc_watchdog;
2252	ifp->if_init = dc_init;
2253	ifp->if_baudrate = 100000000;
2254	ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1;
2255
2256	#if 0
2257	/*
2258	* Do MII setup. If this is a 21143, check for a PHY on the
2259	* MII bus after applying any necessary fixups to twiddle the
2260	* GPIO bits. If we don't end up finding a PHY, restore the
2261	* old selection (SIA only or SIA/SYM) and attach the dcphy
2262	* driver instead.
2263	*/
2264	if (DC_IS_INTEL(sc)) {
2265	dc_apply_fixup(sc, IFM_AUTO);
2266	tmp = sc->dc_pmode;
2267	sc->dc_pmode = DC_PMODE_MII;
2268	}
2269
2270	error = mii_phy_probe(dev, &sc->dc_miibus,
2271	dc_ifmedia_upd, dc_ifmedia_sts);
2272
2273	if (error && DC_IS_INTEL(sc)) {
2274	sc->dc_pmode = tmp;
2275	if (sc->dc_pmode != DC_PMODE_SIA)
2276	sc->dc_pmode = DC_PMODE_SYM;
2277	sc->dc_flags \|= DC_21143_NWAY;
2278	mii_phy_probe(dev, &sc->dc_miibus,
2279	dc_ifmedia_upd, dc_ifmedia_sts);
2280	/*
2281	* For non-MII cards, we need to have the 21143
2282	* drive the LEDs. Except there are some systems
2283	* like the NEC VersaPro NoteBook PC which have no
2284	* LEDs, and twiddling these bits has adverse effects
2285	* on them. (I.e. you suddenly can't get a link.)
2286	*/
2287	if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033)
2288	sc->dc_flags \|= DC_TULIP_LEDS;
2289	error = 0;
2290	}
2291
2292	if (error) {
2293	printk("dc%d: MII without any PHY!\n", sc->dc_unit);
2294	contigfree(sc->dc_ldata, sizeof(struct dc_list_data),
2295	M_DEVBUF);
2296	if (sc->dc_pnic_rx_buf != NULL)
2297	free(sc->dc_pnic_rx_buf, M_DEVBUF);
2298	bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2299	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2300	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2301	error = ENXIO;
2302	goto fail;
2303	}
2304	#endif
2305
2306	/*
2307	* Call MI attach routine.
2308	*/
2309	if_attach(ifp);
2310	ether_ifattach(ifp);
2311	/callout_handle_init(&sc->dc_stat_ch);/
2312
2313	if (DC_IS_ADMTEK(sc)) {
2314	/*
2315	* Set automatic TX underrun recovery for the ADMtek chips
2316	*/
2317	DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2318	}
2319
2320	if(sc->daemontid == 0) {
2321	sc->daemontid = rtems_bsdnet_newproc("decD",4096, \
2322	dc_daemon,(void *)sc);
2323	printk("dec[%d]: daemon process started\n", sc->dc_unit);
2324	}
2325
2326	/*
2327	* Tell the upper layer(s) we support long frames.
2328	*
2329	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2330	*/
2331
2332	#ifdef SRM_MEDIA
2333	sc->dc_srm_media = 0;
2334
2335	/* Remember the SRM console media setting */
2336	if (DC_IS_INTEL(sc)) {
2337	command = pci_read_config(dev, DC_PCI_CFDD, 4);
2338	command &= ~(DC_CFDD_SNOOZE_MODE\|DC_CFDD_SLEEP_MODE);
2339	switch ((command >> 8) & 0xff) {
2340	case 3:
2341	sc->dc_srm_media = IFM_10_T;
2342	break;
2343	case 4:
2344	sc->dc_srm_media = IFM_10_T \| IFM_FDX;
2345	break;
2346	case 5:
2347	sc->dc_srm_media = IFM_100_TX;
2348	break;
2349	case 6:
2350	sc->dc_srm_media = IFM_100_TX \| IFM_FDX;
2351	break;
2352	}
2353	if (sc->dc_srm_media)
2354	sc->dc_srm_media \|= IFM_ACTIVE \| IFM_ETHER;
2355	}
2356	#endif
2357
2358
2359	fail:
2360
2361	return (1); /(error);/
2362	}
2363
2364	#if 0
2365	static int dc_detach(dev)
2366	device_t dev;
2367	{
2368	struct dc_softc *sc;
2369	struct ifnet *ifp;
2370	int s;
2371	struct dc_mediainfo *m;
2372
2373
2374	sc = device_get_softc(dev);
2375	ifp = &sc->arpcom.ac_if;
2376
2377	dc_stop(sc);
2378	ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
2379
2380	bus_generic_detach(dev);
2381	device_delete_child(dev, sc->dc_miibus);
2382
2383	bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2384	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2385	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2386
2387	contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF);
2388	if (sc->dc_pnic_rx_buf != NULL)
2389	free(sc->dc_pnic_rx_buf, M_DEVBUF);
2390
2391	while(sc->dc_mi != NULL) {
2392	m = sc->dc_mi->dc_next;
2393	free(sc->dc_mi, M_DEVBUF);
2394	sc->dc_mi = m;
2395	}
2396	free(sc->dc_srom, M_DEVBUF);
2397
2398
2399	return(0);
2400	}
2401	#endif
2402
2403
2404	/*
2405	* Initialize the transmit descriptors.
2406	*/
2407	static int dc_list_tx_init(sc)
2408	struct dc_softc *sc;
2409	{
2410	struct dc_chain_data *cd;
2411	struct dc_list_data *ld;
2412	int i;
2413
2414	cd = &sc->dc_cdata;
2415	ld = sc->dc_ldata;
2416	for (i = 0; i < DC_TX_LIST_CNT; i++) {
2417	if (i == (DC_TX_LIST_CNT - 1)) {
2418	ld->dc_tx_list[i].dc_next =
2419	vtophys(&ld->dc_tx_list[0]);
2420	} else {
2421	ld->dc_tx_list[i].dc_next =
2422	vtophys(&ld->dc_tx_list[i + 1]);
2423	}
2424	cd->dc_tx_chain[i] = NULL;
2425	ld->dc_tx_list[i].dc_data = 0;
2426	ld->dc_tx_list[i].dc_ctl = 0;
2427	}
2428
2429	cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2430
2431	return(0);
2432	}
2433
2434
2435	/*
2436	* Initialize the RX descriptors and allocate mbufs for them. Note that
2437	* we arrange the descriptors in a closed ring, so that the last descriptor
2438	* points back to the first.
2439	*/
2440	static int dc_list_rx_init(sc)
2441	struct dc_softc *sc;
2442	{
2443	struct dc_chain_data *cd;
2444	struct dc_list_data *ld;
2445	int i;
2446
2447	cd = &sc->dc_cdata;
2448	ld = sc->dc_ldata;
2449
2450	for (i = 0; i < DC_RX_LIST_CNT; i++) {
2451	if (dc_newbuf(sc, i, NULL) == ENOBUFS)
2452	return(ENOBUFS);
2453	if (i == (DC_RX_LIST_CNT - 1)) {
2454	ld->dc_rx_list[i].dc_next =
2455	vtophys(&ld->dc_rx_list[0]);
2456	} else {
2457	ld->dc_rx_list[i].dc_next =
2458	vtophys(&ld->dc_rx_list[i + 1]);
2459	}
2460	}
2461
2462	cd->dc_rx_prod = 0;
2463
2464	return(0);
2465	}
2466
2467	/*
2468	* Initialize an RX descriptor and attach an MBUF cluster.
2469	*/
2470	static int dc_newbuf(sc, i, m)
2471	struct dc_softc *sc;
2472	int i;
2473	struct mbuf *m;
2474	{
2475	struct mbuf *m_new = NULL;
2476	struct dc_desc *c;
2477
2478	c = &sc->dc_ldata->dc_rx_list[i];
2479
2480	if (m == NULL) {
2481	MGETHDR(m_new, M_DONTWAIT, MT_DATA);
2482	if (m_new == NULL)
2483	return(ENOBUFS);
2484
2485	MCLGET(m_new, M_DONTWAIT);
2486	if (!(m_new->m_flags & M_EXT)) {
2487	m_freem(m_new);
2488	return(ENOBUFS);
2489	}
2490	m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2491	} else {
2492	m_new = m;
2493	m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2494	m_new->m_data = m_new->m_ext.ext_buf;
2495	}
2496
2497	m_adj(m_new, sizeof(u_int64_t));
2498
2499	/*
2500	* If this is a PNIC chip, zero the buffer. This is part
2501	* of the workaround for the receive bug in the 82c168 and
2502	* 82c169 chips.
2503	*/
2504	if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2505	bzero((char )mtod(m_new, char ), m_new->m_len);
2506
2507	sc->dc_cdata.dc_rx_chain[i] = m_new;
2508	c->dc_data = vtophys(mtod(m_new, caddr_t));
2509	c->dc_ctl = DC_RXCTL_RLINK \| DC_RXLEN;
2510	c->dc_status = DC_RXSTAT_OWN;
2511
2512	return(0);
2513	}
2514
2515	/*
2516	* Grrrrr.
2517	* The PNIC chip has a terrible bug in it that manifests itself during
2518	* periods of heavy activity. The exact mode of failure if difficult to
2519	* pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2520	* will happen on slow machines. The bug is that sometimes instead of
2521	* uploading one complete frame during reception, it uploads what looks
2522	* like the entire contents of its FIFO memory. The frame we want is at
2523	* the end of the whole mess, but we never know exactly how much data has
2524	* been uploaded, so salvaging the frame is hard.
2525	*
2526	* There is only one way to do it reliably, and it's disgusting.
2527	* Here's what we know:
2528	*
2529	* - We know there will always be somewhere between one and three extra
2530	* descriptors uploaded.
2531	*
2532	* - We know the desired received frame will always be at the end of the
2533	* total data upload.
2534	*
2535	* - We know the size of the desired received frame because it will be
2536	* provided in the length field of the status word in the last descriptor.
2537	*
2538	* Here's what we do:
2539	*
2540	* - When we allocate buffers for the receive ring, we bzero() them.
2541	* This means that we know that the buffer contents should be all
2542	* zeros, except for data uploaded by the chip.
2543	*
2544	* - We also force the PNIC chip to upload frames that include the
2545	* ethernet CRC at the end.
2546	*
2547	* - We gather all of the bogus frame data into a single buffer.
2548	*
2549	* - We then position a pointer at the end of this buffer and scan
2550	* backwards until we encounter the first non-zero byte of data.
2551	* This is the end of the received frame. We know we will encounter
2552	* some data at the end of the frame because the CRC will always be
2553	* there, so even if the sender transmits a packet of all zeros,
2554	* we won't be fooled.
2555	*
2556	* - We know the size of the actual received frame, so we subtract
2557	* that value from the current pointer location. This brings us
2558	* to the start of the actual received packet.
2559	*
2560	* - We copy this into an mbuf and pass it on, along with the actual
2561	* frame length.
2562	*
2563	* The performance hit is tremendous, but it beats dropping frames all
2564	* the time.
2565	*/
2566
2567	#define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG\|DC_RXSTAT_LASTFRAG)
2568	static void dc_pnic_rx_bug_war(sc, idx)
2569	struct dc_softc *sc;
2570	int idx;
2571	{
2572	struct dc_desc *cur_rx;
2573	struct dc_desc *c = NULL;
2574	struct mbuf *m = NULL;
2575	unsigned char *ptr;
2576	int i, total_len;
2577	u_int32_t rxstat = 0;
2578
2579	i = sc->dc_pnic_rx_bug_save;
2580	cur_rx = &sc->dc_ldata->dc_rx_list[idx];
2581	ptr = sc->dc_pnic_rx_buf;
2582	bzero(ptr, sizeof(DC_RXLEN * 5));
2583
2584	/* Copy all the bytes from the bogus buffers. */
2585	while (1) {
2586	c = &sc->dc_ldata->dc_rx_list[i];
2587	rxstat = c->dc_status;
2588	m = sc->dc_cdata.dc_rx_chain[i];
2589	bcopy(mtod(m, char *), ptr, DC_RXLEN);
2590	ptr += DC_RXLEN;
2591	/* If this is the last buffer, break out. */
2592	if (i == idx \|\| rxstat & DC_RXSTAT_LASTFRAG)
2593	break;
2594	dc_newbuf(sc, i, m);
2595	DC_INC(i, DC_RX_LIST_CNT);
2596	}
2597
2598	/* Find the length of the actual receive frame. */
2599	total_len = DC_RXBYTES(rxstat);
2600
2601	/* Scan backwards until we hit a non-zero byte. */
2602	while(*ptr == 0x00)
2603	ptr--;
2604	#if 0
2605	/* Round off. */
2606	if ((uintptr_t)(ptr) & 0x3)
2607	ptr -= 1;
2608	#endif
2609
2610	/* Now find the start of the frame. */
2611	ptr -= total_len;
2612	if (ptr < sc->dc_pnic_rx_buf)
2613	ptr = sc->dc_pnic_rx_buf;
2614
2615	/*
2616	* Now copy the salvaged frame to the last mbuf and fake up
2617	* the status word to make it look like a successful
2618	* frame reception.
2619	*/
2620	dc_newbuf(sc, i, m);
2621	bcopy(ptr, mtod(m, char *), total_len);
2622	cur_rx->dc_status = rxstat \| DC_RXSTAT_FIRSTFRAG;
2623
2624	return;
2625	}
2626
2627	/*
2628	* This routine searches the RX ring for dirty descriptors in the
2629	* event that the rxeof routine falls out of sync with the chip's
2630	* current descriptor pointer. This may happen sometimes as a result
2631	* of a "no RX buffer available" condition that happens when the chip
2632	* consumes all of the RX buffers before the driver has a chance to
2633	* process the RX ring. This routine may need to be called more than
2634	* once to bring the driver back in sync with the chip, however we
2635	* should still be getting RX DONE interrupts to drive the search
2636	* for new packets in the RX ring, so we should catch up eventually.
2637	*/
2638	static int dc_rx_resync(sc)
2639	struct dc_softc *sc;
2640	{
2641	int i, pos;
2642	struct dc_desc *cur_rx;
2643
2644	pos = sc->dc_cdata.dc_rx_prod;
2645
2646	for (i = 0; i < DC_RX_LIST_CNT; i++) {
2647	cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2648	if (!(cur_rx->dc_status & DC_RXSTAT_OWN))
2649	break;
2650	DC_INC(pos, DC_RX_LIST_CNT);
2651	}
2652
2653	/* If the ring really is empty, then just return. */
2654	if (i == DC_RX_LIST_CNT)
2655	return(0);
2656
2657	/* We've fallen behing the chip: catch it. */
2658	sc->dc_cdata.dc_rx_prod = pos;
2659
2660	return(EAGAIN);
2661	}
2662
2663	/*
2664	* A frame has been uploaded: pass the resulting mbuf chain up to
2665	* the higher level protocols.
2666	*/
2667	static void dc_rxeof(sc)
2668	struct dc_softc *sc;
2669	{
2670	struct ether_header *eh;
2671	struct mbuf *m;
2672	struct ifnet *ifp;
2673	struct dc_desc *cur_rx;
2674	int i, total_len = 0;
2675	u_int32_t rxstat;
2676
2677	ifp = &sc->arpcom.ac_if;
2678	i = sc->dc_cdata.dc_rx_prod;
2679
2680	while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) {
2681
2682	#ifdef DEVICE_POLLING
2683	if (ifp->if_ipending & IFF_POLLING) {
2684	if (sc->rxcycles <= 0)
2685	break;
2686	sc->rxcycles--;
2687	}
2688	#endif /* DEVICE_POLLING */
2689	cur_rx = &sc->dc_ldata->dc_rx_list[i];
2690	rxstat = cur_rx->dc_status;
2691	m = sc->dc_cdata.dc_rx_chain[i];
2692	total_len = DC_RXBYTES(rxstat);
2693
2694	if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2695	if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2696	if (rxstat & DC_RXSTAT_FIRSTFRAG)
2697	sc->dc_pnic_rx_bug_save = i;
2698	if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
2699	DC_INC(i, DC_RX_LIST_CNT);
2700	continue;
2701	}
2702	dc_pnic_rx_bug_war(sc, i);
2703	rxstat = cur_rx->dc_status;
2704	total_len = DC_RXBYTES(rxstat);
2705	}
2706	}
2707
2708	sc->dc_cdata.dc_rx_chain[i] = NULL;
2709
2710	/*
2711	* If an error occurs, update stats, clear the
2712	* status word and leave the mbuf cluster in place:
2713	* it should simply get re-used next time this descriptor
2714	* comes up in the ring. However, don't report long
2715	* frames as errors since they could be vlans
2716	*/
2717	if ((rxstat & DC_RXSTAT_RXERR)){
2718	if (!(rxstat & DC_RXSTAT_GIANT) \|\|
2719	(rxstat & (DC_RXSTAT_CRCERR \| DC_RXSTAT_DRIBBLE \|
2720	DC_RXSTAT_MIIERE \| DC_RXSTAT_COLLSEEN \|
2721	DC_RXSTAT_RUNT \| DC_RXSTAT_DE))) {
2722	ifp->if_ierrors++;
2723	if (rxstat & DC_RXSTAT_COLLSEEN)
2724	ifp->if_collisions++;
2725	dc_newbuf(sc, i, m);
2726	if (rxstat & DC_RXSTAT_CRCERR) {
2727	DC_INC(i, DC_RX_LIST_CNT);
2728	continue;
2729	} else {
2730	dc_init(sc);
2731	return;
2732	}
2733	}
2734	}
2735
2736	/* No errors; receive the packet. */
2737	total_len -= ETHER_CRC_LEN;
2738
2739	#ifdef __i386__
2740	/*
2741	* On the x86 we do not have alignment problems, so try to
2742	* allocate a new buffer for the receive ring, and pass up
2743	* the one where the packet is already, saving the expensive
2744	* copy done in m_devget().
2745	* If we are on an architecture with alignment problems, or
2746	* if the allocation fails, then use m_devget and leave the
2747	* existing buffer in the receive ring.
2748	*/
2749	if (dc_quick && dc_newbuf(sc, i, NULL) == 0) {
2750	m->m_pkthdr.rcvif = ifp;
2751	m->m_pkthdr.len = m->m_len = total_len;
2752	DC_INC(i, DC_RX_LIST_CNT);
2753	} else
2754	#endif
2755	{
2756	struct mbuf *m0;
2757
2758	m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
2759	total_len + ETHER_ALIGN, 0, ifp, NULL);
2760	dc_newbuf(sc, i, m);
2761	DC_INC(i, DC_RX_LIST_CNT);
2762	if (m0 == NULL) {
2763	ifp->if_ierrors++;
2764	continue;
2765	}
2766	m_adj(m0, ETHER_ALIGN);
2767	m = m0;
2768	}
2769
2770	ifp->if_ipackets++;
2771	eh = mtod(m, struct ether_header *);
2772
2773	/* Remove header from mbuf and pass it on. */
2774	m_adj(m, sizeof(struct ether_header));
2775	ether_input(ifp, eh, m);
2776	}
2777
2778	sc->dc_cdata.dc_rx_prod = i;
2779	}
2780
2781	/*
2782	* A frame was downloaded to the chip. It's safe for us to clean up
2783	* the list buffers.
2784	*/
2785
2786	static void
2787	dc_txeof(sc)
2788	struct dc_softc *sc;
2789	{
2790	struct dc_desc *cur_tx = NULL;
2791	struct ifnet *ifp;
2792	int idx;
2793
2794	ifp = &sc->arpcom.ac_if;
2795
2796	/*
2797	* Go through our tx list and free mbufs for those
2798	* frames that have been transmitted.
2799	*/
2800	idx = sc->dc_cdata.dc_tx_cons;
2801	while(idx != sc->dc_cdata.dc_tx_prod) {
2802	u_int32_t txstat;
2803
2804	cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2805	txstat = cur_tx->dc_status;
2806
2807	if (txstat & DC_TXSTAT_OWN)
2808	break;
2809
2810	if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) \|\|
2811	cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2812	if (cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2813	/*
2814	* Yes, the PNIC is so brain damaged
2815	* that it will sometimes generate a TX
2816	* underrun error while DMAing the RX
2817	* filter setup frame. If we detect this,
2818	* we have to send the setup frame again,
2819	* or else the filter won't be programmed
2820	* correctly.
2821	*/
2822	if (DC_IS_PNIC(sc)) {
2823	if (txstat & DC_TXSTAT_ERRSUM)
2824	dc_setfilt(sc);
2825	}
2826	sc->dc_cdata.dc_tx_chain[idx] = NULL;
2827	}
2828	sc->dc_cdata.dc_tx_cnt--;
2829	DC_INC(idx, DC_TX_LIST_CNT);
2830	continue;
2831	}
2832
2833	if (DC_IS_CONEXANT(sc)) {
2834	/*
2835	* For some reason Conexant chips like
2836	* setting the CARRLOST flag even when
2837	* the carrier is there. In CURRENT we
2838	* have the same problem for Xircom
2839	* cards !
2840	*/
2841	if (/sc->dc_type == DC_TYPE_21143 &&/
2842	sc->dc_pmode == DC_PMODE_MII &&
2843	((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM\|
2844	DC_TXSTAT_NOCARRIER)))
2845	txstat &= ~DC_TXSTAT_ERRSUM;
2846	} else {
2847	if (/sc->dc_type == DC_TYPE_21143 &&/
2848	sc->dc_pmode == DC_PMODE_MII &&
2849	((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM\|
2850	DC_TXSTAT_NOCARRIER\|DC_TXSTAT_CARRLOST)))
2851	txstat &= ~DC_TXSTAT_ERRSUM;
2852	}
2853
2854	if (txstat & DC_TXSTAT_ERRSUM) {
2855	ifp->if_oerrors++;
2856	if (txstat & DC_TXSTAT_EXCESSCOLL)
2857	ifp->if_collisions++;
2858	if (txstat & DC_TXSTAT_LATECOLL)
2859	ifp->if_collisions++;
2860	if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2861	dc_init(sc);
2862	return;
2863	}
2864	}
2865
2866	ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2867
2868	ifp->if_opackets++;
2869	if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
2870	m_freem(sc->dc_cdata.dc_tx_chain[idx]);
2871	sc->dc_cdata.dc_tx_chain[idx] = NULL;
2872	}
2873
2874	sc->dc_cdata.dc_tx_cnt--;
2875	DC_INC(idx, DC_TX_LIST_CNT);
2876	}
2877
2878	if (idx != sc->dc_cdata.dc_tx_cons) {
2879	/* some buffers have been freed */
2880	sc->dc_cdata.dc_tx_cons = idx;
2881	ifp->if_flags &= ~IFF_OACTIVE;
2882	}
2883	ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5;
2884
2885	return;
2886	}
2887
2888
2889	#if 0
2890	static void dc_tick(xsc)
2891	void *xsc;
2892	{
2893	struct dc_softc *sc;
2894	/struct mii_data mii;*/
2895	struct ifnet *ifp;
2896	int s;
2897	u_int32_t r;
2898
2899
2900	sc = xsc;
2901	ifp = &sc->arpcom.ac_if;
2902	mii = device_get_softc(sc->dc_miibus);
2903
2904	if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2905	if (sc->dc_flags & DC_21143_NWAY) {
2906	r = CSR_READ_4(sc, DC_10BTSTAT);
2907	if (IFM_SUBTYPE(mii->mii_media_active) ==
2908	IFM_100_TX && (r & DC_TSTAT_LS100)) {
2909	sc->dc_link = 0;
2910	mii_mediachg(mii);
2911	}
2912	if (IFM_SUBTYPE(mii->mii_media_active) ==
2913	IFM_10_T && (r & DC_TSTAT_LS10)) {
2914	sc->dc_link = 0;
2915	mii_mediachg(mii);
2916	}
2917	if (sc->dc_link == 0)
2918	mii_tick(mii);
2919	} else {
2920	r = CSR_READ_4(sc, DC_ISR);
2921	if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT &&
2922	sc->dc_cdata.dc_tx_cnt == 0)
2923	mii_tick(mii);
2924	if (!(mii->mii_media_status & IFM_ACTIVE))
2925	sc->dc_link = 0;
2926	}
2927	} else
2928	mii_tick(mii);
2929
2930	/*
2931	* When the init routine completes, we expect to be able to send
2932	* packets right away, and in fact the network code will send a
2933	* gratuitous ARP the moment the init routine marks the interface
2934	* as running. However, even though the MAC may have been initialized,
2935	* there may be a delay of a few seconds before the PHY completes
2936	* autonegotiation and the link is brought up. Any transmissions
2937	* made during that delay will be lost. Dealing with this is tricky:
2938	* we can't just pause in the init routine while waiting for the
2939	* PHY to come ready since that would bring the whole system to
2940	* a screeching halt for several seconds.
2941	*
2942	* What we do here is prevent the TX start routine from sending
2943	* any packets until a link has been established. After the
2944	* interface has been initialized, the tick routine will poll
2945	* the state of the PHY until the IFM_ACTIVE flag is set. Until
2946	* that time, packets will stay in the send queue, and once the
2947	* link comes up, they will be flushed out to the wire.
2948	*/
2949	if (!sc->dc_link) {
2950	mii_pollstat(mii);
2951	if (mii->mii_media_status & IFM_ACTIVE &&
2952	IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2953	sc->dc_link++;
2954	if (ifp->if_snd.ifq_head != NULL)
2955	dc_start(ifp);
2956	}
2957	}
2958
2959	if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2960	sc->dc_stat_ch = timeout(dc_tick, sc, hz/10);
2961	else
2962	sc->dc_stat_ch = timeout(dc_tick, sc, hz);
2963
2964	return;
2965	}
2966	#endif
2967
2968	/*
2969	* A transmit underrun has occurred. Back off the transmit threshold,
2970	* or switch to store and forward mode if we have to.
2971	*/
2972	static void dc_tx_underrun(sc)
2973	struct dc_softc *sc;
2974	{
2975	u_int32_t isr;
2976	int i;
2977
2978	if (DC_IS_DAVICOM(sc))
2979	dc_init(sc);
2980
2981	if (DC_IS_INTEL(sc)) {
2982	/*
2983	* The real 21143 requires that the transmitter be idle
2984	* in order to change the transmit threshold or store
2985	* and forward state.
2986	*/
2987	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2988
2989	for (i = 0; i < DC_TIMEOUT; i++) {
2990	isr = CSR_READ_4(sc, DC_ISR);
2991	if (isr & DC_ISR_TX_IDLE)
2992	break;
2993	DELAY(10);
2994	}
2995	if (i == DC_TIMEOUT) {
2996	printk("dc%d: failed to force tx to idle state\n",
2997	sc->dc_unit);
2998	dc_init(sc);
2999	}
3000	}
3001
3002	printk("dc%d: TX underrun -- ", sc->dc_unit);
3003	sc->dc_txthresh += DC_TXTHRESH_INC;
3004	if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3005	printk("using store and forward mode\n");
3006	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3007	} else {
3008	printk("increasing TX threshold\n");
3009	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3010	DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3011	}
3012
3013	if (DC_IS_INTEL(sc))
3014	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3015
3016	return;
3017	}
3018
3019	#ifdef DEVICE_POLLING
3020	static poll_handler_t dc_poll;
3021
3022	static void
3023	dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3024	{
3025	struct dc_softc *sc = ifp->if_softc;
3026
3027	if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
3028	/* Re-enable interrupts. */
3029	CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3030	return;
3031	}
3032	sc->rxcycles = count;
3033	dc_rxeof(sc);
3034	dc_txeof(sc);
3035	if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE))
3036	dc_start(ifp);
3037
3038	if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
3039	u_int32_t status;
3040
3041	status = CSR_READ_4(sc, DC_ISR);
3042	status &= (DC_ISR_RX_WATDOGTIMEO\|DC_ISR_RX_NOBUF\|
3043	DC_ISR_TX_NOBUF\|DC_ISR_TX_IDLE\|DC_ISR_TX_UNDERRUN\|
3044	DC_ISR_BUS_ERR);
3045	if (!status)
3046	return ;
3047	/* ack what we have */
3048	CSR_WRITE_4(sc, DC_ISR, status);
3049
3050	if (status & (DC_ISR_RX_WATDOGTIMEO\|DC_ISR_RX_NOBUF) ) {
3051	u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3052	ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
3053
3054	if (dc_rx_resync(sc))
3055	dc_rxeof(sc);
3056	}
3057	/* restart transmit unit if necessary */
3058	if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
3059	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3060
3061	if (status & DC_ISR_TX_UNDERRUN)
3062	dc_tx_underrun(sc);
3063
3064	if (status & DC_ISR_BUS_ERR) {
3065	printk("dc_poll: dc%d bus error\n", sc->dc_unit);
3066	dc_reset(sc);
3067	dc_init(sc);
3068	}
3069	}
3070	}
3071	#endif /* DEVICE_POLLING */
3072
3073	static void
3074	dc_intr(rtems_vector_number v)
3075	{
3076	/* Need to make this work for multiple devices ... eventually */
3077	struct dc_softc *sc = &dc_softc_devs[0];
3078
3079
3080	/* Disable interrupts. */
3081	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3082
3083	rtems_event_send(sc->daemontid, IRQ_EVENT);
3084	#if 0
3085	if (sc->suspended) {
3086	return;
3087	}
3088
3089	ifp = &sc->arpcom.ac_if;
3090
3091	#ifdef DEVICE_POLLING
3092	if (ifp->if_ipending & IFF_POLLING)
3093	return;
3094	if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */
3095	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3096	return;
3097	}
3098	#endif /* DEVICE_POLLING */
3099	if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
3100	return ;
3101
3102	/* Suppress unwanted interrupts */
3103	if (!(ifp->if_flags & IFF_UP)) {
3104	if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
3105	dc_stop(sc);
3106	return;
3107	}
3108	#endif
3109	}
3110
3111
3112	static void
3113	dc_daemon(void * arg)
3114	{
3115	struct dc_softc sc = (struct dc_softc )arg;
3116	struct ifnet *ifp;
3117	u_int32_t status;
3118	rtems_event_set events;
3119
3120
3121	for(;;) {
3122	rtems_bsdnet_event_receive(RTEMS_ALL_EVENTS, \
3123	RTEMS_WAIT \| RTEMS_EVENT_ANY, \
3124	RTEMS_NO_TIMEOUT,
3125	&events);
3126
3127
3128	ifp = &sc->arpcom.ac_if;
3129
3130	while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) {
3131
3132	CSR_WRITE_4(sc, DC_ISR, status);
3133
3134	if (status & DC_ISR_RX_OK) {
3135	int curpkts;
3136	curpkts = ifp->if_ipackets;
3137	dc_rxeof(sc);
3138	if (curpkts == ifp->if_ipackets) {
3139	while(dc_rx_resync(sc))
3140	dc_rxeof(sc);
3141	}
3142	}
3143
3144	if (status & (DC_ISR_TX_OK\|DC_ISR_TX_NOBUF))
3145	dc_txeof(sc);
3146
3147	if (status & DC_ISR_TX_IDLE) {
3148	dc_txeof(sc);
3149	if (sc->dc_cdata.dc_tx_cnt) {
3150	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3151	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3152	}
3153	}
3154
3155	if (status & DC_ISR_TX_UNDERRUN)
3156	dc_tx_underrun(sc);
3157
3158	if ((status & DC_ISR_RX_WATDOGTIMEO)
3159	\|\| (status & DC_ISR_RX_NOBUF)) {
3160	int curpkts;
3161	curpkts = ifp->if_ipackets;
3162	dc_rxeof(sc);
3163	if (curpkts == ifp->if_ipackets) {
3164	while(dc_rx_resync(sc))
3165	dc_rxeof(sc);
3166	}
3167	}
3168
3169	if (status & DC_ISR_BUS_ERR) {
3170	dc_reset(sc);
3171	dc_init(sc);
3172	}
3173	}
3174
3175	/* Make atomic !!! */
3176	/* Re-enable interrupts. */
3177	CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3178
3179	if (ifp->if_snd.ifq_head != NULL)
3180	dc_start(ifp);
3181	}
3182
3183	}
3184
3185
3186	/*
3187	* Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
3188	* pointers to the fragment pointers.
3189	*/
3190	static int dc_encap(sc, m_head, txidx)
3191	struct dc_softc *sc;
3192	struct mbuf *m_head;
3193	u_int32_t *txidx;
3194	{
3195	struct dc_desc *f = NULL;
3196	struct mbuf *m;
3197	int frag, cur, cnt = 0;
3198
3199	/*
3200	* Start packing the mbufs in this chain into
3201	* the fragment pointers. Stop when we run out
3202	* of fragments or hit the end of the mbuf chain.
3203	*/
3204	m = m_head;
3205	cur = frag = *txidx;
3206
3207	for (m = m_head; m != NULL; m = m->m_next) {
3208	if (m->m_len != 0) {
3209	if (sc->dc_flags & DC_TX_ADMTEK_WAR) {
3210	if (*txidx != sc->dc_cdata.dc_tx_prod &&
3211	frag == (DC_TX_LIST_CNT - 1))
3212	return(ENOBUFS);
3213	}
3214	if ((DC_TX_LIST_CNT -
3215	(sc->dc_cdata.dc_tx_cnt + cnt)) < 5)
3216	return(ENOBUFS);
3217
3218	f = &sc->dc_ldata->dc_tx_list[frag];
3219	f->dc_ctl = DC_TXCTL_TLINK \| m->m_len;
3220	if (cnt == 0) {
3221	f->dc_status = 0;
3222	f->dc_ctl \|= DC_TXCTL_FIRSTFRAG;
3223	} else
3224	f->dc_status = DC_TXSTAT_OWN;
3225	f->dc_data = vtophys(mtod(m, vm_offset_t));
3226	cur = frag;
3227	DC_INC(frag, DC_TX_LIST_CNT);
3228	cnt++;
3229	}
3230	}
3231
3232	if (m != NULL)
3233	return(ENOBUFS);
3234
3235	sc->dc_cdata.dc_tx_cnt += cnt;
3236	sc->dc_cdata.dc_tx_chain[cur] = m_head;
3237	sc->dc_ldata->dc_tx_list[cur].dc_ctl \|= DC_TXCTL_LASTFRAG;
3238	if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3239	sc->dc_ldata->dc_tx_list[*txidx].dc_ctl \|= DC_TXCTL_FINT;
3240	if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3241	sc->dc_ldata->dc_tx_list[cur].dc_ctl \|= DC_TXCTL_FINT;
3242	if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
3243	sc->dc_ldata->dc_tx_list[cur].dc_ctl \|= DC_TXCTL_FINT;
3244	sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN;
3245	*txidx = frag;
3246
3247	return(0);
3248	}
3249
3250	/*
3251	* Coalesce an mbuf chain into a single mbuf cluster buffer.
3252	* Needed for some really badly behaved chips that just can't
3253	* do scatter/gather correctly.
3254	*/
3255	static int dc_coal(sc, m_head)
3256	struct dc_softc *sc;
3257	struct mbuf **m_head;
3258	{
3259	struct mbuf m_new, m;
3260
3261	m = *m_head;
3262	MGETHDR(m_new, M_DONTWAIT, MT_DATA);
3263	if (m_new == NULL)
3264	return(ENOBUFS);
3265	if (m->m_pkthdr.len > MHLEN) {
3266	MCLGET(m_new, M_DONTWAIT);
3267	if (!(m_new->m_flags & M_EXT)) {
3268	m_freem(m_new);
3269	return(ENOBUFS);
3270	}
3271	}
3272	m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t));
3273	m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len;
3274	m_freem(m);
3275	*m_head = m_new;
3276
3277	return(0);
3278	}
3279
3280	/*
3281	* Main transmit routine. To avoid having to do mbuf copies, we put pointers
3282	* to the mbuf data regions directly in the transmit lists. We also save a
3283	* copy of the pointers since the transmit list fragment pointers are
3284	* physical addresses.
3285	*/
3286
3287	static void dc_start(ifp)
3288	struct ifnet *ifp;
3289	{
3290	struct dc_softc *sc;
3291	struct mbuf *m_head = NULL;
3292	int idx;
3293
3294	sc = ifp->if_softc;
3295	#if 0
3296	if (!sc->dc_link && ifp->if_snd.ifq_len < 10)
3297	return;
3298	#endif
3299	if (ifp->if_flags & IFF_OACTIVE)
3300	return;
3301
3302	idx = sc->dc_cdata.dc_tx_prod;
3303
3304	while(sc->dc_cdata.dc_tx_chain[idx] == NULL) {
3305	IF_DEQUEUE(&ifp->if_snd, m_head);
3306	if (m_head == NULL)
3307	break;
3308
3309	if (sc->dc_flags & DC_TX_COALESCE &&
3310	m_head->m_next != NULL) {
3311	/* only coalesce if have >1 mbufs */
3312	if (dc_coal(sc, &m_head)) {
3313	IF_PREPEND(&ifp->if_snd, m_head);
3314	ifp->if_flags \|= IFF_OACTIVE;
3315	break;
3316	}
3317	}
3318
3319	if (dc_encap(sc, m_head, &idx)) {
3320	IF_PREPEND(&ifp->if_snd, m_head);
3321	ifp->if_flags \|= IFF_OACTIVE;
3322	break;
3323	}
3324	#if 0
3325	/*
3326	* If there's a BPF listener, bounce a copy of this frame
3327	* to him.
3328	*/
3329	if (ifp->if_bpf)
3330	bpf_mtap(ifp, m_head);
3331	#endif
3332	if (sc->dc_flags & DC_TX_ONE) {
3333	ifp->if_flags \|= IFF_OACTIVE;
3334	break;
3335	}
3336	}
3337
3338	/* Transmit */
3339	sc->dc_cdata.dc_tx_prod = idx;
3340	if (!(sc->dc_flags & DC_TX_POLL))
3341	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3342
3343	/*
3344	* Set a timeout in case the chip goes out to lunch.
3345	*/
3346	ifp->if_timer = 5;
3347
3348	return;
3349	}
3350
3351	static void dc_init(xsc)
3352	void *xsc;
3353	{
3354	struct dc_softc *sc = xsc;
3355	struct ifnet *ifp = &sc->arpcom.ac_if;
3356	/struct mii_data mii;*/
3357
3358
3359	/mii = device_get_softc(sc->dc_miibus);/
3360
3361	/*
3362	* Cancel pending I/O and free all RX/TX buffers.
3363	*/
3364	dc_stop(sc);
3365	dc_reset(sc);
3366
3367	/*
3368	* Set cache alignment and burst length.
3369	*/
3370	if (DC_IS_ASIX(sc) \|\| DC_IS_DAVICOM(sc))
3371	CSR_WRITE_4(sc, DC_BUSCTL, 0);
3372	else
3373	CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME\|DC_BUSCTL_MRLE);
3374	/*
3375	* Evenly share the bus between receive and transmit process.
3376	*/
3377	if (DC_IS_INTEL(sc))
3378	DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3379	if (DC_IS_DAVICOM(sc) \|\| DC_IS_INTEL(sc)) {
3380	DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3381	} else {
3382	DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3383	}
3384	if (sc->dc_flags & DC_TX_POLL)
3385	DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3386	switch(sc->dc_cachesize) {
3387	case 32:
3388	DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3389	break;
3390	case 16:
3391	DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3392	break;
3393	case 8:
3394	DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3395	break;
3396	case 0:
3397	default:
3398	DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3399	break;
3400	}
3401
3402	if (sc->dc_flags & DC_TX_STORENFWD)
3403	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3404	else {
3405	if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3406	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3407	} else {
3408	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3409	DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3410	}
3411	}
3412
3413	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3414	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3415
3416	if (DC_IS_MACRONIX(sc) \|\| DC_IS_PNICII(sc)) {
3417	/*
3418	* The app notes for the 98713 and 98715A say that
3419	* in order to have the chips operate properly, a magic
3420	* number must be written to CSR16. Macronix does not
3421	* document the meaning of these bits so there's no way
3422	* to know exactly what they do. The 98713 has a magic
3423	* number all its own; the rest all use a different one.
3424	*/
3425	DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3426	if (sc->dc_type == DC_TYPE_98713)
3427	DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3428	else
3429	DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3430	}
3431
3432	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3433	DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3434
3435	/* Init circular RX list. */
3436	if (dc_list_rx_init(sc) == ENOBUFS) {
3437	printk("dc%d: initialization failed: no "
3438	"memory for rx buffers\n", sc->dc_unit);
3439	dc_stop(sc);
3440	return;
3441	}
3442
3443	/*
3444	* Init tx descriptors.
3445	*/
3446	dc_list_tx_init(sc);
3447
3448	/*
3449	* Load the address of the RX list.
3450	*/
3451	CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0]));
3452	CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0]));
3453
3454	/*
3455	* Enable interrupts.
3456	*/
3457	#ifdef DEVICE_POLLING
3458	/*
3459	* ... but only if we are not polling, and make sure they are off in
3460	* the case of polling. Some cards (e.g. fxp) turn interrupts on
3461	* after a reset.
3462	*/
3463	if (ifp->if_ipending & IFF_POLLING)
3464	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3465	else
3466	#endif
3467	/* Enable interrupts */
3468	CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3469	CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3470
3471	/* Enable transmitter. */
3472	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3473
3474	/*
3475	* If this is an Intel 21143 and we're not using the
3476	* MII port, program the LED control pins so we get
3477	* link and activity indications.
3478	*/
3479	if (sc->dc_flags & DC_TULIP_LEDS) {
3480	CSR_WRITE_4(sc, DC_WATCHDOG,
3481	DC_WDOG_CTLWREN\|DC_WDOG_LINK\|DC_WDOG_ACTIVITY);
3482	CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3483	}
3484
3485	/*
3486	* Load the RX/multicast filter. We do this sort of late
3487	* because the filter programming scheme on the 21143 and
3488	* some clones requires DMAing a setup frame via the TX
3489	* engine, and we need the transmitter enabled for that.
3490	*/
3491	dc_setfilt(sc);
3492
3493	/* Enable receiver. */
3494	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3495	CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3496
3497	/mii_mediachg(mii);/
3498	dc_setcfg(sc, sc->dc_if_media);
3499
3500	ifp->if_flags \|= IFF_RUNNING;
3501	ifp->if_flags &= ~IFF_OACTIVE;
3502
3503
3504	#if 0
3505
3506	/* Don't start the ticker if this is a homePNA link. */
3507	if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_homePNA)
3508	sc->dc_link = 1;
3509	else {
3510	if (sc->dc_flags & DC_21143_NWAY)
3511	sc->dc_stat_ch = timeout(dc_tick, sc, hz/10);
3512	else
3513	sc->dc_stat_ch = timeout(dc_tick, sc, hz);
3514	}
3515
3516	#ifdef SRM_MEDIA
3517	if(sc->dc_srm_media) {
3518	struct ifreq ifr;
3519
3520	ifr.ifr_media = sc->dc_srm_media;
3521	ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA);
3522	sc->dc_srm_media = 0;
3523	}
3524	#endif
3525	#endif /* end if (0) */
3526	return;
3527	}
3528
3529
3530	#if 0
3531	/*
3532	* Set media options.
3533	*/
3534	static int dc_ifmedia_upd(ifp)
3535	struct ifnet *ifp;
3536	{
3537	struct dc_softc *sc;
3538	struct mii_data *mii;
3539	struct ifmedia *ifm;
3540
3541	sc = ifp->if_softc;
3542	mii = device_get_softc(sc->dc_miibus);
3543	mii_mediachg(mii);
3544	ifm = &mii->mii_media;
3545
3546	if (DC_IS_DAVICOM(sc) &&
3547	IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA)
3548	dc_setcfg(sc, ifm->ifm_media);
3549	else
3550	sc->dc_link = 0;
3551
3552	return(0);
3553	}
3554
3555	/*
3556	* Report current media status.
3557	*/
3558	static void dc_ifmedia_sts(ifp, ifmr)
3559	struct ifnet *ifp;
3560	struct ifmediareq *ifmr;
3561	{
3562	struct dc_softc *sc;
3563	struct mii_data *mii;
3564	struct ifmedia *ifm;
3565
3566	sc = ifp->if_softc;
3567	mii = device_get_softc(sc->dc_miibus);
3568	mii_pollstat(mii);
3569	ifm = &mii->mii_media;
3570	if (DC_IS_DAVICOM(sc)) {
3571	if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) {
3572	ifmr->ifm_active = ifm->ifm_media;
3573	ifmr->ifm_status = 0;
3574	return;
3575	}
3576	}
3577	ifmr->ifm_active = mii->mii_media_active;
3578	ifmr->ifm_status = mii->mii_media_status;
3579
3580	return;
3581	}
3582	#endif
3583
3584
3585	static int dc_ioctl(ifp, command, data)
3586	struct ifnet *ifp;
3587	int command;
3588	caddr_t data;
3589	{
3590	struct dc_softc *sc = ifp->if_softc;
3591	/struct ifreq ifr = (struct ifreq *) data;
3592	struct mii_data mii;/
3593	int error = 0;
3594
3595
3596	switch(command) {
3597	case SIOCSIFADDR:
3598	case SIOCGIFADDR:
3599	case SIOCSIFMTU:
3600	error = ether_ioctl(ifp, command, data);
3601	break;
3602	case SIOCSIFFLAGS:
3603	if (ifp->if_flags & IFF_UP) {
3604	int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3605	(IFF_PROMISC \| IFF_ALLMULTI);
3606	if (ifp->if_flags & IFF_RUNNING) {
3607	if (need_setfilt)
3608	dc_setfilt(sc);
3609	} else {
3610	sc->dc_txthresh = 0;
3611	dc_init(sc);
3612	}
3613	} else {
3614	if (ifp->if_flags & IFF_RUNNING)
3615	dc_stop(sc);
3616	}
3617	sc->dc_if_flags = ifp->if_flags;
3618	error = 0;
3619	break;
3620	case SIOCADDMULTI:
3621	case SIOCDELMULTI:
3622	dc_setfilt(sc);
3623	error = 0;
3624	break;
3625	#if 0
3626	case SIOCGIFMEDIA:
3627	case SIOCSIFMEDIA:
3628	mii = device_get_softc(sc->dc_miibus);
3629	error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3630	#ifdef SRM_MEDIA
3631	if (sc->dc_srm_media)
3632	sc->dc_srm_media = 0;
3633	#endif
3634	break;
3635	#endif
3636	default:
3637	error = EINVAL;
3638	break;
3639	}
3640
3641
3642	return(error);
3643	}
3644
3645	static void dc_watchdog(ifp)
3646	struct ifnet *ifp;
3647	{
3648	struct dc_softc *sc;
3649
3650	sc = ifp->if_softc;
3651
3652	ifp->if_oerrors++;
3653	printk("dc%d: watchdog timeout\n", sc->dc_unit);
3654
3655	dc_stop(sc);
3656	dc_reset(sc);
3657	dc_init(sc);
3658
3659	if (ifp->if_snd.ifq_head != NULL)
3660	dc_start(ifp);
3661
3662	return;
3663	}
3664
3665	/*
3666	* Stop the adapter and free any mbufs allocated to the
3667	* RX and TX lists.
3668	*/
3669	static void dc_stop(sc)
3670	struct dc_softc *sc;
3671	{
3672	register int i;
3673	struct ifnet *ifp;
3674
3675	ifp = &sc->arpcom.ac_if;
3676	ifp->if_timer = 0;
3677
3678	/untimeout(dc_tick, sc, sc->dc_stat_ch);/
3679
3680	ifp->if_flags &= ~(IFF_RUNNING \| IFF_OACTIVE);
3681	#ifdef DEVICE_POLLING
3682	ether_poll_deregister(ifp);
3683	#endif
3684
3685	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON\|DC_NETCFG_TX_ON));
3686	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3687	CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3688	CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3689	sc->dc_link = 0;
3690
3691	/*
3692	* Free data in the RX lists.
3693	*/
3694	for (i = 0; i < DC_RX_LIST_CNT; i++) {
3695	if (sc->dc_cdata.dc_rx_chain[i] != NULL) {
3696	m_freem(sc->dc_cdata.dc_rx_chain[i]);
3697	sc->dc_cdata.dc_rx_chain[i] = NULL;
3698	}
3699	}
3700	bzero((char *)&sc->dc_ldata->dc_rx_list,
3701	sizeof(sc->dc_ldata->dc_rx_list));
3702
3703	/*
3704	* Free the TX list buffers.
3705	*/
3706	for (i = 0; i < DC_TX_LIST_CNT; i++) {
3707	if (sc->dc_cdata.dc_tx_chain[i] != NULL) {
3708	if (sc->dc_ldata->dc_tx_list[i].dc_ctl &
3709	DC_TXCTL_SETUP) {
3710	sc->dc_cdata.dc_tx_chain[i] = NULL;
3711	continue;
3712	}
3713	m_freem(sc->dc_cdata.dc_tx_chain[i]);
3714	sc->dc_cdata.dc_tx_chain[i] = NULL;
3715	}
3716	}
3717
3718	bzero((char *)&sc->dc_ldata->dc_tx_list,
3719	sizeof(sc->dc_ldata->dc_tx_list));
3720
3721	return;
3722	}
3723
3724
3725	#if 0
3726	/*
3727	* Stop all chip I/O so that the kernel's probe routines don't
3728	* get confused by errant DMAs when rebooting.
3729	*/
3730	static void dc_shutdown(dev)
3731	device_t dev;
3732	{
3733	struct dc_softc *sc;
3734
3735	sc = device_get_softc(dev);
3736
3737	dc_stop(sc);
3738
3739	return;
3740	}
3741
3742	/*
3743	* Device suspend routine. Stop the interface and save some PCI
3744	* settings in case the BIOS doesn't restore them properly on
3745	* resume.
3746	*/
3747	static int dc_suspend(dev)
3748	device_t dev;
3749	{
3750	register int i;
3751	int s;
3752	struct dc_softc *sc;
3753
3754
3755	sc = device_get_softc(dev);
3756
3757	dc_stop(sc);
3758
3759	for (i = 0; i < 5; i++)
3760	sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
3761	sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
3762	sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
3763	sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3764	sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3765
3766	sc->suspended = 1;
3767
3768	return (0);
3769	}
3770
3771	/*
3772	* Device resume routine. Restore some PCI settings in case the BIOS
3773	* doesn't, re-enable busmastering, and restart the interface if
3774	* appropriate.
3775	*/
3776	static int dc_resume(dev)
3777	device_t dev;
3778	{
3779	register int i;
3780	int s;
3781	struct dc_softc *sc;
3782	struct ifnet *ifp;
3783
3784
3785	sc = device_get_softc(dev);
3786	ifp = &sc->arpcom.ac_if;
3787
3788	dc_acpi(dev);
3789
3790	/* better way to do this? */
3791	for (i = 0; i < 5; i++)
3792	pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
3793	pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
3794	pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
3795	pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
3796	pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
3797
3798	/* reenable busmastering */
3799	pci_enable_busmaster(dev);
3800	pci_enable_io(dev, DC_RES);
3801
3802	/* reinitialize interface if necessary */
3803	if (ifp->if_flags & IFF_UP)
3804	dc_init(sc);
3805
3806	sc->suspended = 0;
3807
3808	return (0);
3809	}
3810	#endif
3811
3812
3813	#endif /* end if supported */

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