1 | /* |
---|
2 | * Ported from FreeBSD --> RTEMS, december 03. |
---|
3 | * Daron Chabot <daron@nucleus.usask.ca> |
---|
4 | * -- only tested with i386 bsp. |
---|
5 | * -- supports *one* card (until the PCI & IRQ APIs get sorted out ;-)) |
---|
6 | * |
---|
7 | * |
---|
8 | * Copyright (c) 1997, 1998, 1999 |
---|
9 | * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. |
---|
10 | * |
---|
11 | * Redistribution and use in source and binary forms, with or without |
---|
12 | * modification, are permitted provided that the following conditions |
---|
13 | * are met: |
---|
14 | * 1. Redistributions of source code must retain the above copyright |
---|
15 | * notice, this list of conditions and the following disclaimer. |
---|
16 | * 2. Redistributions in binary form must reproduce the above copyright |
---|
17 | * notice, this list of conditions and the following disclaimer in the |
---|
18 | * documentation and/or other materials provided with the distribution. |
---|
19 | * 3. All advertising materials mentioning features or use of this software |
---|
20 | * must display the following acknowledgement: |
---|
21 | * This product includes software developed by Bill Paul. |
---|
22 | * 4. Neither the name of the author nor the names of any co-contributors |
---|
23 | * may be used to endorse or promote products derived from this software |
---|
24 | * without specific prior written permission. |
---|
25 | * |
---|
26 | * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND |
---|
27 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
---|
28 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
---|
29 | * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD |
---|
30 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
---|
31 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
---|
32 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
---|
33 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
---|
34 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
---|
35 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
---|
36 | * THE POSSIBILITY OF SUCH DAMAGE. |
---|
37 | * |
---|
38 | * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.41 2003/03/05 18:42:33 njl Exp $ |
---|
39 | */ |
---|
40 | |
---|
41 | /* |
---|
42 | * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 |
---|
43 | * series chips and several workalikes including the following: |
---|
44 | * |
---|
45 | * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) |
---|
46 | * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) |
---|
47 | * Lite-On 82c168/82c169 PNIC (www.litecom.com) |
---|
48 | * ASIX Electronics AX88140A (www.asix.com.tw) |
---|
49 | * ASIX Electronics AX88141 (www.asix.com.tw) |
---|
50 | * ADMtek AL981 (www.admtek.com.tw) |
---|
51 | * ADMtek AN985 (www.admtek.com.tw) |
---|
52 | * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) |
---|
53 | * Accton EN1217 (www.accton.com) |
---|
54 | * Conexant LANfinity (www.conexant.com) |
---|
55 | * |
---|
56 | * Datasheets for the 21143 are available at developer.intel.com. |
---|
57 | * Datasheets for the clone parts can be found at their respective sites. |
---|
58 | * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) |
---|
59 | * The PNIC II is essentially a Macronix 98715A chip; the only difference |
---|
60 | * worth noting is that its multicast hash table is only 128 bits wide |
---|
61 | * instead of 512. |
---|
62 | * |
---|
63 | * Written by Bill Paul <wpaul@ee.columbia.edu> |
---|
64 | * Electrical Engineering Department |
---|
65 | * Columbia University, New York City |
---|
66 | */ |
---|
67 | |
---|
68 | /* |
---|
69 | * The Intel 21143 is the successor to the DEC 21140. It is basically |
---|
70 | * the same as the 21140 but with a few new features. The 21143 supports |
---|
71 | * three kinds of media attachments: |
---|
72 | * |
---|
73 | * o MII port, for 10Mbps and 100Mbps support and NWAY |
---|
74 | * autonegotiation provided by an external PHY. |
---|
75 | * o SYM port, for symbol mode 100Mbps support. |
---|
76 | * o 10baseT port. |
---|
77 | * o AUI/BNC port. |
---|
78 | * |
---|
79 | * The 100Mbps SYM port and 10baseT port can be used together in |
---|
80 | * combination with the internal NWAY support to create a 10/100 |
---|
81 | * autosensing configuration. |
---|
82 | * |
---|
83 | * Note that not all tulip workalikes are handled in this driver: we only |
---|
84 | * deal with those which are relatively well behaved. The Winbond is |
---|
85 | * handled separately due to its different register offsets and the |
---|
86 | * special handling needed for its various bugs. The PNIC is handled |
---|
87 | * here, but I'm not thrilled about it. |
---|
88 | * |
---|
89 | * All of the workalike chips use some form of MII transceiver support |
---|
90 | * with the exception of the Macronix chips, which also have a SYM port. |
---|
91 | * The ASIX AX88140A is also documented to have a SYM port, but all |
---|
92 | * the cards I've seen use an MII transceiver, probably because the |
---|
93 | * AX88140A doesn't support internal NWAY. |
---|
94 | */ |
---|
95 | |
---|
96 | /* |
---|
97 | * This driver only supports architectures with the new style |
---|
98 | * exception processing. The following checks try to keep this |
---|
99 | * from being compiled on systems which can't support this driver. |
---|
100 | */ |
---|
101 | |
---|
102 | #if defined(DRIVER_SUPPORTED) |
---|
103 | #undef DRIVER_SUPPORTED |
---|
104 | #endif |
---|
105 | |
---|
106 | #if defined(__i386__) |
---|
107 | #define DRIVER_SUPPORTED |
---|
108 | #endif |
---|
109 | |
---|
110 | #if defined(__PPC__) |
---|
111 | #define DRIVER_SUPPORTED |
---|
112 | #endif |
---|
113 | |
---|
114 | #include <bsp.h> |
---|
115 | |
---|
116 | #if !defined(PCI_DRAM_OFFSET) |
---|
117 | #undef DRIVER_SUPPORTED |
---|
118 | #endif |
---|
119 | |
---|
120 | #if defined(DRIVER_SUPPORTED) /* this covers the file "globally"... */ |
---|
121 | #include <rtems/pci.h> |
---|
122 | |
---|
123 | #include <rtems/error.h> |
---|
124 | #include <errno.h> |
---|
125 | #include <rtems/rtems_bsdnet.h> |
---|
126 | |
---|
127 | #include <net/if_types.h> |
---|
128 | |
---|
129 | #include <sys/param.h> |
---|
130 | #include <sys/sockio.h> |
---|
131 | #include <sys/socket.h> |
---|
132 | #include <sys/mbuf.h> |
---|
133 | #include <net/if.h> |
---|
134 | #include <netinet/in.h> |
---|
135 | #include <netinet/if_ether.h> |
---|
136 | #include <sys/malloc.h> |
---|
137 | #include <sys/systm.h> |
---|
138 | #include <bsp.h> |
---|
139 | |
---|
140 | /* moved to cpukit/include/rtems in CVS current ! */ |
---|
141 | /*#include "if_media.h" */ |
---|
142 | /*#include "pci.h" */ |
---|
143 | #include <net/if_media.h> |
---|
144 | #include <rtems/pci.h> |
---|
145 | /* |
---|
146 | #include <sys/kernel.h> |
---|
147 | #include <sys/sysctl.h> |
---|
148 | */ |
---|
149 | |
---|
150 | #include <vm/vm.h> /* for vtophys */ |
---|
151 | |
---|
152 | |
---|
153 | #define vtophys(p) (uintptr_t)(p) |
---|
154 | |
---|
155 | /* |
---|
156 | #include <net/if_arp.h> |
---|
157 | #include <net/if_vlan_var.h> |
---|
158 | #include <net/bpf.h> |
---|
159 | */ |
---|
160 | |
---|
161 | #if 0 |
---|
162 | #include <vm/pmap.h> /* for vtophys */ |
---|
163 | #include <machine/clock.h> /* for DELAY */ |
---|
164 | #include <machine/bus_pio.h> |
---|
165 | #include <machine/bus_memio.h> |
---|
166 | #include <machine/bus.h> |
---|
167 | #include <machine/resource.h> |
---|
168 | #include <sys/bus.h> |
---|
169 | #include <sys/rman.h> |
---|
170 | #endif |
---|
171 | #include <dev/mii/mii.h> |
---|
172 | #if 0 |
---|
173 | #include <dev/mii/miivar.h> |
---|
174 | |
---|
175 | #include <pci/pcireg.h> |
---|
176 | #include <pci/pcivar.h> |
---|
177 | #endif |
---|
178 | |
---|
179 | /* NOTE: use mem space mapping (for now ...) |
---|
180 | #define DC_USEIOSPACE |
---|
181 | */ |
---|
182 | |
---|
183 | #ifdef __alpha__ |
---|
184 | #define SRM_MEDIA |
---|
185 | #endif |
---|
186 | |
---|
187 | #include <bsp/irq.h> |
---|
188 | |
---|
189 | |
---|
190 | #include "if_dcreg.h" |
---|
191 | |
---|
192 | |
---|
193 | #define DRIVER_PREFIX "tl" |
---|
194 | #define NDRIVER 1 |
---|
195 | #define IRQ_EVENT RTEMS_EVENT_13 /* Ha ... */ |
---|
196 | static struct dc_softc dc_softc_devs[NDRIVER]; |
---|
197 | |
---|
198 | #define UNUSED |
---|
199 | |
---|
200 | #if 0 |
---|
201 | /* "controller miibus0" required. See GENERIC if you get errors here. */ |
---|
202 | #include "miibus_if.h" |
---|
203 | |
---|
204 | |
---|
205 | |
---|
206 | #ifndef lint |
---|
207 | static const char rcsid[] = |
---|
208 | "$FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.41 2003/03/05 18:42:33 njl Exp $"; |
---|
209 | #endif |
---|
210 | |
---|
211 | #endif |
---|
212 | |
---|
213 | |
---|
214 | /* |
---|
215 | * Various supported device vendors/types and their names. |
---|
216 | * NOTE: |
---|
217 | * ----- |
---|
218 | * Only the "ADMtek AN985" has been tested under RTEMS !!! |
---|
219 | */ |
---|
220 | static struct dc_type dc_devs[] = { |
---|
221 | { DC_VENDORID_DEC, DC_DEVICEID_21143, |
---|
222 | "Intel 21143 10/100BaseTX", 0 }, |
---|
223 | { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, |
---|
224 | "Davicom DM9009 10/100BaseTX", 0 }, |
---|
225 | { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, |
---|
226 | "Davicom DM9100 10/100BaseTX", 0 }, |
---|
227 | { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, |
---|
228 | "Davicom DM9102 10/100BaseTX", 0 }, |
---|
229 | { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, |
---|
230 | "Davicom DM9102A 10/100BaseTX", 0 }, |
---|
231 | { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, |
---|
232 | "ADMtek AL981 10/100BaseTX", 0 }, |
---|
233 | { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, |
---|
234 | "ADMtek AN985 10/100BaseTX", 0 }, |
---|
235 | { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, |
---|
236 | "ASIX AX88140A 10/100BaseTX", 0 }, |
---|
237 | { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, |
---|
238 | "ASIX AX88141 10/100BaseTX", 0 }, |
---|
239 | { DC_VENDORID_MX, DC_DEVICEID_98713, |
---|
240 | "Macronix 98713 10/100BaseTX", 0 }, |
---|
241 | { DC_VENDORID_MX, DC_DEVICEID_98713, |
---|
242 | "Macronix 98713A 10/100BaseTX", 0 }, |
---|
243 | { DC_VENDORID_CP, DC_DEVICEID_98713_CP, |
---|
244 | "Compex RL100-TX 10/100BaseTX", 0 }, |
---|
245 | { DC_VENDORID_CP, DC_DEVICEID_98713_CP, |
---|
246 | "Compex RL100-TX 10/100BaseTX", 0 }, |
---|
247 | { DC_VENDORID_MX, DC_DEVICEID_987x5, |
---|
248 | "Macronix 98715/98715A 10/100BaseTX", 0 }, |
---|
249 | { DC_VENDORID_MX, DC_DEVICEID_987x5, |
---|
250 | "Macronix 98715AEC-C 10/100BaseTX", 0 }, |
---|
251 | { DC_VENDORID_MX, DC_DEVICEID_987x5, |
---|
252 | "Macronix 98725 10/100BaseTX", 0 }, |
---|
253 | { DC_VENDORID_MX, DC_DEVICEID_98727, |
---|
254 | "Macronix 98727/98732 10/100BaseTX", 0 }, |
---|
255 | { DC_VENDORID_LO, DC_DEVICEID_82C115, |
---|
256 | "LC82C115 PNIC II 10/100BaseTX", 0 }, |
---|
257 | { DC_VENDORID_LO, DC_DEVICEID_82C168, |
---|
258 | "82c168 PNIC 10/100BaseTX", 0 }, |
---|
259 | { DC_VENDORID_LO, DC_DEVICEID_82C168, |
---|
260 | "82c169 PNIC 10/100BaseTX", 0 }, |
---|
261 | { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, |
---|
262 | "Accton EN1217 10/100BaseTX", 0 }, |
---|
263 | { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, |
---|
264 | "Accton EN2242 MiniPCI 10/100BaseTX", 0 }, |
---|
265 | { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, |
---|
266 | "Conexant LANfinity MiniPCI 10/100BaseTX", 0 }, |
---|
267 | { 0, 0, NULL, 0 } |
---|
268 | }; |
---|
269 | |
---|
270 | #if 0 |
---|
271 | static int dc_probe __P((device_t)); |
---|
272 | static int dc_attach __P((device_t)); |
---|
273 | static int dc_detach __P((device_t)); |
---|
274 | static int dc_suspend __P((device_t)); |
---|
275 | static int dc_resume __P((device_t)); |
---|
276 | static void dc_shutdown __P((device_t)); |
---|
277 | static void dc_acpi __P((device_t)); |
---|
278 | #endif |
---|
279 | |
---|
280 | static struct dc_type *dc_devtype(int); |
---|
281 | static int dc_newbuf(struct dc_softc *, int, struct mbuf *); |
---|
282 | static int dc_encap(struct dc_softc *, struct mbuf *, |
---|
283 | u_int32_t *); |
---|
284 | static int dc_coal(struct dc_softc *, struct mbuf **); |
---|
285 | static void dc_pnic_rx_bug_war(struct dc_softc *, int); |
---|
286 | static int dc_rx_resync(struct dc_softc *); |
---|
287 | static void dc_rxeof(struct dc_softc *); |
---|
288 | static void dc_txeof(struct dc_softc *); |
---|
289 | /*static void dc_tick((void *));*/ |
---|
290 | static void dc_tx_underrun(struct dc_softc *); |
---|
291 | static void dc_intr(void *); |
---|
292 | static void dc_daemon(void *); |
---|
293 | static void dc_start(struct ifnet *); |
---|
294 | static int dc_ioctl(struct ifnet *, ioctl_command_t, caddr_t); |
---|
295 | static void dc_init(void *); |
---|
296 | static void dc_stop(struct dc_softc *); |
---|
297 | static void dc_watchdog(struct ifnet *); |
---|
298 | #if 0 |
---|
299 | static int dc_ifmedia_upd __P((struct ifnet *)); |
---|
300 | static void dc_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); |
---|
301 | #endif |
---|
302 | |
---|
303 | static void dc_delay(struct dc_softc *); |
---|
304 | static void dc_eeprom_idle(struct dc_softc *); |
---|
305 | static void dc_eeprom_putbyte(struct dc_softc *, int); |
---|
306 | static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *); |
---|
307 | static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *); |
---|
308 | static void dc_eeprom_width(struct dc_softc *); |
---|
309 | static void dc_read_eeprom(struct dc_softc *, caddr_t, int,int, int); |
---|
310 | |
---|
311 | #if 0 |
---|
312 | static void dc_mii_writebit __P((struct dc_softc *, int)); |
---|
313 | static int dc_mii_readbit __P((struct dc_softc *)); |
---|
314 | static void dc_mii_sync __P((struct dc_softc *)); |
---|
315 | static void dc_mii_send __P((struct dc_softc *, u_int32_t, int)); |
---|
316 | static int dc_mii_readreg __P((struct dc_softc *, struct dc_mii_frame *)); |
---|
317 | static int dc_mii_writereg __P((struct dc_softc *, struct dc_mii_frame *)); |
---|
318 | static int dc_miibus_readreg __P((device_t, int, int)); |
---|
319 | static int dc_miibus_writereg __P((device_t, int, int, int)); |
---|
320 | static void dc_miibus_statchg __P((device_t)); |
---|
321 | static void dc_miibus_mediainit __P((device_t)); |
---|
322 | #endif |
---|
323 | |
---|
324 | static void dc_setcfg(struct dc_softc *, int); |
---|
325 | static u_int32_t dc_crc_le(struct dc_softc *, caddr_t); |
---|
326 | #ifndef UNUSED |
---|
327 | static u_int32_t dc_crc_be(caddr_t); |
---|
328 | #endif |
---|
329 | static void dc_setfilt_21143(struct dc_softc *); |
---|
330 | static void dc_setfilt_asix(struct dc_softc *); |
---|
331 | static void dc_setfilt_admtek(struct dc_softc *); |
---|
332 | static void dc_setfilt(struct dc_softc *); |
---|
333 | static void dc_reset(struct dc_softc *); |
---|
334 | static int dc_list_rx_init(struct dc_softc *); |
---|
335 | static int dc_list_tx_init(struct dc_softc *); |
---|
336 | static void dc_read_srom(struct dc_softc *, int); |
---|
337 | static void dc_parse_21143_srom(struct dc_softc *); |
---|
338 | static void dc_apply_fixup(struct dc_softc *, int); |
---|
339 | |
---|
340 | #if 0 |
---|
341 | static void dc_decode_leaf_sia __P((struct dc_softc *, |
---|
342 | struct dc_eblock_sia *)); |
---|
343 | static void dc_decode_leaf_mii __P((struct dc_softc *, |
---|
344 | struct dc_eblock_mii *)); |
---|
345 | static void dc_decode_leaf_sym __P((struct dc_softc *, |
---|
346 | struct dc_eblock_sym *)); |
---|
347 | #endif |
---|
348 | |
---|
349 | |
---|
350 | #ifdef DC_USEIOSPACE |
---|
351 | #define DC_RES SYS_RES_IOPORT |
---|
352 | #define DC_RID DC_PCI_CFBIO |
---|
353 | #else |
---|
354 | #define DC_RES SYS_RES_MEMORY |
---|
355 | #define DC_RID DC_PCI_CFBMA |
---|
356 | #endif |
---|
357 | |
---|
358 | #if 0 |
---|
359 | static device_method_t dc_methods[] = { |
---|
360 | /* Device interface */ |
---|
361 | DEVMETHOD(device_probe, dc_probe), |
---|
362 | DEVMETHOD(device_attach, dc_attach), |
---|
363 | DEVMETHOD(device_detach, dc_detach), |
---|
364 | DEVMETHOD(device_suspend, dc_suspend), |
---|
365 | DEVMETHOD(device_resume, dc_resume), |
---|
366 | DEVMETHOD(device_shutdown, dc_shutdown), |
---|
367 | |
---|
368 | /* bus interface */ |
---|
369 | DEVMETHOD(bus_print_child, bus_generic_print_child), |
---|
370 | DEVMETHOD(bus_driver_added, bus_generic_driver_added), |
---|
371 | |
---|
372 | /* MII interface */ |
---|
373 | DEVMETHOD(miibus_readreg, dc_miibus_readreg), |
---|
374 | DEVMETHOD(miibus_writereg, dc_miibus_writereg), |
---|
375 | DEVMETHOD(miibus_statchg, dc_miibus_statchg), |
---|
376 | DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), |
---|
377 | |
---|
378 | { 0, 0 } |
---|
379 | }; |
---|
380 | |
---|
381 | static driver_t dc_driver = { |
---|
382 | "dc", |
---|
383 | dc_methods, |
---|
384 | sizeof(struct dc_softc) |
---|
385 | }; |
---|
386 | |
---|
387 | static devclass_t dc_devclass; |
---|
388 | #endif |
---|
389 | |
---|
390 | |
---|
391 | #ifdef __i386__ |
---|
392 | static int dc_quick=1; |
---|
393 | #if 0 |
---|
394 | SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, |
---|
395 | &dc_quick,0,"do not mdevget in dc driver"); |
---|
396 | #endif |
---|
397 | #endif |
---|
398 | |
---|
399 | #if 0 |
---|
400 | DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); |
---|
401 | DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); |
---|
402 | #endif |
---|
403 | |
---|
404 | |
---|
405 | #define DC_SETBIT(sc, reg, x) \ |
---|
406 | CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) |
---|
407 | |
---|
408 | #define DC_CLRBIT(sc, reg, x) \ |
---|
409 | CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) |
---|
410 | |
---|
411 | #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) |
---|
412 | #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) |
---|
413 | |
---|
414 | |
---|
415 | /* XXX Fixme: rtems_bsp_delay( ) for the pc386 BSP (at least) |
---|
416 | * needs work... see pc386/include/bsp.h. |
---|
417 | * I have "a" solution, utilizing the 2nd i8254 timer, |
---|
418 | * if anyone is interested (first timer is used for clock_tick ISR)... |
---|
419 | */ |
---|
420 | #ifdef __i386__ |
---|
421 | extern void Wait_X_ms( unsigned int ); |
---|
422 | #define DELAY(n) Wait_X_ms( (unsigned int)((n)/100) ) |
---|
423 | #else |
---|
424 | #define DELAY(n) rtems_bsp_delay(n) |
---|
425 | #endif |
---|
426 | |
---|
427 | |
---|
428 | static void dc_delay(sc) |
---|
429 | struct dc_softc *sc; |
---|
430 | { |
---|
431 | int idx; |
---|
432 | |
---|
433 | for (idx = (300 / 33) + 1; idx > 0; idx--) |
---|
434 | CSR_READ_4(sc, DC_BUSCTL); |
---|
435 | } |
---|
436 | |
---|
437 | static void dc_eeprom_width(sc) |
---|
438 | struct dc_softc *sc; |
---|
439 | { |
---|
440 | int i; |
---|
441 | |
---|
442 | /* Force EEPROM to idle state. */ |
---|
443 | dc_eeprom_idle(sc); |
---|
444 | |
---|
445 | /* Enter EEPROM access mode. */ |
---|
446 | CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); |
---|
447 | dc_delay(sc); |
---|
448 | DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); |
---|
449 | dc_delay(sc); |
---|
450 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
---|
451 | dc_delay(sc); |
---|
452 | DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); |
---|
453 | dc_delay(sc); |
---|
454 | |
---|
455 | for (i = 3; i--;) { |
---|
456 | if (6 & (1 << i)) |
---|
457 | DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); |
---|
458 | else |
---|
459 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); |
---|
460 | dc_delay(sc); |
---|
461 | DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
---|
462 | dc_delay(sc); |
---|
463 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
---|
464 | dc_delay(sc); |
---|
465 | } |
---|
466 | |
---|
467 | for (i = 1; i <= 12; i++) { |
---|
468 | DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
---|
469 | dc_delay(sc); |
---|
470 | if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { |
---|
471 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
---|
472 | dc_delay(sc); |
---|
473 | break; |
---|
474 | } |
---|
475 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
---|
476 | dc_delay(sc); |
---|
477 | } |
---|
478 | |
---|
479 | /* Turn off EEPROM access mode. */ |
---|
480 | dc_eeprom_idle(sc); |
---|
481 | |
---|
482 | if (i < 4 || i > 12) |
---|
483 | sc->dc_romwidth = 6; |
---|
484 | else |
---|
485 | sc->dc_romwidth = i; |
---|
486 | |
---|
487 | /* Enter EEPROM access mode. */ |
---|
488 | CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); |
---|
489 | dc_delay(sc); |
---|
490 | DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); |
---|
491 | dc_delay(sc); |
---|
492 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
---|
493 | dc_delay(sc); |
---|
494 | DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); |
---|
495 | dc_delay(sc); |
---|
496 | |
---|
497 | /* Turn off EEPROM access mode. */ |
---|
498 | dc_eeprom_idle(sc); |
---|
499 | } |
---|
500 | |
---|
501 | static void dc_eeprom_idle(sc) |
---|
502 | struct dc_softc *sc; |
---|
503 | { |
---|
504 | register int i; |
---|
505 | |
---|
506 | CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); |
---|
507 | dc_delay(sc); |
---|
508 | DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); |
---|
509 | dc_delay(sc); |
---|
510 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
---|
511 | dc_delay(sc); |
---|
512 | DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); |
---|
513 | dc_delay(sc); |
---|
514 | |
---|
515 | for (i = 0; i < 25; i++) { |
---|
516 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
---|
517 | dc_delay(sc); |
---|
518 | DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
---|
519 | dc_delay(sc); |
---|
520 | } |
---|
521 | |
---|
522 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
---|
523 | dc_delay(sc); |
---|
524 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); |
---|
525 | dc_delay(sc); |
---|
526 | CSR_WRITE_4(sc, DC_SIO, 0x00000000); |
---|
527 | |
---|
528 | return; |
---|
529 | } |
---|
530 | |
---|
531 | /* |
---|
532 | * Send a read command and address to the EEPROM, check for ACK. |
---|
533 | */ |
---|
534 | static void dc_eeprom_putbyte(sc, addr) |
---|
535 | struct dc_softc *sc; |
---|
536 | int addr; |
---|
537 | { |
---|
538 | register int d, i; |
---|
539 | |
---|
540 | d = DC_EECMD_READ >> 6; |
---|
541 | for (i = 3; i--; ) { |
---|
542 | if (d & (1 << i)) |
---|
543 | DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); |
---|
544 | else |
---|
545 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); |
---|
546 | dc_delay(sc); |
---|
547 | DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
---|
548 | dc_delay(sc); |
---|
549 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
---|
550 | dc_delay(sc); |
---|
551 | } |
---|
552 | |
---|
553 | /* |
---|
554 | * Feed in each bit and strobe the clock. |
---|
555 | */ |
---|
556 | for (i = sc->dc_romwidth; i--;) { |
---|
557 | if (addr & (1 << i)) { |
---|
558 | SIO_SET(DC_SIO_EE_DATAIN); |
---|
559 | } else { |
---|
560 | SIO_CLR(DC_SIO_EE_DATAIN); |
---|
561 | } |
---|
562 | dc_delay(sc); |
---|
563 | SIO_SET(DC_SIO_EE_CLK); |
---|
564 | dc_delay(sc); |
---|
565 | SIO_CLR(DC_SIO_EE_CLK); |
---|
566 | dc_delay(sc); |
---|
567 | } |
---|
568 | |
---|
569 | return; |
---|
570 | } |
---|
571 | |
---|
572 | /* |
---|
573 | * Read a word of data stored in the EEPROM at address 'addr.' |
---|
574 | * The PNIC 82c168/82c169 has its own non-standard way to read |
---|
575 | * the EEPROM. |
---|
576 | */ |
---|
577 | static void dc_eeprom_getword_pnic(sc, addr, dest) |
---|
578 | struct dc_softc *sc; |
---|
579 | int addr; |
---|
580 | u_int16_t *dest; |
---|
581 | { |
---|
582 | register int i; |
---|
583 | u_int32_t r; |
---|
584 | |
---|
585 | CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); |
---|
586 | |
---|
587 | for (i = 0; i < DC_TIMEOUT; i++) { |
---|
588 | DELAY(1); |
---|
589 | r = CSR_READ_4(sc, DC_SIO); |
---|
590 | if (!(r & DC_PN_SIOCTL_BUSY)) { |
---|
591 | *dest = (u_int16_t)(r & 0xFFFF); |
---|
592 | return; |
---|
593 | } |
---|
594 | } |
---|
595 | |
---|
596 | return; |
---|
597 | } |
---|
598 | |
---|
599 | /* |
---|
600 | * Read a word of data stored in the EEPROM at address 'addr.' |
---|
601 | */ |
---|
602 | static void dc_eeprom_getword(sc, addr, dest) |
---|
603 | struct dc_softc *sc; |
---|
604 | int addr; |
---|
605 | u_int16_t *dest; |
---|
606 | { |
---|
607 | register int i; |
---|
608 | u_int16_t word = 0; |
---|
609 | |
---|
610 | /* Force EEPROM to idle state. */ |
---|
611 | dc_eeprom_idle(sc); |
---|
612 | |
---|
613 | /* Enter EEPROM access mode. */ |
---|
614 | CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); |
---|
615 | dc_delay(sc); |
---|
616 | DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); |
---|
617 | dc_delay(sc); |
---|
618 | DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); |
---|
619 | dc_delay(sc); |
---|
620 | DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); |
---|
621 | dc_delay(sc); |
---|
622 | |
---|
623 | /* |
---|
624 | * Send address of word we want to read. |
---|
625 | */ |
---|
626 | dc_eeprom_putbyte(sc, addr); |
---|
627 | |
---|
628 | /* |
---|
629 | * Start reading bits from EEPROM. |
---|
630 | */ |
---|
631 | for (i = 0x8000; i; i >>= 1) { |
---|
632 | SIO_SET(DC_SIO_EE_CLK); |
---|
633 | dc_delay(sc); |
---|
634 | if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) |
---|
635 | word |= i; |
---|
636 | dc_delay(sc); |
---|
637 | SIO_CLR(DC_SIO_EE_CLK); |
---|
638 | dc_delay(sc); |
---|
639 | } |
---|
640 | |
---|
641 | /* Turn off EEPROM access mode. */ |
---|
642 | dc_eeprom_idle(sc); |
---|
643 | |
---|
644 | *dest = word; |
---|
645 | |
---|
646 | return; |
---|
647 | } |
---|
648 | |
---|
649 | /* |
---|
650 | * Read a sequence of words from the EEPROM. |
---|
651 | */ |
---|
652 | static void dc_read_eeprom(sc, dest, off, cnt, swap) |
---|
653 | struct dc_softc *sc; |
---|
654 | caddr_t dest; |
---|
655 | int off; |
---|
656 | int cnt; |
---|
657 | int swap; |
---|
658 | { |
---|
659 | int i; |
---|
660 | u_int16_t word = 0, *ptr; |
---|
661 | |
---|
662 | for (i = 0; i < cnt; i++) { |
---|
663 | if (DC_IS_PNIC(sc)) |
---|
664 | dc_eeprom_getword_pnic(sc, off + i, &word); |
---|
665 | else |
---|
666 | dc_eeprom_getword(sc, off + i, &word); |
---|
667 | ptr = (u_int16_t *)(dest + (i * 2)); |
---|
668 | if (swap) |
---|
669 | *ptr = ntohs(word); |
---|
670 | else |
---|
671 | *ptr = word; |
---|
672 | } |
---|
673 | |
---|
674 | return; |
---|
675 | } |
---|
676 | |
---|
677 | |
---|
678 | #if 0 |
---|
679 | /* |
---|
680 | * The following two routines are taken from the Macronix 98713 |
---|
681 | * Application Notes pp.19-21. |
---|
682 | */ |
---|
683 | /* |
---|
684 | * Write a bit to the MII bus. |
---|
685 | */ |
---|
686 | static void dc_mii_writebit(sc, bit) |
---|
687 | struct dc_softc *sc; |
---|
688 | int bit; |
---|
689 | { |
---|
690 | if (bit) |
---|
691 | CSR_WRITE_4(sc, DC_SIO, |
---|
692 | DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); |
---|
693 | else |
---|
694 | CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); |
---|
695 | |
---|
696 | DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); |
---|
697 | DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); |
---|
698 | |
---|
699 | return; |
---|
700 | } |
---|
701 | |
---|
702 | /* |
---|
703 | * Read a bit from the MII bus. |
---|
704 | */ |
---|
705 | static int dc_mii_readbit(sc) |
---|
706 | struct dc_softc *sc; |
---|
707 | { |
---|
708 | CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); |
---|
709 | CSR_READ_4(sc, DC_SIO); |
---|
710 | DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); |
---|
711 | DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); |
---|
712 | if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) |
---|
713 | return(1); |
---|
714 | |
---|
715 | return(0); |
---|
716 | } |
---|
717 | |
---|
718 | /* |
---|
719 | * Sync the PHYs by setting data bit and strobing the clock 32 times. |
---|
720 | */ |
---|
721 | static void dc_mii_sync(sc) |
---|
722 | struct dc_softc *sc; |
---|
723 | { |
---|
724 | register int i; |
---|
725 | |
---|
726 | CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); |
---|
727 | |
---|
728 | for (i = 0; i < 32; i++) |
---|
729 | dc_mii_writebit(sc, 1); |
---|
730 | |
---|
731 | return; |
---|
732 | } |
---|
733 | |
---|
734 | /* |
---|
735 | * Clock a series of bits through the MII. |
---|
736 | */ |
---|
737 | static void dc_mii_send(sc, bits, cnt) |
---|
738 | struct dc_softc *sc; |
---|
739 | u_int32_t bits; |
---|
740 | int cnt; |
---|
741 | { |
---|
742 | int i; |
---|
743 | |
---|
744 | for (i = (0x1 << (cnt - 1)); i; i >>= 1) |
---|
745 | dc_mii_writebit(sc, bits & i); |
---|
746 | } |
---|
747 | |
---|
748 | /* |
---|
749 | * Read an PHY register through the MII. |
---|
750 | */ |
---|
751 | static int dc_mii_readreg(sc, frame) |
---|
752 | struct dc_softc *sc; |
---|
753 | struct dc_mii_frame *frame; |
---|
754 | |
---|
755 | { |
---|
756 | int i, ack, s; |
---|
757 | |
---|
758 | |
---|
759 | /* |
---|
760 | * Set up frame for RX. |
---|
761 | */ |
---|
762 | frame->mii_stdelim = DC_MII_STARTDELIM; |
---|
763 | frame->mii_opcode = DC_MII_READOP; |
---|
764 | frame->mii_turnaround = 0; |
---|
765 | frame->mii_data = 0; |
---|
766 | |
---|
767 | /* |
---|
768 | * Sync the PHYs. |
---|
769 | */ |
---|
770 | dc_mii_sync(sc); |
---|
771 | |
---|
772 | /* |
---|
773 | * Send command/address info. |
---|
774 | */ |
---|
775 | dc_mii_send(sc, frame->mii_stdelim, 2); |
---|
776 | dc_mii_send(sc, frame->mii_opcode, 2); |
---|
777 | dc_mii_send(sc, frame->mii_phyaddr, 5); |
---|
778 | dc_mii_send(sc, frame->mii_regaddr, 5); |
---|
779 | |
---|
780 | #ifdef notdef |
---|
781 | /* Idle bit */ |
---|
782 | dc_mii_writebit(sc, 1); |
---|
783 | dc_mii_writebit(sc, 0); |
---|
784 | #endif |
---|
785 | |
---|
786 | /* Check for ack */ |
---|
787 | ack = dc_mii_readbit(sc); |
---|
788 | |
---|
789 | /* |
---|
790 | * Now try reading data bits. If the ack failed, we still |
---|
791 | * need to clock through 16 cycles to keep the PHY(s) in sync. |
---|
792 | */ |
---|
793 | if (ack) { |
---|
794 | for(i = 0; i < 16; i++) { |
---|
795 | dc_mii_readbit(sc); |
---|
796 | } |
---|
797 | goto fail; |
---|
798 | } |
---|
799 | |
---|
800 | for (i = 0x8000; i; i >>= 1) { |
---|
801 | if (!ack) { |
---|
802 | if (dc_mii_readbit(sc)) |
---|
803 | frame->mii_data |= i; |
---|
804 | } |
---|
805 | } |
---|
806 | |
---|
807 | fail: |
---|
808 | |
---|
809 | dc_mii_writebit(sc, 0); |
---|
810 | dc_mii_writebit(sc, 0); |
---|
811 | |
---|
812 | |
---|
813 | if (ack) |
---|
814 | return(1); |
---|
815 | return(0); |
---|
816 | } |
---|
817 | |
---|
818 | /* |
---|
819 | * Write to a PHY register through the MII. |
---|
820 | */ |
---|
821 | static int dc_mii_writereg(sc, frame) |
---|
822 | struct dc_softc *sc; |
---|
823 | struct dc_mii_frame *frame; |
---|
824 | |
---|
825 | { |
---|
826 | int s; |
---|
827 | |
---|
828 | /* |
---|
829 | * Set up frame for TX. |
---|
830 | */ |
---|
831 | |
---|
832 | frame->mii_stdelim = DC_MII_STARTDELIM; |
---|
833 | frame->mii_opcode = DC_MII_WRITEOP; |
---|
834 | frame->mii_turnaround = DC_MII_TURNAROUND; |
---|
835 | |
---|
836 | /* |
---|
837 | * Sync the PHYs. |
---|
838 | */ |
---|
839 | dc_mii_sync(sc); |
---|
840 | |
---|
841 | dc_mii_send(sc, frame->mii_stdelim, 2); |
---|
842 | dc_mii_send(sc, frame->mii_opcode, 2); |
---|
843 | dc_mii_send(sc, frame->mii_phyaddr, 5); |
---|
844 | dc_mii_send(sc, frame->mii_regaddr, 5); |
---|
845 | dc_mii_send(sc, frame->mii_turnaround, 2); |
---|
846 | dc_mii_send(sc, frame->mii_data, 16); |
---|
847 | |
---|
848 | /* Idle bit. */ |
---|
849 | dc_mii_writebit(sc, 0); |
---|
850 | dc_mii_writebit(sc, 0); |
---|
851 | |
---|
852 | |
---|
853 | return(0); |
---|
854 | } |
---|
855 | |
---|
856 | static int dc_miibus_readreg(dev, phy, reg) |
---|
857 | device_t dev; |
---|
858 | int phy, reg; |
---|
859 | { |
---|
860 | struct dc_mii_frame frame; |
---|
861 | struct dc_softc *sc; |
---|
862 | int i, rval, phy_reg = 0; |
---|
863 | |
---|
864 | sc = device_get_softc(dev); |
---|
865 | bzero((char *)&frame, sizeof(frame)); |
---|
866 | |
---|
867 | /* |
---|
868 | * Note: both the AL981 and AN985 have internal PHYs, |
---|
869 | * however the AL981 provides direct access to the PHY |
---|
870 | * registers while the AN985 uses a serial MII interface. |
---|
871 | * The AN985's MII interface is also buggy in that you |
---|
872 | * can read from any MII address (0 to 31), but only address 1 |
---|
873 | * behaves normally. To deal with both cases, we pretend |
---|
874 | * that the PHY is at MII address 1. |
---|
875 | */ |
---|
876 | if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) |
---|
877 | return(0); |
---|
878 | |
---|
879 | /* |
---|
880 | * Note: the ukphy probes of the RS7112 report a PHY at |
---|
881 | * MII address 0 (possibly HomePNA?) and 1 (ethernet) |
---|
882 | * so we only respond to correct one. |
---|
883 | */ |
---|
884 | if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) |
---|
885 | return(0); |
---|
886 | |
---|
887 | if (sc->dc_pmode != DC_PMODE_MII) { |
---|
888 | if (phy == (MII_NPHY - 1)) { |
---|
889 | switch(reg) { |
---|
890 | case MII_BMSR: |
---|
891 | /* |
---|
892 | * Fake something to make the probe |
---|
893 | * code think there's a PHY here. |
---|
894 | */ |
---|
895 | return(BMSR_MEDIAMASK); |
---|
896 | break; |
---|
897 | case MII_PHYIDR1: |
---|
898 | if (DC_IS_PNIC(sc)) |
---|
899 | return(DC_VENDORID_LO); |
---|
900 | return(DC_VENDORID_DEC); |
---|
901 | break; |
---|
902 | case MII_PHYIDR2: |
---|
903 | if (DC_IS_PNIC(sc)) |
---|
904 | return(DC_DEVICEID_82C168); |
---|
905 | return(DC_DEVICEID_21143); |
---|
906 | break; |
---|
907 | default: |
---|
908 | return(0); |
---|
909 | break; |
---|
910 | } |
---|
911 | } else |
---|
912 | return(0); |
---|
913 | } |
---|
914 | |
---|
915 | if (DC_IS_PNIC(sc)) { |
---|
916 | CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | |
---|
917 | (phy << 23) | (reg << 18)); |
---|
918 | for (i = 0; i < DC_TIMEOUT; i++) { |
---|
919 | DELAY(1); |
---|
920 | rval = CSR_READ_4(sc, DC_PN_MII); |
---|
921 | if (!(rval & DC_PN_MII_BUSY)) { |
---|
922 | rval &= 0xFFFF; |
---|
923 | return(rval == 0xFFFF ? 0 : rval); |
---|
924 | } |
---|
925 | } |
---|
926 | return(0); |
---|
927 | } |
---|
928 | |
---|
929 | if (DC_IS_COMET(sc)) { |
---|
930 | switch(reg) { |
---|
931 | case MII_BMCR: |
---|
932 | phy_reg = DC_AL_BMCR; |
---|
933 | break; |
---|
934 | case MII_BMSR: |
---|
935 | phy_reg = DC_AL_BMSR; |
---|
936 | break; |
---|
937 | case MII_PHYIDR1: |
---|
938 | phy_reg = DC_AL_VENID; |
---|
939 | break; |
---|
940 | case MII_PHYIDR2: |
---|
941 | phy_reg = DC_AL_DEVID; |
---|
942 | break; |
---|
943 | case MII_ANAR: |
---|
944 | phy_reg = DC_AL_ANAR; |
---|
945 | break; |
---|
946 | case MII_ANLPAR: |
---|
947 | phy_reg = DC_AL_LPAR; |
---|
948 | break; |
---|
949 | case MII_ANER: |
---|
950 | phy_reg = DC_AL_ANER; |
---|
951 | break; |
---|
952 | default: |
---|
953 | printk("dc%d: phy_read: bad phy register %x\n", |
---|
954 | sc->dc_unit, reg); |
---|
955 | return(0); |
---|
956 | break; |
---|
957 | } |
---|
958 | |
---|
959 | rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; |
---|
960 | |
---|
961 | if (rval == 0xFFFF) |
---|
962 | return(0); |
---|
963 | return(rval); |
---|
964 | } |
---|
965 | |
---|
966 | frame.mii_phyaddr = phy; |
---|
967 | frame.mii_regaddr = reg; |
---|
968 | if (sc->dc_type == DC_TYPE_98713) { |
---|
969 | phy_reg = CSR_READ_4(sc, DC_NETCFG); |
---|
970 | CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); |
---|
971 | } |
---|
972 | dc_mii_readreg(sc, &frame); |
---|
973 | if (sc->dc_type == DC_TYPE_98713) |
---|
974 | CSR_WRITE_4(sc, DC_NETCFG, phy_reg); |
---|
975 | |
---|
976 | return(frame.mii_data); |
---|
977 | } |
---|
978 | |
---|
979 | static int dc_miibus_writereg(dev, phy, reg, data) |
---|
980 | device_t dev; |
---|
981 | int phy, reg, data; |
---|
982 | { |
---|
983 | struct dc_softc *sc; |
---|
984 | struct dc_mii_frame frame; |
---|
985 | int i, phy_reg = 0; |
---|
986 | |
---|
987 | sc = device_get_softc(dev); |
---|
988 | bzero((char *)&frame, sizeof(frame)); |
---|
989 | |
---|
990 | if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) |
---|
991 | return(0); |
---|
992 | |
---|
993 | if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) |
---|
994 | return(0); |
---|
995 | |
---|
996 | if (DC_IS_PNIC(sc)) { |
---|
997 | CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | |
---|
998 | (phy << 23) | (reg << 10) | data); |
---|
999 | for (i = 0; i < DC_TIMEOUT; i++) { |
---|
1000 | if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) |
---|
1001 | break; |
---|
1002 | } |
---|
1003 | return(0); |
---|
1004 | } |
---|
1005 | |
---|
1006 | if (DC_IS_COMET(sc)) { |
---|
1007 | switch(reg) { |
---|
1008 | case MII_BMCR: |
---|
1009 | phy_reg = DC_AL_BMCR; |
---|
1010 | break; |
---|
1011 | case MII_BMSR: |
---|
1012 | phy_reg = DC_AL_BMSR; |
---|
1013 | break; |
---|
1014 | case MII_PHYIDR1: |
---|
1015 | phy_reg = DC_AL_VENID; |
---|
1016 | break; |
---|
1017 | case MII_PHYIDR2: |
---|
1018 | phy_reg = DC_AL_DEVID; |
---|
1019 | break; |
---|
1020 | case MII_ANAR: |
---|
1021 | phy_reg = DC_AL_ANAR; |
---|
1022 | break; |
---|
1023 | case MII_ANLPAR: |
---|
1024 | phy_reg = DC_AL_LPAR; |
---|
1025 | break; |
---|
1026 | case MII_ANER: |
---|
1027 | phy_reg = DC_AL_ANER; |
---|
1028 | break; |
---|
1029 | default: |
---|
1030 | printk("dc%d: phy_write: bad phy register %x\n", |
---|
1031 | sc->dc_unit, reg); |
---|
1032 | return(0); |
---|
1033 | break; |
---|
1034 | } |
---|
1035 | |
---|
1036 | CSR_WRITE_4(sc, phy_reg, data); |
---|
1037 | return(0); |
---|
1038 | } |
---|
1039 | |
---|
1040 | frame.mii_phyaddr = phy; |
---|
1041 | frame.mii_regaddr = reg; |
---|
1042 | frame.mii_data = data; |
---|
1043 | |
---|
1044 | if (sc->dc_type == DC_TYPE_98713) { |
---|
1045 | phy_reg = CSR_READ_4(sc, DC_NETCFG); |
---|
1046 | CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); |
---|
1047 | } |
---|
1048 | dc_mii_writereg(sc, &frame); |
---|
1049 | if (sc->dc_type == DC_TYPE_98713) |
---|
1050 | CSR_WRITE_4(sc, DC_NETCFG, phy_reg); |
---|
1051 | |
---|
1052 | return(0); |
---|
1053 | } |
---|
1054 | |
---|
1055 | static void dc_miibus_statchg(dev) |
---|
1056 | device_t dev; |
---|
1057 | { |
---|
1058 | struct dc_softc *sc; |
---|
1059 | struct mii_data *mii; |
---|
1060 | struct ifmedia *ifm; |
---|
1061 | |
---|
1062 | sc = device_get_softc(dev); |
---|
1063 | if (DC_IS_ADMTEK(sc)) |
---|
1064 | return; |
---|
1065 | |
---|
1066 | mii = device_get_softc(sc->dc_miibus); |
---|
1067 | ifm = &mii->mii_media; |
---|
1068 | if (DC_IS_DAVICOM(sc) && |
---|
1069 | IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { |
---|
1070 | dc_setcfg(sc, ifm->ifm_media); |
---|
1071 | sc->dc_if_media = ifm->ifm_media; |
---|
1072 | } else { |
---|
1073 | dc_setcfg(sc, mii->mii_media_active); |
---|
1074 | sc->dc_if_media = mii->mii_media_active; |
---|
1075 | } |
---|
1076 | |
---|
1077 | return; |
---|
1078 | } |
---|
1079 | |
---|
1080 | /* |
---|
1081 | * Special support for DM9102A cards with HomePNA PHYs. Note: |
---|
1082 | * with the Davicom DM9102A/DM9801 eval board that I have, it seems |
---|
1083 | * to be impossible to talk to the management interface of the DM9801 |
---|
1084 | * PHY (its MDIO pin is not connected to anything). Consequently, |
---|
1085 | * the driver has to just 'know' about the additional mode and deal |
---|
1086 | * with it itself. *sigh* |
---|
1087 | */ |
---|
1088 | static void dc_miibus_mediainit(dev) |
---|
1089 | device_t dev; |
---|
1090 | { |
---|
1091 | struct dc_softc *sc; |
---|
1092 | struct mii_data *mii; |
---|
1093 | struct ifmedia *ifm; |
---|
1094 | int rev; |
---|
1095 | |
---|
1096 | rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; |
---|
1097 | |
---|
1098 | sc = device_get_softc(dev); |
---|
1099 | mii = device_get_softc(sc->dc_miibus); |
---|
1100 | ifm = &mii->mii_media; |
---|
1101 | |
---|
1102 | if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) |
---|
1103 | ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL); |
---|
1104 | |
---|
1105 | return; |
---|
1106 | } |
---|
1107 | #endif |
---|
1108 | |
---|
1109 | #define DC_POLY 0xEDB88320 |
---|
1110 | #define DC_BITS_512 9 |
---|
1111 | #define DC_BITS_128 7 |
---|
1112 | #define DC_BITS_64 6 |
---|
1113 | |
---|
1114 | static u_int32_t dc_crc_le(sc, addr) |
---|
1115 | struct dc_softc *sc; |
---|
1116 | caddr_t addr; |
---|
1117 | { |
---|
1118 | u_int32_t idx, bit, data, crc; |
---|
1119 | |
---|
1120 | /* Compute CRC for the address value. */ |
---|
1121 | crc = 0xFFFFFFFF; /* initial value */ |
---|
1122 | |
---|
1123 | for (idx = 0; idx < 6; idx++) { |
---|
1124 | for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) |
---|
1125 | crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); |
---|
1126 | } |
---|
1127 | |
---|
1128 | /* |
---|
1129 | * The hash table on the PNIC II and the MX98715AEC-C/D/E |
---|
1130 | * chips is only 128 bits wide. |
---|
1131 | */ |
---|
1132 | if (sc->dc_flags & DC_128BIT_HASH) |
---|
1133 | return (crc & ((1 << DC_BITS_128) - 1)); |
---|
1134 | |
---|
1135 | /* The hash table on the MX98715BEC is only 64 bits wide. */ |
---|
1136 | if (sc->dc_flags & DC_64BIT_HASH) |
---|
1137 | return (crc & ((1 << DC_BITS_64) - 1)); |
---|
1138 | |
---|
1139 | return (crc & ((1 << DC_BITS_512) - 1)); |
---|
1140 | } |
---|
1141 | |
---|
1142 | #ifndef UNUSED |
---|
1143 | /* |
---|
1144 | * Calculate CRC of a multicast group address, return the lower 6 bits. |
---|
1145 | */ |
---|
1146 | static u_int32_t dc_crc_be(addr) |
---|
1147 | caddr_t addr; |
---|
1148 | { |
---|
1149 | u_int32_t crc, carry; |
---|
1150 | int i, j; |
---|
1151 | u_int8_t c; |
---|
1152 | |
---|
1153 | /* Compute CRC for the address value. */ |
---|
1154 | crc = 0xFFFFFFFF; /* initial value */ |
---|
1155 | |
---|
1156 | for (i = 0; i < 6; i++) { |
---|
1157 | c = *(addr + i); |
---|
1158 | for (j = 0; j < 8; j++) { |
---|
1159 | carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); |
---|
1160 | crc <<= 1; |
---|
1161 | c >>= 1; |
---|
1162 | if (carry) |
---|
1163 | crc = (crc ^ 0x04c11db6) | carry; |
---|
1164 | } |
---|
1165 | } |
---|
1166 | |
---|
1167 | /* return the filter bit position */ |
---|
1168 | return((crc >> 26) & 0x0000003F); |
---|
1169 | } |
---|
1170 | #endif |
---|
1171 | |
---|
1172 | /* |
---|
1173 | * 21143-style RX filter setup routine. Filter programming is done by |
---|
1174 | * downloading a special setup frame into the TX engine. 21143, Macronix, |
---|
1175 | * PNIC, PNIC II and Davicom chips are programmed this way. |
---|
1176 | * |
---|
1177 | * We always program the chip using 'hash perfect' mode, i.e. one perfect |
---|
1178 | * address (our node address) and a 512-bit hash filter for multicast |
---|
1179 | * frames. We also sneak the broadcast address into the hash filter since |
---|
1180 | * we need that too. |
---|
1181 | */ |
---|
1182 | void dc_setfilt_21143(sc) |
---|
1183 | struct dc_softc *sc; |
---|
1184 | { |
---|
1185 | struct dc_desc *sframe; |
---|
1186 | u_int32_t h, *sp; |
---|
1187 | /*struct ifmultiaddr *ifma;*/ |
---|
1188 | struct ifnet *ifp; |
---|
1189 | int i; |
---|
1190 | u_int16_t *ac_enaddr; |
---|
1191 | |
---|
1192 | ifp = &sc->arpcom.ac_if; |
---|
1193 | |
---|
1194 | i = sc->dc_cdata.dc_tx_prod; |
---|
1195 | DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); |
---|
1196 | sc->dc_cdata.dc_tx_cnt++; |
---|
1197 | sframe = &sc->dc_ldata->dc_tx_list[i]; |
---|
1198 | sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; |
---|
1199 | bzero((char *)sp, DC_SFRAME_LEN); |
---|
1200 | |
---|
1201 | sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); |
---|
1202 | sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | |
---|
1203 | DC_FILTER_HASHPERF | DC_TXCTL_FINT; |
---|
1204 | |
---|
1205 | sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; |
---|
1206 | |
---|
1207 | /* If we want promiscuous mode, set the allframes bit. */ |
---|
1208 | if (ifp->if_flags & IFF_PROMISC) |
---|
1209 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); |
---|
1210 | else |
---|
1211 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); |
---|
1212 | |
---|
1213 | if (ifp->if_flags & IFF_ALLMULTI) |
---|
1214 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); |
---|
1215 | else |
---|
1216 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); |
---|
1217 | #if 0 |
---|
1218 | for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; |
---|
1219 | ifma = ifma->ifma_link.le_next) { |
---|
1220 | if (ifma->ifma_addr->sa_family != AF_LINK) |
---|
1221 | continue; |
---|
1222 | h = dc_crc_le(sc, |
---|
1223 | LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); |
---|
1224 | sp[h >> 4] |= 1 << (h & 0xF); |
---|
1225 | } |
---|
1226 | #endif |
---|
1227 | |
---|
1228 | if (ifp->if_flags & IFF_BROADCAST) { |
---|
1229 | h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); |
---|
1230 | sp[h >> 4] |= 1 << (h & 0xF); |
---|
1231 | } |
---|
1232 | |
---|
1233 | /* Set our MAC address */ |
---|
1234 | ac_enaddr = (u_int16_t *)sc->arpcom.ac_enaddr; |
---|
1235 | sp[39] = ac_enaddr[0]; |
---|
1236 | sp[40] = ac_enaddr[1]; |
---|
1237 | sp[41] = ac_enaddr[2]; |
---|
1238 | |
---|
1239 | sframe->dc_status = DC_TXSTAT_OWN; |
---|
1240 | CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); |
---|
1241 | |
---|
1242 | /* |
---|
1243 | * The PNIC takes an exceedingly long time to process its |
---|
1244 | * setup frame; wait 10ms after posting the setup frame |
---|
1245 | * before proceeding, just so it has time to swallow its |
---|
1246 | * medicine. |
---|
1247 | */ |
---|
1248 | DELAY(10000); |
---|
1249 | |
---|
1250 | ifp->if_timer = 5; |
---|
1251 | |
---|
1252 | return; |
---|
1253 | } |
---|
1254 | |
---|
1255 | void dc_setfilt_admtek(sc) |
---|
1256 | struct dc_softc *sc; |
---|
1257 | { |
---|
1258 | struct ifnet *ifp; |
---|
1259 | #if 0 |
---|
1260 | int h = 0; |
---|
1261 | u_int32_t hashes[2] = { 0, 0 }; |
---|
1262 | struct ifmultiaddr *ifma; |
---|
1263 | #endif |
---|
1264 | u_int32_t *ac_enaddr; |
---|
1265 | |
---|
1266 | ifp = &sc->arpcom.ac_if; |
---|
1267 | |
---|
1268 | /* Init our MAC address */ |
---|
1269 | ac_enaddr = (u_int32_t *)&sc->arpcom.ac_enaddr[0]; |
---|
1270 | CSR_WRITE_4(sc, DC_AL_PAR0, *ac_enaddr); |
---|
1271 | ac_enaddr = (u_int32_t *)&sc->arpcom.ac_enaddr[4]; |
---|
1272 | CSR_WRITE_4(sc, DC_AL_PAR1, *ac_enaddr); |
---|
1273 | |
---|
1274 | /* If we want promiscuous mode, set the allframes bit. */ |
---|
1275 | if (ifp->if_flags & IFF_PROMISC) |
---|
1276 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); |
---|
1277 | else |
---|
1278 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); |
---|
1279 | |
---|
1280 | if (ifp->if_flags & IFF_ALLMULTI) |
---|
1281 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); |
---|
1282 | else |
---|
1283 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); |
---|
1284 | |
---|
1285 | /* first, zot all the existing hash bits */ |
---|
1286 | CSR_WRITE_4(sc, DC_AL_MAR0, 0); |
---|
1287 | CSR_WRITE_4(sc, DC_AL_MAR1, 0); |
---|
1288 | |
---|
1289 | #if 0 |
---|
1290 | /* |
---|
1291 | * If we're already in promisc or allmulti mode, we |
---|
1292 | * don't have to bother programming the multicast filter. |
---|
1293 | */ |
---|
1294 | if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) |
---|
1295 | return; |
---|
1296 | |
---|
1297 | /* now program new ones */ |
---|
1298 | for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; |
---|
1299 | ifma = ifma->ifma_link.le_next) { |
---|
1300 | if (ifma->ifma_addr->sa_family != AF_LINK) |
---|
1301 | continue; |
---|
1302 | h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); |
---|
1303 | if (h < 32) |
---|
1304 | hashes[0] |= (1 << h); |
---|
1305 | else |
---|
1306 | hashes[1] |= (1 << (h - 32)); |
---|
1307 | } |
---|
1308 | |
---|
1309 | CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); |
---|
1310 | CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); |
---|
1311 | #endif |
---|
1312 | return; |
---|
1313 | } |
---|
1314 | |
---|
1315 | void dc_setfilt_asix(sc) |
---|
1316 | struct dc_softc *sc; |
---|
1317 | { |
---|
1318 | struct ifnet *ifp; |
---|
1319 | #if 0 |
---|
1320 | int h = 0; |
---|
1321 | u_int32_t hashes[2] = { 0, 0 }; |
---|
1322 | struct ifmultiaddr *ifma; |
---|
1323 | #endif |
---|
1324 | u_int32_t *ac_enaddr; |
---|
1325 | |
---|
1326 | ifp = &sc->arpcom.ac_if; |
---|
1327 | |
---|
1328 | /* Init our MAC address */ |
---|
1329 | CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); |
---|
1330 | ac_enaddr = (u_int32_t *)&sc->arpcom.ac_enaddr[0]; |
---|
1331 | CSR_WRITE_4(sc, DC_AX_FILTDATA, *ac_enaddr); |
---|
1332 | |
---|
1333 | CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); |
---|
1334 | |
---|
1335 | ac_enaddr = (u_int32_t *)&sc->arpcom.ac_enaddr[4]; |
---|
1336 | CSR_WRITE_4(sc, DC_AX_FILTDATA, *ac_enaddr); |
---|
1337 | |
---|
1338 | /* If we want promiscuous mode, set the allframes bit. */ |
---|
1339 | if (ifp->if_flags & IFF_PROMISC) |
---|
1340 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); |
---|
1341 | else |
---|
1342 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); |
---|
1343 | |
---|
1344 | if (ifp->if_flags & IFF_ALLMULTI) |
---|
1345 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); |
---|
1346 | else |
---|
1347 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); |
---|
1348 | |
---|
1349 | /* |
---|
1350 | * The ASIX chip has a special bit to enable reception |
---|
1351 | * of broadcast frames. |
---|
1352 | */ |
---|
1353 | if (ifp->if_flags & IFF_BROADCAST) |
---|
1354 | DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); |
---|
1355 | else |
---|
1356 | DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); |
---|
1357 | |
---|
1358 | /* first, zot all the existing hash bits */ |
---|
1359 | CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); |
---|
1360 | CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); |
---|
1361 | CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); |
---|
1362 | CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); |
---|
1363 | |
---|
1364 | #if 0 |
---|
1365 | /* |
---|
1366 | * If we're already in promisc or allmulti mode, we |
---|
1367 | * don't have to bother programming the multicast filter. |
---|
1368 | */ |
---|
1369 | if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) |
---|
1370 | return; |
---|
1371 | |
---|
1372 | /* now program new ones */ |
---|
1373 | for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; |
---|
1374 | ifma = ifma->ifma_link.le_next) { |
---|
1375 | if (ifma->ifma_addr->sa_family != AF_LINK) |
---|
1376 | continue; |
---|
1377 | h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); |
---|
1378 | if (h < 32) |
---|
1379 | hashes[0] |= (1 << h); |
---|
1380 | else |
---|
1381 | hashes[1] |= (1 << (h - 32)); |
---|
1382 | } |
---|
1383 | |
---|
1384 | CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); |
---|
1385 | CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); |
---|
1386 | CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); |
---|
1387 | CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); |
---|
1388 | #endif |
---|
1389 | return; |
---|
1390 | } |
---|
1391 | |
---|
1392 | static void dc_setfilt(sc) |
---|
1393 | struct dc_softc *sc; |
---|
1394 | { |
---|
1395 | if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || |
---|
1396 | DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) |
---|
1397 | dc_setfilt_21143(sc); |
---|
1398 | |
---|
1399 | if (DC_IS_ASIX(sc)) |
---|
1400 | dc_setfilt_asix(sc); |
---|
1401 | |
---|
1402 | if (DC_IS_ADMTEK(sc)) |
---|
1403 | dc_setfilt_admtek(sc); |
---|
1404 | |
---|
1405 | return; |
---|
1406 | } |
---|
1407 | |
---|
1408 | /* |
---|
1409 | * In order to fiddle with the |
---|
1410 | * 'full-duplex' and '100Mbps' bits in the netconfig register, we |
---|
1411 | * first have to put the transmit and/or receive logic in the idle state. |
---|
1412 | */ |
---|
1413 | static void dc_setcfg(sc, media) |
---|
1414 | struct dc_softc *sc; |
---|
1415 | int media; |
---|
1416 | { |
---|
1417 | int i, restart = 0; |
---|
1418 | u_int32_t isr; |
---|
1419 | |
---|
1420 | if (IFM_SUBTYPE(media) == IFM_NONE) |
---|
1421 | return; |
---|
1422 | |
---|
1423 | if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { |
---|
1424 | restart = 1; |
---|
1425 | DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); |
---|
1426 | |
---|
1427 | for (i = 0; i < DC_TIMEOUT; i++) { |
---|
1428 | isr = CSR_READ_4(sc, DC_ISR); |
---|
1429 | if (isr & DC_ISR_TX_IDLE || |
---|
1430 | (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) |
---|
1431 | break; |
---|
1432 | DELAY(10); |
---|
1433 | } |
---|
1434 | |
---|
1435 | if (i == DC_TIMEOUT) |
---|
1436 | printk("dc%d: failed to force tx and " |
---|
1437 | "rx to idle state\n", sc->dc_unit); |
---|
1438 | } |
---|
1439 | |
---|
1440 | if (IFM_SUBTYPE(media) == IFM_100_TX) { |
---|
1441 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); |
---|
1442 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); |
---|
1443 | if (sc->dc_pmode == DC_PMODE_MII) { |
---|
1444 | int watchdogreg; |
---|
1445 | |
---|
1446 | if (DC_IS_INTEL(sc)) { |
---|
1447 | /* there's a write enable bit here that reads as 1 */ |
---|
1448 | watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); |
---|
1449 | watchdogreg &= ~DC_WDOG_CTLWREN; |
---|
1450 | watchdogreg |= DC_WDOG_JABBERDIS; |
---|
1451 | CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); |
---|
1452 | } else { |
---|
1453 | DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); |
---|
1454 | } |
---|
1455 | DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| |
---|
1456 | DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); |
---|
1457 | if (sc->dc_type == DC_TYPE_98713) |
---|
1458 | DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| |
---|
1459 | DC_NETCFG_SCRAMBLER)); |
---|
1460 | if (!DC_IS_DAVICOM(sc)) |
---|
1461 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); |
---|
1462 | DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); |
---|
1463 | if (DC_IS_INTEL(sc)) |
---|
1464 | dc_apply_fixup(sc, IFM_AUTO); |
---|
1465 | } else { |
---|
1466 | if (DC_IS_PNIC(sc)) { |
---|
1467 | DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); |
---|
1468 | DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); |
---|
1469 | DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); |
---|
1470 | } |
---|
1471 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); |
---|
1472 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); |
---|
1473 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); |
---|
1474 | if (DC_IS_INTEL(sc)) |
---|
1475 | dc_apply_fixup(sc, |
---|
1476 | (media & IFM_GMASK) == IFM_FDX ? |
---|
1477 | IFM_100_TX|IFM_FDX : IFM_100_TX); |
---|
1478 | } |
---|
1479 | } |
---|
1480 | |
---|
1481 | if (IFM_SUBTYPE(media) == IFM_10_T) { |
---|
1482 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); |
---|
1483 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); |
---|
1484 | if (sc->dc_pmode == DC_PMODE_MII) { |
---|
1485 | int watchdogreg; |
---|
1486 | |
---|
1487 | /* there's a write enable bit here that reads as 1 */ |
---|
1488 | if (DC_IS_INTEL(sc)) { |
---|
1489 | watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); |
---|
1490 | watchdogreg &= ~DC_WDOG_CTLWREN; |
---|
1491 | watchdogreg |= DC_WDOG_JABBERDIS; |
---|
1492 | CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); |
---|
1493 | } else { |
---|
1494 | DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); |
---|
1495 | } |
---|
1496 | DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| |
---|
1497 | DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); |
---|
1498 | if (sc->dc_type == DC_TYPE_98713) |
---|
1499 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); |
---|
1500 | if (!DC_IS_DAVICOM(sc)) |
---|
1501 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); |
---|
1502 | DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); |
---|
1503 | if (DC_IS_INTEL(sc)) |
---|
1504 | dc_apply_fixup(sc, IFM_AUTO); |
---|
1505 | } else { |
---|
1506 | if (DC_IS_PNIC(sc)) { |
---|
1507 | DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); |
---|
1508 | DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); |
---|
1509 | DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); |
---|
1510 | } |
---|
1511 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); |
---|
1512 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); |
---|
1513 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); |
---|
1514 | if (DC_IS_INTEL(sc)) { |
---|
1515 | DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); |
---|
1516 | DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); |
---|
1517 | if ((media & IFM_GMASK) == IFM_FDX) |
---|
1518 | DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); |
---|
1519 | else |
---|
1520 | DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); |
---|
1521 | DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); |
---|
1522 | DC_CLRBIT(sc, DC_10BTCTRL, |
---|
1523 | DC_TCTL_AUTONEGENBL); |
---|
1524 | dc_apply_fixup(sc, |
---|
1525 | (media & IFM_GMASK) == IFM_FDX ? |
---|
1526 | IFM_10_T|IFM_FDX : IFM_10_T); |
---|
1527 | DELAY(20000); |
---|
1528 | } |
---|
1529 | } |
---|
1530 | } |
---|
1531 | |
---|
1532 | #if 0 |
---|
1533 | /* |
---|
1534 | * If this is a Davicom DM9102A card with a DM9801 HomePNA |
---|
1535 | * PHY and we want HomePNA mode, set the portsel bit to turn |
---|
1536 | * on the external MII port. |
---|
1537 | */ |
---|
1538 | if (DC_IS_DAVICOM(sc)) { |
---|
1539 | if (IFM_SUBTYPE(media) == IFM_homePNA) { |
---|
1540 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); |
---|
1541 | sc->dc_link = 1; |
---|
1542 | } else { |
---|
1543 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); |
---|
1544 | } |
---|
1545 | } |
---|
1546 | #endif |
---|
1547 | |
---|
1548 | if ((media & IFM_GMASK) == IFM_FDX) { |
---|
1549 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); |
---|
1550 | if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) |
---|
1551 | DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); |
---|
1552 | } else { |
---|
1553 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); |
---|
1554 | if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) |
---|
1555 | DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); |
---|
1556 | } |
---|
1557 | |
---|
1558 | if (restart) |
---|
1559 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); |
---|
1560 | |
---|
1561 | return; |
---|
1562 | } |
---|
1563 | |
---|
1564 | static void dc_reset(sc) |
---|
1565 | struct dc_softc *sc; |
---|
1566 | { |
---|
1567 | register int i; |
---|
1568 | |
---|
1569 | DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); |
---|
1570 | |
---|
1571 | for (i = 0; i < DC_TIMEOUT; i++) { |
---|
1572 | DELAY(10); |
---|
1573 | if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) |
---|
1574 | break; |
---|
1575 | } |
---|
1576 | |
---|
1577 | if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc)) { |
---|
1578 | DELAY(10000); |
---|
1579 | DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); |
---|
1580 | i = 0; |
---|
1581 | } |
---|
1582 | |
---|
1583 | if (i == DC_TIMEOUT) |
---|
1584 | printk("dc%d: reset never completed!\n", sc->dc_unit); |
---|
1585 | |
---|
1586 | /* Wait a little while for the chip to get its brains in order. */ |
---|
1587 | DELAY(1000); |
---|
1588 | |
---|
1589 | CSR_WRITE_4(sc, DC_IMR, 0x00000000); |
---|
1590 | CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); |
---|
1591 | CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); |
---|
1592 | |
---|
1593 | /* |
---|
1594 | * Bring the SIA out of reset. In some cases, it looks |
---|
1595 | * like failing to unreset the SIA soon enough gets it |
---|
1596 | * into a state where it will never come out of reset |
---|
1597 | * until we reset the whole chip again. |
---|
1598 | */ |
---|
1599 | if (DC_IS_INTEL(sc)) { |
---|
1600 | DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); |
---|
1601 | CSR_WRITE_4(sc, DC_10BTCTRL, 0); |
---|
1602 | CSR_WRITE_4(sc, DC_WATCHDOG, 0); |
---|
1603 | } |
---|
1604 | |
---|
1605 | return; |
---|
1606 | } |
---|
1607 | |
---|
1608 | static |
---|
1609 | struct dc_type *dc_devtype( int unitnum ) |
---|
1610 | { |
---|
1611 | struct dc_type *t; |
---|
1612 | uint32_t rev; |
---|
1613 | int rc; |
---|
1614 | |
---|
1615 | |
---|
1616 | t = dc_devs; |
---|
1617 | |
---|
1618 | while(t->dc_name != NULL) { |
---|
1619 | rc = pci_find_device(t->dc_vid, t->dc_did, \ |
---|
1620 | (unitnum - 1), &t->dc_bus, &t->dc_dev, &t->dc_fun); |
---|
1621 | if (rc == PCIB_ERR_SUCCESS) { |
---|
1622 | /* Check the PCI revision */ |
---|
1623 | /*pcib_conf_read32(t->dc_devsig, DC_PCI_CFRV, &rev); */ |
---|
1624 | pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\ |
---|
1625 | DC_PCI_CFRV, &rev); |
---|
1626 | rev &= 0xFF; |
---|
1627 | |
---|
1628 | if (t->dc_did == DC_DEVICEID_98713 && |
---|
1629 | rev >= DC_REVISION_98713A) |
---|
1630 | t++; |
---|
1631 | if (t->dc_did == DC_DEVICEID_98713_CP && |
---|
1632 | rev >= DC_REVISION_98713A) |
---|
1633 | t++; |
---|
1634 | if (t->dc_did == DC_DEVICEID_987x5 && |
---|
1635 | rev >= DC_REVISION_98715AEC_C) |
---|
1636 | t++; |
---|
1637 | if (t->dc_did == DC_DEVICEID_987x5 && |
---|
1638 | rev >= DC_REVISION_98725) |
---|
1639 | t++; |
---|
1640 | if (t->dc_did == DC_DEVICEID_AX88140A && |
---|
1641 | rev >= DC_REVISION_88141) |
---|
1642 | t++; |
---|
1643 | if (t->dc_did == DC_DEVICEID_82C168 && |
---|
1644 | rev >= DC_REVISION_82C169) |
---|
1645 | t++; |
---|
1646 | if (t->dc_did == DC_DEVICEID_DM9102 && |
---|
1647 | rev >= DC_REVISION_DM9102A) |
---|
1648 | t++; |
---|
1649 | return(t); |
---|
1650 | } |
---|
1651 | t++; |
---|
1652 | } |
---|
1653 | |
---|
1654 | return(NULL); |
---|
1655 | } |
---|
1656 | |
---|
1657 | #if 0 |
---|
1658 | /* |
---|
1659 | * Probe for a 21143 or clone chip. Check the PCI vendor and device |
---|
1660 | * IDs against our list and return a device name if we find a match. |
---|
1661 | * We do a little bit of extra work to identify the exact type of |
---|
1662 | * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, |
---|
1663 | * but different revision IDs. The same is true for 98715/98715A |
---|
1664 | * chips and the 98725, as well as the ASIX and ADMtek chips. In some |
---|
1665 | * cases, the exact chip revision affects driver behavior. |
---|
1666 | */ |
---|
1667 | static int dc_probe(dev) |
---|
1668 | device_t dev; |
---|
1669 | { |
---|
1670 | struct dc_type *t; |
---|
1671 | |
---|
1672 | t = dc_devtype(dev); |
---|
1673 | |
---|
1674 | if (t != NULL) { |
---|
1675 | device_set_desc(dev, t->dc_name); |
---|
1676 | return(0); |
---|
1677 | } |
---|
1678 | |
---|
1679 | return(ENXIO); |
---|
1680 | } |
---|
1681 | |
---|
1682 | |
---|
1683 | static void dc_acpi(dev) |
---|
1684 | device_t dev; |
---|
1685 | { |
---|
1686 | u_int32_t r, cptr; |
---|
1687 | int unit; |
---|
1688 | |
---|
1689 | unit = device_get_unit(dev); |
---|
1690 | |
---|
1691 | /* Find the location of the capabilities block */ |
---|
1692 | cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF; |
---|
1693 | |
---|
1694 | r = pci_read_config(dev, cptr, 4) & 0xFF; |
---|
1695 | if (r == 0x01) { |
---|
1696 | |
---|
1697 | r = pci_read_config(dev, cptr + 4, 4); |
---|
1698 | if (r & DC_PSTATE_D3) { |
---|
1699 | u_int32_t iobase, membase, irq; |
---|
1700 | |
---|
1701 | /* Save important PCI config data. */ |
---|
1702 | iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); |
---|
1703 | membase = pci_read_config(dev, DC_PCI_CFBMA, 4); |
---|
1704 | irq = pci_read_config(dev, DC_PCI_CFIT, 4); |
---|
1705 | |
---|
1706 | /* Reset the power state. */ |
---|
1707 | printk("dc%d: chip is in D%d power mode " |
---|
1708 | "-- setting to D0\n", unit, r & DC_PSTATE_D3); |
---|
1709 | r &= 0xFFFFFFFC; |
---|
1710 | pci_write_config(dev, cptr + 4, r, 4); |
---|
1711 | |
---|
1712 | /* Restore PCI config data. */ |
---|
1713 | pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); |
---|
1714 | pci_write_config(dev, DC_PCI_CFBMA, membase, 4); |
---|
1715 | pci_write_config(dev, DC_PCI_CFIT, irq, 4); |
---|
1716 | } |
---|
1717 | } |
---|
1718 | return; |
---|
1719 | } |
---|
1720 | #endif |
---|
1721 | |
---|
1722 | |
---|
1723 | static void dc_apply_fixup(sc, media) |
---|
1724 | struct dc_softc *sc; |
---|
1725 | int media; |
---|
1726 | { |
---|
1727 | struct dc_mediainfo *m; |
---|
1728 | u_int8_t *p; |
---|
1729 | int i; |
---|
1730 | u_int32_t reg; |
---|
1731 | |
---|
1732 | m = sc->dc_mi; |
---|
1733 | |
---|
1734 | while (m != NULL) { |
---|
1735 | if (m->dc_media == media) |
---|
1736 | break; |
---|
1737 | m = m->dc_next; |
---|
1738 | } |
---|
1739 | |
---|
1740 | if (m == NULL) |
---|
1741 | return; |
---|
1742 | |
---|
1743 | for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { |
---|
1744 | reg = (p[0] | (p[1] << 8)) << 16; |
---|
1745 | CSR_WRITE_4(sc, DC_WATCHDOG, reg); |
---|
1746 | } |
---|
1747 | |
---|
1748 | for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { |
---|
1749 | reg = (p[0] | (p[1] << 8)) << 16; |
---|
1750 | CSR_WRITE_4(sc, DC_WATCHDOG, reg); |
---|
1751 | } |
---|
1752 | |
---|
1753 | return; |
---|
1754 | } |
---|
1755 | |
---|
1756 | #if 0 |
---|
1757 | static void dc_decode_leaf_sia(sc, l) |
---|
1758 | struct dc_softc *sc; |
---|
1759 | struct dc_eblock_sia *l; |
---|
1760 | { |
---|
1761 | struct dc_mediainfo *m; |
---|
1762 | |
---|
1763 | m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); |
---|
1764 | bzero(m, sizeof(struct dc_mediainfo)); |
---|
1765 | if (l->dc_sia_code == DC_SIA_CODE_10BT) |
---|
1766 | m->dc_media = IFM_10_T; |
---|
1767 | |
---|
1768 | if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) |
---|
1769 | m->dc_media = IFM_10_T|IFM_FDX; |
---|
1770 | |
---|
1771 | if (l->dc_sia_code == DC_SIA_CODE_10B2) |
---|
1772 | m->dc_media = IFM_10_2; |
---|
1773 | |
---|
1774 | if (l->dc_sia_code == DC_SIA_CODE_10B5) |
---|
1775 | m->dc_media = IFM_10_5; |
---|
1776 | |
---|
1777 | m->dc_gp_len = 2; |
---|
1778 | m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; |
---|
1779 | |
---|
1780 | m->dc_next = sc->dc_mi; |
---|
1781 | sc->dc_mi = m; |
---|
1782 | |
---|
1783 | sc->dc_pmode = DC_PMODE_SIA; |
---|
1784 | |
---|
1785 | return; |
---|
1786 | } |
---|
1787 | |
---|
1788 | static void dc_decode_leaf_sym(sc, l) |
---|
1789 | struct dc_softc *sc; |
---|
1790 | struct dc_eblock_sym *l; |
---|
1791 | { |
---|
1792 | struct dc_mediainfo *m; |
---|
1793 | |
---|
1794 | m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); |
---|
1795 | bzero(m, sizeof(struct dc_mediainfo)); |
---|
1796 | if (l->dc_sym_code == DC_SYM_CODE_100BT) |
---|
1797 | m->dc_media = IFM_100_TX; |
---|
1798 | |
---|
1799 | if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) |
---|
1800 | m->dc_media = IFM_100_TX|IFM_FDX; |
---|
1801 | |
---|
1802 | m->dc_gp_len = 2; |
---|
1803 | m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; |
---|
1804 | |
---|
1805 | m->dc_next = sc->dc_mi; |
---|
1806 | sc->dc_mi = m; |
---|
1807 | |
---|
1808 | sc->dc_pmode = DC_PMODE_SYM; |
---|
1809 | |
---|
1810 | return; |
---|
1811 | } |
---|
1812 | |
---|
1813 | static void dc_decode_leaf_mii(sc, l) |
---|
1814 | struct dc_softc *sc; |
---|
1815 | struct dc_eblock_mii *l; |
---|
1816 | { |
---|
1817 | u_int8_t *p; |
---|
1818 | struct dc_mediainfo *m; |
---|
1819 | |
---|
1820 | m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); |
---|
1821 | bzero(m, sizeof(struct dc_mediainfo)); |
---|
1822 | /* We abuse IFM_AUTO to represent MII. */ |
---|
1823 | m->dc_media = IFM_AUTO; |
---|
1824 | m->dc_gp_len = l->dc_gpr_len; |
---|
1825 | |
---|
1826 | p = (u_int8_t *)l; |
---|
1827 | p += sizeof(struct dc_eblock_mii); |
---|
1828 | m->dc_gp_ptr = p; |
---|
1829 | p += 2 * l->dc_gpr_len; |
---|
1830 | m->dc_reset_len = *p; |
---|
1831 | p++; |
---|
1832 | m->dc_reset_ptr = p; |
---|
1833 | |
---|
1834 | m->dc_next = sc->dc_mi; |
---|
1835 | sc->dc_mi = m; |
---|
1836 | |
---|
1837 | return; |
---|
1838 | } |
---|
1839 | #endif |
---|
1840 | |
---|
1841 | static void dc_read_srom(sc, bits) |
---|
1842 | struct dc_softc *sc; |
---|
1843 | int bits; |
---|
1844 | { |
---|
1845 | int size; |
---|
1846 | |
---|
1847 | size = 2 << bits; |
---|
1848 | sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); |
---|
1849 | dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); |
---|
1850 | } |
---|
1851 | |
---|
1852 | static void dc_parse_21143_srom(sc) |
---|
1853 | struct dc_softc *sc; |
---|
1854 | { |
---|
1855 | struct dc_leaf_hdr *lhdr; |
---|
1856 | struct dc_eblock_hdr *hdr; |
---|
1857 | int i, loff; |
---|
1858 | char *ptr; |
---|
1859 | |
---|
1860 | loff = sc->dc_srom[27]; |
---|
1861 | lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); |
---|
1862 | |
---|
1863 | ptr = (char *)lhdr; |
---|
1864 | ptr += sizeof(struct dc_leaf_hdr) - 1; |
---|
1865 | for (i = 0; i < lhdr->dc_mcnt; i++) { |
---|
1866 | hdr = (struct dc_eblock_hdr *)ptr; |
---|
1867 | switch(hdr->dc_type) { |
---|
1868 | #if 0 |
---|
1869 | case DC_EBLOCK_MII: |
---|
1870 | dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); |
---|
1871 | break; |
---|
1872 | case DC_EBLOCK_SIA: |
---|
1873 | dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr); |
---|
1874 | break; |
---|
1875 | case DC_EBLOCK_SYM: |
---|
1876 | dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr); |
---|
1877 | break; |
---|
1878 | #endif |
---|
1879 | default: |
---|
1880 | /* Don't care. Yet. */ |
---|
1881 | break; |
---|
1882 | } |
---|
1883 | ptr += (hdr->dc_len & 0x7F); |
---|
1884 | ptr++; |
---|
1885 | } |
---|
1886 | |
---|
1887 | return; |
---|
1888 | } |
---|
1889 | |
---|
1890 | |
---|
1891 | static void |
---|
1892 | nop(const rtems_irq_connect_data* unused) |
---|
1893 | { |
---|
1894 | } |
---|
1895 | |
---|
1896 | static int |
---|
1897 | decISON(const rtems_irq_connect_data* irq) |
---|
1898 | { |
---|
1899 | return (BSP_irq_enabled_at_i8259s(irq->name)); |
---|
1900 | } |
---|
1901 | |
---|
1902 | |
---|
1903 | /* |
---|
1904 | * Attach the interface. Allocate softc structures, do ifmedia |
---|
1905 | * setup and ethernet/BPF attach. |
---|
1906 | */ |
---|
1907 | int |
---|
1908 | rtems_dc_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching) |
---|
1909 | { |
---|
1910 | int rc; |
---|
1911 | u_char eaddr[ETHER_ADDR_LEN]; |
---|
1912 | |
---|
1913 | char *unitName; |
---|
1914 | int unitNumber; |
---|
1915 | |
---|
1916 | uint32_t command; |
---|
1917 | struct dc_softc *sc; |
---|
1918 | struct ifnet *ifp; |
---|
1919 | struct dc_type *t; |
---|
1920 | uint32_t revision; |
---|
1921 | int error = 0, mac_offset; |
---|
1922 | uint32_t value; |
---|
1923 | |
---|
1924 | /* |
---|
1925 | * Get the instance number for the board we're going to configure |
---|
1926 | * from the user. |
---|
1927 | */ |
---|
1928 | unitNumber = rtems_bsdnet_parse_driver_name(config, &unitName); |
---|
1929 | if( unitNumber < 0) { |
---|
1930 | return 0; |
---|
1931 | } |
---|
1932 | if( strcmp(unitName, DRIVER_PREFIX) ) { |
---|
1933 | printk("dec2114x : unit name '%s' not %s\n", \ |
---|
1934 | unitName, DRIVER_PREFIX ); |
---|
1935 | return 0; |
---|
1936 | } |
---|
1937 | |
---|
1938 | sc = &dc_softc_devs[unitNumber - 1]; |
---|
1939 | ifp = &sc->arpcom.ac_if; |
---|
1940 | |
---|
1941 | if(ifp->if_softc != NULL) { |
---|
1942 | printk("dec2114x[%d]: unit number already in use.\n", \ |
---|
1943 | unitNumber); |
---|
1944 | return (0); |
---|
1945 | } |
---|
1946 | memset(sc, 0, sizeof(struct dc_softc)); |
---|
1947 | |
---|
1948 | /*unit = device_get_unit(dev);*/ |
---|
1949 | sc->dc_unit = unitNumber; |
---|
1950 | sc->dc_name = unitName; |
---|
1951 | |
---|
1952 | /* |
---|
1953 | * Handle power management nonsense. |
---|
1954 | * |
---|
1955 | dc_acpi(dev); |
---|
1956 | */ |
---|
1957 | |
---|
1958 | /* Scan for dec2114x cards in pci config space */ |
---|
1959 | if( (sc->dc_info = dc_devtype(unitNumber)) == NULL) { |
---|
1960 | printk("Can't find any dec2114x NICs in PCI space.\n"); |
---|
1961 | return 0; |
---|
1962 | } |
---|
1963 | t = sc->dc_info; |
---|
1964 | |
---|
1965 | |
---|
1966 | /* |
---|
1967 | * Map control/status registers. |
---|
1968 | */ |
---|
1969 | /*sig = sc->dc_info->dc_devsig; */ |
---|
1970 | pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\ |
---|
1971 | PCI_COMMAND, &command); |
---|
1972 | /*pcib_conf_read32(sig, PCI_COMMAND, &command); */ |
---|
1973 | command |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
---|
1974 | pci_write_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\ |
---|
1975 | PCI_COMMAND, command); |
---|
1976 | /*pcib_conf_write32(sig, PCI_COMMAND, command); */ |
---|
1977 | pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\ |
---|
1978 | PCI_COMMAND, &command); |
---|
1979 | /*pcib_conf_read32(sig, PCI_COMMAND, &command); */ |
---|
1980 | |
---|
1981 | #ifdef DC_USEIOSPACE |
---|
1982 | if (!(command & PCI_COMMAND_IO)) { |
---|
1983 | printk("dc%d: failed to enable I/O ports!\n", sc->dc_unit); |
---|
1984 | error = ENXIO; |
---|
1985 | goto fail; |
---|
1986 | } |
---|
1987 | #else |
---|
1988 | if (!(command & PCI_COMMAND_MEMORY)) { |
---|
1989 | printk("dc%d: failed to enable memory mapping!\n", sc->dc_unit); |
---|
1990 | error = ENXIO; |
---|
1991 | goto fail; |
---|
1992 | } |
---|
1993 | #endif |
---|
1994 | |
---|
1995 | #if 0 |
---|
1996 | rid = DC_RID; |
---|
1997 | sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, |
---|
1998 | 0, ~0, 1, RF_ACTIVE); |
---|
1999 | |
---|
2000 | if (sc->dc_res == NULL) { |
---|
2001 | printk("dc%d: couldn't map ports/memory\n", unit); |
---|
2002 | error = ENXIO; |
---|
2003 | goto fail; |
---|
2004 | } |
---|
2005 | sc->dc_btag = rman_get_bustag(sc->dc_res); |
---|
2006 | sc->dc_bhandle = rman_get_bushandle(sc->dc_res); |
---|
2007 | #endif |
---|
2008 | |
---|
2009 | /* sc->membase is the address of the card's CSRs !!! */ |
---|
2010 | /*pcib_conf_read32(sig, DC_PCI_CFBMA, &value); */ |
---|
2011 | pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\ |
---|
2012 | DC_PCI_CFBMA, &value); |
---|
2013 | sc->membase = value; |
---|
2014 | |
---|
2015 | /* Allocate interrupt */ |
---|
2016 | memset(&sc->irqInfo, 0, sizeof(rtems_irq_connect_data)); |
---|
2017 | /*pcib_conf_read32(sig, DC_PCI_CFIT, &value); */ |
---|
2018 | pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\ |
---|
2019 | DC_PCI_CFIT, &value); |
---|
2020 | |
---|
2021 | sc->irqInfo.name = value & 0xFF; |
---|
2022 | sc->irqInfo.hdl = (rtems_irq_hdl)dc_intr; |
---|
2023 | sc->irqInfo.handle = (void *)sc; /* new parameter */ |
---|
2024 | sc->irqInfo.on = nop; |
---|
2025 | sc->irqInfo.off = nop; |
---|
2026 | sc->irqInfo.isOn = decISON; |
---|
2027 | |
---|
2028 | #ifdef BSP_SHARED_HANDLER_SUPPORT |
---|
2029 | rc = BSP_install_rtems_shared_irq_handler( &sc->irqInfo ); |
---|
2030 | #else |
---|
2031 | rc = BSP_install_rtems_irq_handler( &sc->irqInfo ); |
---|
2032 | #endif |
---|
2033 | if(!rc) { |
---|
2034 | rtems_panic("Can't install dec2114x irq handler.\n"); |
---|
2035 | } |
---|
2036 | |
---|
2037 | |
---|
2038 | #if 0 |
---|
2039 | rid = 0; |
---|
2040 | sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, |
---|
2041 | RF_SHAREABLE | RF_ACTIVE); |
---|
2042 | |
---|
2043 | if (sc->dc_irq == NULL) { |
---|
2044 | printk("dc%d: couldn't map interrupt\n", unit); |
---|
2045 | bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); |
---|
2046 | error = ENXIO; |
---|
2047 | goto fail; |
---|
2048 | } |
---|
2049 | |
---|
2050 | error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET, |
---|
2051 | dc_intr, sc, &sc->dc_intrhand); |
---|
2052 | |
---|
2053 | if (error) { |
---|
2054 | bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); |
---|
2055 | bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); |
---|
2056 | printk("dc%d: couldn't set up irq\n", unit); |
---|
2057 | goto fail; |
---|
2058 | } |
---|
2059 | #endif |
---|
2060 | |
---|
2061 | |
---|
2062 | /* Need this info to decide on a chip type. |
---|
2063 | sc->dc_info = dc_devtype(dev); |
---|
2064 | */ |
---|
2065 | /*pcib_conf_read32(sig, DC_PCI_CFRV, &revision); */ |
---|
2066 | pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\ |
---|
2067 | DC_PCI_CFRV, &revision); |
---|
2068 | revision &= 0x000000FF; |
---|
2069 | |
---|
2070 | /* Get the eeprom width, but PNIC has diff eeprom */ |
---|
2071 | if (sc->dc_info->dc_did != DC_DEVICEID_82C168) |
---|
2072 | dc_eeprom_width(sc); |
---|
2073 | |
---|
2074 | switch(sc->dc_info->dc_did) { |
---|
2075 | case DC_DEVICEID_21143: |
---|
2076 | sc->dc_type = DC_TYPE_21143; |
---|
2077 | sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; |
---|
2078 | sc->dc_flags |= DC_REDUCED_MII_POLL; |
---|
2079 | /* Save EEPROM contents so we can parse them later. */ |
---|
2080 | dc_read_srom(sc, sc->dc_romwidth); |
---|
2081 | break; |
---|
2082 | case DC_DEVICEID_DM9009: |
---|
2083 | case DC_DEVICEID_DM9100: |
---|
2084 | case DC_DEVICEID_DM9102: |
---|
2085 | sc->dc_type = DC_TYPE_DM9102; |
---|
2086 | sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; |
---|
2087 | sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; |
---|
2088 | sc->dc_pmode = DC_PMODE_MII; |
---|
2089 | /* Increase the latency timer value. */ |
---|
2090 | /*pcib_conf_read32(sig, DC_PCI_CFLT, &command); */ |
---|
2091 | pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\ |
---|
2092 | DC_PCI_CFLT, &command); |
---|
2093 | command &= 0xFFFF00FF; |
---|
2094 | command |= 0x00008000; |
---|
2095 | /*pcib_conf_write32(sig, DC_PCI_CFLT, command); */ |
---|
2096 | pci_write_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\ |
---|
2097 | DC_PCI_CFLT, command); |
---|
2098 | break; |
---|
2099 | case DC_DEVICEID_AL981: |
---|
2100 | sc->dc_type = DC_TYPE_AL981; |
---|
2101 | sc->dc_flags |= DC_TX_USE_TX_INTR; |
---|
2102 | sc->dc_flags |= DC_TX_ADMTEK_WAR; |
---|
2103 | sc->dc_pmode = DC_PMODE_MII; |
---|
2104 | dc_read_srom(sc, sc->dc_romwidth); |
---|
2105 | break; |
---|
2106 | case DC_DEVICEID_AN985: |
---|
2107 | case DC_DEVICEID_EN2242: |
---|
2108 | sc->dc_type = DC_TYPE_AN985; |
---|
2109 | sc->dc_flags |= DC_TX_USE_TX_INTR; |
---|
2110 | sc->dc_flags |= DC_TX_ADMTEK_WAR; |
---|
2111 | sc->dc_pmode = DC_PMODE_MII; |
---|
2112 | dc_read_srom(sc, sc->dc_romwidth); |
---|
2113 | break; |
---|
2114 | case DC_DEVICEID_98713: |
---|
2115 | case DC_DEVICEID_98713_CP: |
---|
2116 | if (revision < DC_REVISION_98713A) { |
---|
2117 | sc->dc_type = DC_TYPE_98713; |
---|
2118 | } |
---|
2119 | if (revision >= DC_REVISION_98713A) { |
---|
2120 | sc->dc_type = DC_TYPE_98713A; |
---|
2121 | sc->dc_flags |= DC_21143_NWAY; |
---|
2122 | } |
---|
2123 | sc->dc_flags |= DC_REDUCED_MII_POLL; |
---|
2124 | sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; |
---|
2125 | break; |
---|
2126 | case DC_DEVICEID_987x5: |
---|
2127 | case DC_DEVICEID_EN1217: |
---|
2128 | /* |
---|
2129 | * Macronix MX98715AEC-C/D/E parts have only a |
---|
2130 | * 128-bit hash table. We need to deal with these |
---|
2131 | * in the same manner as the PNIC II so that we |
---|
2132 | * get the right number of bits out of the |
---|
2133 | * CRC routine. |
---|
2134 | */ |
---|
2135 | if (revision >= DC_REVISION_98715AEC_C && |
---|
2136 | revision < DC_REVISION_98725) |
---|
2137 | sc->dc_flags |= DC_128BIT_HASH; |
---|
2138 | sc->dc_type = DC_TYPE_987x5; |
---|
2139 | sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; |
---|
2140 | sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; |
---|
2141 | break; |
---|
2142 | case DC_DEVICEID_98727: |
---|
2143 | sc->dc_type = DC_TYPE_987x5; |
---|
2144 | sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; |
---|
2145 | sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; |
---|
2146 | break; |
---|
2147 | case DC_DEVICEID_82C115: |
---|
2148 | sc->dc_type = DC_TYPE_PNICII; |
---|
2149 | sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; |
---|
2150 | sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; |
---|
2151 | break; |
---|
2152 | case DC_DEVICEID_82C168: |
---|
2153 | sc->dc_type = DC_TYPE_PNIC; |
---|
2154 | sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; |
---|
2155 | sc->dc_flags |= DC_PNIC_RX_BUG_WAR; |
---|
2156 | sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); |
---|
2157 | if (revision < DC_REVISION_82C169) |
---|
2158 | sc->dc_pmode = DC_PMODE_SYM; |
---|
2159 | break; |
---|
2160 | case DC_DEVICEID_AX88140A: |
---|
2161 | sc->dc_type = DC_TYPE_ASIX; |
---|
2162 | sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; |
---|
2163 | sc->dc_flags |= DC_REDUCED_MII_POLL; |
---|
2164 | sc->dc_pmode = DC_PMODE_MII; |
---|
2165 | break; |
---|
2166 | case DC_DEVICEID_RS7112: |
---|
2167 | sc->dc_type = DC_TYPE_CONEXANT; |
---|
2168 | sc->dc_flags |= DC_TX_INTR_ALWAYS; |
---|
2169 | sc->dc_flags |= DC_REDUCED_MII_POLL; |
---|
2170 | sc->dc_pmode = DC_PMODE_MII; |
---|
2171 | dc_read_srom(sc, sc->dc_romwidth); |
---|
2172 | break; |
---|
2173 | default: |
---|
2174 | printk("dc%d: unknown device: %x\n", sc->dc_unit, |
---|
2175 | sc->dc_info->dc_did); |
---|
2176 | break; |
---|
2177 | } |
---|
2178 | |
---|
2179 | /* Save the cache line size. */ |
---|
2180 | if (DC_IS_DAVICOM(sc)) { |
---|
2181 | sc->dc_cachesize = 0; |
---|
2182 | } |
---|
2183 | else { |
---|
2184 | /*pcib_conf_read32(sig, DC_PCI_CFLT, &value); */ |
---|
2185 | pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\ |
---|
2186 | DC_PCI_CFLT, &value); |
---|
2187 | sc->dc_cachesize = (u_int8_t)(value & 0xFF); |
---|
2188 | } |
---|
2189 | |
---|
2190 | /* Reset the adapter. */ |
---|
2191 | dc_reset(sc); |
---|
2192 | |
---|
2193 | /* Take 21143 out of snooze mode */ |
---|
2194 | if (DC_IS_INTEL(sc)) { |
---|
2195 | /*pcib_conf_read32(sig, DC_PCI_CFDD, &command); */ |
---|
2196 | pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\ |
---|
2197 | DC_PCI_CFDD, &command); |
---|
2198 | command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); |
---|
2199 | /*pcib_conf_write32(sig, DC_PCI_CFDD, command); */ |
---|
2200 | pci_write_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\ |
---|
2201 | DC_PCI_CFDD, command); |
---|
2202 | } |
---|
2203 | |
---|
2204 | |
---|
2205 | /* |
---|
2206 | * Try to learn something about the supported media. |
---|
2207 | * We know that ASIX and ADMtek and Davicom devices |
---|
2208 | * will *always* be using MII media, so that's a no-brainer. |
---|
2209 | * The tricky ones are the Macronix/PNIC II and the |
---|
2210 | * Intel 21143. |
---|
2211 | */ |
---|
2212 | if (DC_IS_INTEL(sc)) |
---|
2213 | dc_parse_21143_srom(sc); |
---|
2214 | else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { |
---|
2215 | if (sc->dc_type == DC_TYPE_98713) |
---|
2216 | sc->dc_pmode = DC_PMODE_MII; |
---|
2217 | else |
---|
2218 | sc->dc_pmode = DC_PMODE_SYM; |
---|
2219 | } else if (!sc->dc_pmode) |
---|
2220 | sc->dc_pmode = DC_PMODE_MII; |
---|
2221 | |
---|
2222 | /* |
---|
2223 | * Get station address from the EEPROM. |
---|
2224 | */ |
---|
2225 | switch(sc->dc_type) { |
---|
2226 | case DC_TYPE_98713: |
---|
2227 | case DC_TYPE_98713A: |
---|
2228 | case DC_TYPE_987x5: |
---|
2229 | case DC_TYPE_PNICII: |
---|
2230 | dc_read_eeprom(sc, (caddr_t)&mac_offset, |
---|
2231 | (DC_EE_NODEADDR_OFFSET / 2), 1, 0); |
---|
2232 | dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); |
---|
2233 | break; |
---|
2234 | case DC_TYPE_PNIC: |
---|
2235 | dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); |
---|
2236 | break; |
---|
2237 | case DC_TYPE_DM9102: |
---|
2238 | case DC_TYPE_21143: |
---|
2239 | case DC_TYPE_ASIX: |
---|
2240 | dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); |
---|
2241 | break; |
---|
2242 | case DC_TYPE_AL981: |
---|
2243 | case DC_TYPE_AN985: |
---|
2244 | bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr, |
---|
2245 | ETHER_ADDR_LEN); |
---|
2246 | dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); |
---|
2247 | break; |
---|
2248 | case DC_TYPE_CONEXANT: |
---|
2249 | bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); |
---|
2250 | break; |
---|
2251 | default: |
---|
2252 | dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); |
---|
2253 | break; |
---|
2254 | } |
---|
2255 | |
---|
2256 | /* |
---|
2257 | * A 21143 or clone chip was detected. Inform the world. |
---|
2258 | */ |
---|
2259 | bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); |
---|
2260 | printk("dc%d: MAC address -- %02x:%02x:%02x:%02x:%02x:%02x\n", \ |
---|
2261 | sc->dc_unit,sc->arpcom.ac_enaddr[0], \ |
---|
2262 | sc->arpcom.ac_enaddr[1], sc->arpcom.ac_enaddr[2], \ |
---|
2263 | sc->arpcom.ac_enaddr[3], sc->arpcom.ac_enaddr[4], \ |
---|
2264 | sc->arpcom.ac_enaddr[5]); |
---|
2265 | |
---|
2266 | |
---|
2267 | sc->dc_ldata = malloc(sizeof(struct dc_list_data), M_DEVBUF, M_NOWAIT); |
---|
2268 | |
---|
2269 | if (sc->dc_ldata == NULL) { |
---|
2270 | printk("dc%d: no memory for list buffers!\n", sc->dc_unit); |
---|
2271 | if (sc->dc_pnic_rx_buf != NULL) |
---|
2272 | free(sc->dc_pnic_rx_buf, M_DEVBUF); |
---|
2273 | #if 0 |
---|
2274 | bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); |
---|
2275 | bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); |
---|
2276 | bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); |
---|
2277 | #endif |
---|
2278 | error = ENXIO; |
---|
2279 | goto fail; |
---|
2280 | } |
---|
2281 | |
---|
2282 | bzero(sc->dc_ldata, sizeof(struct dc_list_data)); |
---|
2283 | |
---|
2284 | ifp = &sc->arpcom.ac_if; |
---|
2285 | ifp->if_softc = sc; |
---|
2286 | ifp->if_unit = unitNumber; /*sc->dc_unit;*/ |
---|
2287 | ifp->if_name = unitName; /*sc->dc_name;*/ |
---|
2288 | ifp->if_mtu = ETHERMTU; |
---|
2289 | ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX; /* | IFF_MULTICAST;*/ |
---|
2290 | ifp->if_ioctl = dc_ioctl; |
---|
2291 | ifp->if_output = ether_output; |
---|
2292 | ifp->if_start = dc_start; |
---|
2293 | ifp->if_watchdog = dc_watchdog; |
---|
2294 | ifp->if_init = dc_init; |
---|
2295 | ifp->if_baudrate = 100000000; |
---|
2296 | ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; |
---|
2297 | |
---|
2298 | #if 0 |
---|
2299 | /* |
---|
2300 | * Do MII setup. If this is a 21143, check for a PHY on the |
---|
2301 | * MII bus after applying any necessary fixups to twiddle the |
---|
2302 | * GPIO bits. If we don't end up finding a PHY, restore the |
---|
2303 | * old selection (SIA only or SIA/SYM) and attach the dcphy |
---|
2304 | * driver instead. |
---|
2305 | */ |
---|
2306 | if (DC_IS_INTEL(sc)) { |
---|
2307 | dc_apply_fixup(sc, IFM_AUTO); |
---|
2308 | tmp = sc->dc_pmode; |
---|
2309 | sc->dc_pmode = DC_PMODE_MII; |
---|
2310 | } |
---|
2311 | |
---|
2312 | error = mii_phy_probe(dev, &sc->dc_miibus, |
---|
2313 | dc_ifmedia_upd, dc_ifmedia_sts); |
---|
2314 | |
---|
2315 | if (error && DC_IS_INTEL(sc)) { |
---|
2316 | sc->dc_pmode = tmp; |
---|
2317 | if (sc->dc_pmode != DC_PMODE_SIA) |
---|
2318 | sc->dc_pmode = DC_PMODE_SYM; |
---|
2319 | sc->dc_flags |= DC_21143_NWAY; |
---|
2320 | mii_phy_probe(dev, &sc->dc_miibus, |
---|
2321 | dc_ifmedia_upd, dc_ifmedia_sts); |
---|
2322 | /* |
---|
2323 | * For non-MII cards, we need to have the 21143 |
---|
2324 | * drive the LEDs. Except there are some systems |
---|
2325 | * like the NEC VersaPro NoteBook PC which have no |
---|
2326 | * LEDs, and twiddling these bits has adverse effects |
---|
2327 | * on them. (I.e. you suddenly can't get a link.) |
---|
2328 | */ |
---|
2329 | if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) |
---|
2330 | sc->dc_flags |= DC_TULIP_LEDS; |
---|
2331 | error = 0; |
---|
2332 | } |
---|
2333 | |
---|
2334 | if (error) { |
---|
2335 | printk("dc%d: MII without any PHY!\n", sc->dc_unit); |
---|
2336 | contigfree(sc->dc_ldata, sizeof(struct dc_list_data), |
---|
2337 | M_DEVBUF); |
---|
2338 | if (sc->dc_pnic_rx_buf != NULL) |
---|
2339 | free(sc->dc_pnic_rx_buf, M_DEVBUF); |
---|
2340 | bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); |
---|
2341 | bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); |
---|
2342 | bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); |
---|
2343 | error = ENXIO; |
---|
2344 | goto fail; |
---|
2345 | } |
---|
2346 | #endif |
---|
2347 | |
---|
2348 | /* |
---|
2349 | * Call MI attach routine. |
---|
2350 | */ |
---|
2351 | if_attach(ifp); |
---|
2352 | ether_ifattach(ifp); |
---|
2353 | /*callout_handle_init(&sc->dc_stat_ch);*/ |
---|
2354 | |
---|
2355 | if (DC_IS_ADMTEK(sc)) { |
---|
2356 | /* |
---|
2357 | * Set automatic TX underrun recovery for the ADMtek chips |
---|
2358 | */ |
---|
2359 | DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); |
---|
2360 | } |
---|
2361 | |
---|
2362 | if(sc->daemontid == 0) { |
---|
2363 | sc->daemontid = rtems_bsdnet_newproc("decD",4096, \ |
---|
2364 | dc_daemon,(void *)sc); |
---|
2365 | printk("dec[%d]: daemon process started\n", sc->dc_unit); |
---|
2366 | } |
---|
2367 | |
---|
2368 | /* |
---|
2369 | * Tell the upper layer(s) we support long frames. |
---|
2370 | * |
---|
2371 | ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); |
---|
2372 | */ |
---|
2373 | |
---|
2374 | #ifdef SRM_MEDIA /* only defined if __alpha__ is defined... */ |
---|
2375 | sc->dc_srm_media = 0; |
---|
2376 | |
---|
2377 | /* Remember the SRM console media setting */ |
---|
2378 | if (DC_IS_INTEL(sc)) { |
---|
2379 | command = pci_read_config(dev, DC_PCI_CFDD, 4); |
---|
2380 | command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); |
---|
2381 | switch ((command >> 8) & 0xff) { |
---|
2382 | case 3: |
---|
2383 | sc->dc_srm_media = IFM_10_T; |
---|
2384 | break; |
---|
2385 | case 4: |
---|
2386 | sc->dc_srm_media = IFM_10_T | IFM_FDX; |
---|
2387 | break; |
---|
2388 | case 5: |
---|
2389 | sc->dc_srm_media = IFM_100_TX; |
---|
2390 | break; |
---|
2391 | case 6: |
---|
2392 | sc->dc_srm_media = IFM_100_TX | IFM_FDX; |
---|
2393 | break; |
---|
2394 | } |
---|
2395 | if (sc->dc_srm_media) |
---|
2396 | sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; |
---|
2397 | } |
---|
2398 | #endif |
---|
2399 | |
---|
2400 | |
---|
2401 | fail: |
---|
2402 | |
---|
2403 | return (1); /*(error);*/ |
---|
2404 | } |
---|
2405 | |
---|
2406 | #if 0 |
---|
2407 | static int dc_detach(dev) |
---|
2408 | device_t dev; |
---|
2409 | { |
---|
2410 | struct dc_softc *sc; |
---|
2411 | struct ifnet *ifp; |
---|
2412 | int s; |
---|
2413 | struct dc_mediainfo *m; |
---|
2414 | |
---|
2415 | |
---|
2416 | sc = device_get_softc(dev); |
---|
2417 | ifp = &sc->arpcom.ac_if; |
---|
2418 | |
---|
2419 | dc_stop(sc); |
---|
2420 | ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); |
---|
2421 | |
---|
2422 | bus_generic_detach(dev); |
---|
2423 | device_delete_child(dev, sc->dc_miibus); |
---|
2424 | |
---|
2425 | bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); |
---|
2426 | bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); |
---|
2427 | bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); |
---|
2428 | |
---|
2429 | contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); |
---|
2430 | if (sc->dc_pnic_rx_buf != NULL) |
---|
2431 | free(sc->dc_pnic_rx_buf, M_DEVBUF); |
---|
2432 | |
---|
2433 | while(sc->dc_mi != NULL) { |
---|
2434 | m = sc->dc_mi->dc_next; |
---|
2435 | free(sc->dc_mi, M_DEVBUF); |
---|
2436 | sc->dc_mi = m; |
---|
2437 | } |
---|
2438 | free(sc->dc_srom, M_DEVBUF); |
---|
2439 | |
---|
2440 | |
---|
2441 | return(0); |
---|
2442 | } |
---|
2443 | #endif |
---|
2444 | |
---|
2445 | |
---|
2446 | /* |
---|
2447 | * Initialize the transmit descriptors. |
---|
2448 | */ |
---|
2449 | static int dc_list_tx_init(sc) |
---|
2450 | struct dc_softc *sc; |
---|
2451 | { |
---|
2452 | struct dc_chain_data *cd; |
---|
2453 | struct dc_list_data *ld; |
---|
2454 | int i; |
---|
2455 | |
---|
2456 | cd = &sc->dc_cdata; |
---|
2457 | ld = sc->dc_ldata; |
---|
2458 | for (i = 0; i < DC_TX_LIST_CNT; i++) { |
---|
2459 | if (i == (DC_TX_LIST_CNT - 1)) { |
---|
2460 | ld->dc_tx_list[i].dc_next = |
---|
2461 | vtophys(&ld->dc_tx_list[0]); |
---|
2462 | } else { |
---|
2463 | ld->dc_tx_list[i].dc_next = |
---|
2464 | vtophys(&ld->dc_tx_list[i + 1]); |
---|
2465 | } |
---|
2466 | cd->dc_tx_chain[i] = NULL; |
---|
2467 | ld->dc_tx_list[i].dc_data = 0; |
---|
2468 | ld->dc_tx_list[i].dc_ctl = 0; |
---|
2469 | } |
---|
2470 | |
---|
2471 | cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; |
---|
2472 | |
---|
2473 | return(0); |
---|
2474 | } |
---|
2475 | |
---|
2476 | |
---|
2477 | /* |
---|
2478 | * Initialize the RX descriptors and allocate mbufs for them. Note that |
---|
2479 | * we arrange the descriptors in a closed ring, so that the last descriptor |
---|
2480 | * points back to the first. |
---|
2481 | */ |
---|
2482 | static int dc_list_rx_init(sc) |
---|
2483 | struct dc_softc *sc; |
---|
2484 | { |
---|
2485 | struct dc_chain_data *cd; |
---|
2486 | struct dc_list_data *ld; |
---|
2487 | int i; |
---|
2488 | |
---|
2489 | cd = &sc->dc_cdata; |
---|
2490 | ld = sc->dc_ldata; |
---|
2491 | |
---|
2492 | for (i = 0; i < DC_RX_LIST_CNT; i++) { |
---|
2493 | if (dc_newbuf(sc, i, NULL) == ENOBUFS) |
---|
2494 | return(ENOBUFS); |
---|
2495 | if (i == (DC_RX_LIST_CNT - 1)) { |
---|
2496 | ld->dc_rx_list[i].dc_next = |
---|
2497 | vtophys(&ld->dc_rx_list[0]); |
---|
2498 | } else { |
---|
2499 | ld->dc_rx_list[i].dc_next = |
---|
2500 | vtophys(&ld->dc_rx_list[i + 1]); |
---|
2501 | } |
---|
2502 | } |
---|
2503 | |
---|
2504 | cd->dc_rx_prod = 0; |
---|
2505 | |
---|
2506 | return(0); |
---|
2507 | } |
---|
2508 | |
---|
2509 | /* |
---|
2510 | * Initialize an RX descriptor and attach an MBUF cluster. |
---|
2511 | */ |
---|
2512 | static int dc_newbuf(sc, i, m) |
---|
2513 | struct dc_softc *sc; |
---|
2514 | int i; |
---|
2515 | struct mbuf *m; |
---|
2516 | { |
---|
2517 | struct mbuf *m_new = NULL; |
---|
2518 | struct dc_desc *c; |
---|
2519 | |
---|
2520 | c = &sc->dc_ldata->dc_rx_list[i]; |
---|
2521 | |
---|
2522 | if (m == NULL) { |
---|
2523 | MGETHDR(m_new, M_DONTWAIT, MT_DATA); |
---|
2524 | if (m_new == NULL) |
---|
2525 | return(ENOBUFS); |
---|
2526 | |
---|
2527 | MCLGET(m_new, M_DONTWAIT); |
---|
2528 | if (!(m_new->m_flags & M_EXT)) { |
---|
2529 | m_freem(m_new); |
---|
2530 | return(ENOBUFS); |
---|
2531 | } |
---|
2532 | m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; |
---|
2533 | } else { |
---|
2534 | m_new = m; |
---|
2535 | m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; |
---|
2536 | m_new->m_data = m_new->m_ext.ext_buf; |
---|
2537 | } |
---|
2538 | |
---|
2539 | m_adj(m_new, sizeof(u_int64_t)); |
---|
2540 | |
---|
2541 | /* |
---|
2542 | * If this is a PNIC chip, zero the buffer. This is part |
---|
2543 | * of the workaround for the receive bug in the 82c168 and |
---|
2544 | * 82c169 chips. |
---|
2545 | */ |
---|
2546 | if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) |
---|
2547 | bzero((char *)mtod(m_new, char *), m_new->m_len); |
---|
2548 | |
---|
2549 | sc->dc_cdata.dc_rx_chain[i] = m_new; |
---|
2550 | c->dc_data = vtophys(mtod(m_new, caddr_t)); |
---|
2551 | c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; |
---|
2552 | c->dc_status = DC_RXSTAT_OWN; |
---|
2553 | |
---|
2554 | return(0); |
---|
2555 | } |
---|
2556 | |
---|
2557 | /* |
---|
2558 | * Grrrrr. |
---|
2559 | * The PNIC chip has a terrible bug in it that manifests itself during |
---|
2560 | * periods of heavy activity. The exact mode of failure if difficult to |
---|
2561 | * pinpoint: sometimes it only happens in promiscuous mode, sometimes it |
---|
2562 | * will happen on slow machines. The bug is that sometimes instead of |
---|
2563 | * uploading one complete frame during reception, it uploads what looks |
---|
2564 | * like the entire contents of its FIFO memory. The frame we want is at |
---|
2565 | * the end of the whole mess, but we never know exactly how much data has |
---|
2566 | * been uploaded, so salvaging the frame is hard. |
---|
2567 | * |
---|
2568 | * There is only one way to do it reliably, and it's disgusting. |
---|
2569 | * Here's what we know: |
---|
2570 | * |
---|
2571 | * - We know there will always be somewhere between one and three extra |
---|
2572 | * descriptors uploaded. |
---|
2573 | * |
---|
2574 | * - We know the desired received frame will always be at the end of the |
---|
2575 | * total data upload. |
---|
2576 | * |
---|
2577 | * - We know the size of the desired received frame because it will be |
---|
2578 | * provided in the length field of the status word in the last descriptor. |
---|
2579 | * |
---|
2580 | * Here's what we do: |
---|
2581 | * |
---|
2582 | * - When we allocate buffers for the receive ring, we bzero() them. |
---|
2583 | * This means that we know that the buffer contents should be all |
---|
2584 | * zeros, except for data uploaded by the chip. |
---|
2585 | * |
---|
2586 | * - We also force the PNIC chip to upload frames that include the |
---|
2587 | * ethernet CRC at the end. |
---|
2588 | * |
---|
2589 | * - We gather all of the bogus frame data into a single buffer. |
---|
2590 | * |
---|
2591 | * - We then position a pointer at the end of this buffer and scan |
---|
2592 | * backwards until we encounter the first non-zero byte of data. |
---|
2593 | * This is the end of the received frame. We know we will encounter |
---|
2594 | * some data at the end of the frame because the CRC will always be |
---|
2595 | * there, so even if the sender transmits a packet of all zeros, |
---|
2596 | * we won't be fooled. |
---|
2597 | * |
---|
2598 | * - We know the size of the actual received frame, so we subtract |
---|
2599 | * that value from the current pointer location. This brings us |
---|
2600 | * to the start of the actual received packet. |
---|
2601 | * |
---|
2602 | * - We copy this into an mbuf and pass it on, along with the actual |
---|
2603 | * frame length. |
---|
2604 | * |
---|
2605 | * The performance hit is tremendous, but it beats dropping frames all |
---|
2606 | * the time. |
---|
2607 | */ |
---|
2608 | |
---|
2609 | #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) |
---|
2610 | static void dc_pnic_rx_bug_war(sc, idx) |
---|
2611 | struct dc_softc *sc; |
---|
2612 | int idx; |
---|
2613 | { |
---|
2614 | struct dc_desc *cur_rx; |
---|
2615 | struct dc_desc *c = NULL; |
---|
2616 | struct mbuf *m = NULL; |
---|
2617 | unsigned char *ptr; |
---|
2618 | int i, total_len; |
---|
2619 | u_int32_t rxstat = 0; |
---|
2620 | |
---|
2621 | i = sc->dc_pnic_rx_bug_save; |
---|
2622 | cur_rx = &sc->dc_ldata->dc_rx_list[idx]; |
---|
2623 | ptr = sc->dc_pnic_rx_buf; |
---|
2624 | bzero(ptr, sizeof(DC_RXLEN * 5)); |
---|
2625 | |
---|
2626 | /* Copy all the bytes from the bogus buffers. */ |
---|
2627 | while (1) { |
---|
2628 | c = &sc->dc_ldata->dc_rx_list[i]; |
---|
2629 | rxstat = c->dc_status; |
---|
2630 | m = sc->dc_cdata.dc_rx_chain[i]; |
---|
2631 | bcopy(mtod(m, char *), ptr, DC_RXLEN); |
---|
2632 | ptr += DC_RXLEN; |
---|
2633 | /* If this is the last buffer, break out. */ |
---|
2634 | if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) |
---|
2635 | break; |
---|
2636 | dc_newbuf(sc, i, m); |
---|
2637 | DC_INC(i, DC_RX_LIST_CNT); |
---|
2638 | } |
---|
2639 | |
---|
2640 | /* Find the length of the actual receive frame. */ |
---|
2641 | total_len = DC_RXBYTES(rxstat); |
---|
2642 | |
---|
2643 | /* Scan backwards until we hit a non-zero byte. */ |
---|
2644 | while(*ptr == 0x00) |
---|
2645 | ptr--; |
---|
2646 | #if 0 |
---|
2647 | /* Round off. */ |
---|
2648 | if ((uintptr_t)(ptr) & 0x3) |
---|
2649 | ptr -= 1; |
---|
2650 | #endif |
---|
2651 | |
---|
2652 | /* Now find the start of the frame. */ |
---|
2653 | ptr -= total_len; |
---|
2654 | if (ptr < sc->dc_pnic_rx_buf) |
---|
2655 | ptr = sc->dc_pnic_rx_buf; |
---|
2656 | |
---|
2657 | /* |
---|
2658 | * Now copy the salvaged frame to the last mbuf and fake up |
---|
2659 | * the status word to make it look like a successful |
---|
2660 | * frame reception. |
---|
2661 | */ |
---|
2662 | dc_newbuf(sc, i, m); |
---|
2663 | bcopy(ptr, mtod(m, char *), total_len); |
---|
2664 | cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; |
---|
2665 | |
---|
2666 | return; |
---|
2667 | } |
---|
2668 | |
---|
2669 | /* |
---|
2670 | * This routine searches the RX ring for dirty descriptors in the |
---|
2671 | * event that the rxeof routine falls out of sync with the chip's |
---|
2672 | * current descriptor pointer. This may happen sometimes as a result |
---|
2673 | * of a "no RX buffer available" condition that happens when the chip |
---|
2674 | * consumes all of the RX buffers before the driver has a chance to |
---|
2675 | * process the RX ring. This routine may need to be called more than |
---|
2676 | * once to bring the driver back in sync with the chip, however we |
---|
2677 | * should still be getting RX DONE interrupts to drive the search |
---|
2678 | * for new packets in the RX ring, so we should catch up eventually. |
---|
2679 | */ |
---|
2680 | static int dc_rx_resync(sc) |
---|
2681 | struct dc_softc *sc; |
---|
2682 | { |
---|
2683 | int i, pos; |
---|
2684 | struct dc_desc *cur_rx; |
---|
2685 | |
---|
2686 | pos = sc->dc_cdata.dc_rx_prod; |
---|
2687 | |
---|
2688 | for (i = 0; i < DC_RX_LIST_CNT; i++) { |
---|
2689 | cur_rx = &sc->dc_ldata->dc_rx_list[pos]; |
---|
2690 | if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) |
---|
2691 | break; |
---|
2692 | DC_INC(pos, DC_RX_LIST_CNT); |
---|
2693 | } |
---|
2694 | |
---|
2695 | /* If the ring really is empty, then just return. */ |
---|
2696 | if (i == DC_RX_LIST_CNT) |
---|
2697 | return(0); |
---|
2698 | |
---|
2699 | /* We've fallen behing the chip: catch it. */ |
---|
2700 | sc->dc_cdata.dc_rx_prod = pos; |
---|
2701 | |
---|
2702 | return(EAGAIN); |
---|
2703 | } |
---|
2704 | |
---|
2705 | /* |
---|
2706 | * A frame has been uploaded: pass the resulting mbuf chain up to |
---|
2707 | * the higher level protocols. |
---|
2708 | */ |
---|
2709 | static void dc_rxeof(sc) |
---|
2710 | struct dc_softc *sc; |
---|
2711 | { |
---|
2712 | struct ether_header *eh; |
---|
2713 | struct mbuf *m; |
---|
2714 | struct ifnet *ifp; |
---|
2715 | struct dc_desc *cur_rx; |
---|
2716 | int i, total_len = 0; |
---|
2717 | u_int32_t rxstat; |
---|
2718 | |
---|
2719 | ifp = &sc->arpcom.ac_if; |
---|
2720 | i = sc->dc_cdata.dc_rx_prod; |
---|
2721 | |
---|
2722 | while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { |
---|
2723 | |
---|
2724 | #ifdef DEVICE_POLLING |
---|
2725 | if (ifp->if_ipending & IFF_POLLING) { |
---|
2726 | if (sc->rxcycles <= 0) |
---|
2727 | break; |
---|
2728 | sc->rxcycles--; |
---|
2729 | } |
---|
2730 | #endif /* DEVICE_POLLING */ |
---|
2731 | cur_rx = &sc->dc_ldata->dc_rx_list[i]; |
---|
2732 | rxstat = cur_rx->dc_status; |
---|
2733 | m = sc->dc_cdata.dc_rx_chain[i]; |
---|
2734 | total_len = DC_RXBYTES(rxstat); |
---|
2735 | |
---|
2736 | if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { |
---|
2737 | if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { |
---|
2738 | if (rxstat & DC_RXSTAT_FIRSTFRAG) |
---|
2739 | sc->dc_pnic_rx_bug_save = i; |
---|
2740 | if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { |
---|
2741 | DC_INC(i, DC_RX_LIST_CNT); |
---|
2742 | continue; |
---|
2743 | } |
---|
2744 | dc_pnic_rx_bug_war(sc, i); |
---|
2745 | rxstat = cur_rx->dc_status; |
---|
2746 | total_len = DC_RXBYTES(rxstat); |
---|
2747 | } |
---|
2748 | } |
---|
2749 | |
---|
2750 | sc->dc_cdata.dc_rx_chain[i] = NULL; |
---|
2751 | |
---|
2752 | /* |
---|
2753 | * If an error occurs, update stats, clear the |
---|
2754 | * status word and leave the mbuf cluster in place: |
---|
2755 | * it should simply get re-used next time this descriptor |
---|
2756 | * comes up in the ring. However, don't report long |
---|
2757 | * frames as errors since they could be vlans |
---|
2758 | */ |
---|
2759 | if ((rxstat & DC_RXSTAT_RXERR)){ |
---|
2760 | if (!(rxstat & DC_RXSTAT_GIANT) || |
---|
2761 | (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | |
---|
2762 | DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | |
---|
2763 | DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { |
---|
2764 | ifp->if_ierrors++; |
---|
2765 | if (rxstat & DC_RXSTAT_COLLSEEN) |
---|
2766 | ifp->if_collisions++; |
---|
2767 | dc_newbuf(sc, i, m); |
---|
2768 | if (rxstat & DC_RXSTAT_CRCERR) { |
---|
2769 | DC_INC(i, DC_RX_LIST_CNT); |
---|
2770 | continue; |
---|
2771 | } else { |
---|
2772 | dc_init(sc); |
---|
2773 | return; |
---|
2774 | } |
---|
2775 | } |
---|
2776 | } |
---|
2777 | |
---|
2778 | /* No errors; receive the packet. */ |
---|
2779 | total_len -= ETHER_CRC_LEN; |
---|
2780 | |
---|
2781 | #ifdef __i386__ |
---|
2782 | /* |
---|
2783 | * On the x86 we do not have alignment problems, so try to |
---|
2784 | * allocate a new buffer for the receive ring, and pass up |
---|
2785 | * the one where the packet is already, saving the expensive |
---|
2786 | * copy done in m_devget(). |
---|
2787 | * If we are on an architecture with alignment problems, or |
---|
2788 | * if the allocation fails, then use m_devget and leave the |
---|
2789 | * existing buffer in the receive ring. |
---|
2790 | */ |
---|
2791 | if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { |
---|
2792 | m->m_pkthdr.rcvif = ifp; |
---|
2793 | m->m_pkthdr.len = m->m_len = total_len; |
---|
2794 | DC_INC(i, DC_RX_LIST_CNT); |
---|
2795 | } else |
---|
2796 | #endif |
---|
2797 | { |
---|
2798 | struct mbuf *m0; |
---|
2799 | |
---|
2800 | m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, |
---|
2801 | total_len + ETHER_ALIGN, 0, ifp, NULL); |
---|
2802 | dc_newbuf(sc, i, m); |
---|
2803 | DC_INC(i, DC_RX_LIST_CNT); |
---|
2804 | if (m0 == NULL) { |
---|
2805 | ifp->if_ierrors++; |
---|
2806 | continue; |
---|
2807 | } |
---|
2808 | m_adj(m0, ETHER_ALIGN); |
---|
2809 | m = m0; |
---|
2810 | } |
---|
2811 | |
---|
2812 | ifp->if_ipackets++; |
---|
2813 | eh = mtod(m, struct ether_header *); |
---|
2814 | |
---|
2815 | /* Remove header from mbuf and pass it on. */ |
---|
2816 | m_adj(m, sizeof(struct ether_header)); |
---|
2817 | ether_input(ifp, eh, m); |
---|
2818 | } |
---|
2819 | |
---|
2820 | sc->dc_cdata.dc_rx_prod = i; |
---|
2821 | } |
---|
2822 | |
---|
2823 | /* |
---|
2824 | * A frame was downloaded to the chip. It's safe for us to clean up |
---|
2825 | * the list buffers. |
---|
2826 | */ |
---|
2827 | |
---|
2828 | static void |
---|
2829 | dc_txeof(sc) |
---|
2830 | struct dc_softc *sc; |
---|
2831 | { |
---|
2832 | struct dc_desc *cur_tx = NULL; |
---|
2833 | struct ifnet *ifp; |
---|
2834 | int idx; |
---|
2835 | |
---|
2836 | ifp = &sc->arpcom.ac_if; |
---|
2837 | |
---|
2838 | /* |
---|
2839 | * Go through our tx list and free mbufs for those |
---|
2840 | * frames that have been transmitted. |
---|
2841 | */ |
---|
2842 | idx = sc->dc_cdata.dc_tx_cons; |
---|
2843 | while(idx != sc->dc_cdata.dc_tx_prod) { |
---|
2844 | u_int32_t txstat; |
---|
2845 | |
---|
2846 | cur_tx = &sc->dc_ldata->dc_tx_list[idx]; |
---|
2847 | txstat = cur_tx->dc_status; |
---|
2848 | |
---|
2849 | if (txstat & DC_TXSTAT_OWN) |
---|
2850 | break; |
---|
2851 | |
---|
2852 | if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || |
---|
2853 | cur_tx->dc_ctl & DC_TXCTL_SETUP) { |
---|
2854 | if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { |
---|
2855 | /* |
---|
2856 | * Yes, the PNIC is so brain damaged |
---|
2857 | * that it will sometimes generate a TX |
---|
2858 | * underrun error while DMAing the RX |
---|
2859 | * filter setup frame. If we detect this, |
---|
2860 | * we have to send the setup frame again, |
---|
2861 | * or else the filter won't be programmed |
---|
2862 | * correctly. |
---|
2863 | */ |
---|
2864 | if (DC_IS_PNIC(sc)) { |
---|
2865 | if (txstat & DC_TXSTAT_ERRSUM) |
---|
2866 | dc_setfilt(sc); |
---|
2867 | } |
---|
2868 | sc->dc_cdata.dc_tx_chain[idx] = NULL; |
---|
2869 | } |
---|
2870 | sc->dc_cdata.dc_tx_cnt--; |
---|
2871 | DC_INC(idx, DC_TX_LIST_CNT); |
---|
2872 | continue; |
---|
2873 | } |
---|
2874 | |
---|
2875 | if (DC_IS_CONEXANT(sc)) { |
---|
2876 | /* |
---|
2877 | * For some reason Conexant chips like |
---|
2878 | * setting the CARRLOST flag even when |
---|
2879 | * the carrier is there. In CURRENT we |
---|
2880 | * have the same problem for Xircom |
---|
2881 | * cards ! |
---|
2882 | */ |
---|
2883 | if (/*sc->dc_type == DC_TYPE_21143 &&*/ |
---|
2884 | sc->dc_pmode == DC_PMODE_MII && |
---|
2885 | ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| |
---|
2886 | DC_TXSTAT_NOCARRIER))) |
---|
2887 | txstat &= ~DC_TXSTAT_ERRSUM; |
---|
2888 | } else { |
---|
2889 | if (/*sc->dc_type == DC_TYPE_21143 &&*/ |
---|
2890 | sc->dc_pmode == DC_PMODE_MII && |
---|
2891 | ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| |
---|
2892 | DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) |
---|
2893 | txstat &= ~DC_TXSTAT_ERRSUM; |
---|
2894 | } |
---|
2895 | |
---|
2896 | if (txstat & DC_TXSTAT_ERRSUM) { |
---|
2897 | ifp->if_oerrors++; |
---|
2898 | if (txstat & DC_TXSTAT_EXCESSCOLL) |
---|
2899 | ifp->if_collisions++; |
---|
2900 | if (txstat & DC_TXSTAT_LATECOLL) |
---|
2901 | ifp->if_collisions++; |
---|
2902 | if (!(txstat & DC_TXSTAT_UNDERRUN)) { |
---|
2903 | dc_init(sc); |
---|
2904 | return; |
---|
2905 | } |
---|
2906 | } |
---|
2907 | |
---|
2908 | ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; |
---|
2909 | |
---|
2910 | ifp->if_opackets++; |
---|
2911 | if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { |
---|
2912 | m_freem(sc->dc_cdata.dc_tx_chain[idx]); |
---|
2913 | sc->dc_cdata.dc_tx_chain[idx] = NULL; |
---|
2914 | } |
---|
2915 | |
---|
2916 | sc->dc_cdata.dc_tx_cnt--; |
---|
2917 | DC_INC(idx, DC_TX_LIST_CNT); |
---|
2918 | } |
---|
2919 | |
---|
2920 | if (idx != sc->dc_cdata.dc_tx_cons) { |
---|
2921 | /* some buffers have been freed */ |
---|
2922 | sc->dc_cdata.dc_tx_cons = idx; |
---|
2923 | ifp->if_flags &= ~IFF_OACTIVE; |
---|
2924 | } |
---|
2925 | ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; |
---|
2926 | |
---|
2927 | return; |
---|
2928 | } |
---|
2929 | |
---|
2930 | |
---|
2931 | #if 0 |
---|
2932 | static void dc_tick(xsc) |
---|
2933 | void *xsc; |
---|
2934 | { |
---|
2935 | struct dc_softc *sc; |
---|
2936 | /*struct mii_data *mii;*/ |
---|
2937 | struct ifnet *ifp; |
---|
2938 | int s; |
---|
2939 | u_int32_t r; |
---|
2940 | |
---|
2941 | |
---|
2942 | sc = xsc; |
---|
2943 | ifp = &sc->arpcom.ac_if; |
---|
2944 | mii = device_get_softc(sc->dc_miibus); |
---|
2945 | |
---|
2946 | if (sc->dc_flags & DC_REDUCED_MII_POLL) { |
---|
2947 | if (sc->dc_flags & DC_21143_NWAY) { |
---|
2948 | r = CSR_READ_4(sc, DC_10BTSTAT); |
---|
2949 | if (IFM_SUBTYPE(mii->mii_media_active) == |
---|
2950 | IFM_100_TX && (r & DC_TSTAT_LS100)) { |
---|
2951 | sc->dc_link = 0; |
---|
2952 | mii_mediachg(mii); |
---|
2953 | } |
---|
2954 | if (IFM_SUBTYPE(mii->mii_media_active) == |
---|
2955 | IFM_10_T && (r & DC_TSTAT_LS10)) { |
---|
2956 | sc->dc_link = 0; |
---|
2957 | mii_mediachg(mii); |
---|
2958 | } |
---|
2959 | if (sc->dc_link == 0) |
---|
2960 | mii_tick(mii); |
---|
2961 | } else { |
---|
2962 | r = CSR_READ_4(sc, DC_ISR); |
---|
2963 | if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && |
---|
2964 | sc->dc_cdata.dc_tx_cnt == 0) |
---|
2965 | mii_tick(mii); |
---|
2966 | if (!(mii->mii_media_status & IFM_ACTIVE)) |
---|
2967 | sc->dc_link = 0; |
---|
2968 | } |
---|
2969 | } else |
---|
2970 | mii_tick(mii); |
---|
2971 | |
---|
2972 | /* |
---|
2973 | * When the init routine completes, we expect to be able to send |
---|
2974 | * packets right away, and in fact the network code will send a |
---|
2975 | * gratuitous ARP the moment the init routine marks the interface |
---|
2976 | * as running. However, even though the MAC may have been initialized, |
---|
2977 | * there may be a delay of a few seconds before the PHY completes |
---|
2978 | * autonegotiation and the link is brought up. Any transmissions |
---|
2979 | * made during that delay will be lost. Dealing with this is tricky: |
---|
2980 | * we can't just pause in the init routine while waiting for the |
---|
2981 | * PHY to come ready since that would bring the whole system to |
---|
2982 | * a screeching halt for several seconds. |
---|
2983 | * |
---|
2984 | * What we do here is prevent the TX start routine from sending |
---|
2985 | * any packets until a link has been established. After the |
---|
2986 | * interface has been initialized, the tick routine will poll |
---|
2987 | * the state of the PHY until the IFM_ACTIVE flag is set. Until |
---|
2988 | * that time, packets will stay in the send queue, and once the |
---|
2989 | * link comes up, they will be flushed out to the wire. |
---|
2990 | */ |
---|
2991 | if (!sc->dc_link) { |
---|
2992 | mii_pollstat(mii); |
---|
2993 | if (mii->mii_media_status & IFM_ACTIVE && |
---|
2994 | IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { |
---|
2995 | sc->dc_link++; |
---|
2996 | if (ifp->if_snd.ifq_head != NULL) |
---|
2997 | dc_start(ifp); |
---|
2998 | } |
---|
2999 | } |
---|
3000 | |
---|
3001 | if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) |
---|
3002 | sc->dc_stat_ch = timeout(dc_tick, sc, hz/10); |
---|
3003 | else |
---|
3004 | sc->dc_stat_ch = timeout(dc_tick, sc, hz); |
---|
3005 | |
---|
3006 | return; |
---|
3007 | } |
---|
3008 | #endif |
---|
3009 | |
---|
3010 | /* |
---|
3011 | * A transmit underrun has occurred. Back off the transmit threshold, |
---|
3012 | * or switch to store and forward mode if we have to. |
---|
3013 | */ |
---|
3014 | static void dc_tx_underrun(sc) |
---|
3015 | struct dc_softc *sc; |
---|
3016 | { |
---|
3017 | u_int32_t isr; |
---|
3018 | int i; |
---|
3019 | |
---|
3020 | if (DC_IS_DAVICOM(sc)) |
---|
3021 | dc_init(sc); |
---|
3022 | |
---|
3023 | if (DC_IS_INTEL(sc)) { |
---|
3024 | /* |
---|
3025 | * The real 21143 requires that the transmitter be idle |
---|
3026 | * in order to change the transmit threshold or store |
---|
3027 | * and forward state. |
---|
3028 | */ |
---|
3029 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); |
---|
3030 | |
---|
3031 | for (i = 0; i < DC_TIMEOUT; i++) { |
---|
3032 | isr = CSR_READ_4(sc, DC_ISR); |
---|
3033 | if (isr & DC_ISR_TX_IDLE) |
---|
3034 | break; |
---|
3035 | DELAY(10); |
---|
3036 | } |
---|
3037 | if (i == DC_TIMEOUT) { |
---|
3038 | printk("dc%d: failed to force tx to idle state\n", |
---|
3039 | sc->dc_unit); |
---|
3040 | dc_init(sc); |
---|
3041 | } |
---|
3042 | } |
---|
3043 | |
---|
3044 | printk("dc%d: TX underrun -- ", sc->dc_unit); |
---|
3045 | sc->dc_txthresh += DC_TXTHRESH_INC; |
---|
3046 | if (sc->dc_txthresh > DC_TXTHRESH_MAX) { |
---|
3047 | printk("using store and forward mode\n"); |
---|
3048 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); |
---|
3049 | } else { |
---|
3050 | printk("increasing TX threshold\n"); |
---|
3051 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); |
---|
3052 | DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); |
---|
3053 | } |
---|
3054 | |
---|
3055 | if (DC_IS_INTEL(sc)) |
---|
3056 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); |
---|
3057 | |
---|
3058 | return; |
---|
3059 | } |
---|
3060 | |
---|
3061 | #ifdef DEVICE_POLLING |
---|
3062 | static poll_handler_t dc_poll; |
---|
3063 | |
---|
3064 | static void |
---|
3065 | dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) |
---|
3066 | { |
---|
3067 | struct dc_softc *sc = ifp->if_softc; |
---|
3068 | |
---|
3069 | if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ |
---|
3070 | /* Re-enable interrupts. */ |
---|
3071 | CSR_WRITE_4(sc, DC_IMR, DC_INTRS); |
---|
3072 | return; |
---|
3073 | } |
---|
3074 | sc->rxcycles = count; |
---|
3075 | dc_rxeof(sc); |
---|
3076 | dc_txeof(sc); |
---|
3077 | if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) |
---|
3078 | dc_start(ifp); |
---|
3079 | |
---|
3080 | if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ |
---|
3081 | u_int32_t status; |
---|
3082 | |
---|
3083 | status = CSR_READ_4(sc, DC_ISR); |
---|
3084 | status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| |
---|
3085 | DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| |
---|
3086 | DC_ISR_BUS_ERR); |
---|
3087 | if (!status) |
---|
3088 | return ; |
---|
3089 | /* ack what we have */ |
---|
3090 | CSR_WRITE_4(sc, DC_ISR, status); |
---|
3091 | |
---|
3092 | if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) { |
---|
3093 | u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); |
---|
3094 | ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); |
---|
3095 | |
---|
3096 | if (dc_rx_resync(sc)) |
---|
3097 | dc_rxeof(sc); |
---|
3098 | } |
---|
3099 | /* restart transmit unit if necessary */ |
---|
3100 | if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) |
---|
3101 | CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); |
---|
3102 | |
---|
3103 | if (status & DC_ISR_TX_UNDERRUN) |
---|
3104 | dc_tx_underrun(sc); |
---|
3105 | |
---|
3106 | if (status & DC_ISR_BUS_ERR) { |
---|
3107 | printk("dc_poll: dc%d bus error\n", sc->dc_unit); |
---|
3108 | dc_reset(sc); |
---|
3109 | dc_init(sc); |
---|
3110 | } |
---|
3111 | } |
---|
3112 | } |
---|
3113 | #endif /* DEVICE_POLLING */ |
---|
3114 | |
---|
3115 | static void |
---|
3116 | dc_intr(void* arg) |
---|
3117 | { |
---|
3118 | /* Need to make this work for multiple devices ... eventually */ |
---|
3119 | struct dc_softc *sc = (struct dc_softc *)arg; |
---|
3120 | |
---|
3121 | |
---|
3122 | /* Disable interrupts. */ |
---|
3123 | CSR_WRITE_4(sc, DC_IMR, 0x00000000); |
---|
3124 | |
---|
3125 | rtems_bsdnet_event_send(sc->daemontid, IRQ_EVENT); |
---|
3126 | #if 0 |
---|
3127 | if (sc->suspended) { |
---|
3128 | return; |
---|
3129 | } |
---|
3130 | |
---|
3131 | ifp = &sc->arpcom.ac_if; |
---|
3132 | |
---|
3133 | #ifdef DEVICE_POLLING |
---|
3134 | if (ifp->if_ipending & IFF_POLLING) |
---|
3135 | return; |
---|
3136 | if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ |
---|
3137 | CSR_WRITE_4(sc, DC_IMR, 0x00000000); |
---|
3138 | return; |
---|
3139 | } |
---|
3140 | #endif /* DEVICE_POLLING */ |
---|
3141 | if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) |
---|
3142 | return ; |
---|
3143 | |
---|
3144 | /* Suppress unwanted interrupts */ |
---|
3145 | if (!(ifp->if_flags & IFF_UP)) { |
---|
3146 | if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) |
---|
3147 | dc_stop(sc); |
---|
3148 | return; |
---|
3149 | } |
---|
3150 | #endif |
---|
3151 | } |
---|
3152 | |
---|
3153 | |
---|
3154 | static void |
---|
3155 | dc_daemon(void * arg) |
---|
3156 | { |
---|
3157 | struct dc_softc *sc = (struct dc_softc *)arg; |
---|
3158 | struct ifnet *ifp; |
---|
3159 | u_int32_t status; |
---|
3160 | rtems_event_set events; |
---|
3161 | |
---|
3162 | |
---|
3163 | for(;;) { |
---|
3164 | rtems_bsdnet_event_receive(RTEMS_ALL_EVENTS, \ |
---|
3165 | RTEMS_WAIT | RTEMS_EVENT_ANY, \ |
---|
3166 | RTEMS_NO_TIMEOUT, |
---|
3167 | &events); |
---|
3168 | |
---|
3169 | |
---|
3170 | ifp = &sc->arpcom.ac_if; |
---|
3171 | |
---|
3172 | while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) { |
---|
3173 | |
---|
3174 | CSR_WRITE_4(sc, DC_ISR, status); |
---|
3175 | |
---|
3176 | if (status & DC_ISR_RX_OK) { |
---|
3177 | int curpkts; |
---|
3178 | curpkts = ifp->if_ipackets; |
---|
3179 | dc_rxeof(sc); |
---|
3180 | if (curpkts == ifp->if_ipackets) { |
---|
3181 | while(dc_rx_resync(sc)) |
---|
3182 | dc_rxeof(sc); |
---|
3183 | } |
---|
3184 | } |
---|
3185 | |
---|
3186 | if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) |
---|
3187 | dc_txeof(sc); |
---|
3188 | |
---|
3189 | if (status & DC_ISR_TX_IDLE) { |
---|
3190 | dc_txeof(sc); |
---|
3191 | if (sc->dc_cdata.dc_tx_cnt) { |
---|
3192 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); |
---|
3193 | CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); |
---|
3194 | } |
---|
3195 | } |
---|
3196 | |
---|
3197 | if (status & DC_ISR_TX_UNDERRUN) |
---|
3198 | dc_tx_underrun(sc); |
---|
3199 | |
---|
3200 | if ((status & DC_ISR_RX_WATDOGTIMEO) |
---|
3201 | || (status & DC_ISR_RX_NOBUF)) { |
---|
3202 | int curpkts; |
---|
3203 | curpkts = ifp->if_ipackets; |
---|
3204 | dc_rxeof(sc); |
---|
3205 | if (curpkts == ifp->if_ipackets) { |
---|
3206 | while(dc_rx_resync(sc)) |
---|
3207 | dc_rxeof(sc); |
---|
3208 | } |
---|
3209 | } |
---|
3210 | |
---|
3211 | if (status & DC_ISR_BUS_ERR) { |
---|
3212 | dc_reset(sc); |
---|
3213 | dc_init(sc); |
---|
3214 | } |
---|
3215 | } |
---|
3216 | |
---|
3217 | /* Make atomic !!! */ |
---|
3218 | /* Re-enable interrupts. */ |
---|
3219 | CSR_WRITE_4(sc, DC_IMR, DC_INTRS); |
---|
3220 | |
---|
3221 | if (ifp->if_snd.ifq_head != NULL) |
---|
3222 | dc_start(ifp); |
---|
3223 | } |
---|
3224 | |
---|
3225 | } |
---|
3226 | |
---|
3227 | |
---|
3228 | /* |
---|
3229 | * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data |
---|
3230 | * pointers to the fragment pointers. |
---|
3231 | */ |
---|
3232 | static int dc_encap(sc, m_head, txidx) |
---|
3233 | struct dc_softc *sc; |
---|
3234 | struct mbuf *m_head; |
---|
3235 | u_int32_t *txidx; |
---|
3236 | { |
---|
3237 | struct dc_desc *f = NULL; |
---|
3238 | struct mbuf *m; |
---|
3239 | int frag, cur, cnt = 0; |
---|
3240 | |
---|
3241 | /* |
---|
3242 | * Start packing the mbufs in this chain into |
---|
3243 | * the fragment pointers. Stop when we run out |
---|
3244 | * of fragments or hit the end of the mbuf chain. |
---|
3245 | */ |
---|
3246 | m = m_head; |
---|
3247 | cur = frag = *txidx; |
---|
3248 | |
---|
3249 | for (m = m_head; m != NULL; m = m->m_next) { |
---|
3250 | if (m->m_len != 0) { |
---|
3251 | if (sc->dc_flags & DC_TX_ADMTEK_WAR) { |
---|
3252 | if (*txidx != sc->dc_cdata.dc_tx_prod && |
---|
3253 | frag == (DC_TX_LIST_CNT - 1)) |
---|
3254 | return(ENOBUFS); |
---|
3255 | } |
---|
3256 | if ((DC_TX_LIST_CNT - |
---|
3257 | (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) |
---|
3258 | return(ENOBUFS); |
---|
3259 | |
---|
3260 | f = &sc->dc_ldata->dc_tx_list[frag]; |
---|
3261 | f->dc_ctl = DC_TXCTL_TLINK | m->m_len; |
---|
3262 | if (cnt == 0) { |
---|
3263 | f->dc_status = 0; |
---|
3264 | f->dc_ctl |= DC_TXCTL_FIRSTFRAG; |
---|
3265 | } else |
---|
3266 | f->dc_status = DC_TXSTAT_OWN; |
---|
3267 | f->dc_data = vtophys(mtod(m, vm_offset_t)); |
---|
3268 | cur = frag; |
---|
3269 | DC_INC(frag, DC_TX_LIST_CNT); |
---|
3270 | cnt++; |
---|
3271 | } |
---|
3272 | } |
---|
3273 | |
---|
3274 | if (m != NULL) |
---|
3275 | return(ENOBUFS); |
---|
3276 | |
---|
3277 | sc->dc_cdata.dc_tx_cnt += cnt; |
---|
3278 | sc->dc_cdata.dc_tx_chain[cur] = m_head; |
---|
3279 | sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; |
---|
3280 | if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) |
---|
3281 | sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; |
---|
3282 | if (sc->dc_flags & DC_TX_INTR_ALWAYS) |
---|
3283 | sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; |
---|
3284 | if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) |
---|
3285 | sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; |
---|
3286 | sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; |
---|
3287 | *txidx = frag; |
---|
3288 | |
---|
3289 | return(0); |
---|
3290 | } |
---|
3291 | |
---|
3292 | /* |
---|
3293 | * Coalesce an mbuf chain into a single mbuf cluster buffer. |
---|
3294 | * Needed for some really badly behaved chips that just can't |
---|
3295 | * do scatter/gather correctly. |
---|
3296 | */ |
---|
3297 | static int dc_coal(sc, m_head) |
---|
3298 | struct dc_softc *sc; |
---|
3299 | struct mbuf **m_head; |
---|
3300 | { |
---|
3301 | struct mbuf *m_new, *m; |
---|
3302 | |
---|
3303 | m = *m_head; |
---|
3304 | MGETHDR(m_new, M_DONTWAIT, MT_DATA); |
---|
3305 | if (m_new == NULL) |
---|
3306 | return(ENOBUFS); |
---|
3307 | if (m->m_pkthdr.len > MHLEN) { |
---|
3308 | MCLGET(m_new, M_DONTWAIT); |
---|
3309 | if (!(m_new->m_flags & M_EXT)) { |
---|
3310 | m_freem(m_new); |
---|
3311 | return(ENOBUFS); |
---|
3312 | } |
---|
3313 | } |
---|
3314 | m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); |
---|
3315 | m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; |
---|
3316 | m_freem(m); |
---|
3317 | *m_head = m_new; |
---|
3318 | |
---|
3319 | return(0); |
---|
3320 | } |
---|
3321 | |
---|
3322 | /* |
---|
3323 | * Main transmit routine. To avoid having to do mbuf copies, we put pointers |
---|
3324 | * to the mbuf data regions directly in the transmit lists. We also save a |
---|
3325 | * copy of the pointers since the transmit list fragment pointers are |
---|
3326 | * physical addresses. |
---|
3327 | */ |
---|
3328 | |
---|
3329 | static void dc_start(ifp) |
---|
3330 | struct ifnet *ifp; |
---|
3331 | { |
---|
3332 | struct dc_softc *sc; |
---|
3333 | struct mbuf *m_head = NULL; |
---|
3334 | u_int32_t idx; |
---|
3335 | |
---|
3336 | sc = ifp->if_softc; |
---|
3337 | #if 0 |
---|
3338 | if (!sc->dc_link && ifp->if_snd.ifq_len < 10) |
---|
3339 | return; |
---|
3340 | #endif |
---|
3341 | if (ifp->if_flags & IFF_OACTIVE) |
---|
3342 | return; |
---|
3343 | |
---|
3344 | idx = sc->dc_cdata.dc_tx_prod; |
---|
3345 | |
---|
3346 | while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { |
---|
3347 | IF_DEQUEUE(&ifp->if_snd, m_head); |
---|
3348 | if (m_head == NULL) |
---|
3349 | break; |
---|
3350 | |
---|
3351 | if (sc->dc_flags & DC_TX_COALESCE && |
---|
3352 | m_head->m_next != NULL) { |
---|
3353 | /* only coalesce if have >1 mbufs */ |
---|
3354 | if (dc_coal(sc, &m_head)) { |
---|
3355 | IF_PREPEND(&ifp->if_snd, m_head); |
---|
3356 | ifp->if_flags |= IFF_OACTIVE; |
---|
3357 | break; |
---|
3358 | } |
---|
3359 | } |
---|
3360 | |
---|
3361 | if (dc_encap(sc, m_head, &idx)) { |
---|
3362 | IF_PREPEND(&ifp->if_snd, m_head); |
---|
3363 | ifp->if_flags |= IFF_OACTIVE; |
---|
3364 | break; |
---|
3365 | } |
---|
3366 | #if 0 |
---|
3367 | /* |
---|
3368 | * If there's a BPF listener, bounce a copy of this frame |
---|
3369 | * to him. |
---|
3370 | */ |
---|
3371 | if (ifp->if_bpf) |
---|
3372 | bpf_mtap(ifp, m_head); |
---|
3373 | #endif |
---|
3374 | if (sc->dc_flags & DC_TX_ONE) { |
---|
3375 | ifp->if_flags |= IFF_OACTIVE; |
---|
3376 | break; |
---|
3377 | } |
---|
3378 | } |
---|
3379 | |
---|
3380 | /* Transmit */ |
---|
3381 | sc->dc_cdata.dc_tx_prod = idx; |
---|
3382 | if (!(sc->dc_flags & DC_TX_POLL)) |
---|
3383 | CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); |
---|
3384 | |
---|
3385 | /* |
---|
3386 | * Set a timeout in case the chip goes out to lunch. |
---|
3387 | */ |
---|
3388 | ifp->if_timer = 5; |
---|
3389 | |
---|
3390 | return; |
---|
3391 | } |
---|
3392 | |
---|
3393 | static void dc_init(xsc) |
---|
3394 | void *xsc; |
---|
3395 | { |
---|
3396 | struct dc_softc *sc = xsc; |
---|
3397 | struct ifnet *ifp = &sc->arpcom.ac_if; |
---|
3398 | /*struct mii_data *mii;*/ |
---|
3399 | |
---|
3400 | |
---|
3401 | /*mii = device_get_softc(sc->dc_miibus);*/ |
---|
3402 | |
---|
3403 | /* |
---|
3404 | * Cancel pending I/O and free all RX/TX buffers. |
---|
3405 | */ |
---|
3406 | dc_stop(sc); |
---|
3407 | dc_reset(sc); |
---|
3408 | |
---|
3409 | /* |
---|
3410 | * Set cache alignment and burst length. |
---|
3411 | */ |
---|
3412 | if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) |
---|
3413 | CSR_WRITE_4(sc, DC_BUSCTL, 0); |
---|
3414 | else |
---|
3415 | CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); |
---|
3416 | /* |
---|
3417 | * Evenly share the bus between receive and transmit process. |
---|
3418 | */ |
---|
3419 | if (DC_IS_INTEL(sc)) |
---|
3420 | DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); |
---|
3421 | if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { |
---|
3422 | DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); |
---|
3423 | } else { |
---|
3424 | DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); |
---|
3425 | } |
---|
3426 | if (sc->dc_flags & DC_TX_POLL) |
---|
3427 | DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); |
---|
3428 | switch(sc->dc_cachesize) { |
---|
3429 | case 32: |
---|
3430 | DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); |
---|
3431 | break; |
---|
3432 | case 16: |
---|
3433 | DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); |
---|
3434 | break; |
---|
3435 | case 8: |
---|
3436 | DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); |
---|
3437 | break; |
---|
3438 | case 0: |
---|
3439 | default: |
---|
3440 | DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); |
---|
3441 | break; |
---|
3442 | } |
---|
3443 | |
---|
3444 | if (sc->dc_flags & DC_TX_STORENFWD) |
---|
3445 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); |
---|
3446 | else { |
---|
3447 | if (sc->dc_txthresh > DC_TXTHRESH_MAX) { |
---|
3448 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); |
---|
3449 | } else { |
---|
3450 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); |
---|
3451 | DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); |
---|
3452 | } |
---|
3453 | } |
---|
3454 | |
---|
3455 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); |
---|
3456 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); |
---|
3457 | |
---|
3458 | if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { |
---|
3459 | /* |
---|
3460 | * The app notes for the 98713 and 98715A say that |
---|
3461 | * in order to have the chips operate properly, a magic |
---|
3462 | * number must be written to CSR16. Macronix does not |
---|
3463 | * document the meaning of these bits so there's no way |
---|
3464 | * to know exactly what they do. The 98713 has a magic |
---|
3465 | * number all its own; the rest all use a different one. |
---|
3466 | */ |
---|
3467 | DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); |
---|
3468 | if (sc->dc_type == DC_TYPE_98713) |
---|
3469 | DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); |
---|
3470 | else |
---|
3471 | DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); |
---|
3472 | } |
---|
3473 | |
---|
3474 | DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); |
---|
3475 | DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); |
---|
3476 | |
---|
3477 | /* Init circular RX list. */ |
---|
3478 | if (dc_list_rx_init(sc) == ENOBUFS) { |
---|
3479 | printk("dc%d: initialization failed: no " |
---|
3480 | "memory for rx buffers\n", sc->dc_unit); |
---|
3481 | dc_stop(sc); |
---|
3482 | return; |
---|
3483 | } |
---|
3484 | |
---|
3485 | /* |
---|
3486 | * Init tx descriptors. |
---|
3487 | */ |
---|
3488 | dc_list_tx_init(sc); |
---|
3489 | |
---|
3490 | /* |
---|
3491 | * Load the address of the RX list. |
---|
3492 | */ |
---|
3493 | CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); |
---|
3494 | CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); |
---|
3495 | |
---|
3496 | /* |
---|
3497 | * Enable interrupts. |
---|
3498 | */ |
---|
3499 | #ifdef DEVICE_POLLING |
---|
3500 | /* |
---|
3501 | * ... but only if we are not polling, and make sure they are off in |
---|
3502 | * the case of polling. Some cards (e.g. fxp) turn interrupts on |
---|
3503 | * after a reset. |
---|
3504 | */ |
---|
3505 | if (ifp->if_ipending & IFF_POLLING) |
---|
3506 | CSR_WRITE_4(sc, DC_IMR, 0x00000000); |
---|
3507 | else |
---|
3508 | #endif |
---|
3509 | /* Enable interrupts */ |
---|
3510 | CSR_WRITE_4(sc, DC_IMR, DC_INTRS); |
---|
3511 | CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); |
---|
3512 | |
---|
3513 | /* Enable transmitter. */ |
---|
3514 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); |
---|
3515 | |
---|
3516 | /* |
---|
3517 | * If this is an Intel 21143 and we're not using the |
---|
3518 | * MII port, program the LED control pins so we get |
---|
3519 | * link and activity indications. |
---|
3520 | */ |
---|
3521 | if (sc->dc_flags & DC_TULIP_LEDS) { |
---|
3522 | CSR_WRITE_4(sc, DC_WATCHDOG, |
---|
3523 | DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); |
---|
3524 | CSR_WRITE_4(sc, DC_WATCHDOG, 0); |
---|
3525 | } |
---|
3526 | |
---|
3527 | /* |
---|
3528 | * Load the RX/multicast filter. We do this sort of late |
---|
3529 | * because the filter programming scheme on the 21143 and |
---|
3530 | * some clones requires DMAing a setup frame via the TX |
---|
3531 | * engine, and we need the transmitter enabled for that. |
---|
3532 | */ |
---|
3533 | dc_setfilt(sc); |
---|
3534 | |
---|
3535 | /* Enable receiver. */ |
---|
3536 | DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); |
---|
3537 | CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); |
---|
3538 | |
---|
3539 | /*mii_mediachg(mii);*/ |
---|
3540 | dc_setcfg(sc, sc->dc_if_media); |
---|
3541 | |
---|
3542 | ifp->if_flags |= IFF_RUNNING; |
---|
3543 | ifp->if_flags &= ~IFF_OACTIVE; |
---|
3544 | |
---|
3545 | |
---|
3546 | #if 0 |
---|
3547 | |
---|
3548 | /* Don't start the ticker if this is a homePNA link. */ |
---|
3549 | if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_homePNA) |
---|
3550 | sc->dc_link = 1; |
---|
3551 | else { |
---|
3552 | if (sc->dc_flags & DC_21143_NWAY) |
---|
3553 | sc->dc_stat_ch = timeout(dc_tick, sc, hz/10); |
---|
3554 | else |
---|
3555 | sc->dc_stat_ch = timeout(dc_tick, sc, hz); |
---|
3556 | } |
---|
3557 | |
---|
3558 | #ifdef SRM_MEDIA |
---|
3559 | if(sc->dc_srm_media) { |
---|
3560 | struct ifreq ifr; |
---|
3561 | |
---|
3562 | ifr.ifr_media = sc->dc_srm_media; |
---|
3563 | ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); |
---|
3564 | sc->dc_srm_media = 0; |
---|
3565 | } |
---|
3566 | #endif |
---|
3567 | #endif /* end if (0) */ |
---|
3568 | return; |
---|
3569 | } |
---|
3570 | |
---|
3571 | |
---|
3572 | #if 0 |
---|
3573 | /* |
---|
3574 | * Set media options. |
---|
3575 | */ |
---|
3576 | static int dc_ifmedia_upd(ifp) |
---|
3577 | struct ifnet *ifp; |
---|
3578 | { |
---|
3579 | struct dc_softc *sc; |
---|
3580 | struct mii_data *mii; |
---|
3581 | struct ifmedia *ifm; |
---|
3582 | |
---|
3583 | sc = ifp->if_softc; |
---|
3584 | mii = device_get_softc(sc->dc_miibus); |
---|
3585 | mii_mediachg(mii); |
---|
3586 | ifm = &mii->mii_media; |
---|
3587 | |
---|
3588 | if (DC_IS_DAVICOM(sc) && |
---|
3589 | IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) |
---|
3590 | dc_setcfg(sc, ifm->ifm_media); |
---|
3591 | else |
---|
3592 | sc->dc_link = 0; |
---|
3593 | |
---|
3594 | return(0); |
---|
3595 | } |
---|
3596 | |
---|
3597 | /* |
---|
3598 | * Report current media status. |
---|
3599 | */ |
---|
3600 | static void dc_ifmedia_sts(ifp, ifmr) |
---|
3601 | struct ifnet *ifp; |
---|
3602 | struct ifmediareq *ifmr; |
---|
3603 | { |
---|
3604 | struct dc_softc *sc; |
---|
3605 | struct mii_data *mii; |
---|
3606 | struct ifmedia *ifm; |
---|
3607 | |
---|
3608 | sc = ifp->if_softc; |
---|
3609 | mii = device_get_softc(sc->dc_miibus); |
---|
3610 | mii_pollstat(mii); |
---|
3611 | ifm = &mii->mii_media; |
---|
3612 | if (DC_IS_DAVICOM(sc)) { |
---|
3613 | if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { |
---|
3614 | ifmr->ifm_active = ifm->ifm_media; |
---|
3615 | ifmr->ifm_status = 0; |
---|
3616 | return; |
---|
3617 | } |
---|
3618 | } |
---|
3619 | ifmr->ifm_active = mii->mii_media_active; |
---|
3620 | ifmr->ifm_status = mii->mii_media_status; |
---|
3621 | |
---|
3622 | return; |
---|
3623 | } |
---|
3624 | #endif |
---|
3625 | |
---|
3626 | |
---|
3627 | static int dc_ioctl(ifp, command, data) |
---|
3628 | struct ifnet *ifp; |
---|
3629 | ioctl_command_t command; |
---|
3630 | caddr_t data; |
---|
3631 | { |
---|
3632 | struct dc_softc *sc = ifp->if_softc; |
---|
3633 | /*struct ifreq *ifr = (struct ifreq *) data; |
---|
3634 | struct mii_data *mii;*/ |
---|
3635 | int error = 0; |
---|
3636 | |
---|
3637 | |
---|
3638 | switch(command) { |
---|
3639 | case SIOCSIFADDR: |
---|
3640 | case SIOCGIFADDR: |
---|
3641 | case SIOCSIFMTU: |
---|
3642 | error = ether_ioctl(ifp, command, data); |
---|
3643 | break; |
---|
3644 | case SIOCSIFFLAGS: |
---|
3645 | if (ifp->if_flags & IFF_UP) { |
---|
3646 | int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & |
---|
3647 | (IFF_PROMISC | IFF_ALLMULTI); |
---|
3648 | if (ifp->if_flags & IFF_RUNNING) { |
---|
3649 | if (need_setfilt) |
---|
3650 | dc_setfilt(sc); |
---|
3651 | } else { |
---|
3652 | sc->dc_txthresh = 0; |
---|
3653 | dc_init(sc); |
---|
3654 | } |
---|
3655 | } else { |
---|
3656 | if (ifp->if_flags & IFF_RUNNING) |
---|
3657 | dc_stop(sc); |
---|
3658 | } |
---|
3659 | sc->dc_if_flags = ifp->if_flags; |
---|
3660 | error = 0; |
---|
3661 | break; |
---|
3662 | case SIOCADDMULTI: |
---|
3663 | case SIOCDELMULTI: |
---|
3664 | dc_setfilt(sc); |
---|
3665 | error = 0; |
---|
3666 | break; |
---|
3667 | #if 0 |
---|
3668 | case SIOCGIFMEDIA: |
---|
3669 | case SIOCSIFMEDIA: |
---|
3670 | mii = device_get_softc(sc->dc_miibus); |
---|
3671 | error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); |
---|
3672 | #ifdef SRM_MEDIA |
---|
3673 | if (sc->dc_srm_media) |
---|
3674 | sc->dc_srm_media = 0; |
---|
3675 | #endif |
---|
3676 | break; |
---|
3677 | #endif |
---|
3678 | default: |
---|
3679 | error = EINVAL; |
---|
3680 | break; |
---|
3681 | } |
---|
3682 | |
---|
3683 | |
---|
3684 | return(error); |
---|
3685 | } |
---|
3686 | |
---|
3687 | static void dc_watchdog(ifp) |
---|
3688 | struct ifnet *ifp; |
---|
3689 | { |
---|
3690 | struct dc_softc *sc; |
---|
3691 | |
---|
3692 | sc = ifp->if_softc; |
---|
3693 | |
---|
3694 | ifp->if_oerrors++; |
---|
3695 | printk("dc%d: watchdog timeout\n", sc->dc_unit); |
---|
3696 | |
---|
3697 | dc_stop(sc); |
---|
3698 | dc_reset(sc); |
---|
3699 | dc_init(sc); |
---|
3700 | |
---|
3701 | if (ifp->if_snd.ifq_head != NULL) |
---|
3702 | dc_start(ifp); |
---|
3703 | |
---|
3704 | return; |
---|
3705 | } |
---|
3706 | |
---|
3707 | /* |
---|
3708 | * Stop the adapter and free any mbufs allocated to the |
---|
3709 | * RX and TX lists. |
---|
3710 | */ |
---|
3711 | static void dc_stop(sc) |
---|
3712 | struct dc_softc *sc; |
---|
3713 | { |
---|
3714 | register int i; |
---|
3715 | struct ifnet *ifp; |
---|
3716 | |
---|
3717 | ifp = &sc->arpcom.ac_if; |
---|
3718 | ifp->if_timer = 0; |
---|
3719 | |
---|
3720 | /*untimeout(dc_tick, sc, sc->dc_stat_ch);*/ |
---|
3721 | |
---|
3722 | ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); |
---|
3723 | #ifdef DEVICE_POLLING |
---|
3724 | ether_poll_deregister(ifp); |
---|
3725 | #endif |
---|
3726 | |
---|
3727 | DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); |
---|
3728 | CSR_WRITE_4(sc, DC_IMR, 0x00000000); |
---|
3729 | CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); |
---|
3730 | CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); |
---|
3731 | sc->dc_link = 0; |
---|
3732 | |
---|
3733 | /* |
---|
3734 | * Free data in the RX lists. |
---|
3735 | */ |
---|
3736 | for (i = 0; i < DC_RX_LIST_CNT; i++) { |
---|
3737 | if (sc->dc_cdata.dc_rx_chain[i] != NULL) { |
---|
3738 | m_freem(sc->dc_cdata.dc_rx_chain[i]); |
---|
3739 | sc->dc_cdata.dc_rx_chain[i] = NULL; |
---|
3740 | } |
---|
3741 | } |
---|
3742 | bzero((char *)&sc->dc_ldata->dc_rx_list, |
---|
3743 | sizeof(sc->dc_ldata->dc_rx_list)); |
---|
3744 | |
---|
3745 | /* |
---|
3746 | * Free the TX list buffers. |
---|
3747 | */ |
---|
3748 | for (i = 0; i < DC_TX_LIST_CNT; i++) { |
---|
3749 | if (sc->dc_cdata.dc_tx_chain[i] != NULL) { |
---|
3750 | if (sc->dc_ldata->dc_tx_list[i].dc_ctl & |
---|
3751 | DC_TXCTL_SETUP) { |
---|
3752 | sc->dc_cdata.dc_tx_chain[i] = NULL; |
---|
3753 | continue; |
---|
3754 | } |
---|
3755 | m_freem(sc->dc_cdata.dc_tx_chain[i]); |
---|
3756 | sc->dc_cdata.dc_tx_chain[i] = NULL; |
---|
3757 | } |
---|
3758 | } |
---|
3759 | |
---|
3760 | bzero((char *)&sc->dc_ldata->dc_tx_list, |
---|
3761 | sizeof(sc->dc_ldata->dc_tx_list)); |
---|
3762 | |
---|
3763 | return; |
---|
3764 | } |
---|
3765 | |
---|
3766 | |
---|
3767 | #if 0 |
---|
3768 | /* |
---|
3769 | * Stop all chip I/O so that the kernel's probe routines don't |
---|
3770 | * get confused by errant DMAs when rebooting. |
---|
3771 | */ |
---|
3772 | static void dc_shutdown(dev) |
---|
3773 | device_t dev; |
---|
3774 | { |
---|
3775 | struct dc_softc *sc; |
---|
3776 | |
---|
3777 | sc = device_get_softc(dev); |
---|
3778 | |
---|
3779 | dc_stop(sc); |
---|
3780 | |
---|
3781 | return; |
---|
3782 | } |
---|
3783 | |
---|
3784 | /* |
---|
3785 | * Device suspend routine. Stop the interface and save some PCI |
---|
3786 | * settings in case the BIOS doesn't restore them properly on |
---|
3787 | * resume. |
---|
3788 | */ |
---|
3789 | static int dc_suspend(dev) |
---|
3790 | device_t dev; |
---|
3791 | { |
---|
3792 | register int i; |
---|
3793 | int s; |
---|
3794 | struct dc_softc *sc; |
---|
3795 | |
---|
3796 | |
---|
3797 | sc = device_get_softc(dev); |
---|
3798 | |
---|
3799 | dc_stop(sc); |
---|
3800 | |
---|
3801 | for (i = 0; i < 5; i++) |
---|
3802 | sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); |
---|
3803 | sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); |
---|
3804 | sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); |
---|
3805 | sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); |
---|
3806 | sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); |
---|
3807 | |
---|
3808 | sc->suspended = 1; |
---|
3809 | |
---|
3810 | return (0); |
---|
3811 | } |
---|
3812 | |
---|
3813 | /* |
---|
3814 | * Device resume routine. Restore some PCI settings in case the BIOS |
---|
3815 | * doesn't, re-enable busmastering, and restart the interface if |
---|
3816 | * appropriate. |
---|
3817 | */ |
---|
3818 | static int dc_resume(dev) |
---|
3819 | device_t dev; |
---|
3820 | { |
---|
3821 | register int i; |
---|
3822 | int s; |
---|
3823 | struct dc_softc *sc; |
---|
3824 | struct ifnet *ifp; |
---|
3825 | |
---|
3826 | |
---|
3827 | sc = device_get_softc(dev); |
---|
3828 | ifp = &sc->arpcom.ac_if; |
---|
3829 | |
---|
3830 | dc_acpi(dev); |
---|
3831 | |
---|
3832 | /* better way to do this? */ |
---|
3833 | for (i = 0; i < 5; i++) |
---|
3834 | pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); |
---|
3835 | pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); |
---|
3836 | pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); |
---|
3837 | pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); |
---|
3838 | pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); |
---|
3839 | |
---|
3840 | /* reenable busmastering */ |
---|
3841 | pci_enable_busmaster(dev); |
---|
3842 | pci_enable_io(dev, DC_RES); |
---|
3843 | |
---|
3844 | /* reinitialize interface if necessary */ |
---|
3845 | if (ifp->if_flags & IFF_UP) |
---|
3846 | dc_init(sc); |
---|
3847 | |
---|
3848 | sc->suspended = 0; |
---|
3849 | |
---|
3850 | return (0); |
---|
3851 | } |
---|
3852 | #endif |
---|
3853 | |
---|
3854 | #endif /* end if supported */ |
---|