Context Navigation

source: rtems/c/src/libchip/network/if_dc.c @ 07e76b9b

4.104.114.84.95

Last change on this file since 07e76b9b was 24af51c5, checked in by Joel Sherrill <joel.sherrill@…>, on 09/14/07 at 14:58:23

2007-09-14 Daron Chabot <djc915@…>

libchip/network/if_dc.c: Changed type of ISR argument to void* from rtems_interrupt_vector, to permit passing arbitrary arguments to the ISR. Clean up of variables to silence compiler warnings.

Property mode set to 100644

File size: 93.0 KB

Line
1	/* $Id$
2	*
3	* Ported from FreeBSD --> RTEMS, december 03.
4	* Daron Chabot <daron@nucleus.usask.ca>
5	* -- only tested with i386 bsp.
6	* -- supports one card (until the PCI & IRQ APIs get sorted out ;-))
7	*
8	*
9	* Copyright (c) 1997, 1998, 1999
10	* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
11	*
12	* Redistribution and use in source and binary forms, with or without
13	* modification, are permitted provided that the following conditions
14	* are met:
15	* 1. Redistributions of source code must retain the above copyright
16	* notice, this list of conditions and the following disclaimer.
17	* 2. Redistributions in binary form must reproduce the above copyright
18	* notice, this list of conditions and the following disclaimer in the
19	* documentation and/or other materials provided with the distribution.
20	* 3. All advertising materials mentioning features or use of this software
21	* must display the following acknowledgement:
22	* This product includes software developed by Bill Paul.
23	* 4. Neither the name of the author nor the names of any co-contributors
24	* may be used to endorse or promote products derived from this software
25	* without specific prior written permission.
26	*
27	* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
28	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30	* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
31	* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
37	* THE POSSIBILITY OF SUCH DAMAGE.
38	*
39	* $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.41 2003/03/05 18:42:33 njl Exp $
40	*/
41
42	/*
43	* DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
44	* series chips and several workalikes including the following:
45	*
46	* Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
47	* Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
48	* Lite-On 82c168/82c169 PNIC (www.litecom.com)
49	* ASIX Electronics AX88140A (www.asix.com.tw)
50	* ASIX Electronics AX88141 (www.asix.com.tw)
51	* ADMtek AL981 (www.admtek.com.tw)
52	* ADMtek AN985 (www.admtek.com.tw)
53	* Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
54	* Accton EN1217 (www.accton.com)
55	* Conexant LANfinity (www.conexant.com)
56	*
57	* Datasheets for the 21143 are available at developer.intel.com.
58	* Datasheets for the clone parts can be found at their respective sites.
59	* (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
60	* The PNIC II is essentially a Macronix 98715A chip; the only difference
61	* worth noting is that its multicast hash table is only 128 bits wide
62	* instead of 512.
63	*
64	* Written by Bill Paul <wpaul@ee.columbia.edu>
65	* Electrical Engineering Department
66	* Columbia University, New York City
67	*/
68
69	/*
70	* The Intel 21143 is the successor to the DEC 21140. It is basically
71	* the same as the 21140 but with a few new features. The 21143 supports
72	* three kinds of media attachments:
73	*
74	* o MII port, for 10Mbps and 100Mbps support and NWAY
75	* autonegotiation provided by an external PHY.
76	* o SYM port, for symbol mode 100Mbps support.
77	* o 10baseT port.
78	* o AUI/BNC port.
79	*
80	* The 100Mbps SYM port and 10baseT port can be used together in
81	* combination with the internal NWAY support to create a 10/100
82	* autosensing configuration.
83	*
84	* Note that not all tulip workalikes are handled in this driver: we only
85	* deal with those which are relatively well behaved. The Winbond is
86	* handled separately due to its different register offsets and the
87	* special handling needed for its various bugs. The PNIC is handled
88	* here, but I'm not thrilled about it.
89	*
90	* All of the workalike chips use some form of MII transceiver support
91	* with the exception of the Macronix chips, which also have a SYM port.
92	* The ASIX AX88140A is also documented to have a SYM port, but all
93	* the cards I've seen use an MII transceiver, probably because the
94	* AX88140A doesn't support internal NWAY.
95	*/
96
97	/*
98	* This driver only supports architectures with the new style
99	* exception processing. The following checks try to keep this
100	* from being compiled on systems which can't support this driver.
101	*/
102
103	#if defined(DRIVER_SUPPORTED)
104	#undef DRIVER_SUPPORTED
105	#endif
106
107	#if defined(__i386__)
108	#define DRIVER_SUPPORTED
109	#endif
110
111	#if defined(__PPC__) && (defined(mpc604) \|\| defined(mpc750) \|\| defined(mpc603e))
112	#define DRIVER_SUPPORTED
113	#warning The if_dc driver is untested on the PPC platform !!!
114	#endif
115
116
117	#if defined(DRIVER_SUPPORTED) /* this covers the file "globally"... */
118	#include <bsp.h>
119	#include <rtems.h>
120	#include <rtems/pci.h>
121
122	#include <rtems/error.h>
123	#include <errno.h>
124	#include <rtems/rtems_bsdnet.h>
125
126	#include <net/if_types.h>
127
128	#include <sys/param.h>
129	#include <sys/sockio.h>
130	#include <sys/socket.h>
131	#include <sys/mbuf.h>
132	#include <net/if.h>
133	#include <netinet/in.h>
134	#include <netinet/if_ether.h>
135	#include <sys/malloc.h>
136	#include <sys/systm.h>
137	#include <bsp.h>
138
139	/* moved to cpukit/include/rtems in CVS current ! */
140	/#include "if_media.h" /
141	/#include "pci.h" /
142	#include <net/if_media.h>
143	#include <rtems/pci.h>
144	/*
145	#include <sys/kernel.h>
146	#include <sys/sysctl.h>
147	*/
148
149	#include <vm/vm.h> /* for vtophys */
150
151
152	#if defined(__i386__)
153	#define vtophys(p) (u_int32_t)(p)
154	#else
155	#define vtophys(p) vtophys(p)
156	#endif
157
158	/*
159	#include <net/if_arp.h>
160	#include <net/if_vlan_var.h>
161	#include <net/bpf.h>
162	*/
163
164	#if 0
165	#include <vm/pmap.h> /* for vtophys */
166	#include <machine/clock.h> /* for DELAY */
167	#include <machine/bus_pio.h>
168	#include <machine/bus_memio.h>
169	#include <machine/bus.h>
170	#include <machine/resource.h>
171	#include <sys/bus.h>
172	#include <sys/rman.h>
173	#endif
174	#include <dev/mii/mii.h>
175	#if 0
176	#include <dev/mii/miivar.h>
177
178	#include <pci/pcireg.h>
179	#include <pci/pcivar.h>
180	#endif
181
182	/* NOTE: use mem space mapping (for now ...)
183	#define DC_USEIOSPACE
184	*/
185
186	#ifdef __alpha__
187	#define SRM_MEDIA
188	#endif
189
190	#include <bsp/irq.h>
191
192
193	#include "if_dcreg.h"
194
195
196	#define DRIVER_PREFIX "tl"
197	#define NDRIVER 1
198	#define IRQ_EVENT RTEMS_EVENT_13 /* Ha ... */
199	static struct dc_softc dc_softc_devs[NDRIVER];
200
201	#define UNUSED
202
203	#if 0
204	/* "controller miibus0" required. See GENERIC if you get errors here. */
205	#include "miibus_if.h"
206
207
208
209	#ifndef lint
210	static const char rcsid[] =
211	"$FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.41 2003/03/05 18:42:33 njl Exp $";
212	#endif
213
214	#endif
215
216
217	/*
218	* Various supported device vendors/types and their names.
219	* NOTE:
220	* -----
221	* Only the "ADMtek AN985" has been tested under RTEMS !!!
222	*/
223	static struct dc_type dc_devs[] = {
224	{ DC_VENDORID_DEC, DC_DEVICEID_21143,
225	"Intel 21143 10/100BaseTX", 0 },
226	{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009,
227	"Davicom DM9009 10/100BaseTX", 0 },
228	{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100,
229	"Davicom DM9100 10/100BaseTX", 0 },
230	{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
231	"Davicom DM9102 10/100BaseTX", 0 },
232	{ DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
233	"Davicom DM9102A 10/100BaseTX", 0 },
234	{ DC_VENDORID_ADMTEK, DC_DEVICEID_AL981,
235	"ADMtek AL981 10/100BaseTX", 0 },
236	{ DC_VENDORID_ADMTEK, DC_DEVICEID_AN985,
237	"ADMtek AN985 10/100BaseTX", 0 },
238	{ DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
239	"ASIX AX88140A 10/100BaseTX", 0 },
240	{ DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
241	"ASIX AX88141 10/100BaseTX", 0 },
242	{ DC_VENDORID_MX, DC_DEVICEID_98713,
243	"Macronix 98713 10/100BaseTX", 0 },
244	{ DC_VENDORID_MX, DC_DEVICEID_98713,
245	"Macronix 98713A 10/100BaseTX", 0 },
246	{ DC_VENDORID_CP, DC_DEVICEID_98713_CP,
247	"Compex RL100-TX 10/100BaseTX", 0 },
248	{ DC_VENDORID_CP, DC_DEVICEID_98713_CP,
249	"Compex RL100-TX 10/100BaseTX", 0 },
250	{ DC_VENDORID_MX, DC_DEVICEID_987x5,
251	"Macronix 98715/98715A 10/100BaseTX", 0 },
252	{ DC_VENDORID_MX, DC_DEVICEID_987x5,
253	"Macronix 98715AEC-C 10/100BaseTX", 0 },
254	{ DC_VENDORID_MX, DC_DEVICEID_987x5,
255	"Macronix 98725 10/100BaseTX", 0 },
256	{ DC_VENDORID_MX, DC_DEVICEID_98727,
257	"Macronix 98727/98732 10/100BaseTX", 0 },
258	{ DC_VENDORID_LO, DC_DEVICEID_82C115,
259	"LC82C115 PNIC II 10/100BaseTX", 0 },
260	{ DC_VENDORID_LO, DC_DEVICEID_82C168,
261	"82c168 PNIC 10/100BaseTX", 0 },
262	{ DC_VENDORID_LO, DC_DEVICEID_82C168,
263	"82c169 PNIC 10/100BaseTX", 0 },
264	{ DC_VENDORID_ACCTON, DC_DEVICEID_EN1217,
265	"Accton EN1217 10/100BaseTX", 0 },
266	{ DC_VENDORID_ACCTON, DC_DEVICEID_EN2242,
267	"Accton EN2242 MiniPCI 10/100BaseTX", 0 },
268	{ DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112,
269	"Conexant LANfinity MiniPCI 10/100BaseTX", 0 },
270	{ 0, 0, NULL, 0 }
271	};
272
273	#if 0
274	static int dc_probe __P((device_t));
275	static int dc_attach __P((device_t));
276	static int dc_detach __P((device_t));
277	static int dc_suspend __P((device_t));
278	static int dc_resume __P((device_t));
279	static void dc_shutdown __P((device_t));
280	static void dc_acpi __P((device_t));
281	#endif
282
283	static struct dc_type *dc_devtype(int);
284	static int dc_newbuf(struct dc_softc , int, struct mbuf );
285	static int dc_encap(struct dc_softc , struct mbuf ,
286	u_int32_t *);
287	static int dc_coal(struct dc_softc , struct mbuf *);
288	static void dc_pnic_rx_bug_war(struct dc_softc *, int);
289	static int dc_rx_resync(struct dc_softc *);
290	static void dc_rxeof(struct dc_softc *);
291	static void dc_txeof(struct dc_softc *);
292	/static void dc_tick((void ));*/
293	static void dc_tx_underrun(struct dc_softc *);
294	static void dc_intr(void *);
295	static void dc_daemon(void *);
296	static void dc_start(struct ifnet *);
297	static int dc_ioctl(struct ifnet *, ioctl_command_t, caddr_t);
298	static void dc_init(void *);
299	static void dc_stop(struct dc_softc *);
300	static void dc_watchdog(struct ifnet *);
301	#if 0
302	static int dc_ifmedia_upd __P((struct ifnet *));
303	static void dc_ifmedia_sts __P((struct ifnet , struct ifmediareq ));
304	#endif
305
306	static void dc_delay(struct dc_softc *);
307	static void dc_eeprom_idle(struct dc_softc *);
308	static void dc_eeprom_putbyte(struct dc_softc *, int);
309	static void dc_eeprom_getword(struct dc_softc , int, u_int16_t );
310	static void dc_eeprom_getword_pnic(struct dc_softc , int, u_int16_t );
311	static void dc_eeprom_width(struct dc_softc *);
312	static void dc_read_eeprom(struct dc_softc *, caddr_t, int,int, int);
313
314	#if 0
315	static void dc_mii_writebit __P((struct dc_softc *, int));
316	static int dc_mii_readbit __P((struct dc_softc *));
317	static void dc_mii_sync __P((struct dc_softc *));
318	static void dc_mii_send __P((struct dc_softc *, u_int32_t, int));
319	static int dc_mii_readreg __P((struct dc_softc , struct dc_mii_frame ));
320	static int dc_mii_writereg __P((struct dc_softc , struct dc_mii_frame ));
321	static int dc_miibus_readreg __P((device_t, int, int));
322	static int dc_miibus_writereg __P((device_t, int, int, int));
323	static void dc_miibus_statchg __P((device_t));
324	static void dc_miibus_mediainit __P((device_t));
325	#endif
326
327	static void dc_setcfg(struct dc_softc *, int);
328	static u_int32_t dc_crc_le(struct dc_softc *, caddr_t);
329	#ifndef UNUSED
330	static u_int32_t dc_crc_be(caddr_t);
331	#endif
332	static void dc_setfilt_21143(struct dc_softc *);
333	static void dc_setfilt_asix(struct dc_softc *);
334	static void dc_setfilt_admtek(struct dc_softc *);
335	static void dc_setfilt(struct dc_softc *);
336	static void dc_reset(struct dc_softc *);
337	static int dc_list_rx_init(struct dc_softc *);
338	static int dc_list_tx_init(struct dc_softc *);
339	static void dc_read_srom(struct dc_softc *, int);
340	static void dc_parse_21143_srom(struct dc_softc *);
341	static void dc_apply_fixup(struct dc_softc *, int);
342
343	#if 0
344	static void dc_decode_leaf_sia __P((struct dc_softc *,
345	struct dc_eblock_sia *));
346	static void dc_decode_leaf_mii __P((struct dc_softc *,
347	struct dc_eblock_mii *));
348	static void dc_decode_leaf_sym __P((struct dc_softc *,
349	struct dc_eblock_sym *));
350	#endif
351
352
353	#ifdef DC_USEIOSPACE
354	#define DC_RES SYS_RES_IOPORT
355	#define DC_RID DC_PCI_CFBIO
356	#else
357	#define DC_RES SYS_RES_MEMORY
358	#define DC_RID DC_PCI_CFBMA
359	#endif
360
361	#if 0
362	static device_method_t dc_methods[] = {
363	/* Device interface */
364	DEVMETHOD(device_probe, dc_probe),
365	DEVMETHOD(device_attach, dc_attach),
366	DEVMETHOD(device_detach, dc_detach),
367	DEVMETHOD(device_suspend, dc_suspend),
368	DEVMETHOD(device_resume, dc_resume),
369	DEVMETHOD(device_shutdown, dc_shutdown),
370
371	/* bus interface */
372	DEVMETHOD(bus_print_child, bus_generic_print_child),
373	DEVMETHOD(bus_driver_added, bus_generic_driver_added),
374
375	/* MII interface */
376	DEVMETHOD(miibus_readreg, dc_miibus_readreg),
377	DEVMETHOD(miibus_writereg, dc_miibus_writereg),
378	DEVMETHOD(miibus_statchg, dc_miibus_statchg),
379	DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
380
381	{ 0, 0 }
382	};
383
384	static driver_t dc_driver = {
385	"dc",
386	dc_methods,
387	sizeof(struct dc_softc)
388	};
389
390	static devclass_t dc_devclass;
391	#endif
392
393
394	#ifdef __i386__
395	static int dc_quick=1;
396	#if 0
397	SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW,
398	&dc_quick,0,"do not mdevget in dc driver");
399	#endif
400	#endif
401
402	#if 0
403	DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0);
404	DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
405	#endif
406
407
408	#define DC_SETBIT(sc, reg, x) \
409	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) \| (x))
410
411	#define DC_CLRBIT(sc, reg, x) \
412	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
413
414	#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
415	#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
416
417
418	/* XXX Fixme: rtems_bsp_delay( ) for the pc386 BSP (at least)
419	* needs work... see pc386/include/bsp.h.
420	* I have "a" solution, utilizing the 2nd i8254 timer,
421	* if anyone is interested (first timer is used for clock_tick ISR)...
422	*/
423	#ifdef __i386__
424	extern void Wait_X_ms( unsigned int );
425	#define DELAY(n) Wait_X_ms( (unsigned int)((n)/100) )
426	#else
427	#define DELAY(n) rtems_bsp_delay(n)
428	#endif
429
430
431	static void dc_delay(sc)
432	struct dc_softc *sc;
433	{
434	int idx;
435
436	for (idx = (300 / 33) + 1; idx > 0; idx--)
437	CSR_READ_4(sc, DC_BUSCTL);
438	}
439
440	static void dc_eeprom_width(sc)
441	struct dc_softc *sc;
442	{
443	int i;
444
445	/* Force EEPROM to idle state. */
446	dc_eeprom_idle(sc);
447
448	/* Enter EEPROM access mode. */
449	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
450	dc_delay(sc);
451	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
452	dc_delay(sc);
453	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
454	dc_delay(sc);
455	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
456	dc_delay(sc);
457
458	for (i = 3; i--;) {
459	if (6 & (1 << i))
460	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
461	else
462	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
463	dc_delay(sc);
464	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
465	dc_delay(sc);
466	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
467	dc_delay(sc);
468	}
469
470	for (i = 1; i <= 12; i++) {
471	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
472	dc_delay(sc);
473	if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
474	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
475	dc_delay(sc);
476	break;
477	}
478	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
479	dc_delay(sc);
480	}
481
482	/* Turn off EEPROM access mode. */
483	dc_eeprom_idle(sc);
484
485	if (i < 4 \|\| i > 12)
486	sc->dc_romwidth = 6;
487	else
488	sc->dc_romwidth = i;
489
490	/* Enter EEPROM access mode. */
491	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
492	dc_delay(sc);
493	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
494	dc_delay(sc);
495	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
496	dc_delay(sc);
497	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
498	dc_delay(sc);
499
500	/* Turn off EEPROM access mode. */
501	dc_eeprom_idle(sc);
502	}
503
504	static void dc_eeprom_idle(sc)
505	struct dc_softc *sc;
506	{
507	register int i;
508
509	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
510	dc_delay(sc);
511	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
512	dc_delay(sc);
513	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
514	dc_delay(sc);
515	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
516	dc_delay(sc);
517
518	for (i = 0; i < 25; i++) {
519	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
520	dc_delay(sc);
521	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
522	dc_delay(sc);
523	}
524
525	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
526	dc_delay(sc);
527	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
528	dc_delay(sc);
529	CSR_WRITE_4(sc, DC_SIO, 0x00000000);
530
531	return;
532	}
533
534	/*
535	* Send a read command and address to the EEPROM, check for ACK.
536	*/
537	static void dc_eeprom_putbyte(sc, addr)
538	struct dc_softc *sc;
539	int addr;
540	{
541	register int d, i;
542
543	d = DC_EECMD_READ >> 6;
544	for (i = 3; i--; ) {
545	if (d & (1 << i))
546	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
547	else
548	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
549	dc_delay(sc);
550	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
551	dc_delay(sc);
552	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
553	dc_delay(sc);
554	}
555
556	/*
557	* Feed in each bit and strobe the clock.
558	*/
559	for (i = sc->dc_romwidth; i--;) {
560	if (addr & (1 << i)) {
561	SIO_SET(DC_SIO_EE_DATAIN);
562	} else {
563	SIO_CLR(DC_SIO_EE_DATAIN);
564	}
565	dc_delay(sc);
566	SIO_SET(DC_SIO_EE_CLK);
567	dc_delay(sc);
568	SIO_CLR(DC_SIO_EE_CLK);
569	dc_delay(sc);
570	}
571
572	return;
573	}
574
575	/*
576	* Read a word of data stored in the EEPROM at address 'addr.'
577	* The PNIC 82c168/82c169 has its own non-standard way to read
578	* the EEPROM.
579	*/
580	static void dc_eeprom_getword_pnic(sc, addr, dest)
581	struct dc_softc *sc;
582	int addr;
583	u_int16_t *dest;
584	{
585	register int i;
586	u_int32_t r;
587
588	CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ\|addr);
589
590	for (i = 0; i < DC_TIMEOUT; i++) {
591	DELAY(1);
592	r = CSR_READ_4(sc, DC_SIO);
593	if (!(r & DC_PN_SIOCTL_BUSY)) {
594	*dest = (u_int16_t)(r & 0xFFFF);
595	return;
596	}
597	}
598
599	return;
600	}
601
602	/*
603	* Read a word of data stored in the EEPROM at address 'addr.'
604	*/
605	static void dc_eeprom_getword(sc, addr, dest)
606	struct dc_softc *sc;
607	int addr;
608	u_int16_t *dest;
609	{
610	register int i;
611	u_int16_t word = 0;
612
613	/* Force EEPROM to idle state. */
614	dc_eeprom_idle(sc);
615
616	/* Enter EEPROM access mode. */
617	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
618	dc_delay(sc);
619	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
620	dc_delay(sc);
621	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
622	dc_delay(sc);
623	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
624	dc_delay(sc);
625
626	/*
627	* Send address of word we want to read.
628	*/
629	dc_eeprom_putbyte(sc, addr);
630
631	/*
632	* Start reading bits from EEPROM.
633	*/
634	for (i = 0x8000; i; i >>= 1) {
635	SIO_SET(DC_SIO_EE_CLK);
636	dc_delay(sc);
637	if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
638	word \|= i;
639	dc_delay(sc);
640	SIO_CLR(DC_SIO_EE_CLK);
641	dc_delay(sc);
642	}
643
644	/* Turn off EEPROM access mode. */
645	dc_eeprom_idle(sc);
646
647	*dest = word;
648
649	return;
650	}
651
652	/*
653	* Read a sequence of words from the EEPROM.
654	*/
655	static void dc_read_eeprom(sc, dest, off, cnt, swap)
656	struct dc_softc *sc;
657	caddr_t dest;
658	int off;
659	int cnt;
660	int swap;
661	{
662	int i;
663	u_int16_t word = 0, *ptr;
664
665	for (i = 0; i < cnt; i++) {
666	if (DC_IS_PNIC(sc))
667	dc_eeprom_getword_pnic(sc, off + i, &word);
668	else
669	dc_eeprom_getword(sc, off + i, &word);
670	ptr = (u_int16_t )(dest + (i 2));
671	if (swap)
672	*ptr = ntohs(word);
673	else
674	*ptr = word;
675	}
676
677	return;
678	}
679
680
681	#if 0
682	/*
683	* The following two routines are taken from the Macronix 98713
684	* Application Notes pp.19-21.
685	*/
686	/*
687	* Write a bit to the MII bus.
688	*/
689	static void dc_mii_writebit(sc, bit)
690	struct dc_softc *sc;
691	int bit;
692	{
693	if (bit)
694	CSR_WRITE_4(sc, DC_SIO,
695	DC_SIO_ROMCTL_WRITE\|DC_SIO_MII_DATAOUT);
696	else
697	CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
698
699	DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
700	DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
701
702	return;
703	}
704
705	/*
706	* Read a bit from the MII bus.
707	*/
708	static int dc_mii_readbit(sc)
709	struct dc_softc *sc;
710	{
711	CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ\|DC_SIO_MII_DIR);
712	CSR_READ_4(sc, DC_SIO);
713	DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
714	DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
715	if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
716	return(1);
717
718	return(0);
719	}
720
721	/*
722	* Sync the PHYs by setting data bit and strobing the clock 32 times.
723	*/
724	static void dc_mii_sync(sc)
725	struct dc_softc *sc;
726	{
727	register int i;
728
729	CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
730
731	for (i = 0; i < 32; i++)
732	dc_mii_writebit(sc, 1);
733
734	return;
735	}
736
737	/*
738	* Clock a series of bits through the MII.
739	*/
740	static void dc_mii_send(sc, bits, cnt)
741	struct dc_softc *sc;
742	u_int32_t bits;
743	int cnt;
744	{
745	int i;
746
747	for (i = (0x1 << (cnt - 1)); i; i >>= 1)
748	dc_mii_writebit(sc, bits & i);
749	}
750
751	/*
752	* Read an PHY register through the MII.
753	*/
754	static int dc_mii_readreg(sc, frame)
755	struct dc_softc *sc;
756	struct dc_mii_frame *frame;
757
758	{
759	int i, ack, s;
760
761
762	/*
763	* Set up frame for RX.
764	*/
765	frame->mii_stdelim = DC_MII_STARTDELIM;
766	frame->mii_opcode = DC_MII_READOP;
767	frame->mii_turnaround = 0;
768	frame->mii_data = 0;
769
770	/*
771	* Sync the PHYs.
772	*/
773	dc_mii_sync(sc);
774
775	/*
776	* Send command/address info.
777	*/
778	dc_mii_send(sc, frame->mii_stdelim, 2);
779	dc_mii_send(sc, frame->mii_opcode, 2);
780	dc_mii_send(sc, frame->mii_phyaddr, 5);
781	dc_mii_send(sc, frame->mii_regaddr, 5);
782
783	#ifdef notdef
784	/* Idle bit */
785	dc_mii_writebit(sc, 1);
786	dc_mii_writebit(sc, 0);
787	#endif
788
789	/* Check for ack */
790	ack = dc_mii_readbit(sc);
791
792	/*
793	* Now try reading data bits. If the ack failed, we still
794	* need to clock through 16 cycles to keep the PHY(s) in sync.
795	*/
796	if (ack) {
797	for(i = 0; i < 16; i++) {
798	dc_mii_readbit(sc);
799	}
800	goto fail;
801	}
802
803	for (i = 0x8000; i; i >>= 1) {
804	if (!ack) {
805	if (dc_mii_readbit(sc))
806	frame->mii_data \|= i;
807	}
808	}
809
810	fail:
811
812	dc_mii_writebit(sc, 0);
813	dc_mii_writebit(sc, 0);
814
815
816	if (ack)
817	return(1);
818	return(0);
819	}
820
821	/*
822	* Write to a PHY register through the MII.
823	*/
824	static int dc_mii_writereg(sc, frame)
825	struct dc_softc *sc;
826	struct dc_mii_frame *frame;
827
828	{
829	int s;
830
831	/*
832	* Set up frame for TX.
833	*/
834
835	frame->mii_stdelim = DC_MII_STARTDELIM;
836	frame->mii_opcode = DC_MII_WRITEOP;
837	frame->mii_turnaround = DC_MII_TURNAROUND;
838
839	/*
840	* Sync the PHYs.
841	*/
842	dc_mii_sync(sc);
843
844	dc_mii_send(sc, frame->mii_stdelim, 2);
845	dc_mii_send(sc, frame->mii_opcode, 2);
846	dc_mii_send(sc, frame->mii_phyaddr, 5);
847	dc_mii_send(sc, frame->mii_regaddr, 5);
848	dc_mii_send(sc, frame->mii_turnaround, 2);
849	dc_mii_send(sc, frame->mii_data, 16);
850
851	/* Idle bit. */
852	dc_mii_writebit(sc, 0);
853	dc_mii_writebit(sc, 0);
854
855
856	return(0);
857	}
858
859	static int dc_miibus_readreg(dev, phy, reg)
860	device_t dev;
861	int phy, reg;
862	{
863	struct dc_mii_frame frame;
864	struct dc_softc *sc;
865	int i, rval, phy_reg = 0;
866
867	sc = device_get_softc(dev);
868	bzero((char *)&frame, sizeof(frame));
869
870	/*
871	* Note: both the AL981 and AN985 have internal PHYs,
872	* however the AL981 provides direct access to the PHY
873	* registers while the AN985 uses a serial MII interface.
874	* The AN985's MII interface is also buggy in that you
875	* can read from any MII address (0 to 31), but only address 1
876	* behaves normally. To deal with both cases, we pretend
877	* that the PHY is at MII address 1.
878	*/
879	if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
880	return(0);
881
882	/*
883	* Note: the ukphy probes of the RS7112 report a PHY at
884	* MII address 0 (possibly HomePNA?) and 1 (ethernet)
885	* so we only respond to correct one.
886	*/
887	if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
888	return(0);
889
890	if (sc->dc_pmode != DC_PMODE_MII) {
891	if (phy == (MII_NPHY - 1)) {
892	switch(reg) {
893	case MII_BMSR:
894	/*
895	* Fake something to make the probe
896	* code think there's a PHY here.
897	*/
898	return(BMSR_MEDIAMASK);
899	break;
900	case MII_PHYIDR1:
901	if (DC_IS_PNIC(sc))
902	return(DC_VENDORID_LO);
903	return(DC_VENDORID_DEC);
904	break;
905	case MII_PHYIDR2:
906	if (DC_IS_PNIC(sc))
907	return(DC_DEVICEID_82C168);
908	return(DC_DEVICEID_21143);
909	break;
910	default:
911	return(0);
912	break;
913	}
914	} else
915	return(0);
916	}
917
918	if (DC_IS_PNIC(sc)) {
919	CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ \|
920	(phy << 23) \| (reg << 18));
921	for (i = 0; i < DC_TIMEOUT; i++) {
922	DELAY(1);
923	rval = CSR_READ_4(sc, DC_PN_MII);
924	if (!(rval & DC_PN_MII_BUSY)) {
925	rval &= 0xFFFF;
926	return(rval == 0xFFFF ? 0 : rval);
927	}
928	}
929	return(0);
930	}
931
932	if (DC_IS_COMET(sc)) {
933	switch(reg) {
934	case MII_BMCR:
935	phy_reg = DC_AL_BMCR;
936	break;
937	case MII_BMSR:
938	phy_reg = DC_AL_BMSR;
939	break;
940	case MII_PHYIDR1:
941	phy_reg = DC_AL_VENID;
942	break;
943	case MII_PHYIDR2:
944	phy_reg = DC_AL_DEVID;
945	break;
946	case MII_ANAR:
947	phy_reg = DC_AL_ANAR;
948	break;
949	case MII_ANLPAR:
950	phy_reg = DC_AL_LPAR;
951	break;
952	case MII_ANER:
953	phy_reg = DC_AL_ANER;
954	break;
955	default:
956	printk("dc%d: phy_read: bad phy register %x\n",
957	sc->dc_unit, reg);
958	return(0);
959	break;
960	}
961
962	rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
963
964	if (rval == 0xFFFF)
965	return(0);
966	return(rval);
967	}
968
969	frame.mii_phyaddr = phy;
970	frame.mii_regaddr = reg;
971	if (sc->dc_type == DC_TYPE_98713) {
972	phy_reg = CSR_READ_4(sc, DC_NETCFG);
973	CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
974	}
975	dc_mii_readreg(sc, &frame);
976	if (sc->dc_type == DC_TYPE_98713)
977	CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
978
979	return(frame.mii_data);
980	}
981
982	static int dc_miibus_writereg(dev, phy, reg, data)
983	device_t dev;
984	int phy, reg, data;
985	{
986	struct dc_softc *sc;
987	struct dc_mii_frame frame;
988	int i, phy_reg = 0;
989
990	sc = device_get_softc(dev);
991	bzero((char *)&frame, sizeof(frame));
992
993	if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
994	return(0);
995
996	if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
997	return(0);
998
999	if (DC_IS_PNIC(sc)) {
1000	CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE \|
1001	(phy << 23) \| (reg << 10) \| data);
1002	for (i = 0; i < DC_TIMEOUT; i++) {
1003	if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
1004	break;
1005	}
1006	return(0);
1007	}
1008
1009	if (DC_IS_COMET(sc)) {
1010	switch(reg) {
1011	case MII_BMCR:
1012	phy_reg = DC_AL_BMCR;
1013	break;
1014	case MII_BMSR:
1015	phy_reg = DC_AL_BMSR;
1016	break;
1017	case MII_PHYIDR1:
1018	phy_reg = DC_AL_VENID;
1019	break;
1020	case MII_PHYIDR2:
1021	phy_reg = DC_AL_DEVID;
1022	break;
1023	case MII_ANAR:
1024	phy_reg = DC_AL_ANAR;
1025	break;
1026	case MII_ANLPAR:
1027	phy_reg = DC_AL_LPAR;
1028	break;
1029	case MII_ANER:
1030	phy_reg = DC_AL_ANER;
1031	break;
1032	default:
1033	printk("dc%d: phy_write: bad phy register %x\n",
1034	sc->dc_unit, reg);
1035	return(0);
1036	break;
1037	}
1038
1039	CSR_WRITE_4(sc, phy_reg, data);
1040	return(0);
1041	}
1042
1043	frame.mii_phyaddr = phy;
1044	frame.mii_regaddr = reg;
1045	frame.mii_data = data;
1046
1047	if (sc->dc_type == DC_TYPE_98713) {
1048	phy_reg = CSR_READ_4(sc, DC_NETCFG);
1049	CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
1050	}
1051	dc_mii_writereg(sc, &frame);
1052	if (sc->dc_type == DC_TYPE_98713)
1053	CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
1054
1055	return(0);
1056	}
1057
1058	static void dc_miibus_statchg(dev)
1059	device_t dev;
1060	{
1061	struct dc_softc *sc;
1062	struct mii_data *mii;
1063	struct ifmedia *ifm;
1064
1065	sc = device_get_softc(dev);
1066	if (DC_IS_ADMTEK(sc))
1067	return;
1068
1069	mii = device_get_softc(sc->dc_miibus);
1070	ifm = &mii->mii_media;
1071	if (DC_IS_DAVICOM(sc) &&
1072	IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) {
1073	dc_setcfg(sc, ifm->ifm_media);
1074	sc->dc_if_media = ifm->ifm_media;
1075	} else {
1076	dc_setcfg(sc, mii->mii_media_active);
1077	sc->dc_if_media = mii->mii_media_active;
1078	}
1079
1080	return;
1081	}
1082
1083	/*
1084	* Special support for DM9102A cards with HomePNA PHYs. Note:
1085	* with the Davicom DM9102A/DM9801 eval board that I have, it seems
1086	* to be impossible to talk to the management interface of the DM9801
1087	* PHY (its MDIO pin is not connected to anything). Consequently,
1088	* the driver has to just 'know' about the additional mode and deal
1089	* with it itself. sigh
1090	*/
1091	static void dc_miibus_mediainit(dev)
1092	device_t dev;
1093	{
1094	struct dc_softc *sc;
1095	struct mii_data *mii;
1096	struct ifmedia *ifm;
1097	int rev;
1098
1099	rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF;
1100
1101	sc = device_get_softc(dev);
1102	mii = device_get_softc(sc->dc_miibus);
1103	ifm = &mii->mii_media;
1104
1105	if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
1106	ifmedia_add(ifm, IFM_ETHER\|IFM_homePNA, 0, NULL);
1107
1108	return;
1109	}
1110	#endif
1111
1112	#define DC_POLY 0xEDB88320
1113	#define DC_BITS_512 9
1114	#define DC_BITS_128 7
1115	#define DC_BITS_64 6
1116
1117	static u_int32_t dc_crc_le(sc, addr)
1118	struct dc_softc *sc;
1119	caddr_t addr;
1120	{
1121	u_int32_t idx, bit, data, crc;
1122
1123	/* Compute CRC for the address value. */
1124	crc = 0xFFFFFFFF; /* initial value */
1125
1126	for (idx = 0; idx < 6; idx++) {
1127	for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1)
1128	crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0);
1129	}
1130
1131	/*
1132	* The hash table on the PNIC II and the MX98715AEC-C/D/E
1133	* chips is only 128 bits wide.
1134	*/
1135	if (sc->dc_flags & DC_128BIT_HASH)
1136	return (crc & ((1 << DC_BITS_128) - 1));
1137
1138	/* The hash table on the MX98715BEC is only 64 bits wide. */
1139	if (sc->dc_flags & DC_64BIT_HASH)
1140	return (crc & ((1 << DC_BITS_64) - 1));
1141
1142	return (crc & ((1 << DC_BITS_512) - 1));
1143	}
1144
1145	#ifndef UNUSED
1146	/*
1147	* Calculate CRC of a multicast group address, return the lower 6 bits.
1148	*/
1149	static u_int32_t dc_crc_be(addr)
1150	caddr_t addr;
1151	{
1152	u_int32_t crc, carry;
1153	int i, j;
1154	u_int8_t c;
1155
1156	/* Compute CRC for the address value. */
1157	crc = 0xFFFFFFFF; /* initial value */
1158
1159	for (i = 0; i < 6; i++) {
1160	c = *(addr + i);
1161	for (j = 0; j < 8; j++) {
1162	carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
1163	crc <<= 1;
1164	c >>= 1;
1165	if (carry)
1166	crc = (crc ^ 0x04c11db6) \| carry;
1167	}
1168	}
1169
1170	/* return the filter bit position */
1171	return((crc >> 26) & 0x0000003F);
1172	}
1173	#endif
1174
1175	/*
1176	* 21143-style RX filter setup routine. Filter programming is done by
1177	* downloading a special setup frame into the TX engine. 21143, Macronix,
1178	* PNIC, PNIC II and Davicom chips are programmed this way.
1179	*
1180	* We always program the chip using 'hash perfect' mode, i.e. one perfect
1181	* address (our node address) and a 512-bit hash filter for multicast
1182	* frames. We also sneak the broadcast address into the hash filter since
1183	* we need that too.
1184	*/
1185	void dc_setfilt_21143(sc)
1186	struct dc_softc *sc;
1187	{
1188	struct dc_desc *sframe;
1189	u_int32_t h, *sp;
1190	/struct ifmultiaddr ifma;*/
1191	struct ifnet *ifp;
1192	int i;
1193
1194	ifp = &sc->arpcom.ac_if;
1195
1196	i = sc->dc_cdata.dc_tx_prod;
1197	DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1198	sc->dc_cdata.dc_tx_cnt++;
1199	sframe = &sc->dc_ldata->dc_tx_list[i];
1200	sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf;
1201	bzero((char *)sp, DC_SFRAME_LEN);
1202
1203	sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf);
1204	sframe->dc_ctl = DC_SFRAME_LEN \| DC_TXCTL_SETUP \| DC_TXCTL_TLINK \|
1205	DC_FILTER_HASHPERF \| DC_TXCTL_FINT;
1206
1207	sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf;
1208
1209	/* If we want promiscuous mode, set the allframes bit. */
1210	if (ifp->if_flags & IFF_PROMISC)
1211	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1212	else
1213	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1214
1215	if (ifp->if_flags & IFF_ALLMULTI)
1216	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1217	else
1218	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1219	#if 0
1220	for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1221	ifma = ifma->ifma_link.le_next) {
1222	if (ifma->ifma_addr->sa_family != AF_LINK)
1223	continue;
1224	h = dc_crc_le(sc,
1225	LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1226	sp[h >> 4] \|= 1 << (h & 0xF);
1227	}
1228	#endif
1229
1230	if (ifp->if_flags & IFF_BROADCAST) {
1231	h = dc_crc_le(sc, (caddr_t)&etherbroadcastaddr);
1232	sp[h >> 4] \|= 1 << (h & 0xF);
1233	}
1234
1235	/* Set our MAC address */
1236	sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0];
1237	sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1];
1238	sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2];
1239
1240	sframe->dc_status = DC_TXSTAT_OWN;
1241	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1242
1243	/*
1244	* The PNIC takes an exceedingly long time to process its
1245	* setup frame; wait 10ms after posting the setup frame
1246	* before proceeding, just so it has time to swallow its
1247	* medicine.
1248	*/
1249	DELAY(10000);
1250
1251	ifp->if_timer = 5;
1252
1253	return;
1254	}
1255
1256	void dc_setfilt_admtek(sc)
1257	struct dc_softc *sc;
1258	{
1259	struct ifnet *ifp;
1260	#if 0
1261	int h = 0;
1262	u_int32_t hashes[2] = { 0, 0 };
1263	struct ifmultiaddr *ifma;
1264	#endif
1265
1266	ifp = &sc->arpcom.ac_if;
1267
1268	/* Init our MAC address */
1269	CSR_WRITE_4(sc, DC_AL_PAR0, (u_int32_t )(&sc->arpcom.ac_enaddr[0]));
1270	CSR_WRITE_4(sc, DC_AL_PAR1, (u_int32_t )(&sc->arpcom.ac_enaddr[4]));
1271
1272	/* If we want promiscuous mode, set the allframes bit. */
1273	if (ifp->if_flags & IFF_PROMISC)
1274	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1275	else
1276	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1277
1278	if (ifp->if_flags & IFF_ALLMULTI)
1279	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1280	else
1281	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1282
1283	/* first, zot all the existing hash bits */
1284	CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1285	CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1286
1287	#if 0
1288	/*
1289	* If we're already in promisc or allmulti mode, we
1290	* don't have to bother programming the multicast filter.
1291	*/
1292	if (ifp->if_flags & (IFF_PROMISC\|IFF_ALLMULTI))
1293	return;
1294
1295	/* now program new ones */
1296	for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1297	ifma = ifma->ifma_link.le_next) {
1298	if (ifma->ifma_addr->sa_family != AF_LINK)
1299	continue;
1300	h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1301	if (h < 32)
1302	hashes[0] \|= (1 << h);
1303	else
1304	hashes[1] \|= (1 << (h - 32));
1305	}
1306
1307	CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1308	CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1309	#endif
1310	return;
1311	}
1312
1313	void dc_setfilt_asix(sc)
1314	struct dc_softc *sc;
1315	{
1316	struct ifnet *ifp;
1317	#if 0
1318	int h = 0;
1319	u_int32_t hashes[2] = { 0, 0 };
1320	struct ifmultiaddr *ifma;
1321	#endif
1322
1323	ifp = &sc->arpcom.ac_if;
1324
1325	/* Init our MAC address */
1326	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1327	CSR_WRITE_4(sc, DC_AX_FILTDATA,
1328	(u_int32_t )(&sc->arpcom.ac_enaddr[0]));
1329	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1330	CSR_WRITE_4(sc, DC_AX_FILTDATA,
1331	(u_int32_t )(&sc->arpcom.ac_enaddr[4]));
1332
1333	/* If we want promiscuous mode, set the allframes bit. */
1334	if (ifp->if_flags & IFF_PROMISC)
1335	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1336	else
1337	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1338
1339	if (ifp->if_flags & IFF_ALLMULTI)
1340	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1341	else
1342	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1343
1344	/*
1345	* The ASIX chip has a special bit to enable reception
1346	* of broadcast frames.
1347	*/
1348	if (ifp->if_flags & IFF_BROADCAST)
1349	DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1350	else
1351	DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1352
1353	/* first, zot all the existing hash bits */
1354	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1355	CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1356	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1357	CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1358
1359	#if 0
1360	/*
1361	* If we're already in promisc or allmulti mode, we
1362	* don't have to bother programming the multicast filter.
1363	*/
1364	if (ifp->if_flags & (IFF_PROMISC\|IFF_ALLMULTI))
1365	return;
1366
1367	/* now program new ones */
1368	for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
1369	ifma = ifma->ifma_link.le_next) {
1370	if (ifma->ifma_addr->sa_family != AF_LINK)
1371	continue;
1372	h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1373	if (h < 32)
1374	hashes[0] \|= (1 << h);
1375	else
1376	hashes[1] \|= (1 << (h - 32));
1377	}
1378
1379	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1380	CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1381	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1382	CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1383	#endif
1384	return;
1385	}
1386
1387	static void dc_setfilt(sc)
1388	struct dc_softc *sc;
1389	{
1390	if (DC_IS_INTEL(sc) \|\| DC_IS_MACRONIX(sc) \|\| DC_IS_PNIC(sc) \|\|
1391	DC_IS_PNICII(sc) \|\| DC_IS_DAVICOM(sc) \|\| DC_IS_CONEXANT(sc))
1392	dc_setfilt_21143(sc);
1393
1394	if (DC_IS_ASIX(sc))
1395	dc_setfilt_asix(sc);
1396
1397	if (DC_IS_ADMTEK(sc))
1398	dc_setfilt_admtek(sc);
1399
1400	return;
1401	}
1402
1403	/*
1404	* In order to fiddle with the
1405	* 'full-duplex' and '100Mbps' bits in the netconfig register, we
1406	* first have to put the transmit and/or receive logic in the idle state.
1407	*/
1408	static void dc_setcfg(sc, media)
1409	struct dc_softc *sc;
1410	int media;
1411	{
1412	int i, restart = 0;
1413	u_int32_t isr;
1414
1415	if (IFM_SUBTYPE(media) == IFM_NONE)
1416	return;
1417
1418	if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON\|DC_NETCFG_RX_ON)) {
1419	restart = 1;
1420	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON\|DC_NETCFG_RX_ON));
1421
1422	for (i = 0; i < DC_TIMEOUT; i++) {
1423	isr = CSR_READ_4(sc, DC_ISR);
1424	if (isr & DC_ISR_TX_IDLE \|\|
1425	(isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED)
1426	break;
1427	DELAY(10);
1428	}
1429
1430	if (i == DC_TIMEOUT)
1431	printk("dc%d: failed to force tx and "
1432	"rx to idle state\n", sc->dc_unit);
1433	}
1434
1435	if (IFM_SUBTYPE(media) == IFM_100_TX) {
1436	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1437	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1438	if (sc->dc_pmode == DC_PMODE_MII) {
1439	int watchdogreg;
1440
1441	if (DC_IS_INTEL(sc)) {
1442	/* there's a write enable bit here that reads as 1 */
1443	watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1444	watchdogreg &= ~DC_WDOG_CTLWREN;
1445	watchdogreg \|= DC_WDOG_JABBERDIS;
1446	CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1447	} else {
1448	DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1449	}
1450	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS\|
1451	DC_NETCFG_PORTSEL\|DC_NETCFG_SCRAMBLER));
1452	if (sc->dc_type == DC_TYPE_98713)
1453	DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS\|
1454	DC_NETCFG_SCRAMBLER));
1455	if (!DC_IS_DAVICOM(sc))
1456	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1457	DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1458	if (DC_IS_INTEL(sc))
1459	dc_apply_fixup(sc, IFM_AUTO);
1460	} else {
1461	if (DC_IS_PNIC(sc)) {
1462	DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1463	DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1464	DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1465	}
1466	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1467	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1468	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1469	if (DC_IS_INTEL(sc))
1470	dc_apply_fixup(sc,
1471	(media & IFM_GMASK) == IFM_FDX ?
1472	IFM_100_TX\|IFM_FDX : IFM_100_TX);
1473	}
1474	}
1475
1476	if (IFM_SUBTYPE(media) == IFM_10_T) {
1477	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1478	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1479	if (sc->dc_pmode == DC_PMODE_MII) {
1480	int watchdogreg;
1481
1482	/* there's a write enable bit here that reads as 1 */
1483	if (DC_IS_INTEL(sc)) {
1484	watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1485	watchdogreg &= ~DC_WDOG_CTLWREN;
1486	watchdogreg \|= DC_WDOG_JABBERDIS;
1487	CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1488	} else {
1489	DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1490	}
1491	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS\|
1492	DC_NETCFG_PORTSEL\|DC_NETCFG_SCRAMBLER));
1493	if (sc->dc_type == DC_TYPE_98713)
1494	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1495	if (!DC_IS_DAVICOM(sc))
1496	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1497	DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1498	if (DC_IS_INTEL(sc))
1499	dc_apply_fixup(sc, IFM_AUTO);
1500	} else {
1501	if (DC_IS_PNIC(sc)) {
1502	DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1503	DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1504	DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1505	}
1506	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1507	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1508	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1509	if (DC_IS_INTEL(sc)) {
1510	DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1511	DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1512	if ((media & IFM_GMASK) == IFM_FDX)
1513	DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1514	else
1515	DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1516	DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1517	DC_CLRBIT(sc, DC_10BTCTRL,
1518	DC_TCTL_AUTONEGENBL);
1519	dc_apply_fixup(sc,
1520	(media & IFM_GMASK) == IFM_FDX ?
1521	IFM_10_T\|IFM_FDX : IFM_10_T);
1522	DELAY(20000);
1523	}
1524	}
1525	}
1526
1527	#if 0
1528	/*
1529	* If this is a Davicom DM9102A card with a DM9801 HomePNA
1530	* PHY and we want HomePNA mode, set the portsel bit to turn
1531	* on the external MII port.
1532	*/
1533	if (DC_IS_DAVICOM(sc)) {
1534	if (IFM_SUBTYPE(media) == IFM_homePNA) {
1535	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1536	sc->dc_link = 1;
1537	} else {
1538	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1539	}
1540	}
1541	#endif
1542
1543	if ((media & IFM_GMASK) == IFM_FDX) {
1544	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1545	if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1546	DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1547	} else {
1548	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1549	if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1550	DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1551	}
1552
1553	if (restart)
1554	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON\|DC_NETCFG_RX_ON);
1555
1556	return;
1557	}
1558
1559	static void dc_reset(sc)
1560	struct dc_softc *sc;
1561	{
1562	register int i;
1563
1564	DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1565
1566	for (i = 0; i < DC_TIMEOUT; i++) {
1567	DELAY(10);
1568	if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1569	break;
1570	}
1571
1572	if (DC_IS_ASIX(sc) \|\| DC_IS_ADMTEK(sc) \|\| DC_IS_CONEXANT(sc)) {
1573	DELAY(10000);
1574	DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1575	i = 0;
1576	}
1577
1578	if (i == DC_TIMEOUT)
1579	printk("dc%d: reset never completed!\n", sc->dc_unit);
1580
1581	/* Wait a little while for the chip to get its brains in order. */
1582	DELAY(1000);
1583
1584	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1585	CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1586	CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1587
1588	/*
1589	* Bring the SIA out of reset. In some cases, it looks
1590	* like failing to unreset the SIA soon enough gets it
1591	* into a state where it will never come out of reset
1592	* until we reset the whole chip again.
1593	*/
1594	if (DC_IS_INTEL(sc)) {
1595	DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1596	CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1597	CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1598	}
1599
1600	return;
1601	}
1602
1603	static
1604	struct dc_type *dc_devtype( int unitnum )
1605	{
1606	struct dc_type *t;
1607	unsigned int rev;
1608	int rc;
1609
1610
1611	t = dc_devs;
1612
1613	while(t->dc_name != NULL) {
1614	rc = pci_find_device(t->dc_vid, t->dc_did, \
1615	(unitnum - 1), &t->dc_bus, &t->dc_dev, &t->dc_fun);
1616	if (rc == PCIB_ERR_SUCCESS) {
1617	/* Check the PCI revision */
1618	/pcib_conf_read32(t->dc_devsig, DC_PCI_CFRV, &rev); /
1619	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
1620	DC_PCI_CFRV, &rev);
1621	rev &= 0xFF;
1622
1623	if (t->dc_did == DC_DEVICEID_98713 &&
1624	rev >= DC_REVISION_98713A)
1625	t++;
1626	if (t->dc_did == DC_DEVICEID_98713_CP &&
1627	rev >= DC_REVISION_98713A)
1628	t++;
1629	if (t->dc_did == DC_DEVICEID_987x5 &&
1630	rev >= DC_REVISION_98715AEC_C)
1631	t++;
1632	if (t->dc_did == DC_DEVICEID_987x5 &&
1633	rev >= DC_REVISION_98725)
1634	t++;
1635	if (t->dc_did == DC_DEVICEID_AX88140A &&
1636	rev >= DC_REVISION_88141)
1637	t++;
1638	if (t->dc_did == DC_DEVICEID_82C168 &&
1639	rev >= DC_REVISION_82C169)
1640	t++;
1641	if (t->dc_did == DC_DEVICEID_DM9102 &&
1642	rev >= DC_REVISION_DM9102A)
1643	t++;
1644	return(t);
1645	}
1646	t++;
1647	}
1648
1649	return(NULL);
1650	}
1651
1652	#if 0
1653	/*
1654	* Probe for a 21143 or clone chip. Check the PCI vendor and device
1655	* IDs against our list and return a device name if we find a match.
1656	* We do a little bit of extra work to identify the exact type of
1657	* chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1658	* but different revision IDs. The same is true for 98715/98715A
1659	* chips and the 98725, as well as the ASIX and ADMtek chips. In some
1660	* cases, the exact chip revision affects driver behavior.
1661	*/
1662	static int dc_probe(dev)
1663	device_t dev;
1664	{
1665	struct dc_type *t;
1666
1667	t = dc_devtype(dev);
1668
1669	if (t != NULL) {
1670	device_set_desc(dev, t->dc_name);
1671	return(0);
1672	}
1673
1674	return(ENXIO);
1675	}
1676
1677
1678	static void dc_acpi(dev)
1679	device_t dev;
1680	{
1681	u_int32_t r, cptr;
1682	int unit;
1683
1684	unit = device_get_unit(dev);
1685
1686	/* Find the location of the capabilities block */
1687	cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF;
1688
1689	r = pci_read_config(dev, cptr, 4) & 0xFF;
1690	if (r == 0x01) {
1691
1692	r = pci_read_config(dev, cptr + 4, 4);
1693	if (r & DC_PSTATE_D3) {
1694	u_int32_t iobase, membase, irq;
1695
1696	/* Save important PCI config data. */
1697	iobase = pci_read_config(dev, DC_PCI_CFBIO, 4);
1698	membase = pci_read_config(dev, DC_PCI_CFBMA, 4);
1699	irq = pci_read_config(dev, DC_PCI_CFIT, 4);
1700
1701	/* Reset the power state. */
1702	printk("dc%d: chip is in D%d power mode "
1703	"-- setting to D0\n", unit, r & DC_PSTATE_D3);
1704	r &= 0xFFFFFFFC;
1705	pci_write_config(dev, cptr + 4, r, 4);
1706
1707	/* Restore PCI config data. */
1708	pci_write_config(dev, DC_PCI_CFBIO, iobase, 4);
1709	pci_write_config(dev, DC_PCI_CFBMA, membase, 4);
1710	pci_write_config(dev, DC_PCI_CFIT, irq, 4);
1711	}
1712	}
1713	return;
1714	}
1715	#endif
1716
1717
1718	static void dc_apply_fixup(sc, media)
1719	struct dc_softc *sc;
1720	int media;
1721	{
1722	struct dc_mediainfo *m;
1723	u_int8_t *p;
1724	int i;
1725	u_int32_t reg;
1726
1727	m = sc->dc_mi;
1728
1729	while (m != NULL) {
1730	if (m->dc_media == media)
1731	break;
1732	m = m->dc_next;
1733	}
1734
1735	if (m == NULL)
1736	return;
1737
1738	for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1739	reg = (p[0] \| (p[1] << 8)) << 16;
1740	CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1741	}
1742
1743	for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1744	reg = (p[0] \| (p[1] << 8)) << 16;
1745	CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1746	}
1747
1748	return;
1749	}
1750
1751	#if 0
1752	static void dc_decode_leaf_sia(sc, l)
1753	struct dc_softc *sc;
1754	struct dc_eblock_sia *l;
1755	{
1756	struct dc_mediainfo *m;
1757
1758	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1759	bzero(m, sizeof(struct dc_mediainfo));
1760	if (l->dc_sia_code == DC_SIA_CODE_10BT)
1761	m->dc_media = IFM_10_T;
1762
1763	if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX)
1764	m->dc_media = IFM_10_T\|IFM_FDX;
1765
1766	if (l->dc_sia_code == DC_SIA_CODE_10B2)
1767	m->dc_media = IFM_10_2;
1768
1769	if (l->dc_sia_code == DC_SIA_CODE_10B5)
1770	m->dc_media = IFM_10_5;
1771
1772	m->dc_gp_len = 2;
1773	m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl;
1774
1775	m->dc_next = sc->dc_mi;
1776	sc->dc_mi = m;
1777
1778	sc->dc_pmode = DC_PMODE_SIA;
1779
1780	return;
1781	}
1782
1783	static void dc_decode_leaf_sym(sc, l)
1784	struct dc_softc *sc;
1785	struct dc_eblock_sym *l;
1786	{
1787	struct dc_mediainfo *m;
1788
1789	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1790	bzero(m, sizeof(struct dc_mediainfo));
1791	if (l->dc_sym_code == DC_SYM_CODE_100BT)
1792	m->dc_media = IFM_100_TX;
1793
1794	if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1795	m->dc_media = IFM_100_TX\|IFM_FDX;
1796
1797	m->dc_gp_len = 2;
1798	m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
1799
1800	m->dc_next = sc->dc_mi;
1801	sc->dc_mi = m;
1802
1803	sc->dc_pmode = DC_PMODE_SYM;
1804
1805	return;
1806	}
1807
1808	static void dc_decode_leaf_mii(sc, l)
1809	struct dc_softc *sc;
1810	struct dc_eblock_mii *l;
1811	{
1812	u_int8_t *p;
1813	struct dc_mediainfo *m;
1814
1815	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT);
1816	bzero(m, sizeof(struct dc_mediainfo));
1817	/* We abuse IFM_AUTO to represent MII. */
1818	m->dc_media = IFM_AUTO;
1819	m->dc_gp_len = l->dc_gpr_len;
1820
1821	p = (u_int8_t *)l;
1822	p += sizeof(struct dc_eblock_mii);
1823	m->dc_gp_ptr = p;
1824	p += 2 * l->dc_gpr_len;
1825	m->dc_reset_len = *p;
1826	p++;
1827	m->dc_reset_ptr = p;
1828
1829	m->dc_next = sc->dc_mi;
1830	sc->dc_mi = m;
1831
1832	return;
1833	}
1834	#endif
1835
1836	static void dc_read_srom(sc, bits)
1837	struct dc_softc *sc;
1838	int bits;
1839	{
1840	int size;
1841
1842	size = 2 << bits;
1843	sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT);
1844	dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1845	}
1846
1847	static void dc_parse_21143_srom(sc)
1848	struct dc_softc *sc;
1849	{
1850	struct dc_leaf_hdr *lhdr;
1851	struct dc_eblock_hdr *hdr;
1852	int i, loff;
1853	char *ptr;
1854
1855	loff = sc->dc_srom[27];
1856	lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1857
1858	ptr = (char *)lhdr;
1859	ptr += sizeof(struct dc_leaf_hdr) - 1;
1860	for (i = 0; i < lhdr->dc_mcnt; i++) {
1861	hdr = (struct dc_eblock_hdr *)ptr;
1862	switch(hdr->dc_type) {
1863	#if 0
1864	case DC_EBLOCK_MII:
1865	dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1866	break;
1867	case DC_EBLOCK_SIA:
1868	dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr);
1869	break;
1870	case DC_EBLOCK_SYM:
1871	dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr);
1872	break;
1873	#endif
1874	default:
1875	/* Don't care. Yet. */
1876	break;
1877	}
1878	ptr += (hdr->dc_len & 0x7F);
1879	ptr++;
1880	}
1881
1882	return;
1883	}
1884
1885
1886	static void
1887	nop(const rtems_irq_connect_data* unused)
1888	{
1889	}
1890
1891	static int
1892	decISON(const rtems_irq_connect_data* irq)
1893	{
1894	return (BSP_irq_enabled_at_i8259s(irq->name));
1895	}
1896
1897
1898	/*
1899	* Attach the interface. Allocate softc structures, do ifmedia
1900	* setup and ethernet/BPF attach.
1901	*/
1902	int
1903	rtems_dc_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching)
1904	{
1905	int rc;
1906	u_char eaddr[ETHER_ADDR_LEN];
1907
1908	char *unitName;
1909	int unitNumber;
1910
1911	unsigned int command;
1912	struct dc_softc *sc;
1913	struct ifnet *ifp;
1914	struct dc_type *t;
1915	unsigned int revision;
1916	int error = 0, mac_offset;
1917	unsigned int value;
1918
1919	/*
1920	* Get the instance number for the board we're going to configure
1921	* from the user.
1922	*/
1923	unitNumber = rtems_bsdnet_parse_driver_name(config, &unitName);
1924	if( unitNumber < 0) {
1925	return 0;
1926	}
1927	if( strcmp(unitName, DRIVER_PREFIX) ) {
1928	printk("dec2114x : unit name '%s' not %s\n", \
1929	unitName, DRIVER_PREFIX );
1930	return 0;
1931	}
1932
1933	sc = &dc_softc_devs[unitNumber - 1];
1934	ifp = &sc->arpcom.ac_if;
1935
1936	if(ifp->if_softc != NULL) {
1937	printk("dec2114x[%d]: unit number already in use.\n", \
1938	unitNumber);
1939	return (0);
1940	}
1941	memset(sc, 0, sizeof(struct dc_softc));
1942
1943	/unit = device_get_unit(dev);/
1944	sc->dc_unit = unitNumber;
1945	sc->dc_name = unitName;
1946
1947	/*
1948	* Handle power management nonsense.
1949	*
1950	dc_acpi(dev);
1951	*/
1952
1953	/* Scan for dec2114x cards in pci config space */
1954	if( (sc->dc_info = dc_devtype(unitNumber)) == NULL) {
1955	printk("Can't find any dec2114x NICs in PCI space.\n");
1956	return 0;
1957	}
1958	t = sc->dc_info;
1959
1960
1961	/*
1962	* Map control/status registers.
1963	*/
1964	/sig = sc->dc_info->dc_devsig; /
1965	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
1966	PCI_COMMAND, &command);
1967	/pcib_conf_read32(sig, PCI_COMMAND, &command); /
1968	command \|= (PCI_COMMAND_IO \| PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
1969	pci_write_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
1970	PCI_COMMAND, command);
1971	/pcib_conf_write32(sig, PCI_COMMAND, command); /
1972	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
1973	PCI_COMMAND, &command);
1974	/pcib_conf_read32(sig, PCI_COMMAND, &command); /
1975
1976	#ifdef DC_USEIOSPACE
1977	if (!(command & PCI_COMMAND_IO)) {
1978	printk("dc%d: failed to enable I/O ports!\n", sc->dc_unit);
1979	error = ENXIO;
1980	goto fail;
1981	}
1982	#else
1983	if (!(command & PCI_COMMAND_MEMORY)) {
1984	printk("dc%d: failed to enable memory mapping!\n", sc->dc_unit);
1985	error = ENXIO;
1986	goto fail;
1987	}
1988	#endif
1989
1990	#if 0
1991	rid = DC_RID;
1992	sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid,
1993	0, ~0, 1, RF_ACTIVE);
1994
1995	if (sc->dc_res == NULL) {
1996	printk("dc%d: couldn't map ports/memory\n", unit);
1997	error = ENXIO;
1998	goto fail;
1999	}
2000	sc->dc_btag = rman_get_bustag(sc->dc_res);
2001	sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
2002	#endif
2003
2004	/* sc->membase is the address of the card's CSRs !!! */
2005	/pcib_conf_read32(sig, DC_PCI_CFBMA, &value); /
2006	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2007	DC_PCI_CFBMA, &value);
2008	sc->membase = value;
2009
2010	/* Allocate interrupt */
2011	memset(&sc->irqInfo, 0, sizeof(rtems_irq_connect_data));
2012	/pcib_conf_read32(sig, DC_PCI_CFIT, &value); /
2013	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2014	DC_PCI_CFIT, &value);
2015
2016	sc->irqInfo.name = value & 0xFF;
2017	sc->irqInfo.hdl = (rtems_irq_hdl)dc_intr;
2018	sc->irqInfo.handle = (void )sc; / new parameter */
2019	sc->irqInfo.on = nop;
2020	sc->irqInfo.off = nop;
2021	sc->irqInfo.isOn = decISON;
2022
2023	#ifdef BSP_SHARED_HANDLER_SUPPORT
2024	rc = BSP_install_rtems_shared_irq_handler( &sc->irqInfo );
2025	#else
2026	rc = BSP_install_rtems_irq_handler( &sc->irqInfo );
2027	#endif
2028	if(!rc) {
2029	rtems_panic("Can't install dec2114x irq handler.\n");
2030	}
2031
2032
2033	#if 0
2034	rid = 0;
2035	sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
2036	RF_SHAREABLE \| RF_ACTIVE);
2037
2038	if (sc->dc_irq == NULL) {
2039	printk("dc%d: couldn't map interrupt\n", unit);
2040	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2041	error = ENXIO;
2042	goto fail;
2043	}
2044
2045	error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET,
2046	dc_intr, sc, &sc->dc_intrhand);
2047
2048	if (error) {
2049	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2050	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2051	printk("dc%d: couldn't set up irq\n", unit);
2052	goto fail;
2053	}
2054	#endif
2055
2056
2057	/* Need this info to decide on a chip type.
2058	sc->dc_info = dc_devtype(dev);
2059	*/
2060	/pcib_conf_read32(sig, DC_PCI_CFRV, &revision); /
2061	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2062	DC_PCI_CFRV, &revision);
2063	revision &= 0x000000FF;
2064
2065	/* Get the eeprom width, but PNIC has diff eeprom */
2066	if (sc->dc_info->dc_did != DC_DEVICEID_82C168)
2067	dc_eeprom_width(sc);
2068
2069	switch(sc->dc_info->dc_did) {
2070	case DC_DEVICEID_21143:
2071	sc->dc_type = DC_TYPE_21143;
2072	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR;
2073	sc->dc_flags \|= DC_REDUCED_MII_POLL;
2074	/* Save EEPROM contents so we can parse them later. */
2075	dc_read_srom(sc, sc->dc_romwidth);
2076	break;
2077	case DC_DEVICEID_DM9009:
2078	case DC_DEVICEID_DM9100:
2079	case DC_DEVICEID_DM9102:
2080	sc->dc_type = DC_TYPE_DM9102;
2081	sc->dc_flags \|= DC_TX_COALESCE\|DC_TX_INTR_ALWAYS;
2082	sc->dc_flags \|= DC_REDUCED_MII_POLL\|DC_TX_STORENFWD;
2083	sc->dc_pmode = DC_PMODE_MII;
2084	/* Increase the latency timer value. */
2085	/pcib_conf_read32(sig, DC_PCI_CFLT, &command); /
2086	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2087	DC_PCI_CFLT, &command);
2088	command &= 0xFFFF00FF;
2089	command \|= 0x00008000;
2090	/pcib_conf_write32(sig, DC_PCI_CFLT, command); /
2091	pci_write_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2092	DC_PCI_CFLT, command);
2093	break;
2094	case DC_DEVICEID_AL981:
2095	sc->dc_type = DC_TYPE_AL981;
2096	sc->dc_flags \|= DC_TX_USE_TX_INTR;
2097	sc->dc_flags \|= DC_TX_ADMTEK_WAR;
2098	sc->dc_pmode = DC_PMODE_MII;
2099	dc_read_srom(sc, sc->dc_romwidth);
2100	break;
2101	case DC_DEVICEID_AN985:
2102	case DC_DEVICEID_EN2242:
2103	sc->dc_type = DC_TYPE_AN985;
2104	sc->dc_flags \|= DC_TX_USE_TX_INTR;
2105	sc->dc_flags \|= DC_TX_ADMTEK_WAR;
2106	sc->dc_pmode = DC_PMODE_MII;
2107	dc_read_srom(sc, sc->dc_romwidth);
2108	break;
2109	case DC_DEVICEID_98713:
2110	case DC_DEVICEID_98713_CP:
2111	if (revision < DC_REVISION_98713A) {
2112	sc->dc_type = DC_TYPE_98713;
2113	}
2114	if (revision >= DC_REVISION_98713A) {
2115	sc->dc_type = DC_TYPE_98713A;
2116	sc->dc_flags \|= DC_21143_NWAY;
2117	}
2118	sc->dc_flags \|= DC_REDUCED_MII_POLL;
2119	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR;
2120	break;
2121	case DC_DEVICEID_987x5:
2122	case DC_DEVICEID_EN1217:
2123	/*
2124	* Macronix MX98715AEC-C/D/E parts have only a
2125	* 128-bit hash table. We need to deal with these
2126	* in the same manner as the PNIC II so that we
2127	* get the right number of bits out of the
2128	* CRC routine.
2129	*/
2130	if (revision >= DC_REVISION_98715AEC_C &&
2131	revision < DC_REVISION_98725)
2132	sc->dc_flags \|= DC_128BIT_HASH;
2133	sc->dc_type = DC_TYPE_987x5;
2134	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR;
2135	sc->dc_flags \|= DC_REDUCED_MII_POLL\|DC_21143_NWAY;
2136	break;
2137	case DC_DEVICEID_98727:
2138	sc->dc_type = DC_TYPE_987x5;
2139	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR;
2140	sc->dc_flags \|= DC_REDUCED_MII_POLL\|DC_21143_NWAY;
2141	break;
2142	case DC_DEVICEID_82C115:
2143	sc->dc_type = DC_TYPE_PNICII;
2144	sc->dc_flags \|= DC_TX_POLL\|DC_TX_USE_TX_INTR\|DC_128BIT_HASH;
2145	sc->dc_flags \|= DC_REDUCED_MII_POLL\|DC_21143_NWAY;
2146	break;
2147	case DC_DEVICEID_82C168:
2148	sc->dc_type = DC_TYPE_PNIC;
2149	sc->dc_flags \|= DC_TX_STORENFWD\|DC_TX_INTR_ALWAYS;
2150	sc->dc_flags \|= DC_PNIC_RX_BUG_WAR;
2151	sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT);
2152	if (revision < DC_REVISION_82C169)
2153	sc->dc_pmode = DC_PMODE_SYM;
2154	break;
2155	case DC_DEVICEID_AX88140A:
2156	sc->dc_type = DC_TYPE_ASIX;
2157	sc->dc_flags \|= DC_TX_USE_TX_INTR\|DC_TX_INTR_FIRSTFRAG;
2158	sc->dc_flags \|= DC_REDUCED_MII_POLL;
2159	sc->dc_pmode = DC_PMODE_MII;
2160	break;
2161	case DC_DEVICEID_RS7112:
2162	sc->dc_type = DC_TYPE_CONEXANT;
2163	sc->dc_flags \|= DC_TX_INTR_ALWAYS;
2164	sc->dc_flags \|= DC_REDUCED_MII_POLL;
2165	sc->dc_pmode = DC_PMODE_MII;
2166	dc_read_srom(sc, sc->dc_romwidth);
2167	break;
2168	default:
2169	printk("dc%d: unknown device: %x\n", sc->dc_unit,
2170	sc->dc_info->dc_did);
2171	break;
2172	}
2173
2174	/* Save the cache line size. */
2175	if (DC_IS_DAVICOM(sc)) {
2176	sc->dc_cachesize = 0;
2177	}
2178	else {
2179	/pcib_conf_read32(sig, DC_PCI_CFLT, &value); /
2180	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2181	DC_PCI_CFLT, &value);
2182	sc->dc_cachesize = (u_int8_t)(value & 0xFF);
2183	}
2184
2185	/* Reset the adapter. */
2186	dc_reset(sc);
2187
2188	/* Take 21143 out of snooze mode */
2189	if (DC_IS_INTEL(sc)) {
2190	/pcib_conf_read32(sig, DC_PCI_CFDD, &command); /
2191	pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2192	DC_PCI_CFDD, &command);
2193	command &= ~(DC_CFDD_SNOOZE_MODE\|DC_CFDD_SLEEP_MODE);
2194	/pcib_conf_write32(sig, DC_PCI_CFDD, command); /
2195	pci_write_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\
2196	DC_PCI_CFDD, command);
2197	}
2198
2199
2200	/*
2201	* Try to learn something about the supported media.
2202	* We know that ASIX and ADMtek and Davicom devices
2203	* will always be using MII media, so that's a no-brainer.
2204	* The tricky ones are the Macronix/PNIC II and the
2205	* Intel 21143.
2206	*/
2207	if (DC_IS_INTEL(sc))
2208	dc_parse_21143_srom(sc);
2209	else if (DC_IS_MACRONIX(sc) \|\| DC_IS_PNICII(sc)) {
2210	if (sc->dc_type == DC_TYPE_98713)
2211	sc->dc_pmode = DC_PMODE_MII;
2212	else
2213	sc->dc_pmode = DC_PMODE_SYM;
2214	} else if (!sc->dc_pmode)
2215	sc->dc_pmode = DC_PMODE_MII;
2216
2217	/*
2218	* Get station address from the EEPROM.
2219	*/
2220	switch(sc->dc_type) {
2221	case DC_TYPE_98713:
2222	case DC_TYPE_98713A:
2223	case DC_TYPE_987x5:
2224	case DC_TYPE_PNICII:
2225	dc_read_eeprom(sc, (caddr_t)&mac_offset,
2226	(DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2227	dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2228	break;
2229	case DC_TYPE_PNIC:
2230	dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2231	break;
2232	case DC_TYPE_DM9102:
2233	case DC_TYPE_21143:
2234	case DC_TYPE_ASIX:
2235	dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2236	break;
2237	case DC_TYPE_AL981:
2238	case DC_TYPE_AN985:
2239	bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr,
2240	ETHER_ADDR_LEN);
2241	dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0);
2242	break;
2243	case DC_TYPE_CONEXANT:
2244	bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6);
2245	break;
2246	default:
2247	dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2248	break;
2249	}
2250
2251	/*
2252	* A 21143 or clone chip was detected. Inform the world.
2253	*/
2254	bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
2255	printk("dc%d: MAC address -- %02x:%02x:%02x:%02x:%02x:%02x\n", \
2256	sc->dc_unit,sc->arpcom.ac_enaddr[0], \
2257	sc->arpcom.ac_enaddr[1], sc->arpcom.ac_enaddr[2], \
2258	sc->arpcom.ac_enaddr[3], sc->arpcom.ac_enaddr[4], \
2259	sc->arpcom.ac_enaddr[5]);
2260
2261
2262	sc->dc_ldata = malloc(sizeof(struct dc_list_data), M_DEVBUF, M_NOWAIT);
2263
2264	if (sc->dc_ldata == NULL) {
2265	printk("dc%d: no memory for list buffers!\n", sc->dc_unit);
2266	if (sc->dc_pnic_rx_buf != NULL)
2267	free(sc->dc_pnic_rx_buf, M_DEVBUF);
2268	#if 0
2269	bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2270	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2271	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2272	#endif
2273	error = ENXIO;
2274	goto fail;
2275	}
2276
2277	bzero(sc->dc_ldata, sizeof(struct dc_list_data));
2278
2279	ifp = &sc->arpcom.ac_if;
2280	ifp->if_softc = sc;
2281	ifp->if_unit = unitNumber; /sc->dc_unit;/
2282	ifp->if_name = unitName; /sc->dc_name;/
2283	ifp->if_mtu = ETHERMTU;
2284	ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX; /* \| IFF_MULTICAST;*/
2285	ifp->if_ioctl = dc_ioctl;
2286	ifp->if_output = ether_output;
2287	ifp->if_start = dc_start;
2288	ifp->if_watchdog = dc_watchdog;
2289	ifp->if_init = dc_init;
2290	ifp->if_baudrate = 100000000;
2291	ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1;
2292
2293	#if 0
2294	/*
2295	* Do MII setup. If this is a 21143, check for a PHY on the
2296	* MII bus after applying any necessary fixups to twiddle the
2297	* GPIO bits. If we don't end up finding a PHY, restore the
2298	* old selection (SIA only or SIA/SYM) and attach the dcphy
2299	* driver instead.
2300	*/
2301	if (DC_IS_INTEL(sc)) {
2302	dc_apply_fixup(sc, IFM_AUTO);
2303	tmp = sc->dc_pmode;
2304	sc->dc_pmode = DC_PMODE_MII;
2305	}
2306
2307	error = mii_phy_probe(dev, &sc->dc_miibus,
2308	dc_ifmedia_upd, dc_ifmedia_sts);
2309
2310	if (error && DC_IS_INTEL(sc)) {
2311	sc->dc_pmode = tmp;
2312	if (sc->dc_pmode != DC_PMODE_SIA)
2313	sc->dc_pmode = DC_PMODE_SYM;
2314	sc->dc_flags \|= DC_21143_NWAY;
2315	mii_phy_probe(dev, &sc->dc_miibus,
2316	dc_ifmedia_upd, dc_ifmedia_sts);
2317	/*
2318	* For non-MII cards, we need to have the 21143
2319	* drive the LEDs. Except there are some systems
2320	* like the NEC VersaPro NoteBook PC which have no
2321	* LEDs, and twiddling these bits has adverse effects
2322	* on them. (I.e. you suddenly can't get a link.)
2323	*/
2324	if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033)
2325	sc->dc_flags \|= DC_TULIP_LEDS;
2326	error = 0;
2327	}
2328
2329	if (error) {
2330	printk("dc%d: MII without any PHY!\n", sc->dc_unit);
2331	contigfree(sc->dc_ldata, sizeof(struct dc_list_data),
2332	M_DEVBUF);
2333	if (sc->dc_pnic_rx_buf != NULL)
2334	free(sc->dc_pnic_rx_buf, M_DEVBUF);
2335	bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2336	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2337	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2338	error = ENXIO;
2339	goto fail;
2340	}
2341	#endif
2342
2343	/*
2344	* Call MI attach routine.
2345	*/
2346	if_attach(ifp);
2347	ether_ifattach(ifp);
2348	/callout_handle_init(&sc->dc_stat_ch);/
2349
2350	if (DC_IS_ADMTEK(sc)) {
2351	/*
2352	* Set automatic TX underrun recovery for the ADMtek chips
2353	*/
2354	DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2355	}
2356
2357	if(sc->daemontid == 0) {
2358	sc->daemontid = rtems_bsdnet_newproc("decD",4096, \
2359	dc_daemon,(void *)sc);
2360	printk("dec[%d]: daemon process started\n", sc->dc_unit);
2361	}
2362
2363	/*
2364	* Tell the upper layer(s) we support long frames.
2365	*
2366	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2367	*/
2368
2369	#ifdef SRM_MEDIA /* only defined if __alpha__ is defined... */
2370	sc->dc_srm_media = 0;
2371
2372	/* Remember the SRM console media setting */
2373	if (DC_IS_INTEL(sc)) {
2374	command = pci_read_config(dev, DC_PCI_CFDD, 4);
2375	command &= ~(DC_CFDD_SNOOZE_MODE\|DC_CFDD_SLEEP_MODE);
2376	switch ((command >> 8) & 0xff) {
2377	case 3:
2378	sc->dc_srm_media = IFM_10_T;
2379	break;
2380	case 4:
2381	sc->dc_srm_media = IFM_10_T \| IFM_FDX;
2382	break;
2383	case 5:
2384	sc->dc_srm_media = IFM_100_TX;
2385	break;
2386	case 6:
2387	sc->dc_srm_media = IFM_100_TX \| IFM_FDX;
2388	break;
2389	}
2390	if (sc->dc_srm_media)
2391	sc->dc_srm_media \|= IFM_ACTIVE \| IFM_ETHER;
2392	}
2393	#endif
2394
2395
2396	fail:
2397
2398	return (1); /(error);/
2399	}
2400
2401	#if 0
2402	static int dc_detach(dev)
2403	device_t dev;
2404	{
2405	struct dc_softc *sc;
2406	struct ifnet *ifp;
2407	int s;
2408	struct dc_mediainfo *m;
2409
2410
2411	sc = device_get_softc(dev);
2412	ifp = &sc->arpcom.ac_if;
2413
2414	dc_stop(sc);
2415	ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
2416
2417	bus_generic_detach(dev);
2418	device_delete_child(dev, sc->dc_miibus);
2419
2420	bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2421	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2422	bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2423
2424	contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF);
2425	if (sc->dc_pnic_rx_buf != NULL)
2426	free(sc->dc_pnic_rx_buf, M_DEVBUF);
2427
2428	while(sc->dc_mi != NULL) {
2429	m = sc->dc_mi->dc_next;
2430	free(sc->dc_mi, M_DEVBUF);
2431	sc->dc_mi = m;
2432	}
2433	free(sc->dc_srom, M_DEVBUF);
2434
2435
2436	return(0);
2437	}
2438	#endif
2439
2440
2441	/*
2442	* Initialize the transmit descriptors.
2443	*/
2444	static int dc_list_tx_init(sc)
2445	struct dc_softc *sc;
2446	{
2447	struct dc_chain_data *cd;
2448	struct dc_list_data *ld;
2449	int i;
2450
2451	cd = &sc->dc_cdata;
2452	ld = sc->dc_ldata;
2453	for (i = 0; i < DC_TX_LIST_CNT; i++) {
2454	if (i == (DC_TX_LIST_CNT - 1)) {
2455	ld->dc_tx_list[i].dc_next =
2456	vtophys(&ld->dc_tx_list[0]);
2457	} else {
2458	ld->dc_tx_list[i].dc_next =
2459	vtophys(&ld->dc_tx_list[i + 1]);
2460	}
2461	cd->dc_tx_chain[i] = NULL;
2462	ld->dc_tx_list[i].dc_data = 0;
2463	ld->dc_tx_list[i].dc_ctl = 0;
2464	}
2465
2466	cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2467
2468	return(0);
2469	}
2470
2471
2472	/*
2473	* Initialize the RX descriptors and allocate mbufs for them. Note that
2474	* we arrange the descriptors in a closed ring, so that the last descriptor
2475	* points back to the first.
2476	*/
2477	static int dc_list_rx_init(sc)
2478	struct dc_softc *sc;
2479	{
2480	struct dc_chain_data *cd;
2481	struct dc_list_data *ld;
2482	int i;
2483
2484	cd = &sc->dc_cdata;
2485	ld = sc->dc_ldata;
2486
2487	for (i = 0; i < DC_RX_LIST_CNT; i++) {
2488	if (dc_newbuf(sc, i, NULL) == ENOBUFS)
2489	return(ENOBUFS);
2490	if (i == (DC_RX_LIST_CNT - 1)) {
2491	ld->dc_rx_list[i].dc_next =
2492	vtophys(&ld->dc_rx_list[0]);
2493	} else {
2494	ld->dc_rx_list[i].dc_next =
2495	vtophys(&ld->dc_rx_list[i + 1]);
2496	}
2497	}
2498
2499	cd->dc_rx_prod = 0;
2500
2501	return(0);
2502	}
2503
2504	/*
2505	* Initialize an RX descriptor and attach an MBUF cluster.
2506	*/
2507	static int dc_newbuf(sc, i, m)
2508	struct dc_softc *sc;
2509	int i;
2510	struct mbuf *m;
2511	{
2512	struct mbuf *m_new = NULL;
2513	struct dc_desc *c;
2514
2515	c = &sc->dc_ldata->dc_rx_list[i];
2516
2517	if (m == NULL) {
2518	MGETHDR(m_new, M_DONTWAIT, MT_DATA);
2519	if (m_new == NULL)
2520	return(ENOBUFS);
2521
2522	MCLGET(m_new, M_DONTWAIT);
2523	if (!(m_new->m_flags & M_EXT)) {
2524	m_freem(m_new);
2525	return(ENOBUFS);
2526	}
2527	m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2528	} else {
2529	m_new = m;
2530	m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2531	m_new->m_data = m_new->m_ext.ext_buf;
2532	}
2533
2534	m_adj(m_new, sizeof(u_int64_t));
2535
2536	/*
2537	* If this is a PNIC chip, zero the buffer. This is part
2538	* of the workaround for the receive bug in the 82c168 and
2539	* 82c169 chips.
2540	*/
2541	if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2542	bzero((char )mtod(m_new, char ), m_new->m_len);
2543
2544	sc->dc_cdata.dc_rx_chain[i] = m_new;
2545	c->dc_data = vtophys(mtod(m_new, caddr_t));
2546	c->dc_ctl = DC_RXCTL_RLINK \| DC_RXLEN;
2547	c->dc_status = DC_RXSTAT_OWN;
2548
2549	return(0);
2550	}
2551
2552	/*
2553	* Grrrrr.
2554	* The PNIC chip has a terrible bug in it that manifests itself during
2555	* periods of heavy activity. The exact mode of failure if difficult to
2556	* pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2557	* will happen on slow machines. The bug is that sometimes instead of
2558	* uploading one complete frame during reception, it uploads what looks
2559	* like the entire contents of its FIFO memory. The frame we want is at
2560	* the end of the whole mess, but we never know exactly how much data has
2561	* been uploaded, so salvaging the frame is hard.
2562	*
2563	* There is only one way to do it reliably, and it's disgusting.
2564	* Here's what we know:
2565	*
2566	* - We know there will always be somewhere between one and three extra
2567	* descriptors uploaded.
2568	*
2569	* - We know the desired received frame will always be at the end of the
2570	* total data upload.
2571	*
2572	* - We know the size of the desired received frame because it will be
2573	* provided in the length field of the status word in the last descriptor.
2574	*
2575	* Here's what we do:
2576	*
2577	* - When we allocate buffers for the receive ring, we bzero() them.
2578	* This means that we know that the buffer contents should be all
2579	* zeros, except for data uploaded by the chip.
2580	*
2581	* - We also force the PNIC chip to upload frames that include the
2582	* ethernet CRC at the end.
2583	*
2584	* - We gather all of the bogus frame data into a single buffer.
2585	*
2586	* - We then position a pointer at the end of this buffer and scan
2587	* backwards until we encounter the first non-zero byte of data.
2588	* This is the end of the received frame. We know we will encounter
2589	* some data at the end of the frame because the CRC will always be
2590	* there, so even if the sender transmits a packet of all zeros,
2591	* we won't be fooled.
2592	*
2593	* - We know the size of the actual received frame, so we subtract
2594	* that value from the current pointer location. This brings us
2595	* to the start of the actual received packet.
2596	*
2597	* - We copy this into an mbuf and pass it on, along with the actual
2598	* frame length.
2599	*
2600	* The performance hit is tremendous, but it beats dropping frames all
2601	* the time.
2602	*/
2603
2604	#define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG\|DC_RXSTAT_LASTFRAG)
2605	static void dc_pnic_rx_bug_war(sc, idx)
2606	struct dc_softc *sc;
2607	int idx;
2608	{
2609	struct dc_desc *cur_rx;
2610	struct dc_desc *c = NULL;
2611	struct mbuf *m = NULL;
2612	unsigned char *ptr;
2613	int i, total_len;
2614	u_int32_t rxstat = 0;
2615
2616	i = sc->dc_pnic_rx_bug_save;
2617	cur_rx = &sc->dc_ldata->dc_rx_list[idx];
2618	ptr = sc->dc_pnic_rx_buf;
2619	bzero(ptr, sizeof(DC_RXLEN * 5));
2620
2621	/* Copy all the bytes from the bogus buffers. */
2622	while (1) {
2623	c = &sc->dc_ldata->dc_rx_list[i];
2624	rxstat = c->dc_status;
2625	m = sc->dc_cdata.dc_rx_chain[i];
2626	bcopy(mtod(m, char *), ptr, DC_RXLEN);
2627	ptr += DC_RXLEN;
2628	/* If this is the last buffer, break out. */
2629	if (i == idx \|\| rxstat & DC_RXSTAT_LASTFRAG)
2630	break;
2631	dc_newbuf(sc, i, m);
2632	DC_INC(i, DC_RX_LIST_CNT);
2633	}
2634
2635	/* Find the length of the actual receive frame. */
2636	total_len = DC_RXBYTES(rxstat);
2637
2638	/* Scan backwards until we hit a non-zero byte. */
2639	while(*ptr == 0x00)
2640	ptr--;
2641	#if 0
2642	/* Round off. */
2643	if ((uintptr_t)(ptr) & 0x3)
2644	ptr -= 1;
2645	#endif
2646
2647	/* Now find the start of the frame. */
2648	ptr -= total_len;
2649	if (ptr < sc->dc_pnic_rx_buf)
2650	ptr = sc->dc_pnic_rx_buf;
2651
2652	/*
2653	* Now copy the salvaged frame to the last mbuf and fake up
2654	* the status word to make it look like a successful
2655	* frame reception.
2656	*/
2657	dc_newbuf(sc, i, m);
2658	bcopy(ptr, mtod(m, char *), total_len);
2659	cur_rx->dc_status = rxstat \| DC_RXSTAT_FIRSTFRAG;
2660
2661	return;
2662	}
2663
2664	/*
2665	* This routine searches the RX ring for dirty descriptors in the
2666	* event that the rxeof routine falls out of sync with the chip's
2667	* current descriptor pointer. This may happen sometimes as a result
2668	* of a "no RX buffer available" condition that happens when the chip
2669	* consumes all of the RX buffers before the driver has a chance to
2670	* process the RX ring. This routine may need to be called more than
2671	* once to bring the driver back in sync with the chip, however we
2672	* should still be getting RX DONE interrupts to drive the search
2673	* for new packets in the RX ring, so we should catch up eventually.
2674	*/
2675	static int dc_rx_resync(sc)
2676	struct dc_softc *sc;
2677	{
2678	int i, pos;
2679	struct dc_desc *cur_rx;
2680
2681	pos = sc->dc_cdata.dc_rx_prod;
2682
2683	for (i = 0; i < DC_RX_LIST_CNT; i++) {
2684	cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2685	if (!(cur_rx->dc_status & DC_RXSTAT_OWN))
2686	break;
2687	DC_INC(pos, DC_RX_LIST_CNT);
2688	}
2689
2690	/* If the ring really is empty, then just return. */
2691	if (i == DC_RX_LIST_CNT)
2692	return(0);
2693
2694	/* We've fallen behing the chip: catch it. */
2695	sc->dc_cdata.dc_rx_prod = pos;
2696
2697	return(EAGAIN);
2698	}
2699
2700	/*
2701	* A frame has been uploaded: pass the resulting mbuf chain up to
2702	* the higher level protocols.
2703	*/
2704	static void dc_rxeof(sc)
2705	struct dc_softc *sc;
2706	{
2707	struct ether_header *eh;
2708	struct mbuf *m;
2709	struct ifnet *ifp;
2710	struct dc_desc *cur_rx;
2711	int i, total_len = 0;
2712	u_int32_t rxstat;
2713
2714	ifp = &sc->arpcom.ac_if;
2715	i = sc->dc_cdata.dc_rx_prod;
2716
2717	while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) {
2718
2719	#ifdef DEVICE_POLLING
2720	if (ifp->if_ipending & IFF_POLLING) {
2721	if (sc->rxcycles <= 0)
2722	break;
2723	sc->rxcycles--;
2724	}
2725	#endif /* DEVICE_POLLING */
2726	cur_rx = &sc->dc_ldata->dc_rx_list[i];
2727	rxstat = cur_rx->dc_status;
2728	m = sc->dc_cdata.dc_rx_chain[i];
2729	total_len = DC_RXBYTES(rxstat);
2730
2731	if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2732	if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2733	if (rxstat & DC_RXSTAT_FIRSTFRAG)
2734	sc->dc_pnic_rx_bug_save = i;
2735	if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
2736	DC_INC(i, DC_RX_LIST_CNT);
2737	continue;
2738	}
2739	dc_pnic_rx_bug_war(sc, i);
2740	rxstat = cur_rx->dc_status;
2741	total_len = DC_RXBYTES(rxstat);
2742	}
2743	}
2744
2745	sc->dc_cdata.dc_rx_chain[i] = NULL;
2746
2747	/*
2748	* If an error occurs, update stats, clear the
2749	* status word and leave the mbuf cluster in place:
2750	* it should simply get re-used next time this descriptor
2751	* comes up in the ring. However, don't report long
2752	* frames as errors since they could be vlans
2753	*/
2754	if ((rxstat & DC_RXSTAT_RXERR)){
2755	if (!(rxstat & DC_RXSTAT_GIANT) \|\|
2756	(rxstat & (DC_RXSTAT_CRCERR \| DC_RXSTAT_DRIBBLE \|
2757	DC_RXSTAT_MIIERE \| DC_RXSTAT_COLLSEEN \|
2758	DC_RXSTAT_RUNT \| DC_RXSTAT_DE))) {
2759	ifp->if_ierrors++;
2760	if (rxstat & DC_RXSTAT_COLLSEEN)
2761	ifp->if_collisions++;
2762	dc_newbuf(sc, i, m);
2763	if (rxstat & DC_RXSTAT_CRCERR) {
2764	DC_INC(i, DC_RX_LIST_CNT);
2765	continue;
2766	} else {
2767	dc_init(sc);
2768	return;
2769	}
2770	}
2771	}
2772
2773	/* No errors; receive the packet. */
2774	total_len -= ETHER_CRC_LEN;
2775
2776	#ifdef __i386__
2777	/*
2778	* On the x86 we do not have alignment problems, so try to
2779	* allocate a new buffer for the receive ring, and pass up
2780	* the one where the packet is already, saving the expensive
2781	* copy done in m_devget().
2782	* If we are on an architecture with alignment problems, or
2783	* if the allocation fails, then use m_devget and leave the
2784	* existing buffer in the receive ring.
2785	*/
2786	if (dc_quick && dc_newbuf(sc, i, NULL) == 0) {
2787	m->m_pkthdr.rcvif = ifp;
2788	m->m_pkthdr.len = m->m_len = total_len;
2789	DC_INC(i, DC_RX_LIST_CNT);
2790	} else
2791	#endif
2792	{
2793	struct mbuf *m0;
2794
2795	m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
2796	total_len + ETHER_ALIGN, 0, ifp, NULL);
2797	dc_newbuf(sc, i, m);
2798	DC_INC(i, DC_RX_LIST_CNT);
2799	if (m0 == NULL) {
2800	ifp->if_ierrors++;
2801	continue;
2802	}
2803	m_adj(m0, ETHER_ALIGN);
2804	m = m0;
2805	}
2806
2807	ifp->if_ipackets++;
2808	eh = mtod(m, struct ether_header *);
2809
2810	/* Remove header from mbuf and pass it on. */
2811	m_adj(m, sizeof(struct ether_header));
2812	ether_input(ifp, eh, m);
2813	}
2814
2815	sc->dc_cdata.dc_rx_prod = i;
2816	}
2817
2818	/*
2819	* A frame was downloaded to the chip. It's safe for us to clean up
2820	* the list buffers.
2821	*/
2822
2823	static void
2824	dc_txeof(sc)
2825	struct dc_softc *sc;
2826	{
2827	struct dc_desc *cur_tx = NULL;
2828	struct ifnet *ifp;
2829	int idx;
2830
2831	ifp = &sc->arpcom.ac_if;
2832
2833	/*
2834	* Go through our tx list and free mbufs for those
2835	* frames that have been transmitted.
2836	*/
2837	idx = sc->dc_cdata.dc_tx_cons;
2838	while(idx != sc->dc_cdata.dc_tx_prod) {
2839	u_int32_t txstat;
2840
2841	cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2842	txstat = cur_tx->dc_status;
2843
2844	if (txstat & DC_TXSTAT_OWN)
2845	break;
2846
2847	if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) \|\|
2848	cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2849	if (cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2850	/*
2851	* Yes, the PNIC is so brain damaged
2852	* that it will sometimes generate a TX
2853	* underrun error while DMAing the RX
2854	* filter setup frame. If we detect this,
2855	* we have to send the setup frame again,
2856	* or else the filter won't be programmed
2857	* correctly.
2858	*/
2859	if (DC_IS_PNIC(sc)) {
2860	if (txstat & DC_TXSTAT_ERRSUM)
2861	dc_setfilt(sc);
2862	}
2863	sc->dc_cdata.dc_tx_chain[idx] = NULL;
2864	}
2865	sc->dc_cdata.dc_tx_cnt--;
2866	DC_INC(idx, DC_TX_LIST_CNT);
2867	continue;
2868	}
2869
2870	if (DC_IS_CONEXANT(sc)) {
2871	/*
2872	* For some reason Conexant chips like
2873	* setting the CARRLOST flag even when
2874	* the carrier is there. In CURRENT we
2875	* have the same problem for Xircom
2876	* cards !
2877	*/
2878	if (/sc->dc_type == DC_TYPE_21143 &&/
2879	sc->dc_pmode == DC_PMODE_MII &&
2880	((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM\|
2881	DC_TXSTAT_NOCARRIER)))
2882	txstat &= ~DC_TXSTAT_ERRSUM;
2883	} else {
2884	if (/sc->dc_type == DC_TYPE_21143 &&/
2885	sc->dc_pmode == DC_PMODE_MII &&
2886	((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM\|
2887	DC_TXSTAT_NOCARRIER\|DC_TXSTAT_CARRLOST)))
2888	txstat &= ~DC_TXSTAT_ERRSUM;
2889	}
2890
2891	if (txstat & DC_TXSTAT_ERRSUM) {
2892	ifp->if_oerrors++;
2893	if (txstat & DC_TXSTAT_EXCESSCOLL)
2894	ifp->if_collisions++;
2895	if (txstat & DC_TXSTAT_LATECOLL)
2896	ifp->if_collisions++;
2897	if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2898	dc_init(sc);
2899	return;
2900	}
2901	}
2902
2903	ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2904
2905	ifp->if_opackets++;
2906	if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
2907	m_freem(sc->dc_cdata.dc_tx_chain[idx]);
2908	sc->dc_cdata.dc_tx_chain[idx] = NULL;
2909	}
2910
2911	sc->dc_cdata.dc_tx_cnt--;
2912	DC_INC(idx, DC_TX_LIST_CNT);
2913	}
2914
2915	if (idx != sc->dc_cdata.dc_tx_cons) {
2916	/* some buffers have been freed */
2917	sc->dc_cdata.dc_tx_cons = idx;
2918	ifp->if_flags &= ~IFF_OACTIVE;
2919	}
2920	ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5;
2921
2922	return;
2923	}
2924
2925
2926	#if 0
2927	static void dc_tick(xsc)
2928	void *xsc;
2929	{
2930	struct dc_softc *sc;
2931	/struct mii_data mii;*/
2932	struct ifnet *ifp;
2933	int s;
2934	u_int32_t r;
2935
2936
2937	sc = xsc;
2938	ifp = &sc->arpcom.ac_if;
2939	mii = device_get_softc(sc->dc_miibus);
2940
2941	if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2942	if (sc->dc_flags & DC_21143_NWAY) {
2943	r = CSR_READ_4(sc, DC_10BTSTAT);
2944	if (IFM_SUBTYPE(mii->mii_media_active) ==
2945	IFM_100_TX && (r & DC_TSTAT_LS100)) {
2946	sc->dc_link = 0;
2947	mii_mediachg(mii);
2948	}
2949	if (IFM_SUBTYPE(mii->mii_media_active) ==
2950	IFM_10_T && (r & DC_TSTAT_LS10)) {
2951	sc->dc_link = 0;
2952	mii_mediachg(mii);
2953	}
2954	if (sc->dc_link == 0)
2955	mii_tick(mii);
2956	} else {
2957	r = CSR_READ_4(sc, DC_ISR);
2958	if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT &&
2959	sc->dc_cdata.dc_tx_cnt == 0)
2960	mii_tick(mii);
2961	if (!(mii->mii_media_status & IFM_ACTIVE))
2962	sc->dc_link = 0;
2963	}
2964	} else
2965	mii_tick(mii);
2966
2967	/*
2968	* When the init routine completes, we expect to be able to send
2969	* packets right away, and in fact the network code will send a
2970	* gratuitous ARP the moment the init routine marks the interface
2971	* as running. However, even though the MAC may have been initialized,
2972	* there may be a delay of a few seconds before the PHY completes
2973	* autonegotiation and the link is brought up. Any transmissions
2974	* made during that delay will be lost. Dealing with this is tricky:
2975	* we can't just pause in the init routine while waiting for the
2976	* PHY to come ready since that would bring the whole system to
2977	* a screeching halt for several seconds.
2978	*
2979	* What we do here is prevent the TX start routine from sending
2980	* any packets until a link has been established. After the
2981	* interface has been initialized, the tick routine will poll
2982	* the state of the PHY until the IFM_ACTIVE flag is set. Until
2983	* that time, packets will stay in the send queue, and once the
2984	* link comes up, they will be flushed out to the wire.
2985	*/
2986	if (!sc->dc_link) {
2987	mii_pollstat(mii);
2988	if (mii->mii_media_status & IFM_ACTIVE &&
2989	IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2990	sc->dc_link++;
2991	if (ifp->if_snd.ifq_head != NULL)
2992	dc_start(ifp);
2993	}
2994	}
2995
2996	if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2997	sc->dc_stat_ch = timeout(dc_tick, sc, hz/10);
2998	else
2999	sc->dc_stat_ch = timeout(dc_tick, sc, hz);
3000
3001	return;
3002	}
3003	#endif
3004
3005	/*
3006	* A transmit underrun has occurred. Back off the transmit threshold,
3007	* or switch to store and forward mode if we have to.
3008	*/
3009	static void dc_tx_underrun(sc)
3010	struct dc_softc *sc;
3011	{
3012	u_int32_t isr;
3013	int i;
3014
3015	if (DC_IS_DAVICOM(sc))
3016	dc_init(sc);
3017
3018	if (DC_IS_INTEL(sc)) {
3019	/*
3020	* The real 21143 requires that the transmitter be idle
3021	* in order to change the transmit threshold or store
3022	* and forward state.
3023	*/
3024	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3025
3026	for (i = 0; i < DC_TIMEOUT; i++) {
3027	isr = CSR_READ_4(sc, DC_ISR);
3028	if (isr & DC_ISR_TX_IDLE)
3029	break;
3030	DELAY(10);
3031	}
3032	if (i == DC_TIMEOUT) {
3033	printk("dc%d: failed to force tx to idle state\n",
3034	sc->dc_unit);
3035	dc_init(sc);
3036	}
3037	}
3038
3039	printk("dc%d: TX underrun -- ", sc->dc_unit);
3040	sc->dc_txthresh += DC_TXTHRESH_INC;
3041	if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3042	printk("using store and forward mode\n");
3043	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3044	} else {
3045	printk("increasing TX threshold\n");
3046	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3047	DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3048	}
3049
3050	if (DC_IS_INTEL(sc))
3051	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3052
3053	return;
3054	}
3055
3056	#ifdef DEVICE_POLLING
3057	static poll_handler_t dc_poll;
3058
3059	static void
3060	dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3061	{
3062	struct dc_softc *sc = ifp->if_softc;
3063
3064	if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
3065	/* Re-enable interrupts. */
3066	CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3067	return;
3068	}
3069	sc->rxcycles = count;
3070	dc_rxeof(sc);
3071	dc_txeof(sc);
3072	if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE))
3073	dc_start(ifp);
3074
3075	if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
3076	u_int32_t status;
3077
3078	status = CSR_READ_4(sc, DC_ISR);
3079	status &= (DC_ISR_RX_WATDOGTIMEO\|DC_ISR_RX_NOBUF\|
3080	DC_ISR_TX_NOBUF\|DC_ISR_TX_IDLE\|DC_ISR_TX_UNDERRUN\|
3081	DC_ISR_BUS_ERR);
3082	if (!status)
3083	return ;
3084	/* ack what we have */
3085	CSR_WRITE_4(sc, DC_ISR, status);
3086
3087	if (status & (DC_ISR_RX_WATDOGTIMEO\|DC_ISR_RX_NOBUF) ) {
3088	u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3089	ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
3090
3091	if (dc_rx_resync(sc))
3092	dc_rxeof(sc);
3093	}
3094	/* restart transmit unit if necessary */
3095	if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
3096	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3097
3098	if (status & DC_ISR_TX_UNDERRUN)
3099	dc_tx_underrun(sc);
3100
3101	if (status & DC_ISR_BUS_ERR) {
3102	printk("dc_poll: dc%d bus error\n", sc->dc_unit);
3103	dc_reset(sc);
3104	dc_init(sc);
3105	}
3106	}
3107	}
3108	#endif /* DEVICE_POLLING */
3109
3110	static void
3111	dc_intr(void* arg)
3112	{
3113	/* Need to make this work for multiple devices ... eventually */
3114	struct dc_softc sc = (struct dc_softc )arg;
3115
3116
3117	/* Disable interrupts. */
3118	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3119
3120	rtems_event_send(sc->daemontid, IRQ_EVENT);
3121	#if 0
3122	if (sc->suspended) {
3123	return;
3124	}
3125
3126	ifp = &sc->arpcom.ac_if;
3127
3128	#ifdef DEVICE_POLLING
3129	if (ifp->if_ipending & IFF_POLLING)
3130	return;
3131	if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */
3132	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3133	return;
3134	}
3135	#endif /* DEVICE_POLLING */
3136	if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
3137	return ;
3138
3139	/* Suppress unwanted interrupts */
3140	if (!(ifp->if_flags & IFF_UP)) {
3141	if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
3142	dc_stop(sc);
3143	return;
3144	}
3145	#endif
3146	}
3147
3148
3149	static void
3150	dc_daemon(void * arg)
3151	{
3152	struct dc_softc sc = (struct dc_softc )arg;
3153	struct ifnet *ifp;
3154	u_int32_t status;
3155	rtems_event_set events;
3156
3157
3158	for(;;) {
3159	rtems_bsdnet_event_receive(RTEMS_ALL_EVENTS, \
3160	RTEMS_WAIT \| RTEMS_EVENT_ANY, \
3161	RTEMS_NO_TIMEOUT,
3162	&events);
3163
3164
3165	ifp = &sc->arpcom.ac_if;
3166
3167	while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) {
3168
3169	CSR_WRITE_4(sc, DC_ISR, status);
3170
3171	if (status & DC_ISR_RX_OK) {
3172	int curpkts;
3173	curpkts = ifp->if_ipackets;
3174	dc_rxeof(sc);
3175	if (curpkts == ifp->if_ipackets) {
3176	while(dc_rx_resync(sc))
3177	dc_rxeof(sc);
3178	}
3179	}
3180
3181	if (status & (DC_ISR_TX_OK\|DC_ISR_TX_NOBUF))
3182	dc_txeof(sc);
3183
3184	if (status & DC_ISR_TX_IDLE) {
3185	dc_txeof(sc);
3186	if (sc->dc_cdata.dc_tx_cnt) {
3187	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3188	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3189	}
3190	}
3191
3192	if (status & DC_ISR_TX_UNDERRUN)
3193	dc_tx_underrun(sc);
3194
3195	if ((status & DC_ISR_RX_WATDOGTIMEO)
3196	\|\| (status & DC_ISR_RX_NOBUF)) {
3197	int curpkts;
3198	curpkts = ifp->if_ipackets;
3199	dc_rxeof(sc);
3200	if (curpkts == ifp->if_ipackets) {
3201	while(dc_rx_resync(sc))
3202	dc_rxeof(sc);
3203	}
3204	}
3205
3206	if (status & DC_ISR_BUS_ERR) {
3207	dc_reset(sc);
3208	dc_init(sc);
3209	}
3210	}
3211
3212	/* Make atomic !!! */
3213	/* Re-enable interrupts. */
3214	CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3215
3216	if (ifp->if_snd.ifq_head != NULL)
3217	dc_start(ifp);
3218	}
3219
3220	}
3221
3222
3223	/*
3224	* Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
3225	* pointers to the fragment pointers.
3226	*/
3227	static int dc_encap(sc, m_head, txidx)
3228	struct dc_softc *sc;
3229	struct mbuf *m_head;
3230	u_int32_t *txidx;
3231	{
3232	struct dc_desc *f = NULL;
3233	struct mbuf *m;
3234	int frag, cur, cnt = 0;
3235
3236	/*
3237	* Start packing the mbufs in this chain into
3238	* the fragment pointers. Stop when we run out
3239	* of fragments or hit the end of the mbuf chain.
3240	*/
3241	m = m_head;
3242	cur = frag = *txidx;
3243
3244	for (m = m_head; m != NULL; m = m->m_next) {
3245	if (m->m_len != 0) {
3246	if (sc->dc_flags & DC_TX_ADMTEK_WAR) {
3247	if (*txidx != sc->dc_cdata.dc_tx_prod &&
3248	frag == (DC_TX_LIST_CNT - 1))
3249	return(ENOBUFS);
3250	}
3251	if ((DC_TX_LIST_CNT -
3252	(sc->dc_cdata.dc_tx_cnt + cnt)) < 5)
3253	return(ENOBUFS);
3254
3255	f = &sc->dc_ldata->dc_tx_list[frag];
3256	f->dc_ctl = DC_TXCTL_TLINK \| m->m_len;
3257	if (cnt == 0) {
3258	f->dc_status = 0;
3259	f->dc_ctl \|= DC_TXCTL_FIRSTFRAG;
3260	} else
3261	f->dc_status = DC_TXSTAT_OWN;
3262	f->dc_data = vtophys(mtod(m, vm_offset_t));
3263	cur = frag;
3264	DC_INC(frag, DC_TX_LIST_CNT);
3265	cnt++;
3266	}
3267	}
3268
3269	if (m != NULL)
3270	return(ENOBUFS);
3271
3272	sc->dc_cdata.dc_tx_cnt += cnt;
3273	sc->dc_cdata.dc_tx_chain[cur] = m_head;
3274	sc->dc_ldata->dc_tx_list[cur].dc_ctl \|= DC_TXCTL_LASTFRAG;
3275	if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3276	sc->dc_ldata->dc_tx_list[*txidx].dc_ctl \|= DC_TXCTL_FINT;
3277	if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3278	sc->dc_ldata->dc_tx_list[cur].dc_ctl \|= DC_TXCTL_FINT;
3279	if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
3280	sc->dc_ldata->dc_tx_list[cur].dc_ctl \|= DC_TXCTL_FINT;
3281	sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN;
3282	*txidx = frag;
3283
3284	return(0);
3285	}
3286
3287	/*
3288	* Coalesce an mbuf chain into a single mbuf cluster buffer.
3289	* Needed for some really badly behaved chips that just can't
3290	* do scatter/gather correctly.
3291	*/
3292	static int dc_coal(sc, m_head)
3293	struct dc_softc *sc;
3294	struct mbuf **m_head;
3295	{
3296	struct mbuf m_new, m;
3297
3298	m = *m_head;
3299	MGETHDR(m_new, M_DONTWAIT, MT_DATA);
3300	if (m_new == NULL)
3301	return(ENOBUFS);
3302	if (m->m_pkthdr.len > MHLEN) {
3303	MCLGET(m_new, M_DONTWAIT);
3304	if (!(m_new->m_flags & M_EXT)) {
3305	m_freem(m_new);
3306	return(ENOBUFS);
3307	}
3308	}
3309	m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t));
3310	m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len;
3311	m_freem(m);
3312	*m_head = m_new;
3313
3314	return(0);
3315	}
3316
3317	/*
3318	* Main transmit routine. To avoid having to do mbuf copies, we put pointers
3319	* to the mbuf data regions directly in the transmit lists. We also save a
3320	* copy of the pointers since the transmit list fragment pointers are
3321	* physical addresses.
3322	*/
3323
3324	static void dc_start(ifp)
3325	struct ifnet *ifp;
3326	{
3327	struct dc_softc *sc;
3328	struct mbuf *m_head = NULL;
3329	unsigned int idx;
3330
3331	sc = ifp->if_softc;
3332	#if 0
3333	if (!sc->dc_link && ifp->if_snd.ifq_len < 10)
3334	return;
3335	#endif
3336	if (ifp->if_flags & IFF_OACTIVE)
3337	return;
3338
3339	idx = sc->dc_cdata.dc_tx_prod;
3340
3341	while(sc->dc_cdata.dc_tx_chain[idx] == NULL) {
3342	IF_DEQUEUE(&ifp->if_snd, m_head);
3343	if (m_head == NULL)
3344	break;
3345
3346	if (sc->dc_flags & DC_TX_COALESCE &&
3347	m_head->m_next != NULL) {
3348	/* only coalesce if have >1 mbufs */
3349	if (dc_coal(sc, &m_head)) {
3350	IF_PREPEND(&ifp->if_snd, m_head);
3351	ifp->if_flags \|= IFF_OACTIVE;
3352	break;
3353	}
3354	}
3355
3356	if (dc_encap(sc, m_head, &idx)) {
3357	IF_PREPEND(&ifp->if_snd, m_head);
3358	ifp->if_flags \|= IFF_OACTIVE;
3359	break;
3360	}
3361	#if 0
3362	/*
3363	* If there's a BPF listener, bounce a copy of this frame
3364	* to him.
3365	*/
3366	if (ifp->if_bpf)
3367	bpf_mtap(ifp, m_head);
3368	#endif
3369	if (sc->dc_flags & DC_TX_ONE) {
3370	ifp->if_flags \|= IFF_OACTIVE;
3371	break;
3372	}
3373	}
3374
3375	/* Transmit */
3376	sc->dc_cdata.dc_tx_prod = idx;
3377	if (!(sc->dc_flags & DC_TX_POLL))
3378	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3379
3380	/*
3381	* Set a timeout in case the chip goes out to lunch.
3382	*/
3383	ifp->if_timer = 5;
3384
3385	return;
3386	}
3387
3388	static void dc_init(xsc)
3389	void *xsc;
3390	{
3391	struct dc_softc *sc = xsc;
3392	struct ifnet *ifp = &sc->arpcom.ac_if;
3393	/struct mii_data mii;*/
3394
3395
3396	/mii = device_get_softc(sc->dc_miibus);/
3397
3398	/*
3399	* Cancel pending I/O and free all RX/TX buffers.
3400	*/
3401	dc_stop(sc);
3402	dc_reset(sc);
3403
3404	/*
3405	* Set cache alignment and burst length.
3406	*/
3407	if (DC_IS_ASIX(sc) \|\| DC_IS_DAVICOM(sc))
3408	CSR_WRITE_4(sc, DC_BUSCTL, 0);
3409	else
3410	CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME\|DC_BUSCTL_MRLE);
3411	/*
3412	* Evenly share the bus between receive and transmit process.
3413	*/
3414	if (DC_IS_INTEL(sc))
3415	DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3416	if (DC_IS_DAVICOM(sc) \|\| DC_IS_INTEL(sc)) {
3417	DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3418	} else {
3419	DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3420	}
3421	if (sc->dc_flags & DC_TX_POLL)
3422	DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3423	switch(sc->dc_cachesize) {
3424	case 32:
3425	DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3426	break;
3427	case 16:
3428	DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3429	break;
3430	case 8:
3431	DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3432	break;
3433	case 0:
3434	default:
3435	DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3436	break;
3437	}
3438
3439	if (sc->dc_flags & DC_TX_STORENFWD)
3440	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3441	else {
3442	if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3443	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3444	} else {
3445	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3446	DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3447	}
3448	}
3449
3450	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3451	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3452
3453	if (DC_IS_MACRONIX(sc) \|\| DC_IS_PNICII(sc)) {
3454	/*
3455	* The app notes for the 98713 and 98715A say that
3456	* in order to have the chips operate properly, a magic
3457	* number must be written to CSR16. Macronix does not
3458	* document the meaning of these bits so there's no way
3459	* to know exactly what they do. The 98713 has a magic
3460	* number all its own; the rest all use a different one.
3461	*/
3462	DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3463	if (sc->dc_type == DC_TYPE_98713)
3464	DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3465	else
3466	DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3467	}
3468
3469	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3470	DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3471
3472	/* Init circular RX list. */
3473	if (dc_list_rx_init(sc) == ENOBUFS) {
3474	printk("dc%d: initialization failed: no "
3475	"memory for rx buffers\n", sc->dc_unit);
3476	dc_stop(sc);
3477	return;
3478	}
3479
3480	/*
3481	* Init tx descriptors.
3482	*/
3483	dc_list_tx_init(sc);
3484
3485	/*
3486	* Load the address of the RX list.
3487	*/
3488	CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0]));
3489	CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0]));
3490
3491	/*
3492	* Enable interrupts.
3493	*/
3494	#ifdef DEVICE_POLLING
3495	/*
3496	* ... but only if we are not polling, and make sure they are off in
3497	* the case of polling. Some cards (e.g. fxp) turn interrupts on
3498	* after a reset.
3499	*/
3500	if (ifp->if_ipending & IFF_POLLING)
3501	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3502	else
3503	#endif
3504	/* Enable interrupts */
3505	CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3506	CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3507
3508	/* Enable transmitter. */
3509	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3510
3511	/*
3512	* If this is an Intel 21143 and we're not using the
3513	* MII port, program the LED control pins so we get
3514	* link and activity indications.
3515	*/
3516	if (sc->dc_flags & DC_TULIP_LEDS) {
3517	CSR_WRITE_4(sc, DC_WATCHDOG,
3518	DC_WDOG_CTLWREN\|DC_WDOG_LINK\|DC_WDOG_ACTIVITY);
3519	CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3520	}
3521
3522	/*
3523	* Load the RX/multicast filter. We do this sort of late
3524	* because the filter programming scheme on the 21143 and
3525	* some clones requires DMAing a setup frame via the TX
3526	* engine, and we need the transmitter enabled for that.
3527	*/
3528	dc_setfilt(sc);
3529
3530	/* Enable receiver. */
3531	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3532	CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3533
3534	/mii_mediachg(mii);/
3535	dc_setcfg(sc, sc->dc_if_media);
3536
3537	ifp->if_flags \|= IFF_RUNNING;
3538	ifp->if_flags &= ~IFF_OACTIVE;
3539
3540
3541	#if 0
3542
3543	/* Don't start the ticker if this is a homePNA link. */
3544	if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_homePNA)
3545	sc->dc_link = 1;
3546	else {
3547	if (sc->dc_flags & DC_21143_NWAY)
3548	sc->dc_stat_ch = timeout(dc_tick, sc, hz/10);
3549	else
3550	sc->dc_stat_ch = timeout(dc_tick, sc, hz);
3551	}
3552
3553	#ifdef SRM_MEDIA
3554	if(sc->dc_srm_media) {
3555	struct ifreq ifr;
3556
3557	ifr.ifr_media = sc->dc_srm_media;
3558	ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA);
3559	sc->dc_srm_media = 0;
3560	}
3561	#endif
3562	#endif /* end if (0) */
3563	return;
3564	}
3565
3566
3567	#if 0
3568	/*
3569	* Set media options.
3570	*/
3571	static int dc_ifmedia_upd(ifp)
3572	struct ifnet *ifp;
3573	{
3574	struct dc_softc *sc;
3575	struct mii_data *mii;
3576	struct ifmedia *ifm;
3577
3578	sc = ifp->if_softc;
3579	mii = device_get_softc(sc->dc_miibus);
3580	mii_mediachg(mii);
3581	ifm = &mii->mii_media;
3582
3583	if (DC_IS_DAVICOM(sc) &&
3584	IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA)
3585	dc_setcfg(sc, ifm->ifm_media);
3586	else
3587	sc->dc_link = 0;
3588
3589	return(0);
3590	}
3591
3592	/*
3593	* Report current media status.
3594	*/
3595	static void dc_ifmedia_sts(ifp, ifmr)
3596	struct ifnet *ifp;
3597	struct ifmediareq *ifmr;
3598	{
3599	struct dc_softc *sc;
3600	struct mii_data *mii;
3601	struct ifmedia *ifm;
3602
3603	sc = ifp->if_softc;
3604	mii = device_get_softc(sc->dc_miibus);
3605	mii_pollstat(mii);
3606	ifm = &mii->mii_media;
3607	if (DC_IS_DAVICOM(sc)) {
3608	if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) {
3609	ifmr->ifm_active = ifm->ifm_media;
3610	ifmr->ifm_status = 0;
3611	return;
3612	}
3613	}
3614	ifmr->ifm_active = mii->mii_media_active;
3615	ifmr->ifm_status = mii->mii_media_status;
3616
3617	return;
3618	}
3619	#endif
3620
3621
3622	static int dc_ioctl(ifp, command, data)
3623	struct ifnet *ifp;
3624	ioctl_command_t command;
3625	caddr_t data;
3626	{
3627	struct dc_softc *sc = ifp->if_softc;
3628	/struct ifreq ifr = (struct ifreq *) data;
3629	struct mii_data mii;/
3630	int error = 0;
3631
3632
3633	switch(command) {
3634	case SIOCSIFADDR:
3635	case SIOCGIFADDR:
3636	case SIOCSIFMTU:
3637	error = ether_ioctl(ifp, command, data);
3638	break;
3639	case SIOCSIFFLAGS:
3640	if (ifp->if_flags & IFF_UP) {
3641	int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3642	(IFF_PROMISC \| IFF_ALLMULTI);
3643	if (ifp->if_flags & IFF_RUNNING) {
3644	if (need_setfilt)
3645	dc_setfilt(sc);
3646	} else {
3647	sc->dc_txthresh = 0;
3648	dc_init(sc);
3649	}
3650	} else {
3651	if (ifp->if_flags & IFF_RUNNING)
3652	dc_stop(sc);
3653	}
3654	sc->dc_if_flags = ifp->if_flags;
3655	error = 0;
3656	break;
3657	case SIOCADDMULTI:
3658	case SIOCDELMULTI:
3659	dc_setfilt(sc);
3660	error = 0;
3661	break;
3662	#if 0
3663	case SIOCGIFMEDIA:
3664	case SIOCSIFMEDIA:
3665	mii = device_get_softc(sc->dc_miibus);
3666	error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3667	#ifdef SRM_MEDIA
3668	if (sc->dc_srm_media)
3669	sc->dc_srm_media = 0;
3670	#endif
3671	break;
3672	#endif
3673	default:
3674	error = EINVAL;
3675	break;
3676	}
3677
3678
3679	return(error);
3680	}
3681
3682	static void dc_watchdog(ifp)
3683	struct ifnet *ifp;
3684	{
3685	struct dc_softc *sc;
3686
3687	sc = ifp->if_softc;
3688
3689	ifp->if_oerrors++;
3690	printk("dc%d: watchdog timeout\n", sc->dc_unit);
3691
3692	dc_stop(sc);
3693	dc_reset(sc);
3694	dc_init(sc);
3695
3696	if (ifp->if_snd.ifq_head != NULL)
3697	dc_start(ifp);
3698
3699	return;
3700	}
3701
3702	/*
3703	* Stop the adapter and free any mbufs allocated to the
3704	* RX and TX lists.
3705	*/
3706	static void dc_stop(sc)
3707	struct dc_softc *sc;
3708	{
3709	register int i;
3710	struct ifnet *ifp;
3711
3712	ifp = &sc->arpcom.ac_if;
3713	ifp->if_timer = 0;
3714
3715	/untimeout(dc_tick, sc, sc->dc_stat_ch);/
3716
3717	ifp->if_flags &= ~(IFF_RUNNING \| IFF_OACTIVE);
3718	#ifdef DEVICE_POLLING
3719	ether_poll_deregister(ifp);
3720	#endif
3721
3722	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON\|DC_NETCFG_TX_ON));
3723	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3724	CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3725	CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3726	sc->dc_link = 0;
3727
3728	/*
3729	* Free data in the RX lists.
3730	*/
3731	for (i = 0; i < DC_RX_LIST_CNT; i++) {
3732	if (sc->dc_cdata.dc_rx_chain[i] != NULL) {
3733	m_freem(sc->dc_cdata.dc_rx_chain[i]);
3734	sc->dc_cdata.dc_rx_chain[i] = NULL;
3735	}
3736	}
3737	bzero((char *)&sc->dc_ldata->dc_rx_list,
3738	sizeof(sc->dc_ldata->dc_rx_list));
3739
3740	/*
3741	* Free the TX list buffers.
3742	*/
3743	for (i = 0; i < DC_TX_LIST_CNT; i++) {
3744	if (sc->dc_cdata.dc_tx_chain[i] != NULL) {
3745	if (sc->dc_ldata->dc_tx_list[i].dc_ctl &
3746	DC_TXCTL_SETUP) {
3747	sc->dc_cdata.dc_tx_chain[i] = NULL;
3748	continue;
3749	}
3750	m_freem(sc->dc_cdata.dc_tx_chain[i]);
3751	sc->dc_cdata.dc_tx_chain[i] = NULL;
3752	}
3753	}
3754
3755	bzero((char *)&sc->dc_ldata->dc_tx_list,
3756	sizeof(sc->dc_ldata->dc_tx_list));
3757
3758	return;
3759	}
3760
3761
3762	#if 0
3763	/*
3764	* Stop all chip I/O so that the kernel's probe routines don't
3765	* get confused by errant DMAs when rebooting.
3766	*/
3767	static void dc_shutdown(dev)
3768	device_t dev;
3769	{
3770	struct dc_softc *sc;
3771
3772	sc = device_get_softc(dev);
3773
3774	dc_stop(sc);
3775
3776	return;
3777	}
3778
3779	/*
3780	* Device suspend routine. Stop the interface and save some PCI
3781	* settings in case the BIOS doesn't restore them properly on
3782	* resume.
3783	*/
3784	static int dc_suspend(dev)
3785	device_t dev;
3786	{
3787	register int i;
3788	int s;
3789	struct dc_softc *sc;
3790
3791
3792	sc = device_get_softc(dev);
3793
3794	dc_stop(sc);
3795
3796	for (i = 0; i < 5; i++)
3797	sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
3798	sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
3799	sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
3800	sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3801	sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3802
3803	sc->suspended = 1;
3804
3805	return (0);
3806	}
3807
3808	/*
3809	* Device resume routine. Restore some PCI settings in case the BIOS
3810	* doesn't, re-enable busmastering, and restart the interface if
3811	* appropriate.
3812	*/
3813	static int dc_resume(dev)
3814	device_t dev;
3815	{
3816	register int i;
3817	int s;
3818	struct dc_softc *sc;
3819	struct ifnet *ifp;
3820
3821
3822	sc = device_get_softc(dev);
3823	ifp = &sc->arpcom.ac_if;
3824
3825	dc_acpi(dev);
3826
3827	/* better way to do this? */
3828	for (i = 0; i < 5; i++)
3829	pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
3830	pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
3831	pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
3832	pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
3833	pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
3834
3835	/* reenable busmastering */
3836	pci_enable_busmaster(dev);
3837	pci_enable_io(dev, DC_RES);
3838
3839	/* reinitialize interface if necessary */
3840	if (ifp->if_flags & IFF_UP)
3841	dc_init(sc);
3842
3843	sc->suspended = 0;
3844
3845	return (0);
3846	}
3847	#endif
3848
3849	#endif /* end if supported */

Note: See TracBrowser for help on using the repository browser.

Download in other formats: