| 1 | #ifndef MAC_REGS_H |
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| 2 | #define MAC_REGS_H |
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| 3 | |
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| 4 | #include <stdint.h> |
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| 5 | |
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| 6 | #define DWMAC_REGS_BIT32(bit) \ |
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| 7 | ((uint32_t) (((uint32_t) 1) << (bit))) |
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| 8 | |
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| 9 | #define DWMAC_REGS_MSK32(first_bit, last_bit) \ |
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| 10 | ((uint32_t) ((DWMAC_REGS_BIT32((last_bit) - (first_bit) + 1) - 1) << (first_bit))) |
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| 11 | |
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| 12 | #define DWMAC_REGS_FLD32(val, first_bit, last_bit) \ |
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| 13 | ((uint32_t) \ |
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| 14 | ((((uint32_t) (val)) << (first_bit)) & DWMAC_REGS_MSK32(first_bit, last_bit))) |
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| 15 | |
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| 16 | #define DWMAC_REGS_FLD32GET(reg, first_bit, last_bit) \ |
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| 17 | ((uint32_t) (((reg) & DWMAC_REGS_MSK32(first_bit, last_bit)) >> (first_bit))) |
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| 18 | |
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| 19 | #define DWMAC_REGS_FLD32SET(reg, val, first_bit, last_bit) \ |
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| 20 | ((uint32_t) (((reg) & ~DWMAC_REGS_MSK32(first_bit, last_bit)) \ |
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| 21 | | DWMAC_REGS_FLD32(val, first_bit, last_bit))) |
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| 22 | |
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| 23 | typedef struct { |
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| 24 | uint32_t high; |
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| 25 | #define MAC_HIGH_ADDRHI(val) DWMAC_REGS_FLD32(val, 0, 15) |
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| 26 | #define MAC_HIGH_ADDRHI_GET(reg) DWMAC_REGS_FLD32GET(reg, 0, 15) |
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| 27 | #define MAC_HIGH_ADDRHI_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 0, 15) |
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| 28 | #define MAC_HIGH_MBC0 DWMAC_REGS_BIT32(24) |
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| 29 | #define MAC_HIGH_MBC1 DWMAC_REGS_BIT32(25) |
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| 30 | #define MAC_HIGH_MBC2 DWMAC_REGS_BIT32(26) |
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| 31 | #define MAC_HIGH_MBC3 DWMAC_REGS_BIT32(27) |
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| 32 | #define MAC_HIGH_MBC4 DWMAC_REGS_BIT32(28) |
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| 33 | #define MAC_HIGH_MBC5 DWMAC_REGS_BIT32(29) |
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| 34 | #define MAC_HIGH_SA DWMAC_REGS_BIT32(30) |
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| 35 | #define MAC_HIGH_AE DWMAC_REGS_BIT32(31) |
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| 36 | uint32_t low; |
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| 37 | #define MAC_LOW_ADDRLO(val) DWMAC_REGS_FLD32(val, 0, 32) |
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| 38 | #define MAC_LOW_ADDRLO_GET(reg) DWMAC_REGS_FLD32GET(reg, 0, 32) |
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| 39 | #define MAC_LOW_ADDRLO_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 0, 32) |
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| 40 | } mac; |
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| 41 | |
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| 42 | typedef struct { |
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| 43 | uint32_t mac_configuration; |
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| 44 | #define MACGRP_MAC_CONFIGURATION_PRELEN(val) DWMAC_REGS_FLD32(val, 0, 1) |
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| 45 | #define MACGRP_MAC_CONFIGURATION_PRELEN_GET(reg) DWMAC_REGS_FLD32GET(reg, 0, 1) |
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| 46 | #define MACGRP_MAC_CONFIGURATION_PRELEN_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 0, 1) |
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| 47 | #define MACGRP_MAC_CONFIGURATION_RE DWMAC_REGS_BIT32(2) |
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| 48 | #define MACGRP_MAC_CONFIGURATION_TE DWMAC_REGS_BIT32(3) |
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| 49 | #define MACGRP_MAC_CONFIGURATION_DC DWMAC_REGS_BIT32(4) |
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| 50 | #define MACGRP_MAC_CONFIGURATION_BL(val) DWMAC_REGS_FLD32(val, 5, 6) |
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| 51 | #define MACGRP_MAC_CONFIGURATION_BL_GET(reg) DWMAC_REGS_FLD32GET(reg, 5, 6) |
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| 52 | #define MACGRP_MAC_CONFIGURATION_BL_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 5, 6) |
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| 53 | #define MACGRP_MAC_CONFIGURATION_ACS DWMAC_REGS_BIT32(7) |
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| 54 | #define MACGRP_MAC_CONFIGURATION_LUD DWMAC_REGS_BIT32(8) |
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| 55 | #define MACGRP_MAC_CONFIGURATION_DR DWMAC_REGS_BIT32(9) |
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| 56 | #define MACGRP_MAC_CONFIGURATION_IPC DWMAC_REGS_BIT32(10) |
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| 57 | #define MACGRP_MAC_CONFIGURATION_DM DWMAC_REGS_BIT32(11) |
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| 58 | #define MACGRP_MAC_CONFIGURATION_LM DWMAC_REGS_BIT32(12) |
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| 59 | #define MACGRP_MAC_CONFIGURATION_DO DWMAC_REGS_BIT32(13) |
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| 60 | #define MACGRP_MAC_CONFIGURATION_FES DWMAC_REGS_BIT32(14) |
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| 61 | #define MACGRP_MAC_CONFIGURATION_PS DWMAC_REGS_BIT32(15) |
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| 62 | #define MACGRP_MAC_CONFIGURATION_DCRS DWMAC_REGS_BIT32(16) |
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| 63 | #define MACGRP_MAC_CONFIGURATION_IFG(val) DWMAC_REGS_FLD32(val, 17, 19) |
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| 64 | #define MACGRP_MAC_CONFIGURATION_IFG_GET(reg) DWMAC_REGS_FLD32GET(reg, 17, 19) |
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| 65 | #define MACGRP_MAC_CONFIGURATION_IFG_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 17, 19) |
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| 66 | #define MACGRP_MAC_CONFIGURATION_JE DWMAC_REGS_BIT32(20) |
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| 67 | #define MACGRP_MAC_CONFIGURATION_BE DWMAC_REGS_BIT32(21) |
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| 68 | #define MACGRP_MAC_CONFIGURATION_JD DWMAC_REGS_BIT32(22) |
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| 69 | #define MACGRP_MAC_CONFIGURATION_WD DWMAC_REGS_BIT32(23) |
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| 70 | #define MACGRP_MAC_CONFIGURATION_TC DWMAC_REGS_BIT32(24) |
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| 71 | #define MACGRP_MAC_CONFIGURATION_CST DWMAC_REGS_BIT32(25) |
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| 72 | #define MACGRP_MAC_CONFIGURATION_TWOKPE DWMAC_REGS_BIT32(27) |
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| 73 | uint32_t mac_frame_filter; |
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| 74 | #define MACGRP_MAC_FRAME_FILTER_PR DWMAC_REGS_BIT32(0) |
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| 75 | #define MACGRP_MAC_FRAME_FILTER_HUC DWMAC_REGS_BIT32(1) |
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| 76 | #define MACGRP_MAC_FRAME_FILTER_HMC DWMAC_REGS_BIT32(2) |
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| 77 | #define MACGRP_MAC_FRAME_FILTER_DAIF DWMAC_REGS_BIT32(3) |
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| 78 | #define MACGRP_MAC_FRAME_FILTER_PM DWMAC_REGS_BIT32(4) |
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| 79 | #define MACGRP_MAC_FRAME_FILTER_DBF DWMAC_REGS_BIT32(5) |
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| 80 | #define MACGRP_MAC_FRAME_FILTER_PCF(val) DWMAC_REGS_FLD32(val, 6, 7) |
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| 81 | #define MACGRP_MAC_FRAME_FILTER_PCF_GET(reg) DWMAC_REGS_FLD32GET(reg, 6, 7) |
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| 82 | #define MACGRP_MAC_FRAME_FILTER_PCF_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 6, 7) |
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| 83 | #define MACGRP_MAC_FRAME_FILTER_SAIF DWMAC_REGS_BIT32(8) |
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| 84 | #define MACGRP_MAC_FRAME_FILTER_SAF DWMAC_REGS_BIT32(9) |
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| 85 | #define MACGRP_MAC_FRAME_FILTER_HPF DWMAC_REGS_BIT32(10) |
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| 86 | #define MACGRP_MAC_FRAME_FILTER_VTFE DWMAC_REGS_BIT32(16) |
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| 87 | #define MACGRP_MAC_FRAME_FILTER_IPFE DWMAC_REGS_BIT32(20) |
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| 88 | #define MACGRP_MAC_FRAME_FILTER_DNTU DWMAC_REGS_BIT32(21) |
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| 89 | #define MACGRP_MAC_FRAME_FILTER_RA DWMAC_REGS_BIT32(31) |
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| 90 | uint32_t reserved_08[2]; |
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| 91 | uint32_t gmii_address; |
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| 92 | #define MACGRP_GMII_ADDRESS_GMII_BUSY DWMAC_REGS_BIT32(0) |
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| 93 | #define MACGRP_GMII_ADDRESS_GMII_WRITE DWMAC_REGS_BIT32(1) |
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| 94 | #define MACGRP_GMII_ADDRESS_CSR_CLOCK_RANGE(val) DWMAC_REGS_FLD32(val, 2, 5) |
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| 95 | #define MACGRP_GMII_ADDRESS_CSR_CLOCK_RANGE_GET(reg) DWMAC_REGS_FLD32GET(reg, 2, 5) |
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| 96 | #define MACGRP_GMII_ADDRESS_CSR_CLOCK_RANGE_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 2, 5) |
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| 97 | #define MACGRP_GMII_ADDRESS_GMII_REGISTER(val) DWMAC_REGS_FLD32(val, 6, 10) |
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| 98 | #define MACGRP_GMII_ADDRESS_GMII_REGISTER_GET(reg) DWMAC_REGS_FLD32GET(reg, 6, 10) |
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| 99 | #define MACGRP_GMII_ADDRESS_GMII_REGISTER_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 6, 10) |
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| 100 | #define MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS(val) DWMAC_REGS_FLD32(val, 11, 15) |
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| 101 | #define MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS_GET(reg) DWMAC_REGS_FLD32GET(reg, 11, 15) |
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| 102 | #define MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 11, 15) |
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| 103 | uint32_t gmii_data; |
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| 104 | #define MACGRP_GMII_DATA_GMII_DATA(val) DWMAC_REGS_FLD32(val, 0, 15) |
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| 105 | #define MACGRP_GMII_DATA_GMII_DATA_GET(reg) DWMAC_REGS_FLD32GET(reg, 0, 15) |
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| 106 | #define MACGRP_GMII_DATA_GMII_DATA_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 0, 15) |
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| 107 | uint32_t reserved_18[9]; |
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| 108 | uint32_t interrupt_mask; |
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| 109 | #define MACGRP_INTERRUPT_MASK_RGSMIIIM DWMAC_REGS_BIT32(0) |
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| 110 | #define MACGRP_INTERRUPT_MASK_PCSLCHGIM DWMAC_REGS_BIT32(1) |
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| 111 | #define MACGRP_INTERRUPT_MASK_PCSANCIM DWMAC_REGS_BIT32(2) |
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| 112 | #define MACGRP_INTERRUPT_MASK_TSIM DWMAC_REGS_BIT32(9) |
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| 113 | #define MACGRP_INTERRUPT_MASK_LPIIM DWMAC_REGS_BIT32(10) |
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| 114 | mac mac_addr0_15[16]; |
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| 115 | uint32_t reserved_c0[16]; |
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| 116 | uint32_t mmc_control; |
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| 117 | #define MACGRP_MMC_CONTROL_CNTRST DWMAC_REGS_BIT32(0) |
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| 118 | #define MACGRP_MMC_CONTROL_CNTSTOPRO DWMAC_REGS_BIT32(1) |
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| 119 | #define MACGRP_MMC_CONTROL_RSTONRD DWMAC_REGS_BIT32(2) |
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| 120 | #define MACGRP_MMC_CONTROL_CNTFREEZ DWMAC_REGS_BIT32(3) |
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| 121 | #define MACGRP_MMC_CONTROL_CNTPRST DWMAC_REGS_BIT32(4) |
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| 122 | #define MACGRP_MMC_CONTROL_CNTPRSTLVL DWMAC_REGS_BIT32(5) |
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| 123 | #define MACGRP_MMC_CONTROL_UCDBC DWMAC_REGS_BIT32(8) |
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| 124 | uint32_t mmc_receive_interrupt; |
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| 125 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RXGBFRMIS DWMAC_REGS_BIT32(0) |
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| 126 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RXGBOCTIS DWMAC_REGS_BIT32(1) |
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| 127 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RXGOCTIS DWMAC_REGS_BIT32(2) |
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| 128 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RXBCGFIS DWMAC_REGS_BIT32(3) |
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| 129 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RXMCGFIS DWMAC_REGS_BIT32(4) |
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| 130 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RXCRCERFIS DWMAC_REGS_BIT32(5) |
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| 131 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RXALGNERFIS DWMAC_REGS_BIT32(6) |
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| 132 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RXRUNTFIS DWMAC_REGS_BIT32(7) |
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| 133 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RXJABERFIS DWMAC_REGS_BIT32(8) |
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| 134 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS DWMAC_REGS_BIT32(9) |
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| 135 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS DWMAC_REGS_BIT32(10) |
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| 136 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS DWMAC_REGS_BIT32(11) |
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| 137 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS DWMAC_REGS_BIT32(12) |
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| 138 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS DWMAC_REGS_BIT32(13) |
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| 139 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS DWMAC_REGS_BIT32(14) |
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| 140 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS DWMAC_REGS_BIT32(15) |
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| 141 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS DWMAC_REGS_BIT32(16) |
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| 142 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RXUCGFIS DWMAC_REGS_BIT32(17) |
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| 143 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RXLENERFIS DWMAC_REGS_BIT32(18) |
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| 144 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RXORANGEFIS DWMAC_REGS_BIT32(19) |
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| 145 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RXPAUSFIS DWMAC_REGS_BIT32(20) |
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| 146 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RXFOVFIS DWMAC_REGS_BIT32(21) |
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| 147 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS DWMAC_REGS_BIT32(22) |
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| 148 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RXWDOGFIS DWMAC_REGS_BIT32(23) |
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| 149 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS DWMAC_REGS_BIT32(24) |
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| 150 | #define MACGRP_MMC_RECEIVE_INTERRUPT_RXCTRLFIS DWMAC_REGS_BIT32(25) |
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| 151 | uint32_t mmc_transmit_interrupt; |
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| 152 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS DWMAC_REGS_BIT32(0) |
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| 153 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS DWMAC_REGS_BIT32(1) |
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| 154 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TXBCGFIS DWMAC_REGS_BIT32(2) |
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| 155 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TXMCGFIS DWMAC_REGS_BIT32(3) |
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| 156 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS DWMAC_REGS_BIT32(4) |
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| 157 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS DWMAC_REGS_BIT32(5) |
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| 158 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS DWMAC_REGS_BIT32(6) |
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| 159 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS DWMAC_REGS_BIT32(7) |
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| 160 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS DWMAC_REGS_BIT32(8) |
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| 161 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS DWMAC_REGS_BIT32(9) |
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| 162 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS DWMAC_REGS_BIT32(10) |
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| 163 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS DWMAC_REGS_BIT32(11) |
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| 164 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS DWMAC_REGS_BIT32(12) |
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| 165 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS DWMAC_REGS_BIT32(13) |
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| 166 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS DWMAC_REGS_BIT32(14) |
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| 167 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS DWMAC_REGS_BIT32(15) |
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| 168 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TXDEFFIS DWMAC_REGS_BIT32(16) |
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| 169 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS DWMAC_REGS_BIT32(17) |
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| 170 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS DWMAC_REGS_BIT32(18) |
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| 171 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TXCARERFIS DWMAC_REGS_BIT32(19) |
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| 172 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TXGOCTIS DWMAC_REGS_BIT32(20) |
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| 173 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TXGFRMIS DWMAC_REGS_BIT32(21) |
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| 174 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS DWMAC_REGS_BIT32(22) |
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| 175 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS DWMAC_REGS_BIT32(23) |
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| 176 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS DWMAC_REGS_BIT32(24) |
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| 177 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS DWMAC_REGS_BIT32(25) |
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| 178 | uint32_t mmc_receive_interrupt_mask; |
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| 179 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM DWMAC_REGS_BIT32(0) |
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| 180 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM DWMAC_REGS_BIT32(1) |
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| 181 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM DWMAC_REGS_BIT32(2) |
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| 182 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM DWMAC_REGS_BIT32(3) |
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| 183 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM DWMAC_REGS_BIT32(4) |
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| 184 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM DWMAC_REGS_BIT32(5) |
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| 185 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM DWMAC_REGS_BIT32(6) |
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| 186 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM DWMAC_REGS_BIT32(7) |
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| 187 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM DWMAC_REGS_BIT32(8) |
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| 188 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM DWMAC_REGS_BIT32(9) |
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| 189 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM DWMAC_REGS_BIT32(10) |
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| 190 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM DWMAC_REGS_BIT32(11) |
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| 191 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM DWMAC_REGS_BIT32(12) |
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| 192 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM DWMAC_REGS_BIT32(13) |
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| 193 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM DWMAC_REGS_BIT32(14) |
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| 194 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM DWMAC_REGS_BIT32(15) |
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| 195 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM DWMAC_REGS_BIT32(16) |
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| 196 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM DWMAC_REGS_BIT32(17) |
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| 197 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM DWMAC_REGS_BIT32(18) |
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| 198 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM DWMAC_REGS_BIT32(19) |
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| 199 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM DWMAC_REGS_BIT32(20) |
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| 200 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM DWMAC_REGS_BIT32(21) |
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| 201 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM DWMAC_REGS_BIT32(22) |
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| 202 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM DWMAC_REGS_BIT32(23) |
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| 203 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM DWMAC_REGS_BIT32(24) |
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| 204 | #define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM DWMAC_REGS_BIT32(25) |
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| 205 | uint32_t mmc_transmit_interrupt_mask; |
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| 206 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM DWMAC_REGS_BIT32(0) |
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| 207 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM DWMAC_REGS_BIT32(1) |
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| 208 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM DWMAC_REGS_BIT32(2) |
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| 209 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM DWMAC_REGS_BIT32(3) |
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| 210 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM DWMAC_REGS_BIT32(4) |
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| 211 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM DWMAC_REGS_BIT32(5) |
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| 212 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM DWMAC_REGS_BIT32(6) |
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| 213 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM DWMAC_REGS_BIT32(7) |
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| 214 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM DWMAC_REGS_BIT32(8) |
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| 215 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM DWMAC_REGS_BIT32(9) |
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| 216 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM DWMAC_REGS_BIT32(10) |
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| 217 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM DWMAC_REGS_BIT32(11) |
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| 218 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM DWMAC_REGS_BIT32(12) |
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| 219 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM DWMAC_REGS_BIT32(13) |
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| 220 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM DWMAC_REGS_BIT32(14) |
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| 221 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM DWMAC_REGS_BIT32(15) |
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| 222 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM DWMAC_REGS_BIT32(16) |
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| 223 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM DWMAC_REGS_BIT32(17) |
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| 224 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM DWMAC_REGS_BIT32(18) |
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| 225 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM DWMAC_REGS_BIT32(19) |
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| 226 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM DWMAC_REGS_BIT32(20) |
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| 227 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM DWMAC_REGS_BIT32(21) |
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| 228 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM DWMAC_REGS_BIT32(22) |
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| 229 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM DWMAC_REGS_BIT32(23) |
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| 230 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM DWMAC_REGS_BIT32(24) |
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| 231 | #define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM DWMAC_REGS_BIT32(25) |
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| 232 | uint32_t txoctetcount_gb; |
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| 233 | uint32_t txframecount_gb; |
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| 234 | uint32_t txbroadcastframes_g; |
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| 235 | uint32_t txmulticastframes_g; |
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| 236 | uint32_t tx64octets_gb; |
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| 237 | uint32_t tx65to127octets_gb; |
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| 238 | uint32_t tx128to255octets_gb; |
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| 239 | uint32_t tx256to511octets_gb; |
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| 240 | uint32_t tx512to1023octets_gb; |
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| 241 | uint32_t tx1024tomaxoctets_gb; |
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| 242 | uint32_t txunicastframes_gb; |
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| 243 | uint32_t txmulticastframes_gb; |
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| 244 | uint32_t txbroadcastframes_gb; |
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| 245 | uint32_t txunderflowerror; |
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| 246 | uint32_t txsinglecol_g; |
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| 247 | uint32_t txmulticol_g; |
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| 248 | uint32_t txdeferred; |
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| 249 | uint32_t txlatecol; |
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| 250 | uint32_t txexesscol; |
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| 251 | uint32_t txcarriererr; |
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| 252 | uint32_t txoctetcnt; |
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| 253 | uint32_t txframecount_g; |
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| 254 | uint32_t txexcessdef; |
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| 255 | uint32_t txpauseframes; |
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| 256 | uint32_t txvlanframes_g; |
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| 257 | uint32_t txoversize_g; |
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| 258 | uint32_t reserved_17c; |
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| 259 | uint32_t rxframecount_gb; |
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| 260 | uint32_t rxoctetcount_gb; |
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| 261 | uint32_t rxoctetcount_g; |
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| 262 | uint32_t rxbroadcastframes_g; |
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| 263 | uint32_t rxmulticastframes_g; |
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| 264 | uint32_t rxcrcerror; |
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| 265 | uint32_t rxalignmenterror; |
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| 266 | uint32_t rxrunterror; |
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| 267 | uint32_t rxjabbererror; |
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| 268 | uint32_t rxundersize_g; |
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| 269 | uint32_t rxoversize_g; |
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| 270 | uint32_t rx64octets_gb; |
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| 271 | uint32_t rx65to127octets_gb; |
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| 272 | uint32_t rx128to255octets_gb; |
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| 273 | uint32_t rx256to511octets_gb; |
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| 274 | uint32_t rx512to1023octets_gb; |
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| 275 | uint32_t rx1024tomaxoctets_gb; |
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| 276 | uint32_t rxunicastframes_g; |
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| 277 | uint32_t rxlengtherror; |
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| 278 | uint32_t rxoutofrangetype; |
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| 279 | uint32_t rxpauseframes; |
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| 280 | uint32_t rxfifooverflow; |
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| 281 | uint32_t rxvlanframes_gb; |
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| 282 | uint32_t rxwatchdogerror; |
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| 283 | uint32_t rxrcverror; |
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| 284 | uint32_t rxctrlframes_g; |
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| 285 | uint32_t reserved_1e8[6]; |
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| 286 | uint32_t mmc_ipc_receive_interrupt_mask; |
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| 287 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM DWMAC_REGS_BIT32(0) |
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| 288 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM DWMAC_REGS_BIT32(1) |
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| 289 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM DWMAC_REGS_BIT32(2) |
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| 290 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM DWMAC_REGS_BIT32(3) |
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| 291 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM DWMAC_REGS_BIT32(4) |
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| 292 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM DWMAC_REGS_BIT32(5) |
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| 293 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM DWMAC_REGS_BIT32(6) |
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| 294 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM DWMAC_REGS_BIT32(7) |
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| 295 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM DWMAC_REGS_BIT32(8) |
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| 296 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM DWMAC_REGS_BIT32(9) |
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| 297 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM DWMAC_REGS_BIT32(10) |
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| 298 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM DWMAC_REGS_BIT32(11) |
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| 299 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM DWMAC_REGS_BIT32(12) |
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| 300 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM DWMAC_REGS_BIT32(13) |
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| 301 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM DWMAC_REGS_BIT32(16) |
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| 302 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM DWMAC_REGS_BIT32(17) |
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| 303 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM DWMAC_REGS_BIT32(18) |
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| 304 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM DWMAC_REGS_BIT32(19) |
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| 305 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM DWMAC_REGS_BIT32(20) |
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| 306 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM DWMAC_REGS_BIT32(21) |
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| 307 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM DWMAC_REGS_BIT32(22) |
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| 308 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM DWMAC_REGS_BIT32(23) |
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| 309 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM DWMAC_REGS_BIT32(24) |
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| 310 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM DWMAC_REGS_BIT32(25) |
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| 311 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM DWMAC_REGS_BIT32(26) |
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| 312 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM DWMAC_REGS_BIT32(27) |
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| 313 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM DWMAC_REGS_BIT32(28) |
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| 314 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM DWMAC_REGS_BIT32(29) |
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| 315 | uint32_t reserved_204; |
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| 316 | uint32_t mmc_ipc_receive_interrupt; |
|---|
| 317 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS DWMAC_REGS_BIT32(0) |
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| 318 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS DWMAC_REGS_BIT32(1) |
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| 319 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS DWMAC_REGS_BIT32(2) |
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| 320 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS DWMAC_REGS_BIT32(3) |
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| 321 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS DWMAC_REGS_BIT32(4) |
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| 322 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS DWMAC_REGS_BIT32(5) |
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| 323 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS DWMAC_REGS_BIT32(6) |
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| 324 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS DWMAC_REGS_BIT32(7) |
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| 325 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS DWMAC_REGS_BIT32(8) |
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| 326 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS DWMAC_REGS_BIT32(9) |
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| 327 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS DWMAC_REGS_BIT32(10) |
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| 328 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS DWMAC_REGS_BIT32(11) |
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| 329 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS DWMAC_REGS_BIT32(12) |
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| 330 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS DWMAC_REGS_BIT32(13) |
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| 331 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS DWMAC_REGS_BIT32(16) |
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| 332 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS DWMAC_REGS_BIT32(17) |
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| 333 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS DWMAC_REGS_BIT32(18) |
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| 334 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS DWMAC_REGS_BIT32(19) |
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| 335 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS DWMAC_REGS_BIT32(20) |
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| 336 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS DWMAC_REGS_BIT32(21) |
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| 337 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS DWMAC_REGS_BIT32(22) |
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| 338 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS DWMAC_REGS_BIT32(23) |
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| 339 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS DWMAC_REGS_BIT32(24) |
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| 340 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS DWMAC_REGS_BIT32(25) |
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| 341 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS DWMAC_REGS_BIT32(26) |
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| 342 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS DWMAC_REGS_BIT32(27) |
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| 343 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS DWMAC_REGS_BIT32(28) |
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| 344 | #define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS DWMAC_REGS_BIT32(29) |
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| 345 | uint32_t reserved_20c; |
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| 346 | uint32_t rxipv4_gd_frms; |
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| 347 | uint32_t rxipv4_hdrerr_frms; |
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| 348 | uint32_t rxipv4_nopay_frms; |
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| 349 | uint32_t rxipv4_frag_frms; |
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| 350 | uint32_t rxipv4_udsbl_frms; |
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| 351 | uint32_t rxipv6_gd_frms; |
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| 352 | uint32_t rxipv6_hdrerr_frms; |
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| 353 | uint32_t rxipv6_nopay_frms; |
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| 354 | uint32_t rxudp_gd_frms; |
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| 355 | uint32_t rxudp_err_frms; |
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| 356 | uint32_t rxtcp_gd_frms; |
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| 357 | uint32_t rxtcp_err_frms; |
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| 358 | uint32_t rxicmp_gd_frms; |
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| 359 | uint32_t rxicmp_err_frms; |
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| 360 | uint32_t reserved_248[2]; |
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| 361 | uint32_t rxipv4_gd_octets; |
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| 362 | uint32_t rxipv4_hdrerr_octets; |
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| 363 | uint32_t rxipv4_nopay_octets; |
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| 364 | uint32_t rxipv4_frag_octets; |
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| 365 | uint32_t rxipv4_udsbl_octets; |
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| 366 | uint32_t rxipv6_gd_octets; |
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| 367 | uint32_t rxipv6_hdrerr_octets; |
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| 368 | uint32_t rxipv6_nopay_octets; |
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| 369 | uint32_t rxudp_gd_octets; |
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| 370 | uint32_t rxudp_err_octets; |
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| 371 | uint32_t rxtcp_gd_octets; |
|---|
| 372 | uint32_t rxtcperroctets; |
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| 373 | uint32_t rxicmp_gd_octets; |
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| 374 | uint32_t rxicmp_err_octets; |
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| 375 | uint32_t reserved_288[158]; |
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| 376 | uint32_t hash_table_reg[8]; |
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| 377 | uint32_t reserved_520[184]; |
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| 378 | mac mac_addr16_127[112]; |
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| 379 | } macgrp; |
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| 380 | |
|---|
| 381 | typedef struct { |
|---|
| 382 | uint32_t bus_mode; |
|---|
| 383 | #define DMAGRP_BUS_MODE_SWR DWMAC_REGS_BIT32(0) |
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| 384 | #define DMAGRP_BUS_MODE_DSL(val) DWMAC_REGS_FLD32(val, 2, 6) |
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| 385 | #define DMAGRP_BUS_MODE_DSL_GET(reg) DWMAC_REGS_FLD32GET(reg, 2, 6) |
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| 386 | #define DMAGRP_BUS_MODE_DSL_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 2, 6) |
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| 387 | #define DMAGRP_BUS_MODE_ATDS DWMAC_REGS_BIT32(7) |
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| 388 | #define DMAGRP_BUS_MODE_PBL(val) DWMAC_REGS_FLD32(val, 8, 13) |
|---|
| 389 | #define DMAGRP_BUS_MODE_PBL_GET(reg) DWMAC_REGS_FLD32GET(reg, 8, 13) |
|---|
| 390 | #define DMAGRP_BUS_MODE_PBL_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 8, 13) |
|---|
| 391 | #define DMAGRP_BUS_MODE_FB DWMAC_REGS_BIT32(16) |
|---|
| 392 | #define DMAGRP_BUS_MODE_RPBL(val) DWMAC_REGS_FLD32(val, 17, 22) |
|---|
| 393 | #define DMAGRP_BUS_MODE_RPBL_GET(reg) DWMAC_REGS_FLD32GET(reg, 17, 22) |
|---|
| 394 | #define DMAGRP_BUS_MODE_RPBL_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 17, 22) |
|---|
| 395 | #define DMAGRP_BUS_MODE_USP DWMAC_REGS_BIT32(23) |
|---|
| 396 | #define DMAGRP_BUS_MODE_EIGHTXPBL DWMAC_REGS_BIT32(24) |
|---|
| 397 | #define DMAGRP_BUS_MODE_AAL DWMAC_REGS_BIT32(25) |
|---|
| 398 | #define DMAGRP_BUS_MODE_MB DWMAC_REGS_BIT32(26) |
|---|
| 399 | uint32_t transmit_poll_demand; |
|---|
| 400 | #define DMAGRP_TRANSMIT_POLL_DEMAND_TPD(val) DWMAC_REGS_FLD32(val, 0, 31) |
|---|
| 401 | #define DMAGRP_TRANSMIT_POLL_DEMAND_TPD_GET(reg) DWMAC_REGS_FLD32GET(reg, 0, 31) |
|---|
| 402 | #define DMAGRP_TRANSMIT_POLL_DEMAND_TPD_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 0, 31) |
|---|
| 403 | uint32_t receive_poll_demand; |
|---|
| 404 | #define DMAGRP_RECEIVE_POLL_DEMAND_RPD(val) DWMAC_REGS_FLD32(val, 0, 31) |
|---|
| 405 | #define DMAGRP_RECEIVE_POLL_DEMAND_RPD_GET(reg) DWMAC_REGS_FLD32GET(reg, 0, 31) |
|---|
| 406 | #define DMAGRP_RECEIVE_POLL_DEMAND_RPD_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 0, 31) |
|---|
| 407 | uint32_t receive_descr_list_addr; |
|---|
| 408 | #define DMAGRP_RECEIVE_DESCR_LIST_ADDR_RDESLA_32BIT(val) DWMAC_REGS_FLD32(val, 2, 31) |
|---|
| 409 | #define DMAGRP_RECEIVE_DESCR_LIST_ADDR_RDESLA_32BIT_GET(reg) DWMAC_REGS_FLD32GET(reg, 2, 31) |
|---|
| 410 | #define DMAGRP_RECEIVE_DESCR_LIST_ADDR_RDESLA_32BIT_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 2, 31) |
|---|
| 411 | uint32_t transmit_descr_list_addr; |
|---|
| 412 | #define DMAGRP_TRANSMIT_DESCR_LIST_ADDR_TDESLA_32BIT(val) DWMAC_REGS_FLD32(val, 2, 31) |
|---|
| 413 | #define DMAGRP_TRANSMIT_DESCR_LIST_ADDR_TDESLA_32BIT_GET(reg) DWMAC_REGS_FLD32GET(reg, 2, 31) |
|---|
| 414 | #define DMAGRP_TRANSMIT_DESCR_LIST_ADDR_TDESLA_32BIT_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 2, 31) |
|---|
| 415 | uint32_t status; |
|---|
| 416 | #define DMAGRP_STATUS_TI DWMAC_REGS_BIT32(0) |
|---|
| 417 | #define DMAGRP_STATUS_TPS DWMAC_REGS_BIT32(1) |
|---|
| 418 | #define DMAGRP_STATUS_TU DWMAC_REGS_BIT32(2) |
|---|
| 419 | #define DMAGRP_STATUS_TJT DWMAC_REGS_BIT32(3) |
|---|
| 420 | #define DMAGRP_STATUS_OVF DWMAC_REGS_BIT32(4) |
|---|
| 421 | #define DMAGRP_STATUS_UNF DWMAC_REGS_BIT32(5) |
|---|
| 422 | #define DMAGRP_STATUS_RI DWMAC_REGS_BIT32(6) |
|---|
| 423 | #define DMAGRP_STATUS_RU DWMAC_REGS_BIT32(7) |
|---|
| 424 | #define DMAGRP_STATUS_RPS DWMAC_REGS_BIT32(8) |
|---|
| 425 | #define DMAGRP_STATUS_RWT DWMAC_REGS_BIT32(9) |
|---|
| 426 | #define DMAGRP_STATUS_ETI DWMAC_REGS_BIT32(10) |
|---|
| 427 | #define DMAGRP_STATUS_FBI DWMAC_REGS_BIT32(13) |
|---|
| 428 | #define DMAGRP_STATUS_ERI DWMAC_REGS_BIT32(14) |
|---|
| 429 | #define DMAGRP_STATUS_AIS DWMAC_REGS_BIT32(15) |
|---|
| 430 | #define DMAGRP_STATUS_NIS DWMAC_REGS_BIT32(16) |
|---|
| 431 | #define DMAGRP_STATUS_RS(val) DWMAC_REGS_FLD32(val, 17, 19) |
|---|
| 432 | #define DMAGRP_STATUS_RS_GET(reg) DWMAC_REGS_FLD32GET(reg, 17, 19) |
|---|
| 433 | #define DMAGRP_STATUS_RS_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 17, 19) |
|---|
| 434 | #define DMAGRP_STATUS_TS(val) DWMAC_REGS_FLD32(val, 20, 22) |
|---|
| 435 | #define DMAGRP_STATUS_TS_GET(reg) DWMAC_REGS_FLD32GET(reg, 20, 22) |
|---|
| 436 | #define DMAGRP_STATUS_TS_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 20, 22) |
|---|
| 437 | #define DMAGRP_STATUS_EB(val) DWMAC_REGS_FLD32(val, 23, 25) |
|---|
| 438 | #define DMAGRP_STATUS_EB_GET(reg) DWMAC_REGS_FLD32GET(reg, 23, 25) |
|---|
| 439 | #define DMAGRP_STATUS_EB_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 23, 25) |
|---|
| 440 | #define DMAGRP_STATUS_GLI DWMAC_REGS_BIT32(26) |
|---|
| 441 | #define DMAGRP_STATUS_GMI DWMAC_REGS_BIT32(27) |
|---|
| 442 | #define DMAGRP_STATUS_TTI DWMAC_REGS_BIT32(29) |
|---|
| 443 | #define DMAGRP_STATUS_GLPII DWMAC_REGS_BIT32(30) |
|---|
| 444 | uint32_t operation_mode; |
|---|
| 445 | #define DMAGRP_OPERATION_MODE_SR DWMAC_REGS_BIT32(1) |
|---|
| 446 | #define DMAGRP_OPERATION_MODE_OSF DWMAC_REGS_BIT32(2) |
|---|
| 447 | #define DMAGRP_OPERATION_MODE_RTC(val) DWMAC_REGS_FLD32(val, 3, 4) |
|---|
| 448 | #define DMAGRP_OPERATION_MODE_RTC_GET(reg) DWMAC_REGS_FLD32GET(reg, 3, 4) |
|---|
| 449 | #define DMAGRP_OPERATION_MODE_RTC_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 3, 4) |
|---|
| 450 | #define DMAGRP_OPERATION_MODE_FUF DWMAC_REGS_BIT32(6) |
|---|
| 451 | #define DMAGRP_OPERATION_MODE_FEF DWMAC_REGS_BIT32(7) |
|---|
| 452 | #define DMAGRP_OPERATION_MODE_EFC DWMAC_REGS_BIT32(8) |
|---|
| 453 | #define DMAGRP_OPERATION_MODE_RFA(val) DWMAC_REGS_FLD32(val, 9, 10) |
|---|
| 454 | #define DMAGRP_OPERATION_MODE_RFA_GET(reg) DWMAC_REGS_FLD32GET(reg, 9, 10) |
|---|
| 455 | #define DMAGRP_OPERATION_MODE_RFA_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 9, 10) |
|---|
| 456 | #define DMAGRP_OPERATION_MODE_RFD(val) DWMAC_REGS_FLD32(val, 11, 12) |
|---|
| 457 | #define DMAGRP_OPERATION_MODE_RFD_GET(reg) DWMAC_REGS_FLD32GET(reg, 11, 12) |
|---|
| 458 | #define DMAGRP_OPERATION_MODE_RFD_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 11, 12) |
|---|
| 459 | #define DMAGRP_OPERATION_MODE_ST DWMAC_REGS_BIT32(13) |
|---|
| 460 | #define DMAGRP_OPERATION_MODE_TTC(val) DWMAC_REGS_FLD32(val, 14, 16) |
|---|
| 461 | #define DMAGRP_OPERATION_MODE_TTC_GET(reg) DWMAC_REGS_FLD32GET(reg, 14, 16) |
|---|
| 462 | #define DMAGRP_OPERATION_MODE_TTC_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 14, 16) |
|---|
| 463 | #define DMAGRP_OPERATION_MODE_FTF DWMAC_REGS_BIT32(20) |
|---|
| 464 | #define DMAGRP_OPERATION_MODE_TSF DWMAC_REGS_BIT32(21) |
|---|
| 465 | #define DMAGRP_OPERATION_MODE_DFF DWMAC_REGS_BIT32(24) |
|---|
| 466 | #define DMAGRP_OPERATION_MODE_RSF DWMAC_REGS_BIT32(25) |
|---|
| 467 | #define DMAGRP_OPERATION_MODE_DT DWMAC_REGS_BIT32(26) |
|---|
| 468 | uint32_t interrupt_enable; |
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| 469 | #define DMAGRP_INTERRUPT_ENABLE_TIE DWMAC_REGS_BIT32(0) |
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| 470 | #define DMAGRP_INTERRUPT_ENABLE_TSE DWMAC_REGS_BIT32(1) |
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| 471 | #define DMAGRP_INTERRUPT_ENABLE_TUE DWMAC_REGS_BIT32(2) |
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| 472 | #define DMAGRP_INTERRUPT_ENABLE_TJE DWMAC_REGS_BIT32(3) |
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| 473 | #define DMAGRP_INTERRUPT_ENABLE_OVE DWMAC_REGS_BIT32(4) |
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| 474 | #define DMAGRP_INTERRUPT_ENABLE_UNE DWMAC_REGS_BIT32(5) |
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| 475 | #define DMAGRP_INTERRUPT_ENABLE_RIE DWMAC_REGS_BIT32(6) |
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| 476 | #define DMAGRP_INTERRUPT_ENABLE_RUE DWMAC_REGS_BIT32(7) |
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| 477 | #define DMAGRP_INTERRUPT_ENABLE_RSE DWMAC_REGS_BIT32(8) |
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| 478 | #define DMAGRP_INTERRUPT_ENABLE_RWE DWMAC_REGS_BIT32(9) |
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| 479 | #define DMAGRP_INTERRUPT_ENABLE_ETE DWMAC_REGS_BIT32(10) |
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| 480 | #define DMAGRP_INTERRUPT_ENABLE_FBE DWMAC_REGS_BIT32(13) |
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| 481 | #define DMAGRP_INTERRUPT_ENABLE_ERE DWMAC_REGS_BIT32(14) |
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| 482 | #define DMAGRP_INTERRUPT_ENABLE_AIE DWMAC_REGS_BIT32(15) |
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| 483 | #define DMAGRP_INTERRUPT_ENABLE_NIE DWMAC_REGS_BIT32(16) |
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| 484 | uint32_t reserved_20[2]; |
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| 485 | uint32_t axi_bus_mode; |
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| 486 | #define DMAGRP_AXI_BUS_MODE_UNDEFINED DWMAC_REGS_BIT32(0) |
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| 487 | #define DMAGRP_AXI_BUS_MODE_BLEND4 DWMAC_REGS_BIT32(1) |
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| 488 | #define DMAGRP_AXI_BUS_MODE_BLEND8 DWMAC_REGS_BIT32(2) |
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| 489 | #define DMAGRP_AXI_BUS_MODE_BLEND16 DWMAC_REGS_BIT32(3) |
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| 490 | #define DMAGRP_AXI_BUS_MODE_AXI_AAL DWMAC_REGS_BIT32(12) |
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| 491 | #define DMAGRP_AXI_BUS_MODE_ONEKBBE DWMAC_REGS_BIT32(13) |
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| 492 | #define DMAGRP_AXI_BUS_MODE_RD_OSR_LMT(val) DWMAC_REGS_FLD32(val, 16, 19) |
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| 493 | #define DMAGRP_AXI_BUS_MODE_RD_OSR_LMT_GET(reg) DWMAC_REGS_FLD32GET(reg, 16, 19) |
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| 494 | #define DMAGRP_AXI_BUS_MODE_RD_OSR_LMT_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 16, 19) |
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| 495 | #define DMAGRP_AXI_BUS_MODE_WR_OSR_LMT(val) DWMAC_REGS_FLD32(val, 20, 23) |
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| 496 | #define DMAGRP_AXI_BUS_MODE_WR_OSR_LMT_GET(reg) DWMAC_REGS_FLD32GET(reg, 20, 23) |
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| 497 | #define DMAGRP_AXI_BUS_MODE_WR_OSR_LMT_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 20, 23) |
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| 498 | #define DMAGRP_AXI_BUS_MODE_LPI_XIT_FRM DWMAC_REGS_BIT32(30) |
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| 499 | #define DMAGRP_AXI_BUS_MODE_EN_LPI DWMAC_REGS_BIT32(31) |
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| 500 | uint32_t reserved_2c[11]; |
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| 501 | uint32_t hw_feature; |
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| 502 | #define DMAGRP_HW_FEATURE_MIISEL DWMAC_REGS_BIT32(0) |
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| 503 | #define DMAGRP_HW_FEATURE_GMIISEL DWMAC_REGS_BIT32(1) |
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| 504 | #define DMAGRP_HW_FEATURE_HDSEL DWMAC_REGS_BIT32(2) |
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| 505 | #define DMAGRP_HW_FEATURE_HASHSEL DWMAC_REGS_BIT32(4) |
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| 506 | #define DMAGRP_HW_FEATURE_ADDMACADRSEL DWMAC_REGS_BIT32(5) |
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| 507 | #define DMAGRP_HW_FEATURE_PCSSEL DWMAC_REGS_BIT32(6) |
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| 508 | #define DMAGRP_HW_FEATURE_SMASEL DWMAC_REGS_BIT32(8) |
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| 509 | #define DMAGRP_HW_FEATURE_RWKSEL DWMAC_REGS_BIT32(9) |
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| 510 | #define DMAGRP_HW_FEATURE_MGKSEL DWMAC_REGS_BIT32(10) |
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| 511 | #define DMAGRP_HW_FEATURE_MMCSEL DWMAC_REGS_BIT32(11) |
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| 512 | #define DMAGRP_HW_FEATURE_TSVER1SEL DWMAC_REGS_BIT32(12) |
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| 513 | #define DMAGRP_HW_FEATURE_TSVER2SEL DWMAC_REGS_BIT32(13) |
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| 514 | #define DMAGRP_HW_FEATURE_EEESEL DWMAC_REGS_BIT32(14) |
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| 515 | #define DMAGRP_HW_FEATURE_AVSEL DWMAC_REGS_BIT32(15) |
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| 516 | #define DMAGRP_HW_FEATURE_TXOESEL DWMAC_REGS_BIT32(16) |
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| 517 | #define DMAGRP_HW_FEATURE_RXTYP1COE DWMAC_REGS_BIT32(17) |
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| 518 | #define DMAGRP_HW_FEATURE_RXTYP2COE DWMAC_REGS_BIT32(18) |
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| 519 | #define DMAGRP_HW_FEATURE_RXFIFOSIZE DWMAC_REGS_BIT32(19) |
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| 520 | #define DMAGRP_HW_FEATURE_RXCHCNT(val) DWMAC_REGS_FLD32(val, 20, 21) |
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| 521 | #define DMAGRP_HW_FEATURE_RXCHCNT_GET(reg) DWMAC_REGS_FLD32GET(reg, 20, 21) |
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| 522 | #define DMAGRP_HW_FEATURE_RXCHCNT_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 20, 21) |
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| 523 | #define DMAGRP_HW_FEATURE_TXCHCNT(val) DWMAC_REGS_FLD32(val, 22, 23) |
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| 524 | #define DMAGRP_HW_FEATURE_TXCHCNT_GET(reg) DWMAC_REGS_FLD32GET(reg, 22, 23) |
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| 525 | #define DMAGRP_HW_FEATURE_TXCHCNT_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 22, 23) |
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| 526 | #define DMAGRP_HW_FEATURE_ENHDESSEL DWMAC_REGS_BIT32(24) |
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| 527 | #define DMAGRP_HW_FEATURE_ACTPHYIF(val) DWMAC_REGS_FLD32(val, 28, 30) |
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| 528 | #define DMAGRP_HW_FEATURE_ACTPHYIF_GET(reg) DWMAC_REGS_FLD32GET(reg, 28, 30) |
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| 529 | #define DMAGRP_HW_FEATURE_ACTPHYIF_SET(reg, val) DWMAC_REGS_FLD32SET(reg, val, 28, 30) |
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| 530 | } dmagrp; |
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| 531 | |
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| 532 | #endif /* MAC_REGS_H */ |
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