| 1 | #ifndef DWMAC_DESC_RX_REGS_H |
|---|
| 2 | #define DWMAC_DESC_RX_REGS_H |
|---|
| 3 | |
|---|
| 4 | #include <stdint.h> |
|---|
| 5 | |
|---|
| 6 | #define DWMAC_DESC_BIT32(bit) \ |
|---|
| 7 | ((uint32_t) (((uint32_t) 1) << (bit))) |
|---|
| 8 | |
|---|
| 9 | #define DWMAC_DESC_MSK32(first_bit, last_bit) \ |
|---|
| 10 | ((uint32_t) ((DWMAC_DESC_BIT32((last_bit) - (first_bit) + 1) - 1) << (first_bit))) |
|---|
| 11 | |
|---|
| 12 | #define DWMAC_DESC_FLD32(val, first_bit, last_bit) \ |
|---|
| 13 | ((uint32_t) \ |
|---|
| 14 | ((((uint32_t) (val)) << (first_bit)) & DWMAC_DESC_MSK32(first_bit, last_bit))) |
|---|
| 15 | |
|---|
| 16 | #define DWMAC_DESC_FLD32GET(reg, first_bit, last_bit) \ |
|---|
| 17 | ((uint32_t) (((reg) & DWMAC_DESC_MSK32(first_bit, last_bit)) >> (first_bit))) |
|---|
| 18 | |
|---|
| 19 | #define DWMAC_DESC_FLD32SET(reg, val, first_bit, last_bit) \ |
|---|
| 20 | ((uint32_t) (((reg) & ~DWMAC_DESC_MSK32(first_bit, last_bit)) \ |
|---|
| 21 | | DWMAC_DESC_FLD32(val, first_bit, last_bit))) |
|---|
| 22 | |
|---|
| 23 | typedef struct { |
|---|
| 24 | uint32_t des0; |
|---|
| 25 | #define DWMAC_DESC_RX_DES0_OWN_BIT DWMAC_DESC_BIT32(31) |
|---|
| 26 | #define DWMAC_DESC_RX_DES0_DEST_ADDR_FILTER_FAIL DWMAC_DESC_BIT32(30) |
|---|
| 27 | #define DWMAC_DESC_RX_DES0_FRAME_LENGTH(val) DWMAC_DESC_FLD32(val, 16, 29) |
|---|
| 28 | #define DWMAC_DESC_RX_DES0_FRAME_LENGTH_GET(reg) DWMAC_DESC_FLD32GET(reg, 16, 29) |
|---|
| 29 | #define DWMAC_DESC_RX_DES0_FRAME_LENGTH_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 16, 29) |
|---|
| 30 | #define DWMAC_DESC_RX_DES0_ERROR_SUMMARY DWMAC_DESC_BIT32(15) |
|---|
| 31 | #define DWMAC_DESC_RX_DES0_DESCRIPTOR_ERROR DWMAC_DESC_BIT32(14) |
|---|
| 32 | #define DWMAC_DESC_RX_DES0_SRC_ADDR_FILTER_FAIL DWMAC_DESC_BIT32(13) |
|---|
| 33 | #define DWMAC_DESC_RX_DES0_LENGTH_ERROR DWMAC_DESC_BIT32(12) |
|---|
| 34 | #define DWMAC_DESC_RX_DES0_OVERFLOW_ERROR DWMAC_DESC_BIT32(11) |
|---|
| 35 | #define DWMAC_DESC_RX_DES0_VLAN_TAG DWMAC_DESC_BIT32(10) |
|---|
| 36 | #define DWMAC_DESC_RX_DES0_FIRST_DESCRIPTOR DWMAC_DESC_BIT32(9) |
|---|
| 37 | #define DWMAC_DESC_RX_DES0_LAST_DESCRIPTOR DWMAC_DESC_BIT32(8) |
|---|
| 38 | #define DWMAC_DESC_RX_DES0_CHECKSUM_ERROR DWMAC_DESC_BIT32(7) |
|---|
| 39 | #define DWMAC_DESC_RX_DES0_LATE_COLLISION DWMAC_DESC_BIT32(6) |
|---|
| 40 | #define DWMAC_DESC_RX_DES0_FRAME_TYPE DWMAC_DESC_BIT32(5) |
|---|
| 41 | #define DWMAC_DESC_RX_DES0_RECEIVE_WATCHDOG_TIMEOUT DWMAC_DESC_BIT32(4) |
|---|
| 42 | #define DWMAC_DESC_RX_DES0_RECEIVE_ERROR DWMAC_DESC_BIT32(3) |
|---|
| 43 | #define DWMAC_DESC_RX_DES0_DRIBBLE_BIT_ERROR DWMAC_DESC_BIT32(2) |
|---|
| 44 | #define DWMAC_DESC_RX_DES0_CRC_ERROR DWMAC_DESC_BIT32(1) |
|---|
| 45 | #define DWMAC_DESC_RX_DES0_RX_MAC_ADDR_OR_PAYLOAD_CHECKSUM_ERROR DWMAC_DESC_BIT32(0) |
|---|
| 46 | uint32_t des1; |
|---|
| 47 | #define DWMAC_DESC_RX_DES1_DISABLE_IRQ_ON_COMPLETION DWMAC_DESC_BIT32(31) |
|---|
| 48 | #define DWMAC_DESC_RX_DES1_RECEIVE_END_OF_RING DWMAC_DESC_BIT32(25) |
|---|
| 49 | #define DWMAC_DESC_RX_DES1_SECOND_ADDR_CHAINED DWMAC_DESC_BIT32(24) |
|---|
| 50 | #define DWMAC_DESC_RX_DES1_RECEIVE_BUFFER_2_SIZE(val) DWMAC_DESC_FLD32(val, 11, 21) |
|---|
| 51 | #define DWMAC_DESC_RX_DES1_RECEIVE_BUFFER_2_SIZE_GET(reg) DWMAC_DESC_FLD32GET(reg, 11, 21) |
|---|
| 52 | #define DWMAC_DESC_RX_DES1_RECEIVE_BUFFER_2_SIZE_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 11, 21) |
|---|
| 53 | #define DWMAC_DESC_RX_DES1_RECIVE_BUFFER_1_SIZE(val) DWMAC_DESC_FLD32(val, 0, 10) |
|---|
| 54 | #define DWMAC_DESC_RX_DES1_RECIVE_BUFFER_1_SIZE_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 10) |
|---|
| 55 | #define DWMAC_DESC_RX_DES1_RECIVE_BUFFER_1_SIZE_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 10) |
|---|
| 56 | uint32_t des2; |
|---|
| 57 | #define DWMAC_DESC_RX_DES2_BUFF_1_ADDR_PTR(val) DWMAC_DESC_FLD32(val, 0, 31) |
|---|
| 58 | #define DWMAC_DESC_RX_DES2_BUFF_1_ADDR_PTR_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31) |
|---|
| 59 | #define DWMAC_DESC_RX_DES2_BUFF_1_ADDR_PTR_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31) |
|---|
| 60 | #define DWMAC_DESC_RX_DES2_IEEE_RECEIVE_FRAME_TIMESTAMP_LOW(val) DWMAC_DESC_FLD32(val, 0, 31) |
|---|
| 61 | #define DWMAC_DESC_RX_DES2_IEEE_RECEIVE_FRAME_TIMESTAMP_LOW_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31) |
|---|
| 62 | #define DWMAC_DESC_RX_DES2_IEEE_RECEIVE_FRAME_TIMESTAMP_LOW_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31) |
|---|
| 63 | uint32_t des3; |
|---|
| 64 | #define DWMAC_DESC_RX_DES3_BUFF_2_ADDR_PTR(val) DWMAC_DESC_FLD32(val, 0, 31) |
|---|
| 65 | #define DWMAC_DESC_RX_DES3_BUFF_2_ADDR_PTR_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31) |
|---|
| 66 | #define DWMAC_DESC_RX_DES3_BUFF_2_ADDR_PTR_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31) |
|---|
| 67 | #define DWMAC_DESC_RX_DES3_IEEE_RECEIVE_FRAME_TIMESTAMP_LOW(val) DWMAC_DESC_FLD32(val, 0, 31) |
|---|
| 68 | #define DWMAC_DESC_RX_DES3_IEEE_RECEIVE_FRAME_TIMESTAMP_LOW_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31) |
|---|
| 69 | #define DWMAC_DESC_RX_DES3_IEEE_RECEIVE_FRAME_TIMESTAMP_LOW_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31) |
|---|
| 70 | } dwmac_desc_rx; |
|---|
| 71 | |
|---|
| 72 | typedef struct { |
|---|
| 73 | uint32_t des0; |
|---|
| 74 | #define DWMAC_DESC_TX_DES0_OWN_BIT DWMAC_DESC_BIT32(31) |
|---|
| 75 | #define DWMAC_DESC_TX_DES0_TX_TIMESTAMP_STATUS DWMAC_DESC_BIT32(17) |
|---|
| 76 | #define DWMAC_DESC_TX_DES0_IP_HEADER_ERROR DWMAC_DESC_BIT32(16) |
|---|
| 77 | #define DWMAC_DESC_TX_DES0_ERROR_SUMMARY DWMAC_DESC_BIT32(15) |
|---|
| 78 | #define DWMAC_DESC_TX_DES0_JABBER_TIMEOUT DWMAC_DESC_BIT32(14) |
|---|
| 79 | #define DWMAC_DESC_TX_DES0_FRAME_FLUSHED DWMAC_DESC_BIT32(13) |
|---|
| 80 | #define DWMAC_DESC_TX_DES0_PAYLOAD_CHECKSUM_ERROR DWMAC_DESC_BIT32(12) |
|---|
| 81 | #define DWMAC_DESC_TX_DES0_LOSS_OF_CARRIER DWMAC_DESC_BIT32(11) |
|---|
| 82 | #define DWMAC_DESC_TX_DES0_NO_CARRIER DWMAC_DESC_BIT32(10) |
|---|
| 83 | #define DWMAC_DESC_TX_DES0_EXCESSIVE_COLLISION DWMAC_DESC_BIT32(8) |
|---|
| 84 | #define DWMAC_DESC_TX_DES0_VLAN_FRAME DWMAC_DESC_BIT32(7) |
|---|
| 85 | #define DWMAC_DESC_TX_DES0_COLLISION_TIMEOUT(val) DWMAC_DESC_FLD32(val, 3, 6) |
|---|
| 86 | #define DWMAC_DESC_TX_DES0_COLLISION_TIMEOUT_GET(reg) DWMAC_DESC_FLD32GET(reg, 3, 6) |
|---|
| 87 | #define DWMAC_DESC_TX_DES0_COLLISION_TIMEOUT_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 3, 6) |
|---|
| 88 | #define DWMAC_DESC_TX_DES0_EXCESSIVE_DEFERAL DWMAC_DESC_BIT32(2) |
|---|
| 89 | #define DWMAC_DESC_TX_DES0_UNDERFLOW_ERROR DWMAC_DESC_BIT32(1) |
|---|
| 90 | #define DWMAC_DESC_TX_DES0_DEFERED_BIT DWMAC_DESC_BIT32(0) |
|---|
| 91 | uint32_t des1; |
|---|
| 92 | #define DWMAC_DESC_TX_DES1_IRQ_ON_COMPLETION DWMAC_DESC_BIT32(31) |
|---|
| 93 | #define DWMAC_DESC_TX_DES1_LAST_SEGMENT DWMAC_DESC_BIT32(30) |
|---|
| 94 | #define DWMAC_DESC_TX_DES1_FIRST_SEGMENT DWMAC_DESC_BIT32(29) |
|---|
| 95 | #define DWMAC_DESC_TX_DES1_CHECKSUM_INSERTION_CONTROL(val) DWMAC_DESC_FLD32(val, 27, 28) |
|---|
| 96 | #define DWMAC_DESC_TX_DES1_CHECKSUM_INSERTION_CONTROL_GET(reg) DWMAC_DESC_FLD32GET(reg, 27, 28) |
|---|
| 97 | #define DWMAC_DESC_TX_DES1_CHECKSUM_INSERTION_CONTROL_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 27, 28) |
|---|
| 98 | #define DWMAC_DESC_TX_DES1_DISABLE_CRC DWMAC_DESC_BIT32(26) |
|---|
| 99 | #define DWMAC_DESC_TX_DES1_TRANSMIT_END_OF_RING DWMAC_DESC_BIT32(25) |
|---|
| 100 | #define DWMAC_DESC_TX_DES1_SECOND_ADDRESS_CHAINED DWMAC_DESC_BIT32(24) |
|---|
| 101 | #define DWMAC_DESC_TX_DES1_DISABLE_PADDING DWMAC_DESC_BIT32(23) |
|---|
| 102 | #define DWMAC_DESC_TX_DES1_TRANSMIT_TIMESTAMP_ENABLE DWMAC_DESC_BIT32(22) |
|---|
| 103 | #define DWMAC_DESC_TX_DES1_TRANMIT_BUFFER_2_SIZE(val) DWMAC_DESC_FLD32(val, 11, 21) |
|---|
| 104 | #define DWMAC_DESC_TX_DES1_TRANMIT_BUFFER_2_SIZE_GET(reg) DWMAC_DESC_FLD32GET(reg, 11, 21) |
|---|
| 105 | #define DWMAC_DESC_TX_DES1_TRANMIT_BUFFER_2_SIZE_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 11, 21) |
|---|
| 106 | #define DWMAC_DESC_TX_DES1_TRANSMIT_BUFFER_1_SIZE(val) DWMAC_DESC_FLD32(val, 0, 10) |
|---|
| 107 | #define DWMAC_DESC_TX_DES1_TRANSMIT_BUFFER_1_SIZE_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 10) |
|---|
| 108 | #define DWMAC_DESC_TX_DES1_TRANSMIT_BUFFER_1_SIZE_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 10) |
|---|
| 109 | uint32_t des2; |
|---|
| 110 | #define DWMAC_DESC_TX_DES2_BUFF_1_ADDR_PTR(val) DWMAC_DESC_FLD32(val, 0, 31) |
|---|
| 111 | #define DWMAC_DESC_TX_DES2_BUFF_1_ADDR_PTR_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31) |
|---|
| 112 | #define DWMAC_DESC_TX_DES2_BUFF_1_ADDR_PTR_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31) |
|---|
| 113 | #define DWMAC_DESC_TX_DES2_IEEE_TRANSMIT_FRAME_TIMESTAMP_LOW(val) DWMAC_DESC_FLD32(val, 0, 31) |
|---|
| 114 | #define DWMAC_DESC_TX_DES2_IEEE_TRANSMIT_FRAME_TIMESTAMP_LOW_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31) |
|---|
| 115 | #define DWMAC_DESC_TX_DES2_IEEE_TRANSMIT_FRAME_TIMESTAMP_LOW_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31) |
|---|
| 116 | uint32_t des3; |
|---|
| 117 | #define DWMAC_DESC_TX_DES3_BUFF_2_ADDR_PTR(val) DWMAC_DESC_FLD32(val, 0, 31) |
|---|
| 118 | #define DWMAC_DESC_TX_DES3_BUFF_2_ADDR_PTR_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31) |
|---|
| 119 | #define DWMAC_DESC_TX_DES3_BUFF_2_ADDR_PTR_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31) |
|---|
| 120 | #define DWMAC_DESC_TX_DES3_IEEE_TRANSMIT_FRAME_TIMESTAMP_LOW(val) DWMAC_DESC_FLD32(val, 0, 31) |
|---|
| 121 | #define DWMAC_DESC_TX_DES3_IEEE_TRANSMIT_FRAME_TIMESTAMP_LOW_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31) |
|---|
| 122 | #define DWMAC_DESC_TX_DES3_IEEE_TRANSMIT_FRAME_TIMESTAMP_LOW_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31) |
|---|
| 123 | } dwmac_desc_tx; |
|---|
| 124 | |
|---|
| 125 | typedef struct { |
|---|
| 126 | uint32_t des0; |
|---|
| 127 | #define DWMAC_DESC_ERX_DES0_OWN_BIT DWMAC_DESC_BIT32(31) |
|---|
| 128 | #define DWMAC_DESC_ERX_DES0_DEST_ADDR_FILTER_FAIL DWMAC_DESC_BIT32(30) |
|---|
| 129 | #define DWMAC_DESC_ERX_DES0_FRAME_LENGTH(val) DWMAC_DESC_FLD32(val, 16, 29) |
|---|
| 130 | #define DWMAC_DESC_ERX_DES0_FRAME_LENGTH_GET(reg) DWMAC_DESC_FLD32GET(reg, 16, 29) |
|---|
| 131 | #define DWMAC_DESC_ERX_DES0_FRAME_LENGTH_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 16, 29) |
|---|
| 132 | #define DWMAC_DESC_ERX_DES0_ERROR_SUMMARY DWMAC_DESC_BIT32(15) |
|---|
| 133 | #define DWMAC_DESC_ERX_DES0_DESCRIPTOR_ERROR DWMAC_DESC_BIT32(14) |
|---|
| 134 | #define DWMAC_DESC_ERX_DES0_SRC_ADDR_FILTER_FAIL DWMAC_DESC_BIT32(13) |
|---|
| 135 | #define DWMAC_DESC_ERX_DES0_LENGTH_ERROR DWMAC_DESC_BIT32(12) |
|---|
| 136 | #define DWMAC_DESC_ERX_DES0_OVERFLOW_ERROR DWMAC_DESC_BIT32(11) |
|---|
| 137 | #define DWMAC_DESC_ERX_DES0_VLAN_TAG DWMAC_DESC_BIT32(10) |
|---|
| 138 | #define DWMAC_DESC_ERX_DES0_FIRST_DESCRIPTOR DWMAC_DESC_BIT32(9) |
|---|
| 139 | #define DWMAC_DESC_ERX_DES0_LAST_DESCRIPTOR DWMAC_DESC_BIT32(8) |
|---|
| 140 | #define DWMAC_DESC_ERX_DES0_TIMESTAMP_AVAIL_OR_CHECKSUM_ERROR_OR_GIANT_FRAME DWMAC_DESC_BIT32(7) |
|---|
| 141 | #define DWMAC_DESC_ERX_DES0_LATE_COLLISION DWMAC_DESC_BIT32(6) |
|---|
| 142 | #define DWMAC_DESC_ERX_DES0_FREAME_TYPE DWMAC_DESC_BIT32(5) |
|---|
| 143 | #define DWMAC_DESC_ERX_DES0_RECEIVE_WATCHDOG_TIMEOUT DWMAC_DESC_BIT32(4) |
|---|
| 144 | #define DWMAC_DESC_ERX_DES0_RECEIVE_ERROR DWMAC_DESC_BIT32(3) |
|---|
| 145 | #define DWMAC_DESC_ERX_DES0_DRIBBLE_BIT_ERROR DWMAC_DESC_BIT32(2) |
|---|
| 146 | #define DWMAC_DESC_ERX_DES0_CRC_ERROR DWMAC_DESC_BIT32(1) |
|---|
| 147 | #define DWMAC_DESC_ERX_DES0_EXT_STATUS_AVAIL_OR_RX_MAC_ADDR_STATUS DWMAC_DESC_BIT32(0) |
|---|
| 148 | uint32_t des1; |
|---|
| 149 | #define DWMAC_DESC_ERX_DES1_DISABLE_IRQ_ON_COMPLETION DWMAC_DESC_BIT32(31) |
|---|
| 150 | #define DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_2_SIZE(val) DWMAC_DESC_FLD32(val, 16, 28) |
|---|
| 151 | #define DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_2_SIZE_GET(reg) DWMAC_DESC_FLD32GET(reg, 16, 28) |
|---|
| 152 | #define DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_2_SIZE_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 16, 28) |
|---|
| 153 | #define DWMAC_DESC_ERX_DES1_RECEIVE_END_OF_RING DWMAC_DESC_BIT32(15) |
|---|
| 154 | #define DWMAC_DESC_ERX_DES1_SECOND_ADDR_CHAINED DWMAC_DESC_BIT32(14) |
|---|
| 155 | #define DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_1_SIZE(val) DWMAC_DESC_FLD32(val, 0, 12) |
|---|
| 156 | #define DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_1_SIZE_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 12) |
|---|
| 157 | #define DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_1_SIZE_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 12) |
|---|
| 158 | uint32_t des2; |
|---|
| 159 | #define DWMAC_DESC_ERX_DES2_BUFF_1_ADDR_PTR(val) DWMAC_DESC_FLD32(val, 0, 31) |
|---|
| 160 | #define DWMAC_DESC_ERX_DES2_BUFF_1_ADDR_PTR_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31) |
|---|
| 161 | #define DWMAC_DESC_ERX_DES2_BUFF_1_ADDR_PTR_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31) |
|---|
| 162 | uint32_t des3; |
|---|
| 163 | #define DWMAC_DESC_ERX_DES3_BUFF_2_ADDR_PTR(val) DWMAC_DESC_FLD32(val, 0, 31) |
|---|
| 164 | #define DWMAC_DESC_ERX_DES3_BUFF_2_ADDR_PTR_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31) |
|---|
| 165 | #define DWMAC_DESC_ERX_DES3_BUFF_2_ADDR_PTR_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31) |
|---|
| 166 | } dwmac_desc_erx; |
|---|
| 167 | |
|---|
| 168 | typedef struct { |
|---|
| 169 | uint32_t des0; |
|---|
| 170 | #define DWMAC_DESC_ETX_DES0_OWN_BIT DWMAC_DESC_BIT32(31) |
|---|
| 171 | #define DWMAC_DESC_ETX_DES0_IRQ_ON_COMPLETION DWMAC_DESC_BIT32(30) |
|---|
| 172 | #define DWMAC_DESC_ETX_DES0_LAST_SEGMENT DWMAC_DESC_BIT32(29) |
|---|
| 173 | #define DWMAC_DESC_ETX_DES0_FIRST_SEGMENT DWMAC_DESC_BIT32(28) |
|---|
| 174 | #define DWMAC_DESC_ETX_DES0_DISABLE_CRC DWMAC_DESC_BIT32(27) |
|---|
| 175 | #define DWMAC_DESC_ETX_DES0_DISABLE_PAD DWMAC_DESC_BIT32(26) |
|---|
| 176 | #define DWMAC_DESC_ETX_DES0_TRANSMIT_TIMESTAMP_ENABLE DWMAC_DESC_BIT32(25) |
|---|
| 177 | #define DWMAC_DESC_ETX_DES0_CHECKSUM_INSERTION_CONTROL(val) DWMAC_DESC_FLD32(val, 22, 23) |
|---|
| 178 | #define DWMAC_DESC_ETX_DES0_CHECKSUM_INSERTION_CONTROL_GET(reg) DWMAC_DESC_FLD32GET(reg, 22, 23) |
|---|
| 179 | #define DWMAC_DESC_ETX_DES0_CHECKSUM_INSERTION_CONTROL_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 22, 23) |
|---|
| 180 | #define DWMAC_DESC_ETX_DES0_TRANSMIT_END_OF_RING DWMAC_DESC_BIT32(21) |
|---|
| 181 | #define DWMAC_DESC_ETX_DES0_SECOND_ADDR_CHAINED DWMAC_DESC_BIT32(20) |
|---|
| 182 | #define DWMAC_DESC_ETX_DES0_TRANSMIT_TIMESTAMP_STATUS DWMAC_DESC_BIT32(17) |
|---|
| 183 | #define DWMAC_DESC_ETX_DES0_IP_HEADER_ERROR DWMAC_DESC_BIT32(16) |
|---|
| 184 | #define DWMAC_DESC_ETX_DES0_ERROR_SUMMARY DWMAC_DESC_BIT32(15) |
|---|
| 185 | #define DWMAC_DESC_ETX_DES0_JABBER_TIMEOUT DWMAC_DESC_BIT32(14) |
|---|
| 186 | #define DWMAC_DESC_ETX_DES0_FRAME_FLUSHED DWMAC_DESC_BIT32(13) |
|---|
| 187 | #define DWMAC_DESC_ETX_DES0_IP_PAYLOAD_ERROR DWMAC_DESC_BIT32(12) |
|---|
| 188 | #define DWMAC_DESC_ETX_DES0_LOSS_OF_CARRIER DWMAC_DESC_BIT32(11) |
|---|
| 189 | #define DWMAC_DESC_ETX_DES0_NO_CARRIER DWMAC_DESC_BIT32(10) |
|---|
| 190 | #define DWMAC_DESC_ETX_DES0_EXCESSIVE_COLLISION DWMAC_DESC_BIT32(8) |
|---|
| 191 | #define DWMAC_DESC_ETX_DES0_VLAN_FRAME DWMAC_DESC_BIT32(7) |
|---|
| 192 | #define DWMAC_DESC_ETX_DES0_COLLISION_COUNT(val) DWMAC_DESC_FLD32(val, 3, 6) |
|---|
| 193 | #define DWMAC_DESC_ETX_DES0_COLLISION_COUNT_GET(reg) DWMAC_DESC_FLD32GET(reg, 3, 6) |
|---|
| 194 | #define DWMAC_DESC_ETX_DES0_COLLISION_COUNT_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 3, 6) |
|---|
| 195 | #define DWMAC_DESC_ETX_DES0_EXCESSIVE_DEFERAL DWMAC_DESC_BIT32(2) |
|---|
| 196 | #define DWMAC_DESC_ETX_DES0_UNDERFLOW_ERROR DWMAC_DESC_BIT32(1) |
|---|
| 197 | #define DWMAC_DESC_ETX_DES0_DEFERRED_BIT DWMAC_DESC_BIT32(0) |
|---|
| 198 | uint32_t des1; |
|---|
| 199 | #define DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_2_SIZE(val) DWMAC_DESC_FLD32(val, 16, 28) |
|---|
| 200 | #define DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_2_SIZE_GET(reg) DWMAC_DESC_FLD32GET(reg, 16, 28) |
|---|
| 201 | #define DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_2_SIZE_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 16, 28) |
|---|
| 202 | #define DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_1_SIZE(val) DWMAC_DESC_FLD32(val, 0, 12) |
|---|
| 203 | #define DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_1_SIZE_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 12) |
|---|
| 204 | #define DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_1_SIZE_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 12) |
|---|
| 205 | uint32_t des2; |
|---|
| 206 | #define DWMAC_DESC_ETX_DES2_BUFF_1_ADDR_PTR(val) DWMAC_DESC_FLD32(val, 0, 31) |
|---|
| 207 | #define DWMAC_DESC_ETX_DES2_BUFF_1_ADDR_PTR_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31) |
|---|
| 208 | #define DWMAC_DESC_ETX_DES2_BUFF_1_ADDR_PTR_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31) |
|---|
| 209 | uint32_t des3; |
|---|
| 210 | #define DWMAC_DESC_ETX_DES3_BUFF_2_ADDR_PTR(val) DWMAC_DESC_FLD32(val, 0, 31) |
|---|
| 211 | #define DWMAC_DESC_ETX_DES3_BUFF_2_ADDR_PTR_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31) |
|---|
| 212 | #define DWMAC_DESC_ETX_DES3_BUFF_2_ADDR_PTR_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31) |
|---|
| 213 | } dwmac_desc_etx; |
|---|
| 214 | |
|---|
| 215 | typedef union { |
|---|
| 216 | dwmac_desc_rx rx; |
|---|
| 217 | dwmac_desc_tx tx; |
|---|
| 218 | dwmac_desc_erx erx; |
|---|
| 219 | dwmac_desc_etx etx; |
|---|
| 220 | } dwmac_desc; |
|---|
| 221 | |
|---|
| 222 | typedef struct { |
|---|
| 223 | dwmac_desc_erx des0_3; |
|---|
| 224 | uint32_t des4; |
|---|
| 225 | #define DWMAC_DESC_EXT_ERX_DES4_LAYER3_AND_LAYER4_FILTER_MATCHED(val) DWMAC_DESC_FLD32(val, 26, 27) |
|---|
| 226 | #define DWMAC_DESC_EXT_ERX_DES4_LAYER3_AND_LAYER4_FILTER_MATCHED_GET(reg) DWMAC_DESC_FLD32GET(reg, 26, 27) |
|---|
| 227 | #define DWMAC_DESC_EXT_ERX_DES4_LAYER3_AND_LAYER4_FILTER_MATCHED_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 26, 27) |
|---|
| 228 | #define DWMAC_DESC_EXT_ERX_DES4_LAYER4_FILTER_MATCH DWMAC_DESC_BIT32(25) |
|---|
| 229 | #define DWMAC_DESC_EXT_ERX_DES4_LAYER3_FILTER_MATCH DWMAC_DESC_BIT32(24) |
|---|
| 230 | #define DWMAC_DESC_EXT_ERX_DES4_TIMESTAMP_DROPPED DWMAC_DESC_BIT32(14) |
|---|
| 231 | #define DWMAC_DESC_EXT_ERX_DES4_PTP_VERSION DWMAC_DESC_BIT32(13) |
|---|
| 232 | #define DWMAC_DESC_EXT_ERX_DES4_PTP_FRAME_TYPE DWMAC_DESC_BIT32(12) |
|---|
| 233 | #define DWMAC_DESC_EXT_ERX_DES4_MESSAGE_TYPE(val) DWMAC_DESC_FLD32(val, 8, 11) |
|---|
| 234 | #define DWMAC_DESC_EXT_ERX_DES4_MESSAGE_TYPE_GET(reg) DWMAC_DESC_FLD32GET(reg, 8, 11) |
|---|
| 235 | #define DWMAC_DESC_EXT_ERX_DES4_MESSAGE_TYPE_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 8, 11) |
|---|
| 236 | #define DWMAC_DESC_EXT_ERX_DES4_IPV6_PACKET_RECEIVED DWMAC_DESC_BIT32(7) |
|---|
| 237 | #define DWMAC_DESC_EXT_ERX_DES4_IPV4_PACKET_RECEIVED DWMAC_DESC_BIT32(6) |
|---|
| 238 | #define DWMAC_DESC_EXT_ERX_DES4_IP_CHECKSUM_BYPASSED DWMAC_DESC_BIT32(5) |
|---|
| 239 | #define DWMAC_DESC_EXT_ERX_DES4_IP_PAYLOAD_ERROR DWMAC_DESC_BIT32(4) |
|---|
| 240 | #define DWMAC_DESC_EXT_ERX_DES4_IP_HEADER_ERROR DWMAC_DESC_BIT32(3) |
|---|
| 241 | #define DWMAC_DESC_EXT_ERX_DES4_IP_PAYLOAD_TYPE(val) DWMAC_DESC_FLD32(val, 0, 2) |
|---|
| 242 | #define DWMAC_DESC_EXT_ERX_DES4_IP_PAYLOAD_TYPE_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 2) |
|---|
| 243 | #define DWMAC_DESC_EXT_ERX_DES4_IP_PAYLOAD_TYPE_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 2) |
|---|
| 244 | uint32_t des5; |
|---|
| 245 | uint32_t des6; |
|---|
| 246 | #define DWMAC_DESC_EXT_ERX_DES6_RECEIVE_FRAME_TIMESTAMP_LOW(val) DWMAC_DESC_FLD32(val, 0, 31) |
|---|
| 247 | #define DWMAC_DESC_EXT_ERX_DES6_RECEIVE_FRAME_TIMESTAMP_LOW_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31) |
|---|
| 248 | #define DWMAC_DESC_EXT_ERX_DES6_RECEIVE_FRAME_TIMESTAMP_LOW_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31) |
|---|
| 249 | uint32_t des7; |
|---|
| 250 | #define DWMAC_DESC_EXT_ERX_DES7_RECEIVE_FRAME_TIMESTAMP_HIGH(val) DWMAC_DESC_FLD32(val, 0, 31) |
|---|
| 251 | #define DWMAC_DESC_EXT_ERX_DES7_RECEIVE_FRAME_TIMESTAMP_HIGH_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31) |
|---|
| 252 | #define DWMAC_DESC_EXT_ERX_DES7_RECEIVE_FRAME_TIMESTAMP_HIGH_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31) |
|---|
| 253 | } dwmac_desc_ext_erx; |
|---|
| 254 | |
|---|
| 255 | typedef struct { |
|---|
| 256 | dwmac_desc_etx des0_3; |
|---|
| 257 | uint32_t des4; |
|---|
| 258 | uint32_t des5; |
|---|
| 259 | uint32_t des6; |
|---|
| 260 | #define DWMAC_DESC_EXT_ETX_DES6_TRANSMIT_FRAME_TIMESTAMP_LOW(val) DWMAC_DESC_FLD32(val, 0, 31) |
|---|
| 261 | #define DWMAC_DESC_EXT_ETX_DES6_TRANSMIT_FRAME_TIMESTAMP_LOW_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31) |
|---|
| 262 | #define DWMAC_DESC_EXT_ETX_DES6_TRANSMIT_FRAME_TIMESTAMP_LOW_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31) |
|---|
| 263 | uint32_t des7; |
|---|
| 264 | #define DWMAC_DESC_EXT_ETX_DES7_TRANSMIT_FRAME_TIMESTAMP_HIGH(val) DWMAC_DESC_FLD32(val, 0, 31) |
|---|
| 265 | #define DWMAC_DESC_EXT_ETX_DES7_TRANSMIT_FRAME_TIMESTAMP_HIGH_GET(reg) DWMAC_DESC_FLD32GET(reg, 0, 31) |
|---|
| 266 | #define DWMAC_DESC_EXT_ETX_DES7_TRANSMIT_FRAME_TIMESTAMP_HIGH_SET(reg, val) DWMAC_DESC_FLD32SET(reg, val, 0, 31) |
|---|
| 267 | } dwmac_desc_ext_etx; |
|---|
| 268 | |
|---|
| 269 | typedef union { |
|---|
| 270 | dwmac_desc_ext_erx erx; |
|---|
| 271 | dwmac_desc_ext_etx etx; |
|---|
| 272 | } dwmac_desc_ext; |
|---|
| 273 | |
|---|
| 274 | #endif /* DWMAC_DESC_RX_REGS_H */ |
|---|
![[RTEMS Logo]](/images/logo.png){kind=logo}
