[4953b724] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @brief DWMAC 10/100/1000 Enhanced DMA Descriptor Handling. |
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| 5 | * |
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| 6 | * DWMAC 10/100/1000 on-chip Ethernet controllers. |
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| 7 | * Functions and data for the handling of enhanced DMA descriptors. |
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| 8 | */ |
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| 9 | |
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| 10 | /* |
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| 11 | * Copyright (c) 2013 embedded brains GmbH. All rights reserved. |
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| 12 | * |
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| 13 | * embedded brains GmbH |
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| 14 | * Dornierstr. 4 |
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| 15 | * 82178 Puchheim |
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| 16 | * Germany |
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| 17 | * <rtems@embedded-brains.de> |
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| 18 | * |
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| 19 | * The license and distribution terms for this file may be |
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| 20 | * found in the file LICENSE in this distribution or at |
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| 21 | * http://www.rtems.org/license/LICENSE. |
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| 22 | */ |
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| 23 | |
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| 24 | #include <assert.h> |
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| 25 | #include <stdlib.h> |
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| 26 | #include <stdio.h> |
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| 27 | #include "dwmac-common.h" |
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| 28 | #include "dwmac-desc-com.h" |
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| 29 | #include "dwmac-core.h" |
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| 30 | #include <sys/queue.h> |
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| 31 | |
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| 32 | #undef DWMAC_DESC_ENH_DEBUG |
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| 33 | #ifdef DWMAC_DESC_ENH_DEBUG |
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| 34 | #define DWMAC_DESC_ENH_PRINT_DBG( fmt, args ... ) printk( fmt, ## args ) |
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| 35 | #else |
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| 36 | #define DWMAC_DESC_ENH_PRINT_DBG( fmt, args ... ) do { } while ( 0 ) |
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| 37 | #endif |
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| 38 | |
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| 39 | typedef enum { |
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| 40 | DWMAC_IP_PAYLOAD_TYPE_UNKNOWN, |
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| 41 | DWMAC_IP_PAYLOAD_TYPE_UDP, |
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| 42 | DWMAC_IP_PAYLOAD_TYPE_TCP, |
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| 43 | DWMAC_IP_PAYLOAD_TYPE_ICMP |
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| 44 | } dwmac_ip_payload_type; |
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| 45 | |
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| 46 | static void dwmac_desc_enh_rx_set_on_ring_chain( |
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| 47 | volatile dwmac_desc_ext *p, int end ) |
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| 48 | { |
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| 49 | /* For simplicity reasons we will not use the second buffer. |
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| 50 | * If we would use it we would have to set the size to MCLBYTES -1 */ |
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| 51 | p->erx.des0_3.des1 = DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_2_SIZE_SET( |
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| 52 | p->erx.des0_3.des1, 0 |
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| 53 | ); |
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| 54 | p->erx.des0_3.des3 = (uint32_t) NULL; |
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| 55 | |
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| 56 | if ( end ) |
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| 57 | p->erx.des0_3.des1 |= DWMAC_DESC_ERX_DES1_RECEIVE_END_OF_RING; |
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| 58 | } |
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| 59 | |
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| 60 | static void dwmac_desc_enh_tx_set_on_ring_chain( |
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| 61 | volatile dwmac_desc_ext *p, const bool end ) |
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| 62 | { |
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| 63 | if ( end ) |
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| 64 | p->etx.des0_3.des0 |= DWMAC_DESC_ETX_DES0_TRANSMIT_END_OF_RING; |
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| 65 | } |
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| 66 | |
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| 67 | static void dwmac_desc_enh_set_tx_desc_len( |
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| 68 | volatile dwmac_desc_ext *p_enh, size_t len ) |
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| 69 | { |
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| 70 | p_enh->etx.des0_3.des1 = DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_1_SIZE_SET( |
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| 71 | p_enh->etx.des0_3.des1, |
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| 72 | len |
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| 73 | ); |
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| 74 | } |
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| 75 | |
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| 76 | static bool dwmac_desc_enh_is_giant_frame( const uint32_t des0 ) |
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| 77 | { |
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| 78 | return ( |
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| 79 | ( des0 |
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| 80 | & DWMAC_DESC_ERX_DES0_TIMESTAMP_AVAIL_OR_CHECKSUM_ERROR_OR_GIANT_FRAME |
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| 81 | ) != 0 |
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| 82 | ); |
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| 83 | } |
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| 84 | |
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| 85 | static bool dwmac_desc_enh_is_udp_payload( const uint32_t des4 ) |
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| 86 | { |
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| 87 | return ( |
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| 88 | DWMAC_DESC_EXT_ERX_DES4_IP_PAYLOAD_TYPE_GET( des4 ) |
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| 89 | == DWMAC_IP_PAYLOAD_TYPE_UDP |
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| 90 | ); |
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| 91 | } |
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| 92 | |
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| 93 | static bool dwmac_desc_enh_is_tcp_payload( const uint32_t des4 ) |
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| 94 | { |
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| 95 | return ( |
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| 96 | DWMAC_DESC_EXT_ERX_DES4_IP_PAYLOAD_TYPE_GET( des4 ) |
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| 97 | == DWMAC_IP_PAYLOAD_TYPE_TCP |
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| 98 | ); |
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| 99 | } |
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| 100 | |
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| 101 | static bool dwmac_desc_enh_is_icmp_payload( const uint32_t des4 ) |
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| 102 | { |
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| 103 | return ( |
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| 104 | DWMAC_DESC_EXT_ERX_DES4_IP_PAYLOAD_TYPE_GET( des4 ) |
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| 105 | == DWMAC_IP_PAYLOAD_TYPE_ICMP |
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| 106 | ); |
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| 107 | } |
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| 108 | |
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| 109 | static dwmac_common_rx_frame_status dwmac_desc_enh_coe_status( |
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| 110 | volatile dwmac_desc_ext *p_enh ) |
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| 111 | { |
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| 112 | dwmac_common_rx_frame_status ret = DWMAC_COMMON_RX_FRAME_STATUS_GOOD; |
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| 113 | const uint32_t DES0 = p_enh->erx.des0_3.des0; |
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| 114 | const uint32_t DES4 = p_enh->erx.des4; |
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| 115 | |
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| 116 | |
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| 117 | if ( ( DES0 & DWMAC_DESC_ERX_DES0_EXT_STATUS_AVAIL_OR_RX_MAC_ADDR_STATUS ) |
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| 118 | != 0 ) { |
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| 119 | if ( !dwmac_desc_enh_is_giant_frame( DES0 ) |
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| 120 | && ( DES0 & DWMAC_DESC_ERX_DES0_FREAME_TYPE ) == 0 |
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| 121 | && ( DES4 & DWMAC_DESC_EXT_ERX_DES4_IPV6_PACKET_RECEIVED ) == 0 |
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| 122 | && ( DES4 & DWMAC_DESC_EXT_ERX_DES4_IPV4_PACKET_RECEIVED ) == 0 |
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| 123 | && ( DES4 & DWMAC_DESC_EXT_ERX_DES4_IP_PAYLOAD_ERROR ) == 0 |
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| 124 | && ( DES4 & DWMAC_DESC_EXT_ERX_DES4_IP_HEADER_ERROR ) == 0 ) { |
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| 125 | DWMAC_DESC_ENH_PRINT_DBG( "RX Des0 status: IEEE 802.3 Type frame.\n" ); |
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| 126 | ret = DWMAC_COMMON_RX_FRAME_STATUS_LLC_SNAP; |
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| 127 | } else if ( ( ( DES4 & DWMAC_DESC_EXT_ERX_DES4_IPV6_PACKET_RECEIVED ) != 0 |
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| 128 | || ( DES4 & DWMAC_DESC_EXT_ERX_DES4_IPV4_PACKET_RECEIVED ) |
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| 129 | != 0 ) |
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| 130 | && dwmac_desc_enh_is_giant_frame( DES0 ) ) { |
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| 131 | DWMAC_DESC_ENH_PRINT_DBG( "RX Des0 status: IPv4/6 No CSUM Error.\n" ); |
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| 132 | ret = DWMAC_COMMON_RX_FRAME_STATUS_GOOD; |
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| 133 | } else if ( ( ( DES4 & DWMAC_DESC_EXT_ERX_DES4_IPV6_PACKET_RECEIVED ) != 0 |
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| 134 | || ( DES4 & DWMAC_DESC_EXT_ERX_DES4_IPV4_PACKET_RECEIVED ) |
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| 135 | != 0 ) |
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| 136 | && ( DES4 & DWMAC_DESC_EXT_ERX_DES4_IP_PAYLOAD_ERROR ) != 0 ) { |
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| 137 | DWMAC_DESC_ENH_PRINT_DBG( "RX Des0 status: IPv4/6 Payload Error.\n" ); |
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| 138 | ret = DWMAC_COMMON_RX_FRAME_STATUS_CSUM_NONE; |
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| 139 | } else if ( ( ( DES4 & DWMAC_DESC_EXT_ERX_DES4_IPV6_PACKET_RECEIVED ) != 0 |
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| 140 | || ( DES4 & DWMAC_DESC_EXT_ERX_DES4_IPV4_PACKET_RECEIVED ) |
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| 141 | != 0 ) |
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| 142 | && ( DES4 & DWMAC_DESC_EXT_ERX_DES4_IP_HEADER_ERROR ) != 0 ) { |
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| 143 | DWMAC_DESC_ENH_PRINT_DBG( "RX Des0 status: IPv4/6 Header Error.\n" ); |
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| 144 | ret = DWMAC_COMMON_RX_FRAME_STATUS_CSUM_NONE; |
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| 145 | } else if ( ( ( DES4 & DWMAC_DESC_EXT_ERX_DES4_IPV6_PACKET_RECEIVED ) != 0 |
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| 146 | || ( DES4 & DWMAC_DESC_EXT_ERX_DES4_IPV4_PACKET_RECEIVED ) |
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| 147 | != 0 ) |
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| 148 | && ( DES4 & DWMAC_DESC_EXT_ERX_DES4_IP_PAYLOAD_ERROR ) != 0 |
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| 149 | && ( DES4 & DWMAC_DESC_EXT_ERX_DES4_IP_HEADER_ERROR ) != 0 ) { |
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| 150 | DWMAC_DESC_ENH_PRINT_DBG( |
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| 151 | "RX Des0 status: IPv4/6 Header and Payload Error.\n" ); |
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| 152 | ret = DWMAC_COMMON_RX_FRAME_STATUS_CSUM_NONE; |
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| 153 | } else if ( ( ( DES4 & DWMAC_DESC_EXT_ERX_DES4_IPV6_PACKET_RECEIVED ) != 0 |
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| 154 | || ( DES4 & DWMAC_DESC_EXT_ERX_DES4_IPV4_PACKET_RECEIVED ) |
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| 155 | != 0 ) |
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| 156 | && ( !dwmac_desc_enh_is_udp_payload( DES4 ) ) |
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| 157 | && ( !dwmac_desc_enh_is_tcp_payload( DES4 ) ) |
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| 158 | && ( !dwmac_desc_enh_is_icmp_payload( DES4 ) ) ) { |
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| 159 | DWMAC_DESC_ENH_PRINT_DBG( |
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| 160 | "RX Des0 status: IPv4/6 unsupported IP PAYLOAD.\n" ); |
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| 161 | ret = DWMAC_COMMON_RX_FRAME_STATUS_DISCARD; |
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| 162 | } else if ( ( DES4 & DWMAC_DESC_EXT_ERX_DES4_IPV6_PACKET_RECEIVED ) == 0 |
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| 163 | && ( DES4 & DWMAC_DESC_EXT_ERX_DES4_IPV4_PACKET_RECEIVED ) |
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| 164 | == 0 ) { |
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| 165 | DWMAC_DESC_ENH_PRINT_DBG( "RX Des0 status: No IPv4, IPv6 frame.\n" ); |
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| 166 | ret = DWMAC_COMMON_RX_FRAME_STATUS_DISCARD; |
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| 167 | } |
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| 168 | } else { |
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| 169 | uint32_t status = ( |
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| 170 | (uint32_t) ( dwmac_desc_enh_is_giant_frame( DES0 ) << 2U ) |
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| 171 | | (uint32_t) ( ( ( DES0 & DWMAC_DESC_ERX_DES0_FREAME_TYPE ) |
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| 172 | != 0 ) << 1U ) ) |
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| 173 | & 0x7U; |
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| 174 | |
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| 175 | /* bits 5 7 0 | Frame status |
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| 176 | * ---------------------------------------------------------- |
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| 177 | * 0 0 0 | IEEE 802.3 Type frame (length < 1536 octects) |
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| 178 | * 1 0 0 | IPv4/6 No CSUM errorS. |
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| 179 | * 1 0 1 | IPv4/6 CSUM PAYLOAD error |
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| 180 | * 1 1 0 | IPv4/6 CSUM IP HR error |
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| 181 | * 1 1 1 | IPv4/6 IP PAYLOAD AND HEADER errorS |
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| 182 | * 0 0 1 | IPv4/6 unsupported IP PAYLOAD |
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| 183 | * 0 1 1 | COE bypassed.. no IPv4/6 frame |
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| 184 | * 0 1 0 | Reserved. |
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| 185 | */ |
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| 186 | if ( status == 0x0 ) { |
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| 187 | DWMAC_DESC_ENH_PRINT_DBG( "RX Des0 status: IEEE 802.3 Type frame.\n" ); |
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| 188 | ret = DWMAC_COMMON_RX_FRAME_STATUS_LLC_SNAP; |
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| 189 | } else if ( status == 0x4 ) { |
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| 190 | DWMAC_DESC_ENH_PRINT_DBG( "RX Des0 status: IPv4/6 No CSUM errorS.\n" ); |
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| 191 | ret = DWMAC_COMMON_RX_FRAME_STATUS_GOOD; |
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| 192 | } else if ( status == 0x5 ) { |
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| 193 | DWMAC_DESC_ENH_PRINT_DBG( "RX Des0 status: IPv4/6 Payload Error.\n" ); |
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| 194 | ret = DWMAC_COMMON_RX_FRAME_STATUS_CSUM_NONE; |
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| 195 | } else if ( status == 0x6 ) { |
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| 196 | DWMAC_DESC_ENH_PRINT_DBG( "RX Des0 status: IPv4/6 Header Error.\n" ); |
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| 197 | ret = DWMAC_COMMON_RX_FRAME_STATUS_CSUM_NONE; |
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| 198 | } else if ( status == 0x7 ) { |
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| 199 | DWMAC_DESC_ENH_PRINT_DBG( |
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| 200 | "RX Des0 status: IPv4/6 Header and Payload Error.\n" ); |
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| 201 | ret = DWMAC_COMMON_RX_FRAME_STATUS_CSUM_NONE; |
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| 202 | } else if ( status == 0x1 ) { |
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| 203 | DWMAC_DESC_ENH_PRINT_DBG( |
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| 204 | "RX Des0 status: IPv4/6 unsupported IP PAYLOAD.\n" ); |
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| 205 | ret = DWMAC_COMMON_RX_FRAME_STATUS_DISCARD; |
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| 206 | } else if ( status == 0x3 ) { |
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| 207 | DWMAC_DESC_ENH_PRINT_DBG( "RX Des0 status: No IPv4, IPv6 frame.\n" ); |
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| 208 | ret = DWMAC_COMMON_RX_FRAME_STATUS_DISCARD; |
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| 209 | } |
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| 210 | } |
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| 211 | |
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| 212 | return ret; |
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| 213 | } |
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| 214 | |
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| 215 | static int dwmac_desc_enh_get_tx_status( |
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| 216 | dwmac_common_context *self, |
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| 217 | const unsigned int idx_tx ) |
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| 218 | { |
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| 219 | int ret = 0; |
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| 220 | volatile dwmac_desc_ext *dma_tx = |
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| 221 | (volatile dwmac_desc_ext *) self->dma_tx; |
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| 222 | volatile dwmac_desc_ext *p_desc = &dma_tx[idx_tx]; |
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| 223 | dwmac_common_desc_status_counts_tx *counts = |
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| 224 | &self->stats.desc_status_counts_tx; |
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| 225 | |
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| 226 | |
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| 227 | if ( ( p_desc->etx.des0_3.des0 & DWMAC_DESC_ETX_DES0_ERROR_SUMMARY ) != 0 ) { |
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| 228 | DWMAC_DESC_ENH_PRINT_DBG( "DWMAC TX error... 0x%08x\n", p->des01.etx ); |
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| 229 | |
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| 230 | if ( ( p_desc->etx.des0_3.des0 & DWMAC_DESC_ETX_DES0_JABBER_TIMEOUT ) |
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| 231 | != 0 ) { |
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| 232 | DWMAC_DESC_ENH_PRINT_DBG( "\tjabber_timeout error\n" ); |
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| 233 | ++counts->jabber; |
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| 234 | } |
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| 235 | |
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| 236 | if ( ( p_desc->etx.des0_3.des0 & DWMAC_DESC_ETX_DES0_FRAME_FLUSHED ) |
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| 237 | != 0 ) { |
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| 238 | DWMAC_DESC_ENH_PRINT_DBG( "\tframe_flushed error\n" ); |
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| 239 | ++counts->frame_flushed; |
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| 240 | dwmac_core_dma_flush_tx_fifo( self ); |
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| 241 | } |
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| 242 | |
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| 243 | if ( ( p_desc->etx.des0_3.des0 & DWMAC_DESC_ETX_DES0_LOSS_OF_CARRIER ) |
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| 244 | != 0 ) { |
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| 245 | DWMAC_DESC_ENH_PRINT_DBG( "\tloss_carrier error\n" ); |
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| 246 | ++counts->losscarrier; |
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| 247 | } |
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| 248 | |
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| 249 | if ( ( p_desc->etx.des0_3.des0 & DWMAC_DESC_ETX_DES0_NO_CARRIER ) |
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| 250 | != 0 ) { |
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| 251 | DWMAC_DESC_ENH_PRINT_DBG( "\tno_carrier error\n" ); |
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| 252 | ++counts->no_carrier; |
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| 253 | } |
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| 254 | |
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| 255 | if ( ( p_desc->etx.des0_3.des0 & DWMAC_DESC_ETX_DES0_EXCESSIVE_COLLISION ) |
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| 256 | != 0 ) { |
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| 257 | DWMAC_DESC_ENH_PRINT_DBG( "\texcessive_collisions\n" ); |
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| 258 | ++counts->excessive_collisions; |
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| 259 | } |
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| 260 | |
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| 261 | if ( ( p_desc->etx.des0_3.des0 & DWMAC_DESC_ETX_DES0_EXCESSIVE_DEFERAL ) |
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| 262 | != 0 ) { |
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| 263 | DWMAC_DESC_ENH_PRINT_DBG( "\texcessive tx_deferral\n" ); |
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| 264 | ++counts->excessive_deferral; |
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| 265 | } |
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| 266 | |
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| 267 | if ( ( p_desc->etx.des0_3.des0 & DWMAC_DESC_ETX_DES0_UNDERFLOW_ERROR ) |
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| 268 | != 0 ) { |
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| 269 | DWMAC_DESC_ENH_PRINT_DBG( "\tunderflow error\n" ); |
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| 270 | dwmac_core_dma_flush_tx_fifo( self ); |
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| 271 | ++counts->underflow; |
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| 272 | } |
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| 273 | |
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| 274 | if ( ( p_desc->etx.des0_3.des0 & DWMAC_DESC_ETX_DES0_IP_HEADER_ERROR ) |
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| 275 | != 0 ) { |
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| 276 | DWMAC_DESC_ENH_PRINT_DBG( "\tTX IP header csum error\n" ); |
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| 277 | ++counts->ip_header_error; |
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| 278 | } |
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| 279 | |
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| 280 | if ( ( p_desc->etx.des0_3.des0 & DWMAC_DESC_ETX_DES0_IP_PAYLOAD_ERROR ) |
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| 281 | != 0 ) { |
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| 282 | DWMAC_DESC_ENH_PRINT_DBG( "\tAddr/Payload csum error\n" ); |
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| 283 | ++counts->payload_error; |
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| 284 | dwmac_core_dma_flush_tx_fifo( self ); |
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| 285 | } |
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| 286 | |
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| 287 | ret = -1; |
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| 288 | } |
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| 289 | |
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| 290 | if ( ( p_desc->etx.des0_3.des0 & DWMAC_DESC_ETX_DES0_DEFERRED_BIT ) != 0 ) { |
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| 291 | DWMAC_DESC_ENH_PRINT_DBG( "GMAC TX status: tx deferred\n" ); |
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| 292 | ++counts->deferred; |
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| 293 | } |
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| 294 | |
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| 295 | if ( ( p_desc->etx.des0_3.des0 & DWMAC_DESC_ETX_DES0_VLAN_FRAME ) != 0 ) { |
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| 296 | DWMAC_DESC_ENH_PRINT_DBG( "GMAC TX status: VLAN frame\n" ); |
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| 297 | ++counts->vlan; |
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| 298 | } |
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| 299 | |
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| 300 | return ret; |
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| 301 | } |
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| 302 | |
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| 303 | static dwmac_common_rx_frame_status dwmac_desc_enh_get_rx_status( |
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| 304 | dwmac_common_context *self, |
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| 305 | const unsigned int desc_idx ) |
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| 306 | { |
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| 307 | dwmac_common_desc_status_counts_rx *counts = |
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| 308 | &self->stats.desc_status_counts_rx; |
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| 309 | dwmac_common_rx_frame_status ret = |
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| 310 | DWMAC_COMMON_RX_FRAME_STATUS_GOOD; |
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| 311 | volatile dwmac_desc_ext *dma_rx = |
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| 312 | (volatile dwmac_desc_ext *) self->dma_rx; |
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| 313 | const uint32_t DES0 = dma_rx[desc_idx].erx.des0_3.des0; |
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| 314 | |
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| 315 | |
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| 316 | if ( ( DES0 & DWMAC_DESC_ERX_DES0_ERROR_SUMMARY ) != 0 ) { |
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| 317 | DWMAC_DESC_ENH_PRINT_DBG( "GMAC RX Error Summary 0x%08x\n", |
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| 318 | DES0 ); |
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| 319 | |
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| 320 | if ( ( DES0 & DWMAC_DESC_ERX_DES0_DESCRIPTOR_ERROR ) != 0 ) { |
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| 321 | DWMAC_DESC_ENH_PRINT_DBG( "\tdescriptor error\n" ); |
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| 322 | ++counts->descriptor_error; |
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| 323 | } |
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| 324 | |
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| 325 | if ( ( DES0 & DWMAC_DESC_ERX_DES0_OVERFLOW_ERROR ) != 0 ) { |
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| 326 | DWMAC_DESC_ENH_PRINT_DBG( "\toverflow error\n" ); |
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| 327 | ++counts->overflow_error; |
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| 328 | } |
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| 329 | |
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| 330 | if ( dwmac_desc_enh_is_giant_frame( DES0 ) ) { |
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| 331 | DWMAC_DESC_ENH_PRINT_DBG( "\tIPC Csum Error/Giant frame\n" ); |
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| 332 | ++counts->giant_frame; |
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| 333 | } |
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| 334 | |
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| 335 | if ( ( DES0 & DWMAC_DESC_ERX_DES0_LATE_COLLISION ) != 0 ) { |
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| 336 | DWMAC_DESC_ENH_PRINT_DBG( "\tlate_collision error\n" ); |
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| 337 | ++counts->late_collision; |
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| 338 | } |
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| 339 | |
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| 340 | if ( ( DES0 & DWMAC_DESC_ERX_DES0_RECEIVE_WATCHDOG_TIMEOUT ) |
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| 341 | != 0 ) { |
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| 342 | DWMAC_DESC_ENH_PRINT_DBG( "\treceive_watchdog error\n" ); |
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| 343 | ++counts->watchdog_timeout; |
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| 344 | } |
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| 345 | |
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| 346 | if ( ( DES0 & DWMAC_DESC_ERX_DES0_RECEIVE_ERROR ) != 0 ) { |
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| 347 | DWMAC_DESC_ENH_PRINT_DBG( "\tReceive Error\n" ); |
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| 348 | ++counts->receive_error; |
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| 349 | } |
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| 350 | |
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| 351 | if ( ( DES0 & DWMAC_DESC_ERX_DES0_CRC_ERROR ) != 0 ) { |
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| 352 | DWMAC_DESC_ENH_PRINT_DBG( "\tCRC error\n" ); |
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| 353 | ++counts->crc_error; |
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| 354 | } |
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| 355 | |
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| 356 | ret = DWMAC_COMMON_RX_FRAME_STATUS_DISCARD; |
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| 357 | } |
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| 358 | |
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| 359 | if ( ret == DWMAC_COMMON_RX_FRAME_STATUS_GOOD ) { |
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| 360 | /* After a payload csum error, the ES bit is set. |
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| 361 | * It doesn't match with the information reported into the databook. |
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| 362 | * At any rate, we need to understand if the CSUM hw computation is ok |
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| 363 | * and report this info to the upper layers. */ |
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| 364 | ret = dwmac_desc_enh_coe_status( &dma_rx[desc_idx] ); |
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| 365 | } |
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| 366 | |
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| 367 | if ( ( DES0 & DWMAC_DESC_ERX_DES0_DRIBBLE_BIT_ERROR ) != 0 ) { |
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| 368 | DWMAC_DESC_ENH_PRINT_DBG( "GMAC RX: dribbling error\n" ); |
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| 369 | ++counts->dribble_bit_error; |
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| 370 | } |
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| 371 | |
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| 372 | if ( ( DES0 & DWMAC_DESC_ERX_DES0_SRC_ADDR_FILTER_FAIL ) != 0 ) { |
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| 373 | DWMAC_DESC_ENH_PRINT_DBG( "GMAC RX : Source Address filter fail\n" ); |
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| 374 | ++counts->source_addr_fail; |
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| 375 | ret = DWMAC_COMMON_RX_FRAME_STATUS_DISCARD; |
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| 376 | } |
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| 377 | |
---|
| 378 | if ( ( DES0 & DWMAC_DESC_ERX_DES0_DEST_ADDR_FILTER_FAIL ) != 0 ) { |
---|
| 379 | DWMAC_DESC_ENH_PRINT_DBG( "GMAC RX : Dest Address filter fail\n" ); |
---|
| 380 | ++counts->dest_addr_fail; |
---|
| 381 | ret = DWMAC_COMMON_RX_FRAME_STATUS_DISCARD; |
---|
| 382 | } |
---|
| 383 | |
---|
| 384 | if ( ( DES0 & DWMAC_DESC_ERX_DES0_LENGTH_ERROR ) != 0 ) { |
---|
| 385 | DWMAC_DESC_ENH_PRINT_DBG( "GMAC RX: length_error error\n" ); |
---|
| 386 | ++counts->length_error; |
---|
| 387 | ret = DWMAC_COMMON_RX_FRAME_STATUS_DISCARD; |
---|
| 388 | } |
---|
| 389 | |
---|
| 390 | if ( ( DES0 & DWMAC_DESC_ERX_DES0_VLAN_TAG ) != 0 ) { |
---|
| 391 | DWMAC_DESC_ENH_PRINT_DBG( "GMAC RX: VLAN frame tagged\n" ); |
---|
| 392 | ++counts->vlan_tag; |
---|
| 393 | } |
---|
| 394 | |
---|
| 395 | return ret; |
---|
| 396 | } |
---|
| 397 | |
---|
| 398 | static void dwmac_desc_enh_print_tx_desc( |
---|
| 399 | volatile dwmac_desc *p, |
---|
| 400 | const unsigned int count ) |
---|
| 401 | { |
---|
| 402 | volatile dwmac_desc_ext *p_enh = (volatile dwmac_desc_ext *) p; |
---|
| 403 | unsigned int index; |
---|
| 404 | |
---|
| 405 | |
---|
| 406 | if ( p_enh != NULL ) { |
---|
| 407 | for ( index = 0; index < count; ++index ) { |
---|
| 408 | printf( "Transmit DMA Descriptor %d\n", index ); |
---|
| 409 | printf( "des0\n" ); |
---|
| 410 | printf( |
---|
| 411 | " %u own bit\n" |
---|
| 412 | " %u IRQ on Completion\n" |
---|
| 413 | " %u Last Segment\n" |
---|
| 414 | " %u First Segment\n" |
---|
| 415 | " %u Disable CRC\n" |
---|
| 416 | " %u Disable Pad\n" |
---|
| 417 | " %u Transmit Timestamp Enable\n" |
---|
| 418 | " %lu Checksum Insertion Control\n" |
---|
| 419 | " %u Transmit End of Ring\n" |
---|
| 420 | " %u Second Address Chained\n" |
---|
| 421 | " %u Transmit Timestamp Status\n" |
---|
| 422 | " %u IP Header Error\n" |
---|
| 423 | " %u VLAN Frame\n" |
---|
| 424 | " %lu Collision Count\n" |
---|
| 425 | " %u Deferred Bit\n", |
---|
| 426 | ( p_enh[index].etx.des0_3.des0 & DWMAC_DESC_ETX_DES0_OWN_BIT ) != 0, |
---|
| 427 | ( p_enh[index].etx.des0_3.des0 & DWMAC_DESC_ETX_DES0_IRQ_ON_COMPLETION ) != 0, |
---|
| 428 | ( p_enh[index].etx.des0_3.des0 & DWMAC_DESC_ETX_DES0_LAST_SEGMENT ) != 0, |
---|
| 429 | ( p_enh[index].etx.des0_3.des0 & DWMAC_DESC_ETX_DES0_FIRST_SEGMENT ) != 0, |
---|
| 430 | ( p_enh[index].etx.des0_3.des0 & DWMAC_DESC_ETX_DES0_DISABLE_CRC ) != 0, |
---|
| 431 | ( p_enh[index].etx.des0_3.des0 & DWMAC_DESC_ETX_DES0_DISABLE_PAD ) != 0, |
---|
| 432 | ( p_enh[index].etx.des0_3.des0 |
---|
| 433 | & DWMAC_DESC_ETX_DES0_TRANSMIT_TIMESTAMP_ENABLE ) != 0, |
---|
| 434 | DWMAC_DESC_ETX_DES0_CHECKSUM_INSERTION_CONTROL_GET( p_enh[index].etx. |
---|
| 435 | des0_3.des0 ), |
---|
| 436 | ( p_enh[index].etx.des0_3.des0 |
---|
| 437 | & DWMAC_DESC_ETX_DES0_TRANSMIT_END_OF_RING ) != 0, |
---|
| 438 | ( p_enh[index].etx.des0_3.des0 & DWMAC_DESC_ETX_DES0_SECOND_ADDR_CHAINED ) != 0, |
---|
| 439 | ( p_enh[index].etx.des0_3.des0 |
---|
| 440 | & DWMAC_DESC_ETX_DES0_TRANSMIT_TIMESTAMP_STATUS ) != 0, |
---|
| 441 | ( p_enh[index].etx.des0_3.des0 & DWMAC_DESC_ETX_DES0_IP_HEADER_ERROR ) != 0, |
---|
| 442 | ( p_enh[index].etx.des0_3.des0 & DWMAC_DESC_ETX_DES0_VLAN_FRAME ) != 0, |
---|
| 443 | DWMAC_DESC_ETX_DES0_COLLISION_COUNT_GET( p_enh[index].etx.des0_3.des0 ), |
---|
| 444 | ( p_enh[index].etx.des0_3.des0 & DWMAC_DESC_ETX_DES0_DEFERRED_BIT ) != 0 |
---|
| 445 | ); |
---|
| 446 | |
---|
| 447 | if ( ( p_enh[index].etx.des0_3.des0 |
---|
| 448 | & DWMAC_DESC_ETX_DES0_ERROR_SUMMARY ) != 0 ) { |
---|
| 449 | printf( " Error Summary:\n" ); |
---|
| 450 | |
---|
| 451 | if ( p_enh[index].etx.des0_3.des0 |
---|
| 452 | & DWMAC_DESC_ETX_DES0_JABBER_TIMEOUT ) { |
---|
| 453 | printf( " Jabber Timeout\n" ); |
---|
| 454 | } |
---|
| 455 | |
---|
| 456 | if ( ( p_enh[index].etx.des0_3.des0 |
---|
| 457 | & DWMAC_DESC_ETX_DES0_FRAME_FLUSHED ) != 0 ) { |
---|
| 458 | printf( " Frame Flush\n" ); |
---|
| 459 | } |
---|
| 460 | |
---|
| 461 | if ( ( p_enh[index].etx.des0_3.des0 |
---|
| 462 | & DWMAC_DESC_ETX_DES0_IP_PAYLOAD_ERROR ) != 0 ) { |
---|
| 463 | printf( " Payload Error\n" ); |
---|
| 464 | } |
---|
| 465 | |
---|
| 466 | if ( ( p_enh[index].etx.des0_3.des0 |
---|
| 467 | & DWMAC_DESC_ETX_DES0_LOSS_OF_CARRIER ) != 0 ) { |
---|
| 468 | printf( " Loss of Carrier\n" ); |
---|
| 469 | } |
---|
| 470 | |
---|
| 471 | if ( ( p_enh[index].etx.des0_3.des0 |
---|
| 472 | & DWMAC_DESC_ETX_DES0_NO_CARRIER ) != 0 ) { |
---|
| 473 | printf( " No Carrier\n" ); |
---|
| 474 | } |
---|
| 475 | |
---|
| 476 | if ( ( p_enh[index].etx.des0_3.des0 |
---|
| 477 | & DWMAC_DESC_ETX_DES0_EXCESSIVE_COLLISION ) != 0 ) { |
---|
| 478 | printf( " Excessive Collision\n" ); |
---|
| 479 | } |
---|
| 480 | |
---|
| 481 | if ( ( p_enh[index].etx.des0_3.des0 |
---|
| 482 | & DWMAC_DESC_ETX_DES0_EXCESSIVE_COLLISION ) != 0 ) { |
---|
| 483 | printf( " Ecessive Deferral\n" ); |
---|
| 484 | } |
---|
| 485 | |
---|
| 486 | if ( ( p_enh[index].etx.des0_3.des0 |
---|
| 487 | & DWMAC_DESC_ETX_DES0_UNDERFLOW_ERROR ) != 0 ) { |
---|
| 488 | printf( " Undeflow Error\n" ); |
---|
| 489 | } |
---|
| 490 | } |
---|
| 491 | |
---|
| 492 | printf( "des1\n" ); |
---|
| 493 | printf( |
---|
| 494 | " %lu Transmit Buffer 2 Size\n" |
---|
| 495 | " %lu Transmit Buffer 1 Size\n", |
---|
| 496 | DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_2_SIZE_GET( p_enh[index].etx.des0_3. |
---|
| 497 | des1 ), |
---|
| 498 | DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_1_SIZE_GET( p_enh[index].etx.des0_3. |
---|
| 499 | des1 ) |
---|
| 500 | ); |
---|
| 501 | printf( "des2\n" ); |
---|
| 502 | printf( " %p Buffer 1 Address\n", (void *) p_enh[index].etx.des0_3.des2 ); |
---|
| 503 | printf( "des3\n" ); |
---|
| 504 | printf( " %p Buffer 2 Address\n", (void *) p_enh[index].etx.des0_3.des3 ); |
---|
| 505 | } |
---|
| 506 | } |
---|
| 507 | } |
---|
| 508 | |
---|
| 509 | static void dwmac_desc_enh_print_rx_desc( |
---|
| 510 | volatile dwmac_desc *p, |
---|
| 511 | const unsigned int count ) |
---|
| 512 | { |
---|
| 513 | volatile dwmac_desc_ext *p_enh = (volatile dwmac_desc_ext *) p; |
---|
| 514 | unsigned int index; |
---|
| 515 | |
---|
| 516 | |
---|
| 517 | if ( p_enh != NULL ) { |
---|
| 518 | for ( index = 0; index < count; ++index ) { |
---|
| 519 | printf( "Receive DMA Descriptor %d\n", index ); |
---|
| 520 | printf( "des0\n" ); |
---|
| 521 | printf( |
---|
| 522 | " %u Own Bit\n" |
---|
| 523 | " %u Dest. Addr. Filter Fail\n" |
---|
| 524 | " %lu Frame Length\n" |
---|
| 525 | " %u Source Addr. Filter Fail\n" |
---|
| 526 | " %u Length Error\n" |
---|
| 527 | " %u VLAN Tag\n" |
---|
| 528 | " %u First Descriptor\n" |
---|
| 529 | " %u Last Descriptor\n" |
---|
| 530 | " %u Frame Type\n" |
---|
| 531 | " %u Dribble Bit Error\n" |
---|
| 532 | " %u Extended Status Available\n", |
---|
| 533 | ( p_enh[index].erx.des0_3.des0 & DWMAC_DESC_ERX_DES0_OWN_BIT ) != 0, |
---|
| 534 | ( p_enh[index].erx.des0_3.des0 |
---|
| 535 | & DWMAC_DESC_ERX_DES0_DEST_ADDR_FILTER_FAIL ) != 0, |
---|
| 536 | DWMAC_DESC_ERX_DES0_FRAME_LENGTH_GET( |
---|
| 537 | p_enh[index].erx.des0_3.des0 ), |
---|
| 538 | ( p_enh[index].erx.des0_3.des0 |
---|
| 539 | & DWMAC_DESC_ERX_DES0_SRC_ADDR_FILTER_FAIL ) != 0, |
---|
| 540 | ( p_enh[index].erx.des0_3.des0 & DWMAC_DESC_ERX_DES0_LENGTH_ERROR ) != 0, |
---|
| 541 | ( p_enh[index].erx.des0_3.des0 & DWMAC_DESC_ERX_DES0_VLAN_TAG ) != 0, |
---|
| 542 | ( p_enh[index].erx.des0_3.des0 & DWMAC_DESC_ERX_DES0_FIRST_DESCRIPTOR ) != 0, |
---|
| 543 | ( p_enh[index].erx.des0_3.des0 & DWMAC_DESC_ERX_DES0_LAST_DESCRIPTOR ) != 0, |
---|
| 544 | ( p_enh[index].erx.des0_3.des0 & DWMAC_DESC_ERX_DES0_FREAME_TYPE ) != 0, |
---|
| 545 | ( p_enh[index].erx.des0_3.des0 & DWMAC_DESC_ERX_DES0_DRIBBLE_BIT_ERROR ) != 0, |
---|
| 546 | ( p_enh[index].erx.des0_3.des0 |
---|
| 547 | & DWMAC_DESC_ERX_DES0_EXT_STATUS_AVAIL_OR_RX_MAC_ADDR_STATUS ) != 0 |
---|
| 548 | ); |
---|
| 549 | |
---|
| 550 | if ( ( p_enh[index].erx.des0_3.des0 |
---|
| 551 | & DWMAC_DESC_ERX_DES0_ERROR_SUMMARY ) != 0 ) { |
---|
| 552 | printf( " Error Summary:\n" ); |
---|
| 553 | |
---|
| 554 | if ( ( p_enh[index].erx.des0_3.des0 |
---|
| 555 | & DWMAC_DESC_ERX_DES0_DESCRIPTOR_ERROR ) != 0 ) { |
---|
| 556 | printf( " Descriptor Error\n" ); |
---|
| 557 | } |
---|
| 558 | |
---|
| 559 | if ( ( p_enh[index].erx.des0_3.des0 |
---|
| 560 | & DWMAC_DESC_ERX_DES0_OVERFLOW_ERROR ) != 0 ) { |
---|
| 561 | printf( " Overflow Error\n" ); |
---|
| 562 | } |
---|
| 563 | |
---|
| 564 | if ( ( p_enh[index].erx.des0_3.des0 |
---|
| 565 | & |
---|
| 566 | DWMAC_DESC_ERX_DES0_TIMESTAMP_AVAIL_OR_CHECKSUM_ERROR_OR_GIANT_FRAME ) |
---|
| 567 | != 0 ) { |
---|
| 568 | printf( " Giant Frame\n" ); |
---|
| 569 | } |
---|
| 570 | |
---|
| 571 | if ( ( p_enh[index].erx.des0_3.des0 |
---|
| 572 | & DWMAC_DESC_ERX_DES0_LATE_COLLISION ) != 0 ) { |
---|
| 573 | printf( " Late Collision\n" ); |
---|
| 574 | } |
---|
| 575 | |
---|
| 576 | if ( ( p_enh[index].erx.des0_3.des0 |
---|
| 577 | & DWMAC_DESC_ERX_DES0_RECEIVE_WATCHDOG_TIMEOUT ) != 0 |
---|
| 578 | || ( p_enh[index].erx.des0_3.des0 |
---|
| 579 | & DWMAC_DESC_ERX_DES0_RECEIVE_ERROR ) != 0 ) { |
---|
| 580 | printf( " IP Header or IP Payload:\n" ); |
---|
| 581 | |
---|
| 582 | if ( ( p_enh[index].erx.des0_3.des0 |
---|
| 583 | & DWMAC_DESC_ERX_DES0_RECEIVE_WATCHDOG_TIMEOUT ) != 0 ) { |
---|
| 584 | printf( " Watchdog Timeout\n" ); |
---|
| 585 | } |
---|
| 586 | |
---|
| 587 | if ( ( p_enh[index].erx.des0_3.des0 |
---|
| 588 | & DWMAC_DESC_ERX_DES0_RECEIVE_ERROR ) != 0 ) { |
---|
| 589 | printf( " Receive Error\n" ); |
---|
| 590 | } |
---|
| 591 | } |
---|
| 592 | |
---|
| 593 | if ( ( p_enh[index].erx.des0_3.des0 & DWMAC_DESC_ERX_DES0_CRC_ERROR ) |
---|
| 594 | != 0 ) { |
---|
| 595 | printf( " CRC Error\n" ); |
---|
| 596 | } |
---|
| 597 | } |
---|
| 598 | |
---|
| 599 | printf( "des1\n" ); |
---|
| 600 | printf( |
---|
| 601 | " %u Disable Interrupt on Completion\n" |
---|
| 602 | " %lu Receive Buffer 2 Size\n" |
---|
| 603 | " %u Receive End of Ring\n" |
---|
| 604 | " %u Second Addr. Chained\n" |
---|
| 605 | " %lu Receive Buffer 1 Size\n", |
---|
| 606 | ( p_enh[index].erx.des0_3.des1 |
---|
| 607 | & DWMAC_DESC_ERX_DES1_DISABLE_IRQ_ON_COMPLETION ) != 0, |
---|
| 608 | DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_2_SIZE_GET( p_enh[index].erx.des0_3. |
---|
| 609 | des1 ), |
---|
| 610 | ( p_enh[index].erx.des0_3.des1 & DWMAC_DESC_ERX_DES1_RECEIVE_END_OF_RING ) != 0, |
---|
| 611 | ( p_enh[index].erx.des0_3.des1 & DWMAC_DESC_ERX_DES1_SECOND_ADDR_CHAINED ) != 0, |
---|
| 612 | DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_1_SIZE_GET( p_enh[index].erx.des0_3. |
---|
| 613 | des1 ) |
---|
| 614 | ); |
---|
| 615 | printf( "des2\n" ); |
---|
| 616 | printf( " %p Buffer 1 Address\n", (void *) p_enh[index].erx.des0_3.des2 ); |
---|
| 617 | printf( "des3\n" ); |
---|
| 618 | printf( " %p Buffer 2 Address\n", (void *) p_enh[index].erx.des0_3.des3 ); |
---|
| 619 | } |
---|
| 620 | } |
---|
| 621 | } |
---|
| 622 | |
---|
| 623 | static int dwmac_desc_enh_create_rx_desc( dwmac_common_context *self ) |
---|
| 624 | { |
---|
| 625 | int eno = 0; |
---|
| 626 | const size_t NUM_DESCS = (size_t) self->bsd_config->rbuf_count; |
---|
| 627 | const size_t SIZE_DESCS = NUM_DESCS * sizeof( dwmac_desc_ext ); |
---|
| 628 | void *desc_mem = NULL; |
---|
| 629 | |
---|
| 630 | |
---|
| 631 | assert( NULL == self->dma_rx ); |
---|
| 632 | |
---|
| 633 | /* Allocate an array of mbuf pointers */ |
---|
| 634 | self->mbuf_addr_rx = calloc( NUM_DESCS, sizeof( struct mbuf * ) ); |
---|
| 635 | |
---|
| 636 | if ( self->mbuf_addr_rx == NULL ) { |
---|
| 637 | eno = ENOMEM; |
---|
| 638 | } |
---|
| 639 | |
---|
| 640 | /* Allocate an array of dma descriptors */ |
---|
| 641 | if ( eno == 0 ) { |
---|
| 642 | eno = ( self->CFG->CALLBACK.mem_alloc_nocache )( |
---|
| 643 | self->arg, |
---|
| 644 | &desc_mem, |
---|
| 645 | SIZE_DESCS |
---|
| 646 | ); |
---|
| 647 | } |
---|
| 648 | |
---|
| 649 | if ( eno == 0 ) { |
---|
| 650 | if ( desc_mem != NULL ) { |
---|
| 651 | memset( desc_mem, 0, SIZE_DESCS ); |
---|
| 652 | DWMAC_COMMON_DSB(); |
---|
| 653 | } else { |
---|
| 654 | eno = ENOMEM; |
---|
| 655 | } |
---|
| 656 | } |
---|
| 657 | |
---|
| 658 | if ( eno == 0 ) { |
---|
| 659 | self->dma_rx = (volatile dwmac_desc *) desc_mem; |
---|
| 660 | DWMAC_COMMON_DSB(); |
---|
| 661 | } |
---|
| 662 | |
---|
| 663 | return eno; |
---|
| 664 | } |
---|
| 665 | |
---|
| 666 | static void dwmac_desc_enh_init_rx_desc( |
---|
| 667 | dwmac_common_context *self, |
---|
| 668 | const unsigned int index ) |
---|
| 669 | { |
---|
| 670 | volatile dwmac_desc_ext *p_enh = |
---|
| 671 | (volatile dwmac_desc_ext *) self->dma_rx; |
---|
| 672 | const size_t NUM_DESCS = (size_t) self->bsd_config->rbuf_count; |
---|
| 673 | char *clust_start = |
---|
| 674 | mtod( self->mbuf_addr_rx[index], char * ); |
---|
| 675 | |
---|
| 676 | |
---|
| 677 | assert( NULL != p_enh ); |
---|
| 678 | |
---|
| 679 | DWMAC_COMMON_DSB(); |
---|
| 680 | |
---|
| 681 | rtems_cache_invalidate_multiple_data_lines( |
---|
| 682 | clust_start, |
---|
| 683 | DWMAC_DESC_COM_BUF_SIZE + ETHER_ALIGN |
---|
| 684 | ); |
---|
| 685 | |
---|
| 686 | if ( self->mbuf_addr_rx[index] != NULL ) { |
---|
| 687 | p_enh[index].erx.des0_3.des1 = DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_1_SIZE_SET( |
---|
| 688 | p_enh->erx.des0_3.des1, |
---|
| 689 | DWMAC_DESC_COM_BUF_SIZE ); |
---|
| 690 | } else { |
---|
| 691 | p_enh[index].erx.des0_3.des1 = DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_1_SIZE_SET( |
---|
| 692 | p_enh->erx.des0_3.des1, |
---|
| 693 | 0 ); |
---|
| 694 | } |
---|
| 695 | |
---|
| 696 | p_enh[index].erx.des0_3.des2 = (uint32_t) clust_start; |
---|
| 697 | |
---|
| 698 | /* The network controller supports adding a second data buffer to |
---|
| 699 | * p_enh->erx.des0_3.des3. For simplicity reasons we will not do this */ |
---|
| 700 | dwmac_desc_enh_rx_set_on_ring_chain( &p_enh[index], |
---|
| 701 | ( index == NUM_DESCS - 1 ) ); |
---|
| 702 | DWMAC_COMMON_DSB(); |
---|
| 703 | p_enh[index].erx.des0_3.des0 = DWMAC_DESC_ERX_DES0_OWN_BIT; |
---|
| 704 | } |
---|
| 705 | |
---|
| 706 | static int dwmac_desc_enh_destroy_rx_desc( dwmac_common_context *self ) |
---|
| 707 | { |
---|
[8118b670] | 708 | int eno = 0; |
---|
| 709 | volatile dwmac_desc *dma_rx = self->dma_rx; |
---|
[4953b724] | 710 | |
---|
| 711 | |
---|
| 712 | if ( self->mbuf_addr_rx != NULL ) { |
---|
| 713 | free( self->mbuf_addr_rx, 0 ); |
---|
| 714 | self->mbuf_addr_rx = NULL; |
---|
| 715 | } |
---|
| 716 | |
---|
[8118b670] | 717 | if ( dma_rx != NULL ) { |
---|
| 718 | eno = self->CFG->CALLBACK.mem_free_nocache( self->arg, dma_rx ); |
---|
| 719 | self->dma_rx = NULL; |
---|
[4953b724] | 720 | } |
---|
| 721 | |
---|
| 722 | DWMAC_COMMON_DSB(); |
---|
| 723 | |
---|
| 724 | return eno; |
---|
| 725 | } |
---|
| 726 | |
---|
| 727 | static void dwmac_desc_enh_release_rx_bufs( dwmac_common_context *self ) |
---|
| 728 | { |
---|
| 729 | volatile dwmac_desc_ext *p_enh = (volatile dwmac_desc_ext *) self->dma_rx; |
---|
| 730 | const size_t NUM_DESCS = (size_t) self->bsd_config->rbuf_count; |
---|
| 731 | unsigned int i; |
---|
| 732 | |
---|
| 733 | |
---|
| 734 | assert( p_enh != NULL ); |
---|
| 735 | |
---|
| 736 | for ( i = 0; i < NUM_DESCS; ++i ) { |
---|
| 737 | if ( p_enh[i].erx.des0_3.des2 != 0 ) { |
---|
| 738 | struct mbuf *dummy; |
---|
| 739 | |
---|
| 740 | assert( self->mbuf_addr_rx[i] != NULL ); |
---|
| 741 | |
---|
| 742 | MFREE( self->mbuf_addr_rx[i], dummy ); |
---|
| 743 | (void) dummy; |
---|
[8118b670] | 744 | memset(&p_enh[i].erx, 0, sizeof( dwmac_desc_ext ) ); |
---|
[4953b724] | 745 | } |
---|
| 746 | } |
---|
| 747 | |
---|
| 748 | self->dma_rx = (volatile dwmac_desc *) p_enh; |
---|
| 749 | DWMAC_COMMON_DSB(); |
---|
| 750 | } |
---|
| 751 | |
---|
| 752 | static int dwmac_desc_enh_create_tx_desc( dwmac_common_context *self ) |
---|
| 753 | { |
---|
| 754 | int eno = 0; |
---|
[8118b670] | 755 | void *mem_desc = NULL; |
---|
[4953b724] | 756 | const size_t NUM_DESCS = (size_t) self->bsd_config->xbuf_count; |
---|
| 757 | const size_t SIZE_DESCS = NUM_DESCS * sizeof( dwmac_desc_ext ); |
---|
| 758 | |
---|
| 759 | |
---|
[8118b670] | 760 | assert( self->dma_tx == NULL ); |
---|
[4953b724] | 761 | |
---|
| 762 | /* Allocate an array of mbuf pointers */ |
---|
| 763 | self->mbuf_addr_tx = calloc( NUM_DESCS, sizeof( struct mbuf * ) ); |
---|
| 764 | |
---|
| 765 | if ( self->mbuf_addr_tx == NULL ) { |
---|
| 766 | eno = ENOMEM; |
---|
| 767 | } |
---|
| 768 | |
---|
| 769 | if ( eno == 0 ) { |
---|
| 770 | eno = ( self->CFG->CALLBACK.mem_alloc_nocache )( |
---|
| 771 | self->arg, |
---|
| 772 | &mem_desc, |
---|
| 773 | SIZE_DESCS |
---|
| 774 | ); |
---|
| 775 | } |
---|
| 776 | |
---|
| 777 | if ( eno == 0 ) { |
---|
| 778 | if ( mem_desc != NULL ) { |
---|
| 779 | memset( mem_desc, 0, SIZE_DESCS ); |
---|
| 780 | DWMAC_COMMON_DSB(); |
---|
| 781 | } else { |
---|
| 782 | eno = ENOMEM; |
---|
| 783 | } |
---|
| 784 | } |
---|
| 785 | |
---|
| 786 | if ( eno == 0 ) { |
---|
[8118b670] | 787 | self->dma_tx = mem_desc; |
---|
[4953b724] | 788 | DWMAC_COMMON_DSB(); |
---|
| 789 | } |
---|
| 790 | |
---|
| 791 | return eno; |
---|
| 792 | } |
---|
| 793 | |
---|
| 794 | static void dwmac_desc_enh_init_tx_desc( dwmac_common_context *self ) |
---|
| 795 | { |
---|
| 796 | volatile dwmac_desc_ext *p_enh = (volatile dwmac_desc_ext *) self->dma_tx; |
---|
| 797 | const size_t NUM_DESCS = (size_t) self->bsd_config->xbuf_count; |
---|
| 798 | unsigned int i; |
---|
| 799 | |
---|
| 800 | |
---|
| 801 | assert( p_enh != NULL ); |
---|
| 802 | |
---|
| 803 | for ( i = 0; i < NUM_DESCS; ++i ) { |
---|
| 804 | dwmac_desc_enh_tx_set_on_ring_chain( &p_enh[i], ( i == NUM_DESCS - 1 ) ); |
---|
| 805 | } |
---|
| 806 | |
---|
| 807 | self->dma_tx = (volatile dwmac_desc *) &p_enh[0]; |
---|
| 808 | DWMAC_COMMON_DSB(); |
---|
| 809 | } |
---|
| 810 | |
---|
| 811 | static int dwmac_desc_enh_destroy_tx_desc( dwmac_common_context *self ) |
---|
| 812 | { |
---|
| 813 | int eno = 0; |
---|
| 814 | void *mem_desc = __DEVOLATILE( void *, self->dma_tx ); |
---|
| 815 | |
---|
| 816 | |
---|
| 817 | if ( self->mbuf_addr_tx != NULL ) { |
---|
| 818 | free( self->mbuf_addr_tx, 0 ); |
---|
| 819 | self->mbuf_addr_tx = NULL; |
---|
| 820 | } |
---|
| 821 | |
---|
| 822 | if ( mem_desc != NULL ) { |
---|
| 823 | eno = self->CFG->CALLBACK.mem_free_nocache( self->arg, mem_desc ); |
---|
| 824 | mem_desc = NULL; |
---|
| 825 | self->dma_tx = (volatile dwmac_desc *) mem_desc; |
---|
| 826 | } |
---|
| 827 | |
---|
| 828 | DWMAC_COMMON_DSB(); |
---|
| 829 | |
---|
| 830 | return eno; |
---|
| 831 | } |
---|
| 832 | |
---|
| 833 | static void dwmac_desc_enh_release_tx_bufs( dwmac_common_context *self ) |
---|
| 834 | { |
---|
| 835 | volatile dwmac_desc_ext *p_enh = (volatile dwmac_desc_ext *) self->dma_tx; |
---|
| 836 | const size_t NUM_DESCS = (size_t) self->bsd_config->xbuf_count; |
---|
| 837 | unsigned int i; |
---|
| 838 | |
---|
| 839 | |
---|
| 840 | assert( p_enh != NULL ); |
---|
| 841 | |
---|
| 842 | for ( i = 0; i < NUM_DESCS; ++i ) { |
---|
| 843 | if ( p_enh[i].etx.des0_3.des1 != 0 ) { |
---|
| 844 | struct mbuf *dummy; |
---|
| 845 | |
---|
| 846 | assert( self->mbuf_addr_tx[i] != NULL ); |
---|
| 847 | |
---|
| 848 | MFREE( self->mbuf_addr_tx[i], dummy ); |
---|
| 849 | (void) dummy; |
---|
| 850 | memset( __DEVOLATILE( void *, |
---|
| 851 | &p_enh[i].etx ), 0, sizeof( dwmac_desc_ext ) ); |
---|
| 852 | } |
---|
| 853 | } |
---|
| 854 | |
---|
| 855 | self->dma_tx = (volatile dwmac_desc *) p_enh; |
---|
| 856 | DWMAC_COMMON_DSB(); |
---|
| 857 | } |
---|
| 858 | |
---|
| 859 | static inline size_t dwmac_desc_enh_get_rx_frame_len( |
---|
| 860 | dwmac_common_context *self, |
---|
| 861 | const unsigned int desc_idx ) |
---|
| 862 | { |
---|
| 863 | volatile dwmac_desc_ext *p_enh = (volatile dwmac_desc_ext *) self->dma_rx; |
---|
| 864 | |
---|
| 865 | |
---|
| 866 | /* The type-1 checksum offload engines append the checksum at |
---|
| 867 | * the end of frame and the two bytes of checksum are added in |
---|
| 868 | * the length. |
---|
| 869 | * Adjust for that in the framelen for type-1 checksum offload |
---|
| 870 | * engines. */ |
---|
| 871 | if ( self->dmagrp->hw_feature & DMAGRP_HW_FEATURE_RXTYP1COE ) { |
---|
| 872 | return DWMAC_DESC_ERX_DES0_FRAME_LENGTH_GET( p_enh[desc_idx].erx.des0_3.des0 ) |
---|
| 873 | - 2U; |
---|
| 874 | } else { |
---|
| 875 | return DWMAC_DESC_ERX_DES0_FRAME_LENGTH_GET( p_enh[desc_idx].erx.des0_3.des0 ); |
---|
| 876 | } |
---|
| 877 | } |
---|
| 878 | |
---|
| 879 | static bool dwmac_desc_enh_am_i_rx_owner( |
---|
| 880 | dwmac_common_context *self, |
---|
| 881 | const unsigned int desc_idx ) |
---|
| 882 | { |
---|
| 883 | volatile dwmac_desc_ext *p_enh = (volatile dwmac_desc_ext *) self->dma_rx; |
---|
| 884 | bool am_i_owner; |
---|
| 885 | |
---|
| 886 | |
---|
| 887 | DWMAC_COMMON_DSB(); |
---|
| 888 | am_i_owner = |
---|
| 889 | ( p_enh[desc_idx].erx.des0_3.des0 & DWMAC_DESC_ERX_DES0_OWN_BIT ) == 0; |
---|
| 890 | |
---|
| 891 | return am_i_owner; |
---|
| 892 | } |
---|
| 893 | |
---|
| 894 | static bool dwmac_desc_enh_am_i_tx_owner( |
---|
| 895 | dwmac_common_context *self, |
---|
| 896 | const unsigned int idx_tx ) |
---|
| 897 | { |
---|
| 898 | volatile dwmac_desc_ext *p_enh = (volatile dwmac_desc_ext *) self->dma_tx; |
---|
| 899 | bool am_i_owner; |
---|
| 900 | |
---|
| 901 | |
---|
| 902 | DWMAC_COMMON_DSB(); |
---|
| 903 | am_i_owner = |
---|
| 904 | ( p_enh[idx_tx].etx.des0_3.des0 & DWMAC_DESC_ETX_DES0_OWN_BIT ) == 0; |
---|
| 905 | |
---|
| 906 | return am_i_owner; |
---|
| 907 | } |
---|
| 908 | |
---|
| 909 | static void dwmac_desc_enh_release_tx_ownership( |
---|
| 910 | dwmac_common_context *self, |
---|
| 911 | const unsigned int idx_tx ) |
---|
| 912 | { |
---|
| 913 | volatile dwmac_desc_ext *p_enh = (volatile dwmac_desc_ext *) self->dma_tx; |
---|
| 914 | |
---|
| 915 | |
---|
| 916 | DWMAC_COMMON_DSB(); |
---|
| 917 | p_enh[idx_tx].erx.des0_3.des0 |= DWMAC_DESC_ETX_DES0_OWN_BIT; |
---|
| 918 | } |
---|
| 919 | |
---|
| 920 | static int dwmac_desc_enh_get_tx_ls( |
---|
| 921 | dwmac_common_context *self, |
---|
| 922 | const unsigned int idx_tx ) |
---|
| 923 | { |
---|
| 924 | volatile dwmac_desc_ext *p_enh = (volatile dwmac_desc_ext *) self->dma_tx; |
---|
| 925 | |
---|
| 926 | |
---|
| 927 | return ( ( p_enh[idx_tx].etx.des0_3.des0 |
---|
| 928 | & DWMAC_DESC_ETX_DES0_LAST_SEGMENT ) != 0 ); |
---|
| 929 | } |
---|
| 930 | |
---|
| 931 | static void dwmac_desc_enh_release_tx_desc( |
---|
| 932 | dwmac_common_context *self, |
---|
| 933 | const unsigned int idx_tx ) |
---|
| 934 | { |
---|
| 935 | volatile dwmac_desc_ext *p_enh = (volatile dwmac_desc_ext *) self->dma_tx; |
---|
| 936 | |
---|
| 937 | |
---|
| 938 | p_enh[idx_tx].etx.des0_3.des0 = |
---|
| 939 | p_enh[idx_tx].etx.des0_3.des0 |
---|
| 940 | & ( DWMAC_DESC_ETX_DES0_TRANSMIT_END_OF_RING |
---|
| 941 | | DWMAC_DESC_ETX_DES0_SECOND_ADDR_CHAINED ); |
---|
| 942 | |
---|
| 943 | p_enh[idx_tx].etx.des0_3.des1 = 0; |
---|
| 944 | } |
---|
| 945 | |
---|
| 946 | static void dwmac_desc_enh_prepare_tx_desc( |
---|
| 947 | dwmac_common_context *self, |
---|
| 948 | const unsigned int idx, |
---|
| 949 | const bool is_first, |
---|
| 950 | const size_t len, |
---|
| 951 | const void *pdata ) |
---|
| 952 | { |
---|
| 953 | volatile dwmac_desc_ext *p_enh = (volatile dwmac_desc_ext *) self->dma_tx; |
---|
| 954 | |
---|
| 955 | |
---|
| 956 | if ( is_first ) { |
---|
| 957 | p_enh[idx].etx.des0_3.des0 |= DWMAC_DESC_ETX_DES0_FIRST_SEGMENT; |
---|
| 958 | } |
---|
| 959 | |
---|
| 960 | dwmac_desc_enh_set_tx_desc_len( &p_enh[idx], len ); |
---|
| 961 | |
---|
| 962 | p_enh[idx].etx.des0_3.des2 = (uintptr_t) pdata; |
---|
| 963 | } |
---|
| 964 | |
---|
| 965 | static void dwmac_desc_enh_close_tx_desc( |
---|
| 966 | dwmac_common_context *self, |
---|
[f28b8d45] | 967 | const unsigned int idx_tx |
---|
| 968 | ) |
---|
[4953b724] | 969 | { |
---|
| 970 | volatile dwmac_desc_ext *p_enh = (volatile dwmac_desc_ext *) self->dma_tx; |
---|
| 971 | |
---|
| 972 | p_enh[idx_tx].etx.des0_3.des0 |= DWMAC_DESC_ETX_DES0_LAST_SEGMENT; |
---|
| 973 | p_enh[idx_tx].etx.des0_3.des0 |= DWMAC_DESC_ETX_DES0_IRQ_ON_COMPLETION; |
---|
| 974 | } |
---|
| 975 | |
---|
| 976 | static bool dwmac_desc_enh_is_first_rx_segment( |
---|
| 977 | dwmac_common_context *self, |
---|
| 978 | const unsigned int descriptor_index ) |
---|
| 979 | { |
---|
| 980 | volatile dwmac_desc_ext *p_descs = (volatile dwmac_desc_ext *) self->dma_rx; |
---|
| 981 | |
---|
| 982 | |
---|
| 983 | return ( ( p_descs[descriptor_index].erx.des0_3.des0 |
---|
| 984 | & DWMAC_DESC_ERX_DES0_FIRST_DESCRIPTOR ) != 0 ); |
---|
| 985 | } |
---|
| 986 | |
---|
| 987 | static bool dwmac_desc_enh_is_last_rx_segment( |
---|
| 988 | dwmac_common_context *self, |
---|
| 989 | const unsigned int descriptor_index ) |
---|
| 990 | { |
---|
| 991 | volatile dwmac_desc_ext *p_descs = (volatile dwmac_desc_ext *) self->dma_rx; |
---|
| 992 | |
---|
| 993 | |
---|
| 994 | return ( ( p_descs[descriptor_index].erx.des0_3.des0 |
---|
| 995 | & DWMAC_DESC_ERX_DES0_LAST_DESCRIPTOR ) != 0 ); |
---|
| 996 | } |
---|
| 997 | |
---|
| 998 | static int dwmac_desc_enh_validate( dwmac_common_context *self ) |
---|
| 999 | { |
---|
| 1000 | /* Does the hardware support enhanced descriptors? */ |
---|
| 1001 | if ( ( self->dmagrp->hw_feature & DMAGRP_HW_FEATURE_ENHDESSEL ) != 0 ) { |
---|
| 1002 | return 0; |
---|
| 1003 | } else { |
---|
| 1004 | return EINVAL; |
---|
| 1005 | } |
---|
| 1006 | } |
---|
| 1007 | |
---|
| 1008 | static bool dwmac_desc_enh_use_enhanced_descs( dwmac_common_context *self ) |
---|
| 1009 | { |
---|
| 1010 | (void) self; |
---|
| 1011 | |
---|
| 1012 | /* Yes, we use enhanced descriptors */ |
---|
| 1013 | return true; |
---|
| 1014 | } |
---|
| 1015 | |
---|
| 1016 | const dwmac_common_desc_ops dwmac_desc_ops_enhanced = { |
---|
| 1017 | .validate = dwmac_desc_enh_validate, |
---|
| 1018 | .use_enhanced_descs = dwmac_desc_enh_use_enhanced_descs, |
---|
| 1019 | .tx_status = dwmac_desc_enh_get_tx_status, |
---|
| 1020 | .rx_status = dwmac_desc_enh_get_rx_status, |
---|
| 1021 | .create_rx_desc = dwmac_desc_enh_create_rx_desc, |
---|
| 1022 | .create_tx_desc = dwmac_desc_enh_create_tx_desc, |
---|
| 1023 | .destroy_rx_desc = dwmac_desc_enh_destroy_rx_desc, |
---|
| 1024 | .destroy_tx_desc = dwmac_desc_enh_destroy_tx_desc, |
---|
| 1025 | .init_rx_desc = dwmac_desc_enh_init_rx_desc, |
---|
| 1026 | .init_tx_desc = dwmac_desc_enh_init_tx_desc, |
---|
| 1027 | .release_rx_bufs = dwmac_desc_enh_release_rx_bufs, |
---|
| 1028 | .release_tx_bufs = dwmac_desc_enh_release_tx_bufs, |
---|
| 1029 | .alloc_data_buf = dwmac_desc_com_new_mbuf, |
---|
| 1030 | .am_i_tx_owner = dwmac_desc_enh_am_i_tx_owner, |
---|
| 1031 | .am_i_rx_owner = dwmac_desc_enh_am_i_rx_owner, |
---|
| 1032 | .release_tx_desc = dwmac_desc_enh_release_tx_desc, |
---|
| 1033 | .prepare_tx_desc = dwmac_desc_enh_prepare_tx_desc, |
---|
| 1034 | .close_tx_desc = dwmac_desc_enh_close_tx_desc, |
---|
| 1035 | .get_tx_ls = dwmac_desc_enh_get_tx_ls, |
---|
| 1036 | .release_tx_ownership = dwmac_desc_enh_release_tx_ownership, |
---|
| 1037 | .get_rx_frame_len = dwmac_desc_enh_get_rx_frame_len, |
---|
| 1038 | .is_first_rx_segment = dwmac_desc_enh_is_first_rx_segment, |
---|
| 1039 | .is_last_rx_segment = dwmac_desc_enh_is_last_rx_segment, |
---|
| 1040 | .print_tx_desc = dwmac_desc_enh_print_tx_desc, |
---|
| 1041 | .print_rx_desc = dwmac_desc_enh_print_rx_desc, |
---|
| 1042 | }; |
---|
| 1043 | |
---|
| 1044 | /* This wrapped function pointer struct can be passed into the |
---|
| 1045 | * configuration initializer for the driver */ |
---|
| 1046 | const dwmac_descriptor_ops DWMAC_DESCRIPTOR_OPS_ENHANCED = |
---|
| 1047 | DWMAC_DESCRIPTOR_OPS_INITIALIZER( |
---|
| 1048 | &dwmac_desc_ops_enhanced |
---|
| 1049 | ); |
---|