1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief DWMAC 1000 on-chip Ethernet controllers Core Handling |
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5 | * |
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6 | * Functions and data which are specific to the DWMAC 1000 Core Handling. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2013 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Dornierstr. 4 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #include <assert.h> |
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24 | #include "dwmac-core.h" |
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25 | #include "dwmac-common.h" |
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26 | |
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27 | #define DWMAC_1000_CORE_DEBUG |
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28 | |
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29 | //#undef DWMAC_1000_CORE_DEBUG |
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30 | #ifdef DWMAC_1000_CORE_DEBUG |
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31 | #define DWMAC_1000_CORE_PRINT_DBG( fmt, args ... ) printk( fmt, ## args ) |
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32 | #else |
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33 | #define DWMAC_1000_CORE_PRINT_DBG( fmt, args ... ) do { } while ( 0 ) |
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34 | #endif |
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35 | |
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36 | #define DWMAC_1000_CORE_INIT \ |
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37 | ( \ |
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38 | ( MACGRP_MAC_CONFIGURATION_JD \ |
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39 | | MACGRP_MAC_CONFIGURATION_BE ) \ |
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40 | & ~MACGRP_MAC_CONFIGURATION_PS \ |
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41 | ) |
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42 | |
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43 | #define DWMAC_1000_CORE_HASH_TABLE_SIZE 256 |
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44 | |
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45 | static volatile uint32_t *dwmac_1000_core_get_mac_addr_low( |
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46 | dwmac_common_context *self, |
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47 | const unsigned int mac_addr_index ) |
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48 | { |
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49 | volatile uint32_t *addr = NULL; |
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50 | |
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51 | assert( self != NULL ); |
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52 | assert( mac_addr_index <= 127 ); |
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53 | |
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54 | if ( mac_addr_index > 15 ) { |
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55 | addr = &self->macgrp->mac_addr16_127[mac_addr_index].low; |
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56 | } else { |
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57 | addr = &self->macgrp->mac_addr0_15[mac_addr_index].low; |
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58 | } |
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59 | |
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60 | return addr; |
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61 | } |
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62 | |
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63 | static volatile uint32_t *dwmac_1000_core_get_mac_addr_high( |
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64 | dwmac_common_context *self, |
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65 | const unsigned int mac_addr_index ) |
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66 | { |
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67 | volatile uint32_t *addr = NULL; |
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68 | |
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69 | assert( self != NULL ); |
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70 | assert( mac_addr_index <= 127 ); |
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71 | |
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72 | if ( mac_addr_index > 15 ) { |
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73 | addr = &self->macgrp->mac_addr16_127[mac_addr_index].high; |
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74 | } else { |
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75 | addr = &self->macgrp->mac_addr0_15[mac_addr_index].high; |
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76 | } |
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77 | |
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78 | return addr; |
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79 | } |
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80 | |
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81 | static void dwmac_1000_core_init( dwmac_common_context *self ) |
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82 | { |
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83 | uint32_t value = self->macgrp->mac_configuration; |
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84 | |
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85 | value |= DWMAC_1000_CORE_INIT; |
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86 | |
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87 | if ( ( self->dmagrp->hw_feature & DMAGRP_HW_FEATURE_RXTYP1COE ) != 0 |
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88 | || ( self->dmagrp->hw_feature & DMAGRP_HW_FEATURE_RXTYP2COE ) != 0 ) { |
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89 | /* Enable RX checksum calculation offload to hardware */ |
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90 | value |= MACGRP_MAC_CONFIGURATION_IPC; |
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91 | } |
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92 | |
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93 | /* No Jumbo- or Giant frames. The network stack does not support them */ |
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94 | value &= ~MACGRP_MAC_CONFIGURATION_JE; |
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95 | value &= ~MACGRP_MAC_CONFIGURATION_TWOKPE; |
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96 | self->macgrp->mac_configuration = value; |
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97 | |
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98 | /* Mask GMAC interrupts */ |
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99 | self->macgrp->interrupt_mask = |
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100 | MACGRP_INTERRUPT_MASK_RGSMIIIM |
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101 | | MACGRP_INTERRUPT_MASK_PCSLCHGIM |
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102 | | MACGRP_INTERRUPT_MASK_PCSANCIM |
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103 | | MACGRP_INTERRUPT_MASK_TSIM; |
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104 | |
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105 | /* mask out interrupts because we don't handle them yet */ |
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106 | self->macgrp->mmc_receive_interrupt_mask = ( uint32_t ) ~0L; |
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107 | self->macgrp->mmc_transmit_interrupt_mask = ( uint32_t ) ~0L; |
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108 | self->macgrp->mmc_ipc_receive_interrupt_mask = ( uint32_t ) ~0L; |
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109 | } |
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110 | |
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111 | static void dwmac_1000_core_set_umac_addr( |
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112 | dwmac_common_context *self, |
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113 | const uint8_t *addr, |
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114 | unsigned int reg_n ) |
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115 | { |
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116 | dwmac_core_set_mac_addr( |
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117 | addr, |
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118 | dwmac_1000_core_get_mac_addr_high( self, reg_n ), |
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119 | dwmac_1000_core_get_mac_addr_low( self, reg_n ) |
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120 | ); |
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121 | } |
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122 | |
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123 | static void dwmac_1000_core_set_hash_filter( |
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124 | dwmac_common_context *self, |
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125 | const bool add, |
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126 | struct ifreq *ifr ) |
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127 | { |
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128 | int eno = 0; |
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129 | struct arpcom *ac = &self->arpcom; |
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130 | |
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131 | if ( add ) { |
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132 | eno = ether_addmulti( ifr, ac ); |
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133 | } else { |
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134 | eno = ether_delmulti( ifr, ac ); |
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135 | } |
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136 | |
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137 | if ( eno == ENETRESET ) { |
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138 | struct ether_multistep step; |
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139 | struct ether_multi *enm; |
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140 | unsigned int num_multi = 0; |
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141 | unsigned int index; |
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142 | |
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143 | ETHER_FIRST_MULTI( step, ac, enm ); |
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144 | |
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145 | while ( enm != NULL ) { |
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146 | /* Find out how many multicast addresses we have to handle */ |
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147 | uint64_t addrlo = 0; |
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148 | uint64_t addrhi = 0; |
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149 | |
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150 | memcpy( &addrlo, enm->enm_addrlo, ETHER_ADDR_LEN ); |
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151 | memcpy( &addrhi, enm->enm_addrhi, ETHER_ADDR_LEN ); |
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152 | num_multi += 1U + (uint32_t) ( addrhi - addrlo ); |
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153 | } |
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154 | |
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155 | if ( num_multi > DWMAC_1000_CORE_HASH_TABLE_SIZE ) { |
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156 | /* Too many addresses to be hashed, Use the |
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157 | * pass all multi option instead */ |
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158 | |
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159 | for ( index = 0; index < 8; ++index ) { |
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160 | self->macgrp->hash_table_reg[index] = 0xffffffff; |
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161 | } |
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162 | |
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163 | self->macgrp->mac_frame_filter |= MACGRP_MAC_FRAME_FILTER_PM; |
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164 | } else if ( num_multi > 0 ) { |
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165 | uint32_t hash_shadow[8] = {0, 0, 0, 0, 0, 0, 0, 0}; |
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166 | ETHER_FIRST_MULTI( step, ac, enm ); |
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167 | |
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168 | while ( enm != NULL ) { |
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169 | uint64_t addrlo = 0; |
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170 | uint64_t addrhi = 0; |
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171 | |
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172 | memcpy( &addrlo, enm->enm_addrlo, ETHER_ADDR_LEN ); |
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173 | memcpy( &addrhi, enm->enm_addrhi, ETHER_ADDR_LEN ); |
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174 | |
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175 | while ( addrlo <= addrhi ) { |
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176 | /* XXX: ether_crc32_le() does not work, why? */ |
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177 | uint32_t crc = ether_crc32_be( (uint8_t *) &addrlo, ETHER_ADDR_LEN ); |
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178 | |
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179 | /* The upper 8 bits of the bit reversed 32 bit CRC are used for hash filtering. |
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180 | * The most significant bits determine the register to be used and the |
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181 | * least significant five bits determine which bit to be set within the register */ |
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182 | uint32_t index_reg = ( crc >> 29 ) & 0x7; |
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183 | uint32_t index_bit = ( crc >> 24 ) & 0x1f; |
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184 | |
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185 | hash_shadow[index_reg] |= 1U << index_bit; |
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186 | ++addrlo; |
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187 | } |
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188 | |
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189 | ETHER_NEXT_MULTI( step, enm ); |
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190 | } |
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191 | |
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192 | for ( index = 0; index < 8; ++index ) { |
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193 | self->macgrp->hash_table_reg[index] = hash_shadow[index]; |
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194 | } |
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195 | |
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196 | /* Hash filter for multicast */ |
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197 | self->macgrp->mac_frame_filter |= MACGRP_MAC_FRAME_FILTER_HMC; |
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198 | } else { |
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199 | /* Set all hash registers to accect to accept no multicast packets */ |
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200 | for ( index = 0; index < 8; ++index ) { |
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201 | self->macgrp->hash_table_reg[index] = 0x00000000; |
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202 | } |
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203 | |
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204 | /* Hash filter for multicast */ |
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205 | self->macgrp->mac_frame_filter |= MACGRP_MAC_FRAME_FILTER_HMC; |
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206 | } |
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207 | |
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208 | DWMAC_1000_CORE_PRINT_DBG( |
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209 | "Frame Filter reg: 0x%08x\n", |
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210 | self->macgrp->mac_frame_filter |
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211 | ); |
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212 | DWMAC_1000_CORE_PRINT_DBG( |
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213 | "Hash regs:\n" |
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214 | "0x%08x\n" |
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215 | "0x%08x\n" |
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216 | "0x%08x\n" |
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217 | "0x%08x\n" |
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218 | "0x%08x\n" |
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219 | "0x%08x\n" |
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220 | "0x%08x\n" |
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221 | "0x%08x\n", |
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222 | self->macgrp->hash_table_reg[0], |
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223 | self->macgrp->hash_table_reg[1], |
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224 | self->macgrp->hash_table_reg[2], |
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225 | self->macgrp->hash_table_reg[3], |
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226 | self->macgrp->hash_table_reg[4], |
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227 | self->macgrp->hash_table_reg[5], |
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228 | self->macgrp->hash_table_reg[6], |
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229 | self->macgrp->hash_table_reg[7] |
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230 | ); |
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231 | } |
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232 | } |
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233 | |
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234 | const dwmac_common_core_ops dwmac_core_ops_1000 = { |
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235 | .core_init = dwmac_1000_core_init, |
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236 | .set_hash_filter = dwmac_1000_core_set_hash_filter, |
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237 | .set_umac_addr = dwmac_1000_core_set_umac_addr, |
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238 | }; |
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