source: rtems/c/src/libchip/network/dec21140.c @ ac8f462

4.104.114.84.95
Last change on this file since ac8f462 was ac8f462, checked in by Joel Sherrill <joel.sherrill@…>, on 11/10/04 at 23:53:09

2004-11-10 Richard Campbell <richard.campbell@…>

  • libchip/network/dec21140.c: Cleanup a bit and remove message about not supported on PowerPC since it works on the MVME2100 BSP.
  • Property mode set to 100644
File size: 30.8 KB
Line 
1/*
2 *  RTEMS driver for TULIP based Ethernet Controller
3 *
4 *  Copyright (C) 1999 Emmanuel Raguet. raguet@crf.canon.fr
5 *
6 *  The license and distribution terms for this file may be
7 *  found in found in the file LICENSE in this distribution or at
8 *  http://www.rtems.com/license/LICENSE.
9 *
10 * $Id$
11 *
12 * ------------------------------------------------------------------------
13 * [22.05.2000,StWi/CWA] added support for the DEC/Intel 21143 chip
14 *
15 * Thanks go to Andrew Klossner who provided the vital information about the
16 * Intel 21143 chip.  FWIW: The 21143 additions to this driver were initially
17 * tested with a PC386 BSP using a Kingston KNE100TX with 21143PD chip.
18 *
19 * The driver will automatically detect whether there is a 21140 or 21143
20 * network card in the system and activate support accordingly. It will
21 * look for the 21140 first. If the 21140 is not found the driver will
22 * look for the 21143.
23 *
24 * 2004-11-10, Joel/Richard - 21143 support works on MVME2100.
25 * ------------------------------------------------------------------------
26 *
27 * 2003-03-13, Greg Menke, gregory.menke@gsfc.nasa.gov
28 *
29 * Added support for up to 8 units (which is an arbitrary limit now),
30 * consolidating their support into a single pair of rx/tx daemons and a
31 * single ISR for all vectors servicing the DEC units.  The driver now
32 * simply uses whatever INTERRUPT_LINE the card supplies, requiring it
33 * be configured either by the boot monitor or bspstart() hackery.
34 * Tested on a MCP750 PPC based system with 2 DEC21140 boards.
35 *
36 * Also fixed a few bugs related to board configuration, start and stop.
37 *
38 */
39
40#include <rtems.h>
41
42/*
43 *  This driver only supports architectures with the new style
44 *  exception processing.  The following checks try to keep this
45 *  from being compiled on systems which can't support this driver.
46 */
47
48#if defined(__i386__)
49  #define DEC21140_SUPPORTED
50#endif
51
52#if defined(__PPC__) && (defined(mpc604) || defined(mpc750) || defined(mpc603e))
53  #define DEC21140_SUPPORTED
54#endif
55
56#if defined(DEC21140_SUPPORTED)
57#include <bsp.h>
58#include <rtems/pci.h>
59#if defined(__i386__)
60#include <pcibios.h>
61#endif
62#if defined(__PPC__)
63#include <libcpu/byteorder.h>
64#include <libcpu/io.h>
65#endif
66
67#include <stdlib.h>
68#include <stdio.h>
69#include <stdarg.h>
70#include <string.h>
71#include <errno.h>
72#include <rtems/error.h>
73#include <rtems/bspIo.h>
74#include <rtems/rtems_bsdnet.h>
75
76#include <sys/param.h>
77#include <sys/mbuf.h>
78
79#include <sys/socket.h>
80#include <sys/sockio.h>
81#include <net/if.h>
82#include <netinet/in.h>
83#include <netinet/if_ether.h>
84
85#if defined(__i386__)
86#include <irq.h>
87#endif
88#if defined(__PPC__)
89#include <bsp/irq.h>
90#endif
91
92#ifdef malloc
93#undef malloc
94#endif
95#ifdef free
96#undef free
97#endif
98
99#define DEC_DEBUG
100
101/* note: the 21143 isn't really a DEC, it's an Intel chip */
102#define PCI_INVALID_VENDORDEVICEID      0xffffffff
103#define PCI_VENDOR_ID_DEC               0x1011
104#define PCI_DEVICE_ID_DEC_21140         0x0009
105#define PCI_DEVICE_ID_DEC_21143         0x0019
106
107#define DRIVER_PREFIX   "dc"
108
109#define IO_MASK   0x3
110#define MEM_MASK  0xF
111
112/* command and status registers, 32-bit access, only if IO-ACCESS */
113#define ioCSR0  0x00    /* bus mode register */
114#define ioCSR1  0x08    /* transmit poll demand */
115#define ioCSR2  0x10    /* receive poll demand */
116#define ioCSR3  0x18    /* receive list base address */
117#define ioCSR4  0x20    /* transmit list base address */
118#define ioCSR5  0x28    /* status register */
119#define ioCSR6  0x30    /* operation mode register */
120#define ioCSR7  0x38    /* interrupt mask register */
121#define ioCSR8  0x40    /* missed frame counter */
122#define ioCSR9  0x48    /* Ethernet ROM register */
123#define ioCSR10 0x50    /* reserved */
124#define ioCSR11 0x58    /* full-duplex register */
125#define ioCSR12 0x60    /* SIA status register */
126#define ioCSR13 0x68
127#define ioCSR14 0x70
128#define ioCSR15 0x78    /* SIA general register */
129
130/* command and status registers, 32-bit access, only if MEMORY-ACCESS */
131#define memCSR0  0x00   /* bus mode register */
132#define memCSR1  0x02   /* transmit poll demand */
133#define memCSR2  0x04   /* receive poll demand */
134#define memCSR3  0x06   /* receive list base address */
135#define memCSR4  0x08   /* transmit list base address */
136#define memCSR5  0x0A   /* status register */
137#define memCSR6  0x0C   /* operation mode register */
138#define memCSR7  0x0E   /* interrupt mask register */
139#define memCSR8  0x10   /* missed frame counter */
140#define memCSR9  0x12   /* Ethernet ROM register */
141#define memCSR10 0x14   /* reserved */
142#define memCSR11 0x16   /* full-duplex register */
143#define memCSR12 0x18   /* SIA status register */
144#define memCSR13 0x1A
145#define memCSR14 0x1C
146#define memCSR15 0x1E   /* SIA general register */
147
148#define DEC_REGISTER_SIZE    0x100   /* to reserve virtual memory */
149
150
151
152
153#define RESET_CHIP   0x00000001
154#if defined(__PPC__)
155#define CSR0_MODE    0x0030e002   /* 01b08000 */
156#else
157#define CSR0_MODE    0x0020e002   /* 01b08000 */
158#endif
159#define ROM_ADDRESS  0x00004800
160#define CSR6_INIT    0x022cc000   /* 022c0000 020c0000 */
161#define CSR6_TX      0x00002000
162#define CSR6_TXRX    0x00002002
163#define IT_SETUP     0x000100c0   /* 000100e0 */
164#define CLEAR_IT     0xFFFFFFFF
165#define NO_IT        0x00000000
166
167
168
169/* message descriptor entry */
170struct MD {
171    /* used by hardware */
172    volatile uint32_t   status;
173    volatile uint32_t   counts;
174    volatile uint32_t   buf1, buf2;
175    /* used by software */
176    volatile struct mbuf *m;
177    volatile struct MD *next;
178} __attribute__ ((packed));
179
180
181
182
183/*
184** These buffers allocated for each unit, so ensure
185**
186**   rtems_bsdnet_config.mbuf_bytecount
187**   rtems_bsdnet_config.mbuf_cluster_bytecount
188**
189** are adequately sized to provide enough clusters and mbufs for all the
190** units.  The default bsdnet configuration is sufficient for one dec
191** unit, but will be nearing exhaustion with 2 or more.  Although a
192** little expensive in memory, the following configuration should
193** eliminate all mbuf/cluster issues;
194**
195**   rtems_bsdnet_config.mbuf_bytecount           = 128*1024;
196**   rtems_bsdnet_config.mbuf_cluster_bytecount   = 256*1024;
197*/
198
199#define NRXBUFS 16      /* number of receive buffers */
200#define NTXBUFS 16      /* number of transmit buffers */
201
202
203/*
204 * Number of DEC boards supported by this driver
205 */
206#define NDECDRIVER      8
207
208
209/*
210 * Receive buffer size -- Allow for a full ethernet packet including CRC
211 */
212#define RBUF_SIZE       1536
213
214#define ET_MINLEN       60      /* minimum message length */
215
216
217/*
218** Events, one per unit.  The event is sent to the rx task from the isr
219** or from the stack to the tx task whenever a unit needs service.  The
220** rx/tx tasks identify the requesting unit(s) by their particular
221** events so only requesting units are serviced.
222*/
223
224static rtems_event_set unit_signals[NDECDRIVER]= { RTEMS_EVENT_1,
225                                                   RTEMS_EVENT_2,
226                                                   RTEMS_EVENT_3,
227                                                   RTEMS_EVENT_4,
228                                                   RTEMS_EVENT_5,
229                                                   RTEMS_EVENT_6,
230                                                   RTEMS_EVENT_7,
231                                                   RTEMS_EVENT_8 };
232
233
234#if defined(__PPC__)
235#define phys_to_bus(address) ((unsigned int)((address)) + PCI_DRAM_OFFSET)
236#define bus_to_phys(address) ((unsigned int)((address)) - PCI_DRAM_OFFSET)
237#define CPU_CACHE_ALIGNMENT_FOR_BUFFER PPC_CACHE_ALIGNMENT
238#else
239extern void Wait_X_ms( unsigned int timeToWait );
240#define phys_to_bus(address) ((unsigned int) ((address)))
241#define bus_to_phys(address) ((unsigned int) ((address)))
242#define rtems_bsp_delay_in_bus_cycles(cycle) Wait_X_ms( cycle/100 )
243#define CPU_CACHE_ALIGNMENT_FOR_BUFFER PG_SIZE
244
245static inline void st_le32(volatile uint32_t   *addr, uint32_t   value)
246{
247  *(addr)=value ;
248}
249
250static inline uint32_t   ld_le32(volatile uint32_t   *addr)
251{
252  return(*addr);
253}
254
255#endif
256
257#if (MCLBYTES < RBUF_SIZE)
258# error "Driver must have MCLBYTES > RBUF_SIZE"
259#endif
260
261
262
263
264
265/*
266 * Per-device data
267 */
268struct dec21140_softc {
269
270      struct arpcom             arpcom;
271
272      rtems_irq_connect_data    irqInfo;
273      rtems_event_set           ioevent;
274
275      int                       numRxbuffers, numTxbuffers;
276
277      volatile struct MD        *MDbase;
278      volatile struct MD        *nextRxMD;
279      volatile unsigned char    *bufferBase;
280      int                       acceptBroadcast;
281
282      volatile struct MD   *TxMD;
283      volatile struct MD   *SentTxMD;
284      int         PendingTxCount;
285      int         TxSuspended;
286
287      unsigned int                      port;
288      volatile unsigned int             *base;
289
290      /*
291       * Statistics
292       */
293      unsigned long     rxInterrupts;
294      unsigned long     rxNotFirst;
295      unsigned long     rxNotLast;
296      unsigned long     rxGiant;
297      unsigned long     rxNonOctet;
298      unsigned long     rxRunt;
299      unsigned long     rxBadCRC;
300      unsigned long     rxOverrun;
301      unsigned long     rxCollision;
302
303      unsigned long     txInterrupts;
304      unsigned long     txDeferred;
305      unsigned long     txHeartbeat;
306      unsigned long     txLateCollision;
307      unsigned long     txRetryLimit;
308      unsigned long     txUnderrun;
309      unsigned long     txLostCarrier;
310      unsigned long     txRawWait;
311};
312
313static struct dec21140_softc dec21140_softc[NDECDRIVER];
314static rtems_id rxDaemonTid;
315static rtems_id txDaemonTid;
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333/*
334 * This routine reads a word (16 bits) from the serial EEPROM.
335 */
336/*  EEPROM_Ctrl bits. */
337#define EE_SHIFT_CLK            0x02    /* EEPROM shift clock. */
338#define EE_CS                   0x01    /* EEPROM chip select. */
339#define EE_DATA_WRITE           0x04    /* EEPROM chip data in. */
340#define EE_WRITE_0              0x01
341#define EE_WRITE_1              0x05
342#define EE_DATA_READ            0x08    /* EEPROM chip data out. */
343#define EE_ENB                  (0x4800 | EE_CS)
344
345/* The EEPROM commands include the alway-set leading bit. */
346#define EE_WRITE_CMD    (5 << 6)
347#define EE_READ_CMD     (6 << 6)
348#define EE_ERASE_CMD    (7 << 6)
349
350static int eeget16(volatile unsigned int *ioaddr, int location)
351{
352   int i;
353   unsigned short retval = 0;
354   int read_cmd = location | EE_READ_CMD;
355
356   st_le32(ioaddr, EE_ENB & ~EE_CS);
357   st_le32(ioaddr, EE_ENB);
358
359   /* Shift the read command bits out. */
360   for (i = 10; i >= 0; i--) {
361      short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
362      st_le32(ioaddr, EE_ENB | dataval);
363      rtems_bsp_delay_in_bus_cycles(200);
364      st_le32(ioaddr, EE_ENB | dataval | EE_SHIFT_CLK);
365      rtems_bsp_delay_in_bus_cycles(200);
366      st_le32(ioaddr, EE_ENB | dataval); /* Finish EEPROM a clock tick. */
367      rtems_bsp_delay_in_bus_cycles(200);
368   }
369   st_le32(ioaddr, EE_ENB);
370
371   for (i = 16; i > 0; i--) {
372      st_le32(ioaddr, EE_ENB | EE_SHIFT_CLK);
373      rtems_bsp_delay_in_bus_cycles(200);
374      retval = (retval << 1) | ((ld_le32(ioaddr) & EE_DATA_READ) ? 1 : 0);
375      st_le32(ioaddr, EE_ENB);
376      rtems_bsp_delay_in_bus_cycles(200);
377   }
378
379   /* Terminate the EEPROM access. */
380   st_le32(ioaddr, EE_ENB & ~EE_CS);
381   return ( ((retval<<8)&0xff00) | ((retval>>8)&0xff) );
382}
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405static void no_op(const rtems_irq_connect_data* irq)
406{
407   return;
408}
409
410
411
412
413static int dec21140IsOn(const rtems_irq_connect_data* irq)
414{
415  return BSP_irq_enabled_at_i8259s (irq->name);
416}
417
418
419
420
421/*
422 * DEC21140 interrupt handler
423 */
424static rtems_isr
425dec21140Enet_interrupt_handler ( struct dec21140_softc *sc )
426{
427   volatile uint32_t      *tbase;
428   uint32_t               status;
429
430   tbase = (uint32_t*)(sc->base);
431
432   /*
433    * Read status
434    */
435   status = ld_le32(tbase+memCSR5);
436   st_le32((tbase+memCSR5), status);
437
438   /*
439    * Frame received?
440    */
441   if( status & 0x000000c0 )
442   {
443      sc->rxInterrupts++;
444      rtems_event_send(rxDaemonTid, sc->ioevent);
445   }
446}
447
448
449
450static rtems_isr
451dec21140Enet_interrupt_handler_entry()
452{
453   int i;
454
455   /*
456   ** Check all the initialized dec units for interrupt service
457   */
458
459   for(i=0; i< NDECDRIVER; i++ )
460   {
461      if( dec21140_softc[i].base )
462         dec21140Enet_interrupt_handler( &dec21140_softc[i] );
463   }
464}
465
466
467
468
469
470
471
472
473
474
475/*
476 * Initialize the ethernet hardware
477 */
478static void
479dec21140Enet_initialize_hardware (struct dec21140_softc *sc)
480{
481   int i,st;
482   volatile unsigned int  *tbase;
483   volatile unsigned char *cp, *setup_frm, *eaddrs;
484   volatile unsigned char *buffer;
485   volatile struct MD     *rmd;
486
487
488#ifdef DEC_DEBUG
489   printk("dec2114x : %02x:%02x:%02x:%02x:%02x:%02x   name '%s%d', io %x, mem %x, int %d\n",
490          sc->arpcom.ac_enaddr[0], sc->arpcom.ac_enaddr[1],
491          sc->arpcom.ac_enaddr[2], sc->arpcom.ac_enaddr[3],
492          sc->arpcom.ac_enaddr[4], sc->arpcom.ac_enaddr[5],
493          sc->arpcom.ac_if.if_name, sc->arpcom.ac_if.if_unit,
494          sc->port, (unsigned) sc->base, sc->irqInfo.name );
495#endif
496
497
498
499   tbase = sc->base;
500
501   /*
502    * WARNING : First write in CSR6
503    *           Then Reset the chip ( 1 in CSR0)
504    */
505   st_le32( (tbase+memCSR6), CSR6_INIT);
506   st_le32( (tbase+memCSR0), RESET_CHIP);
507   rtems_bsp_delay_in_bus_cycles(200);
508
509   st_le32( (tbase+memCSR7), NO_IT);
510
511   /*
512    * Init CSR0
513    */
514   st_le32( (tbase+memCSR0), CSR0_MODE);
515
516   /*
517    * Init RX ring
518    */
519   cp = (volatile unsigned char *)malloc(((sc->numRxbuffers+sc->numTxbuffers)*sizeof(struct MD))
520                                         + (sc->numTxbuffers*RBUF_SIZE)
521                                         + CPU_CACHE_ALIGNMENT_FOR_BUFFER);
522   sc->bufferBase = cp;
523   cp += (CPU_CACHE_ALIGNMENT_FOR_BUFFER - (int)cp) & (CPU_CACHE_ALIGNMENT_FOR_BUFFER - 1);
524#if defined(__i386__)
525#ifdef PCI_BRIDGE_DOES_NOT_ENSURE_CACHE_COHERENCY_FOR_DMA
526   if (_CPU_is_paging_enabled())
527      _CPU_change_memory_mapping_attribute
528         (NULL, cp,
529          ((sc->numRxbuffers+sc->numTxbuffers)*sizeof(struct MD))
530          + (sc->numTxbuffers*RBUF_SIZE),
531          PTE_CACHE_DISABLE | PTE_WRITABLE);
532#endif
533#endif
534   rmd = (volatile struct MD*)cp;
535   sc->MDbase = rmd;
536   sc->nextRxMD = sc->MDbase;
537
538   buffer = cp + ((sc->numRxbuffers+sc->numTxbuffers)*sizeof(struct MD));
539   st_le32( (tbase+memCSR3), (long)(phys_to_bus((long)(sc->MDbase))));
540
541   for (i=0 ; i<sc->numRxbuffers; i++)
542   {
543      struct mbuf *m;
544
545      /* allocate an mbuf for each receive descriptor */
546      MGETHDR (m, M_WAIT, MT_DATA);
547      MCLGET (m, M_WAIT);
548      m->m_pkthdr.rcvif = &sc->arpcom.ac_if;
549      rmd->m = m;
550
551      rmd->buf2   = phys_to_bus(rmd+1);
552      rmd->buf1   = phys_to_bus(mtod(m, void *));
553      rmd->status = 0x80000000;
554      rmd->counts = 0xfdc00000 | (RBUF_SIZE);
555      rmd->next   = rmd+1;
556      rmd++;
557   }
558   /*
559    * mark last RX buffer.
560    */
561   sc->MDbase [sc->numRxbuffers-1].buf2   = 0;
562   sc->MDbase [sc->numRxbuffers-1].counts = 0xfec00000 | (RBUF_SIZE);
563   sc->MDbase [sc->numRxbuffers-1].next   = sc->MDbase;
564
565
566
567   /*
568    * Init TX ring
569    */
570   st_le32( (tbase+memCSR4), (long)(phys_to_bus((long)(rmd))) );
571   for (i=0 ; i<sc->numTxbuffers; i++){
572      (rmd+i)->buf2   = phys_to_bus(rmd+i+1);
573      (rmd+i)->buf1   = phys_to_bus(buffer + (i*RBUF_SIZE));
574      (rmd+i)->counts = 0x01000000;
575      (rmd+i)->status = 0x0;
576      (rmd+i)->next   = rmd+i+1;
577      (rmd+i)->m      = 0;
578   }
579
580   /*
581    * mark last TX buffer.
582    */
583   (rmd+sc->numTxbuffers-1)->buf2   = phys_to_bus(rmd);
584   (rmd+sc->numTxbuffers-1)->next   = rmd;
585
586
587   /*
588    * Build setup frame
589    */
590   setup_frm = (volatile unsigned char *)(bus_to_phys(rmd->buf1));
591   eaddrs = (char *)(sc->arpcom.ac_enaddr);
592   /* Fill the buffer with our physical address. */
593   for (i = 1; i < 16; i++) {
594      *setup_frm++ = eaddrs[0];
595      *setup_frm++ = eaddrs[1];
596      *setup_frm++ = eaddrs[0];
597      *setup_frm++ = eaddrs[1];
598      *setup_frm++ = eaddrs[2];
599      *setup_frm++ = eaddrs[3];
600      *setup_frm++ = eaddrs[2];
601      *setup_frm++ = eaddrs[3];
602      *setup_frm++ = eaddrs[4];
603      *setup_frm++ = eaddrs[5];
604      *setup_frm++ = eaddrs[4];
605      *setup_frm++ = eaddrs[5];
606   }
607
608   /* Add the broadcast address when doing perfect filtering */
609   memset((void*) setup_frm, 0xff, 12);
610   rmd->counts = 0x09000000 | 192 ;
611   rmd->status = 0x80000000;
612   st_le32( (tbase+memCSR6), CSR6_INIT | CSR6_TX);
613   st_le32( (tbase+memCSR1), 1);
614
615   while (rmd->status != 0x7fffffff);
616   rmd->counts = 0x01000000;
617
618   sc->TxMD = rmd+1;
619
620
621
622
623
624   sc->irqInfo.hdl  = (rtems_irq_hdl)dec21140Enet_interrupt_handler_entry;
625   sc->irqInfo.on   = no_op;
626   sc->irqInfo.off  = no_op;
627   sc->irqInfo.isOn = dec21140IsOn;
628
629#ifdef DEC_DEBUG
630   printk( "dec2114x: Installing IRQ %d\n", sc->irqInfo.name );
631#endif
632#ifdef BSP_SHARED_HANDLER_SUPPORT
633   st = BSP_install_rtems_shared_irq_handler( &sc->irqInfo );
634#else
635   st = BSP_install_rtems_irq_handler( &sc->irqInfo );
636#endif
637
638   if (!st)
639      rtems_panic ("dec2114x : Interrupt name %d already in use\n", sc->irqInfo.name );
640}
641
642
643
644
645
646
647
648static void
649dec21140_rxDaemon (void *arg)
650{
651   volatile unsigned int *tbase;
652   volatile struct MD    *rmd;
653   struct dec21140_softc *sc;
654   struct ifnet          *ifp;
655   struct ether_header   *eh;
656   struct mbuf           *m;
657   unsigned int          i,len;
658   rtems_event_set       events;
659
660   for (;;)
661   {
662
663      rtems_bsdnet_event_receive( RTEMS_ALL_EVENTS,
664                                  RTEMS_WAIT|RTEMS_EVENT_ANY,
665                                  RTEMS_NO_TIMEOUT,
666                                  &events);
667
668      for(i=0; i< NDECDRIVER; i++ )
669      {
670         sc = &dec21140_softc[i];
671         if( sc->base )
672         {
673            if( events & sc->ioevent )
674            {
675               ifp   = &sc->arpcom.ac_if;
676               tbase = sc->base;
677               rmd   = sc->nextRxMD;
678
679               /*
680               ** Read off all the packets we've received on this unit
681               */
682               while((rmd->status & 0x80000000) == 0)
683               {
684                  /* printk("unit %i rx\n", ifp->if_unit ); */
685
686                  /* pass on the packet in the mbuf */
687                  len = (rmd->status >> 16) & 0x7ff;
688                  m = (struct mbuf *)(rmd->m);
689                  m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header);
690                  eh = mtod (m, struct ether_header *);
691                  m->m_data += sizeof(struct ether_header);
692                  ether_input (ifp, eh, m);
693
694                  /* get a new mbuf for the 21140 */
695                  MGETHDR (m, M_WAIT, MT_DATA);
696                  MCLGET (m, M_WAIT);
697                  m->m_pkthdr.rcvif = ifp;
698                  rmd->m = m;
699                  rmd->buf1 = phys_to_bus(mtod(m, void *));
700
701                  /* mark the descriptor as ready to receive */
702                  rmd->status = 0x80000000;
703
704                  rmd=rmd->next;
705               }
706
707               sc->nextRxMD = rmd;
708            }
709         }
710      }
711
712   }
713}
714
715
716
717
718
719
720
721static void
722sendpacket (struct ifnet *ifp, struct mbuf *m)
723{
724   struct dec21140_softc   *dp = ifp->if_softc;
725   volatile struct MD      *tmd;
726   volatile unsigned char  *temp;
727   struct mbuf             *n;
728   unsigned int            len;
729   volatile unsigned int   *tbase;
730
731   tbase = dp->base;
732   /*
733    * Waiting for Transmitter ready
734    */
735
736   tmd = dp->TxMD;
737   n = m;
738
739   while ((tmd->status & 0x80000000) != 0)
740   {
741      tmd=tmd->next;
742   }
743
744   len = 0;
745   temp = (volatile unsigned char *)(bus_to_phys(tmd->buf1));
746
747   for (;;)
748   {
749      len += m->m_len;
750      memcpy((void*) temp, (char *)m->m_data, m->m_len);
751      temp += m->m_len ;
752      if ((m = m->m_next) == NULL)
753         break;
754   }
755
756   if (len < ET_MINLEN) len = ET_MINLEN;
757   tmd->counts =  0xe1000000 | (len & 0x7ff);
758   tmd->status = 0x80000000;
759
760   st_le32( (tbase+memCSR1), 0x1);
761
762   m_freem(n);
763
764   dp->TxMD = tmd->next;
765}
766
767
768
769
770
771/*
772 * Driver transmit daemon
773 */
774void
775dec21140_txDaemon (void *arg)
776{
777   struct dec21140_softc *sc;
778   struct ifnet          *ifp;
779   struct mbuf           *m;
780   int i;
781   rtems_event_set       events;
782
783   for (;;)
784   {
785      /*
786       * Wait for packets bound for any of the dec units
787       */
788      rtems_bsdnet_event_receive( RTEMS_ALL_EVENTS,
789                                  RTEMS_EVENT_ANY | RTEMS_WAIT,
790                                  RTEMS_NO_TIMEOUT, &events);
791
792      for(i=0; i< NDECDRIVER; i++ )
793      {
794         sc  = &dec21140_softc[i];
795         if( sc->base )
796         {
797            if( events & sc->ioevent )
798            {
799               ifp = &sc->arpcom.ac_if;
800
801               /*
802                * Send packets till queue is empty
803                */
804               for(;;)
805               {
806                  IF_DEQUEUE(&ifp->if_snd, m);
807                  if( !m ) break;
808                  /* printk("unit %i tx\n", ifp->if_unit ); */
809                  sendpacket (ifp, m);
810               }
811
812               ifp->if_flags &= ~IFF_OACTIVE;
813            }
814         }
815      }
816
817   }
818}
819
820
821
822
823static void
824dec21140_start (struct ifnet *ifp)
825{
826   struct dec21140_softc *sc = ifp->if_softc;
827   rtems_event_send( txDaemonTid, sc->ioevent );
828   ifp->if_flags |= IFF_OACTIVE;
829}
830
831
832
833
834
835/*
836 * Initialize and start the device
837 */
838static void
839dec21140_init (void *arg)
840{
841   struct dec21140_softc *sc = arg;
842   struct ifnet *ifp = &sc->arpcom.ac_if;
843   volatile unsigned int *tbase;
844
845   /*
846    * Set up DEC21140 hardware if its not already been done
847    */
848   if( !sc->irqInfo.hdl )
849   {
850      dec21140Enet_initialize_hardware (sc);
851   }
852
853   /*
854    * Enable RX and TX
855    */
856   tbase = sc->base;
857   st_le32( (tbase+memCSR5), IT_SETUP);
858   st_le32( (tbase+memCSR7), IT_SETUP);
859   st_le32( (unsigned int*)(tbase+memCSR6), CSR6_INIT | CSR6_TXRX);
860
861   /*
862    * Tell the world that we're running.
863    */
864   ifp->if_flags |= IFF_RUNNING;
865}
866
867
868
869
870
871
872
873/*
874 * Stop the device
875 */
876static void
877dec21140_stop (struct dec21140_softc *sc)
878{
879  volatile unsigned int *tbase;
880  struct ifnet *ifp = &sc->arpcom.ac_if;
881
882  ifp->if_flags &= ~IFF_RUNNING;
883
884  /*
885   * Stop the transmitter
886   */
887  tbase = sc->base;
888  st_le32( (tbase+memCSR7), NO_IT);
889  st_le32( (tbase+memCSR6), CSR6_INIT);
890
891  /*  free((void*)sc->bufferBase); */
892}
893
894
895/*
896 * Show interface statistics
897 */
898static void
899dec21140_stats (struct dec21140_softc *sc)
900{
901        printf ("      Rx Interrupts:%-8lu", sc->rxInterrupts);
902        printf ("       Not First:%-8lu", sc->rxNotFirst);
903        printf ("        Not Last:%-8lu\n", sc->rxNotLast);
904        printf ("              Giant:%-8lu", sc->rxGiant);
905        printf ("            Runt:%-8lu", sc->rxRunt);
906        printf ("       Non-octet:%-8lu\n", sc->rxNonOctet);
907        printf ("            Bad CRC:%-8lu", sc->rxBadCRC);
908        printf ("         Overrun:%-8lu", sc->rxOverrun);
909        printf ("       Collision:%-8lu\n", sc->rxCollision);
910
911        printf ("      Tx Interrupts:%-8lu", sc->txInterrupts);
912        printf ("        Deferred:%-8lu", sc->txDeferred);
913        printf (" Missed Hearbeat:%-8lu\n", sc->txHeartbeat);
914        printf ("         No Carrier:%-8lu", sc->txLostCarrier);
915        printf ("Retransmit Limit:%-8lu", sc->txRetryLimit);
916        printf ("  Late Collision:%-8lu\n", sc->txLateCollision);
917        printf ("           Underrun:%-8lu", sc->txUnderrun);
918        printf (" Raw output wait:%-8lu\n", sc->txRawWait);
919}
920
921
922
923
924/*
925 * Driver ioctl handler
926 */
927static int
928dec21140_ioctl (struct ifnet *ifp, int command, caddr_t data)
929{
930   struct dec21140_softc *sc = ifp->if_softc;
931   int error = 0;
932
933   switch (command) {
934      case SIOCGIFADDR:
935      case SIOCSIFADDR:
936         ether_ioctl (ifp, command, data);
937         break;
938
939      case SIOCSIFFLAGS:
940         switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
941            case IFF_RUNNING:
942               dec21140_stop (sc);
943               break;
944
945            case IFF_UP:
946               dec21140_init (sc);
947               break;
948
949            case IFF_UP | IFF_RUNNING:
950               dec21140_stop (sc);
951               dec21140_init (sc);
952               break;
953
954            default:
955               break;
956         }
957         break;
958
959      case SIO_RTEMS_SHOW_STATS:
960         dec21140_stats (sc);
961         break;
962
963         /*
964          * FIXME: All sorts of multicast commands need to be added here!
965          */
966      default:
967         error = EINVAL;
968         break;
969   }
970
971   return error;
972}
973
974
975
976
977
978
979
980/*
981int iftap(struct ifnet *ifp, struct ether_header *eh, struct mbuf *m )
982{
983   int i;
984
985   if(  ifp->if_unit == 1 ) return 0;
986
987   printf("unit %i, src ", ifp->if_unit );
988   for(i=0; i< ETHER_ADDR_LEN; i++) printf("%02x", (char) eh->ether_shost[i] );
989   printf(" dest ");
990   for(i=0; i< ETHER_ADDR_LEN; i++) printf("%02x", (char) eh->ether_dhost[i] );
991   printf("\n");
992
993   return -1;
994}
995*/
996
997
998
999
1000
1001/*
1002 * Attach an DEC21140 driver to the system
1003 */
1004int
1005rtems_dec21140_driver_attach (struct rtems_bsdnet_ifconfig *config, int attach)
1006{
1007   struct dec21140_softc *sc;
1008   struct ifnet *ifp;
1009   char         *unitName;
1010   int          unitNumber;
1011   int          mtu;
1012   unsigned char cvalue;
1013#if defined(__i386__)
1014   int          signature;
1015   int          value;
1016   char         interrupt;
1017   int          diag;
1018   unsigned int deviceId;
1019#endif
1020#if defined(__PPC__)
1021   int          pbus, pdev, pfun;
1022   int          tmp;
1023   unsigned int lvalue;
1024#endif
1025
1026
1027   /*
1028    * Get the instance number for the board we're going to configure
1029    * from the user.
1030    */
1031   if( (unitNumber = rtems_bsdnet_parse_driver_name(config, &unitName)) == -1 )
1032   {
1033      return 0;
1034   }
1035   if( strcmp(unitName, DRIVER_PREFIX) )
1036   {
1037      printk("dec2114x : unit name '%s' not %s\n", unitName, DRIVER_PREFIX );
1038      return 0;
1039   }
1040
1041
1042#if defined(__i386__)
1043   /*
1044    * First, find a DEC board
1045    */
1046
1047   if (pcib_init() == PCIB_ERR_NOTPRESENT)
1048      rtems_panic("PCI BIOS not found !!");
1049
1050   /*
1051    * Try to find the network card on the PCI bus. Probe for a DEC 21140
1052    * card first. If not found probe the bus for a DEC/Intel 21143 card.
1053    */
1054   deviceId = PCI_DEVICE_ID_DEC_21140;
1055   diag = pcib_find_by_devid( PCI_VENDOR_ID_DEC, deviceId, unitNumber-1, &signature);
1056
1057   if ( diag == PCIB_ERR_SUCCESS)
1058      printk( "DEC 21140 PCI network card found\n" );
1059   else
1060   {
1061      deviceId = PCI_DEVICE_ID_DEC_21143;
1062      diag = pcib_find_by_devid( PCI_VENDOR_ID_DEC, deviceId, unitNumber-1, &signature);
1063      if ( diag == PCIB_ERR_SUCCESS)
1064         printk( "DEC/Intel 21143 PCI network card found\n" );
1065      else
1066      {
1067         printk("No DEC/Intel 21140/3 PCI network card found !!\n");
1068         return 0;
1069      }
1070   }
1071#endif
1072#if defined(__PPC__)
1073   /*
1074    * Find the board
1075    */
1076   if( BSP_pciFindDevice( PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21140,
1077                          unitNumber-1, &pbus, &pdev, &pfun) == -1 )
1078   {
1079      if( BSP_pciFindDevice( PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21143,
1080                             unitNumber-1, &pbus, &pdev, &pfun) != -1 )
1081      {
1082
1083         pci_write_config_dword(pbus,
1084                                pdev,
1085                                pfun,
1086                                0x40,
1087                                PCI_DEVICE_ID_DEC_21143 );
1088
1089      }
1090      else
1091      {
1092         printk("dec2114x : device '%s' not found on PCI bus\n", config->name );
1093         return 0;
1094      }
1095   }
1096
1097#ifdef DEC_DEBUG
1098   else
1099   {
1100      printk("dec21140 : found device '%s', bus 0x%02x, dev 0x%02x, func 0x%02x\n",
1101             config->name, pbus, pdev, pfun);
1102   }
1103#endif
1104
1105#endif
1106
1107
1108
1109
1110   if ((unitNumber < 1) || (unitNumber > NDECDRIVER))
1111   {
1112      printk("dec2114x : unit %i is invalid, must be (1 <= n <= %d)\n", unitNumber);
1113      return 0;
1114   }
1115
1116   sc = &dec21140_softc[unitNumber - 1];
1117   ifp = &sc->arpcom.ac_if;
1118   if (ifp->if_softc != NULL)
1119   {
1120      printk("dec2114x : unit %i already in use.\n", unitNumber );
1121      return 0;
1122   }
1123
1124
1125   /*
1126   ** Get this unit's rx/tx event
1127   */
1128   sc->ioevent = unit_signals[unitNumber-1];
1129
1130   /*
1131   ** Save the buffer counts
1132   */
1133   sc->numRxbuffers = (config->rbuf_count) ? config->rbuf_count : NRXBUFS;
1134   sc->numTxbuffers = (config->xbuf_count) ? config->xbuf_count : NTXBUFS;
1135
1136
1137   /*
1138    * Get card address spaces & retrieve its isr vector
1139    */
1140#if defined(__i386__)
1141
1142   /* the 21143 chip must be enabled before it can be accessed */
1143   if ( deviceId == PCI_DEVICE_ID_DEC_21143 )
1144      pcib_conf_write32( signature, 0x40, 0 );
1145
1146   pcib_conf_read32(signature, 16, &value);
1147   sc->port = value & ~IO_MASK;
1148
1149   pcib_conf_read32(signature, 20, &value);
1150   if (_CPU_is_paging_enabled())
1151      _CPU_map_phys_address((void **) &(sc->base),
1152                            (void *)(value & ~MEM_MASK),
1153                            DEC_REGISTER_SIZE ,
1154                            PTE_CACHE_DISABLE | PTE_WRITABLE);
1155   else
1156      sc->base = (unsigned int *)(value & ~MEM_MASK);
1157
1158   pcib_conf_read8(signature, 60, &interrupt);
1159   cvalue = interrupt;
1160#endif
1161#if defined(__PPC__)
1162   (void)pci_read_config_dword(pbus,
1163                               pdev,
1164                               pfun,
1165                               PCI_BASE_ADDRESS_0,
1166                               &lvalue);
1167
1168   sc->port = lvalue & (unsigned int)(~IO_MASK);
1169
1170   (void)pci_read_config_dword(pbus,
1171                               pdev,
1172                               pfun,
1173                               PCI_BASE_ADDRESS_1,
1174                               &lvalue);
1175
1176   tmp = (unsigned int)(lvalue & (unsigned int)(~MEM_MASK))
1177      + (unsigned int)PCI_MEM_BASE_ADJUSTMENT;
1178
1179   sc->base = (unsigned int *)(tmp);
1180
1181   pci_read_config_byte(pbus,
1182                        pdev,
1183                        pfun,
1184                        PCI_INTERRUPT_LINE,
1185                        &cvalue);
1186
1187#endif
1188
1189   /*
1190   ** Prep the board
1191   */
1192
1193#if defined(__PPC__)
1194   pci_write_config_word(pbus, pdev, pfun,
1195#endif
1196#if defined(__i386__)
1197   pcib_conf_write16(signature,
1198#endif
1199      PCI_COMMAND,
1200      (uint16_t) ( PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER ) );
1201
1202   /*
1203   ** Store the interrupt name, we'll use it later when we initialize
1204   ** the board.
1205   */
1206   memset(&sc->irqInfo,0,sizeof(rtems_irq_connect_data));
1207   sc->irqInfo.name = cvalue;
1208
1209
1210#ifdef DEC_DEBUG
1211   printk("dec2114x : unit %d base address %08x.\n", unitNumber, sc->base );
1212#endif
1213
1214
1215   /*
1216   ** Setup ethernet address
1217   */
1218   if (config->hardware_address) {
1219      memcpy (sc->arpcom.ac_enaddr, config->hardware_address,
1220              ETHER_ADDR_LEN);
1221   }
1222   else {
1223      union {char c[64]; unsigned short s[32];} rombuf;
1224      int i;
1225
1226      for (i=0; i<32; i++){
1227         rombuf.s[i] = eeget16( sc->base + memCSR9, i);
1228      }
1229#if defined(__i386__)
1230      for (i=0 ; i<(ETHER_ADDR_LEN/2); i++){
1231         sc->arpcom.ac_enaddr[2*i]   = rombuf.c[20+2*i+1];
1232         sc->arpcom.ac_enaddr[2*i+1] = rombuf.c[20+2*i];
1233      }
1234#endif
1235#if defined(__PPC__)
1236      memcpy (sc->arpcom.ac_enaddr, rombuf.c+20, ETHER_ADDR_LEN);
1237#endif
1238   }
1239
1240   if (config->mtu)
1241      mtu = config->mtu;
1242   else
1243      mtu = ETHERMTU;
1244
1245   sc->acceptBroadcast = !config->ignore_broadcast;
1246
1247   /*
1248    * Set up network interface values
1249    */
1250
1251/*   ifp->if_tap = iftap; */
1252
1253   ifp->if_softc = sc;
1254   ifp->if_unit = unitNumber;
1255   ifp->if_name = unitName;
1256   ifp->if_mtu = mtu;
1257   ifp->if_init = dec21140_init;
1258   ifp->if_ioctl = dec21140_ioctl;
1259   ifp->if_start = dec21140_start;
1260   ifp->if_output = ether_output;
1261   ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX;
1262   if (ifp->if_snd.ifq_maxlen == 0)
1263      ifp->if_snd.ifq_maxlen = ifqmaxlen;
1264
1265   /*
1266    * Attach the interface
1267    */
1268   if_attach (ifp);
1269   ether_ifattach (ifp);
1270
1271#ifdef DEC_DEBUG
1272   printk( "dec2114x : driver attached\n" );
1273#endif
1274
1275
1276   /*
1277    * Start driver tasks if this is the first dec unit initialized
1278    */
1279   if (txDaemonTid == 0)
1280   {
1281      rxDaemonTid = rtems_bsdnet_newproc( "DCrx", 4096,
1282                                          dec21140_rxDaemon, NULL);
1283
1284      txDaemonTid = rtems_bsdnet_newproc( "DCtx", 4096,
1285                                          dec21140_txDaemon, NULL);
1286#ifdef DEC_DEBUG
1287      printk( "dec2114x : driver tasks created\n" );
1288#endif
1289   }
1290
1291   return 1;
1292};
1293
1294#endif /* DEC21140_SUPPORTED */
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