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source: rtems/c/src/libchip/network/dec21140.c @ a1efd7a

4.104.114.84.95

Last change on this file since a1efd7a was a1efd7a, checked in by Joel Sherrill <joel.sherrill@…>, on 12/03/99 at 14:48:27
Made to compile on other CPU families.
Property mode set to `100644`
File size: 21.9 KB

Line
1	/*
2	* RTEMS driver for TULIP based Ethernet Controller
3	*
4	* Copyright (C) 1999 Emmanuel Raguet. raguet@crf.canon.fr
5	*
6	* The license and distribution terms for this file may be
7	* found in found in the file LICENSE in this distribution or at
8	* http://www.OARcorp.com/rtems/license.html.
9	*
10	* $Id$
11	*/
12
13	#include <rtems.h>
14
15	/*
16	* This driver only supports architectures with the new style
17	* exception processing. The following checks try to keep this
18	* from being compiled on systems which can't support this driver.
19	*/
20
21	#if defined(__i386)
22	#define DEC21140_SUPPORTED
23	#endif
24
25	#if defined(__PPC) && (defined(mpc604) \|\| defined(mpc750))
26	#define DEC21140_SUPPORTED
27	#endif
28
29	#if defined(DEC21140_SUPPORTED)
30	#include <bsp.h>
31	#if defined(i386)
32	#include <pcibios.h>
33	#endif
34	#if defined(__PPC)
35	#include <bsp/pci.h>
36	#include <libcpu/byteorder.h>
37	#include <libcpu/io.h>
38	#endif
39
40	#include <stdlib.h>
41	#include <stdio.h>
42	#include <stdarg.h>
43	#include <rtems/error.h>
44	#include <rtems/rtems_bsdnet.h>
45
46	#include <libcpu/cpu.h>
47
48	#include <sys/param.h>
49	#include <sys/mbuf.h>
50
51	#include <sys/socket.h>
52	#include <sys/sockio.h>
53	#include <net/if.h>
54	#include <netinet/in.h>
55	#include <netinet/if_ether.h>
56
57	#if defined(i386)
58	#include <irq.h>
59	#endif
60	#if defined(__PPC)
61	#include <bsp/irq.h>
62	#endif
63
64	#ifdef malloc
65	#undef malloc
66	#endif
67	#ifdef free
68	#undef free
69	#endif
70
71	#define DEC_DEBUG
72
73	#define PCI_INVALID_VENDORDEVICEID 0xffffffff
74	#define PCI_VENDOR_ID_DEC 0x1011
75	#define PCI_DEVICE_ID_DEC_TULIP_FAST 0x0009
76
77	#define IO_MASK 0x3
78	#define MEM_MASK 0xF
79	#define MASK_OFFSET 0xF
80
81	/* command and status registers, 32-bit access, only if IO-ACCESS */
82	#define ioCSR0 0x00 /* bus mode register */
83	#define ioCSR1 0x08 /* transmit poll demand */
84	#define ioCSR2 0x10 /* receive poll demand */
85	#define ioCSR3 0x18 /* receive list base address */
86	#define ioCSR4 0x20 /* transmit list base address */
87	#define ioCSR5 0x28 /* status register */
88	#define ioCSR6 0x30 /* operation mode register */
89	#define ioCSR7 0x38 /* interrupt mask register */
90	#define ioCSR8 0x40 /* missed frame counter */
91	#define ioCSR9 0x48 /* Ethernet ROM register */
92	#define ioCSR10 0x50 /* reserved */
93	#define ioCSR11 0x58 /* full-duplex register */
94	#define ioCSR12 0x60 /* SIA status register */
95	#define ioCSR13 0x68
96	#define ioCSR14 0x70
97	#define ioCSR15 0x78 /* SIA general register */
98
99	/* command and status registers, 32-bit access, only if MEMORY-ACCESS */
100	#define memCSR0 0x00 /* bus mode register */
101	#define memCSR1 0x02 /* transmit poll demand */
102	#define memCSR2 0x04 /* receive poll demand */
103	#define memCSR3 0x06 /* receive list base address */
104	#define memCSR4 0x08 /* transmit list base address */
105	#define memCSR5 0x0A /* status register */
106	#define memCSR6 0x0C /* operation mode register */
107	#define memCSR7 0x0E /* interrupt mask register */
108	#define memCSR8 0x10 /* missed frame counter */
109	#define memCSR9 0x12 /* Ethernet ROM register */
110	#define memCSR10 0x14 /* reserved */
111	#define memCSR11 0x16 /* full-duplex register */
112	#define memCSR12 0x18 /* SIA status register */
113	#define memCSR13 0x1A
114	#define memCSR14 0x1C
115	#define memCSR15 0x1E /* SIA general register */
116
117	#define DEC_REGISTER_SIZE 0x100 /* to reserve virtual memory */
118
119	#define RESET_CHIP 0x00000001
120	#if defined(__PPC)
121	#define CSR0_MODE 0x0030e002 /* 01b08000 */
122	#else
123	#define CSR0_MODE 0x0020e002 /* 01b08000 */
124	#endif
125	#define ROM_ADDRESS 0x00004800
126	#define CSR6_INIT 0x022cc000 /* 022c0000 020c0000 */
127	#define CSR6_TX 0x00002000
128	#define CSR6_TXRX 0x00002002
129	#define IT_SETUP 0x000100c0 /* 000100e0 */
130	#define CLEAR_IT 0xFFFFFFFF
131	#define NO_IT 0x00000000
132
133	#define NRXBUFS 32 /* number of receive buffers */
134	#define NTXBUFS 16 /* number of transmit buffers */
135
136	/* message descriptor entry */
137	struct MD {
138	/* used by hardware */
139	volatile unsigned32 status;
140	volatile unsigned32 counts;
141	unsigned32 buf1, buf2;
142	/* used by software */
143	volatile struct mbuf *m;
144	volatile struct MD *next;
145	};
146
147	/*
148	* Number of DECs supported by this driver
149	*/
150	#define NDECDRIVER 1
151
152	/*
153	* Receive buffer size -- Allow for a full ethernet packet including CRC
154	*/
155	#define RBUF_SIZE 1536
156
157	#define ET_MINLEN 60 /* minimum message length */
158
159	/*
160	* RTEMS event used by interrupt handler to signal driver tasks.
161	* This must not be any of the events used by the network task synchronization.
162	*/
163	#define INTERRUPT_EVENT RTEMS_EVENT_1
164
165	/*
166	* RTEMS event used to start transmit daemon.
167	* This must not be the same as INTERRUPT_EVENT.
168	*/
169	#define START_TRANSMIT_EVENT RTEMS_EVENT_2
170
171	#if defined(__PPC)
172	#define phys_to_bus(address) ((unsigned int)(address) + PREP_PCI_DRAM_OFFSET)
173	#define bus_to_phys(address) ((unsigned int)(address) - PREP_PCI_DRAM_OFFSET)
174	#define CPU_CACHE_ALIGNMENT_FOR_BUFFER PPC_CACHE_ALIGNMENT
175	#else
176	#define phys_to_bus(address) address
177	#define bus_to_phys(address) address
178	#define delay_in_bus_cycles(cycle) Wait_X_ms( cycle/100 )
179	#define CPU_CACHE_ALIGNMENT_FOR_BUFFER PG_SIZE
180
181	inline void st_le32(volatile unsigned32 *addr, unsigned32 value)
182	{
183	*(addr)=value ;
184	}
185
186	inline unsigned32 ld_le32(volatile unsigned32 *addr)
187	{
188	return(*addr);
189	}
190
191	#endif
192
193	#if (MCLBYTES < RBUF_SIZE)
194	# error "Driver must have MCLBYTES > RBUF_SIZE"
195	#endif
196
197	/*
198	* Per-device data
199	*/
200	struct dec21140_softc {
201
202	struct arpcom arpcom;
203
204	rtems_irq_connect_data irqInfo;
205
206	volatile struct MD *MDbase;
207	volatile unsigned char *bufferBase;
208	int acceptBroadcast;
209	rtems_id rxDaemonTid;
210	rtems_id txDaemonTid;
211
212	volatile struct MD *TxMD;
213	volatile struct MD *SentTxMD;
214	int PendingTxCount;
215	int TxSuspended;
216
217	unsigned int port;
218	volatile unsigned int *base;
219
220	/*
221	* Statistics
222	*/
223	unsigned long rxInterrupts;
224	unsigned long rxNotFirst;
225	unsigned long rxNotLast;
226	unsigned long rxGiant;
227	unsigned long rxNonOctet;
228	unsigned long rxRunt;
229	unsigned long rxBadCRC;
230	unsigned long rxOverrun;
231	unsigned long rxCollision;
232
233	unsigned long txInterrupts;
234	unsigned long txDeferred;
235	unsigned long txHeartbeat;
236	unsigned long txLateCollision;
237	unsigned long txRetryLimit;
238	unsigned long txUnderrun;
239	unsigned long txLostCarrier;
240	unsigned long txRawWait;
241	};
242
243	static struct dec21140_softc dec21140_softc[NDECDRIVER];
244
245	/*
246	* DEC21140 interrupt handler
247	*/
248	static rtems_isr
249	dec21140Enet_interrupt_handler (rtems_vector_number v)
250	{
251	volatile unsigned32 *tbase;
252	unsigned32 status;
253	struct dec21140_softc *sc;
254
255	sc = &dec21140_softc[0];
256	tbase = (unsigned32 *)(sc->base) ;
257
258	/*
259	* Read status
260	*/
261	status = ld_le32(tbase+memCSR5);
262	st_le32((tbase+memCSR5), status); /* clear the bits we've read */
263
264	/*
265	* Frame received?
266	*/
267	if (status & 0x000000c0){
268	sc->rxInterrupts++;
269	rtems_event_send (sc->rxDaemonTid, INTERRUPT_EVENT);
270	}
271	}
272
273	static void nopOn(const rtems_irq_connect_data* notUsed)
274	{
275	/*
276	* code should be moved from dec21140Enet_initialize_hardware
277	* to this location
278	*/
279	}
280
281	static int dec21140IsOn(const rtems_irq_connect_data* irq)
282	{
283	return BSP_irq_enabled_at_i8259s (irq->name);
284	}
285
286
287	/*
288	* This routine reads a word (16 bits) from the serial EEPROM.
289	*/
290	/* EEPROM_Ctrl bits. */
291	#define EE_SHIFT_CLK 0x02 /* EEPROM shift clock. */
292	#define EE_CS 0x01 /* EEPROM chip select. */
293	#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
294	#define EE_WRITE_0 0x01
295	#define EE_WRITE_1 0x05
296	#define EE_DATA_READ 0x08 /* EEPROM chip data out. */
297	#define EE_ENB (0x4800 \| EE_CS)
298
299	/* The EEPROM commands include the alway-set leading bit. */
300	#define EE_WRITE_CMD (5 << 6)
301	#define EE_READ_CMD (6 << 6)
302	#define EE_ERASE_CMD (7 << 6)
303
304	static int eeget16(volatile unsigned int *ioaddr, int location)
305	{
306	int i;
307	unsigned short retval = 0;
308	int read_cmd = location \| EE_READ_CMD;
309
310	st_le32(ioaddr, EE_ENB & ~EE_CS);
311	st_le32(ioaddr, EE_ENB);
312
313	/* Shift the read command bits out. */
314	for (i = 10; i >= 0; i--) {
315	short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
316	st_le32(ioaddr, EE_ENB \| dataval);
317	delay_in_bus_cycles(200);
318	st_le32(ioaddr, EE_ENB \| dataval \| EE_SHIFT_CLK);
319	delay_in_bus_cycles(200);
320	st_le32(ioaddr, EE_ENB \| dataval); /* Finish EEPROM a clock tick. */
321	delay_in_bus_cycles(200);
322	}
323	st_le32(ioaddr, EE_ENB);
324
325	for (i = 16; i > 0; i--) {
326	st_le32(ioaddr, EE_ENB \| EE_SHIFT_CLK);
327	delay_in_bus_cycles(200);
328	retval = (retval << 1) \| ((ld_le32(ioaddr) & EE_DATA_READ) ? 1 : 0);
329	st_le32(ioaddr, EE_ENB);
330	delay_in_bus_cycles(200);
331	}
332
333	/* Terminate the EEPROM access. */
334	st_le32(ioaddr, EE_ENB & ~EE_CS);
335	return ( ((retval<<8)&0xff00) \| ((retval>>8)&0xff) );
336	}
337
338	/*
339	* Initialize the ethernet hardware
340	*/
341	static void
342	dec21140Enet_initialize_hardware (struct dec21140_softc *sc)
343	{
344	rtems_status_code st;
345	volatile unsigned int *tbase;
346	union {char c[64]; unsigned short s[32];} rombuf;
347	int i;
348	volatile unsigned char cp, setup_frm, *eaddrs;
349	volatile unsigned char *buffer;
350	volatile struct MD *rmd;
351
352	tbase = sc->base;
353
354	/*
355	* WARNING : First write in CSR6
356	* Then Reset the chip ( 1 in CSR0)
357	*/
358	st_le32( (tbase+memCSR6), CSR6_INIT);
359	st_le32( (tbase+memCSR0), RESET_CHIP);
360	delay_in_bus_cycles(200);
361
362	/*
363	* Init CSR0
364	*/
365	st_le32( (tbase+memCSR0), CSR0_MODE);
366
367	/* csr12_val = ld_le32( (tbase+memCSR8) );*/
368
369	for (i=0; i<32; i++){
370	rombuf.s[i] = eeget16(tbase+memCSR9, i);
371	}
372	memcpy (sc->arpcom.ac_enaddr, rombuf.c+20, ETHER_ADDR_LEN);
373
374	#ifdef DEC_DEBUG
375	printk("DC21140 %x:%x:%x:%x:%x:%x IRQ %d IO %x M %x .........\n",
376	sc->arpcom.ac_enaddr[0], sc->arpcom.ac_enaddr[1],
377	sc->arpcom.ac_enaddr[2], sc->arpcom.ac_enaddr[3],
378	sc->arpcom.ac_enaddr[4], sc->arpcom.ac_enaddr[5],
379	sc->irqInfo.name, sc->port, (unsigned) sc->base);
380	#endif
381
382	/*
383	* Init RX ring
384	*/
385	cp = (volatile unsigned char )malloc(((NRXBUFS+NTXBUFS)sizeof(struct MD))
386	+ (NTXBUFS*RBUF_SIZE)
387	+ CPU_CACHE_ALIGNMENT_FOR_BUFFER);
388	sc->bufferBase = cp;
389	cp += (CPU_CACHE_ALIGNMENT_FOR_BUFFER - (int)cp)
390	& (CPU_CACHE_ALIGNMENT_FOR_BUFFER - 1);
391	#if defined(__i386)
392	#ifdef PCI_BRIDGE_DOES_NOT_ENSURE_CACHE_COHERENCY_FOR_DMA
393	if (_CPU_is_paging_enabled())
394	_CPU_change_memory_mapping_attribute
395	(NULL, cp,
396	((NRXBUFS+NTXBUFS)*sizeof(struct MD))
397	+ (NTXBUFS*RBUF_SIZE),
398	PTE_CACHE_DISABLE \| PTE_WRITABLE);
399	#endif
400	#endif
401	rmd = (volatile struct MD*)cp;
402	sc->MDbase = rmd;
403	buffer = cp + ((NRXBUFS+NTXBUFS)*sizeof(struct MD));
404	st_le32( (tbase+memCSR3), (long)(phys_to_bus((long)(sc->MDbase))));
405	for (i=0 ; i<NRXBUFS; i++){
406	struct mbuf *m;
407
408	/* allocate an mbuf for each receive descriptor */
409	MGETHDR (m, M_WAIT, MT_DATA);
410	MCLGET (m, M_WAIT);
411	m->m_pkthdr.rcvif = &sc->arpcom.ac_if;
412	rmd->m = m;
413
414	rmd->buf2 = phys_to_bus(rmd+1);
415	rmd->buf1 = phys_to_bus(mtod(m, void *));
416	rmd->counts = 0xfdc00000 \| (RBUF_SIZE);
417	rmd->status = 0x80000000;
418	rmd->next = rmd + 1;
419	rmd++;
420	}
421	/*
422	* mark last RX buffer.
423	*/
424	sc->MDbase [NRXBUFS-1].counts = 0xfec00000 \| (RBUF_SIZE);
425	sc->MDbase [NRXBUFS-1].next = sc->MDbase;
426
427	/*
428	* Init TX ring
429	*/
430	st_le32( (tbase+memCSR4), (long)(phys_to_bus((long)(rmd))) );
431	for (i=0 ; i<NTXBUFS; i++){
432	(rmd+i)->buf2 = phys_to_bus(rmd+i+1);
433	(rmd+i)->buf1 = phys_to_bus(buffer + (i*RBUF_SIZE));
434	(rmd+i)->counts = 0x01000000;
435	(rmd+i)->status = 0x0;
436	(rmd+i)->next = rmd+i+1;
437	(rmd+i)->m = 0;
438	}
439
440	/*
441	* mark last TX buffer.
442	*/
443	(rmd+NTXBUFS-1)->buf2 = phys_to_bus(rmd);
444	(rmd+NTXBUFS-1)->next = rmd;
445
446	/*
447	* Set up interrupts
448	*/
449	sc->irqInfo.hdl = (rtems_irq_hdl)dec21140Enet_interrupt_handler;
450	sc->irqInfo.on = nopOn;
451	sc->irqInfo.off = nopOn;
452	sc->irqInfo.isOn = dec21140IsOn;
453	st = BSP_install_rtems_irq_handler (&sc->irqInfo);
454	if (!st)
455	rtems_panic ("Can't attach DEC21140 interrupt handler for irq %d\n",
456	sc->irqInfo.name);
457
458	st_le32( (tbase+memCSR7), NO_IT);
459
460	/*
461	* Build setup frame
462	*/
463	setup_frm = (volatile unsigned char *)(bus_to_phys(rmd->buf1));
464	eaddrs = (char *)(sc->arpcom.ac_enaddr);
465	/* Fill the buffer with our physical address. */
466	for (i = 1; i < 16; i++) {
467	*setup_frm++ = eaddrs[0];
468	*setup_frm++ = eaddrs[1];
469	*setup_frm++ = eaddrs[0];
470	*setup_frm++ = eaddrs[1];
471	*setup_frm++ = eaddrs[2];
472	*setup_frm++ = eaddrs[3];
473	*setup_frm++ = eaddrs[2];
474	*setup_frm++ = eaddrs[3];
475	*setup_frm++ = eaddrs[4];
476	*setup_frm++ = eaddrs[5];
477	*setup_frm++ = eaddrs[4];
478	*setup_frm++ = eaddrs[5];
479	}
480	/* Add the broadcast address when doing perfect filtering */
481	memset((void*) setup_frm, 0xff, 12);
482	rmd->counts = 0x09000000 \| 192 ;
483	rmd->status = 0x80000000;
484	st_le32( (tbase+memCSR6), CSR6_INIT \| CSR6_TX);
485	st_le32( (tbase+memCSR1), 1);
486	while (rmd->status != 0x7fffffff);
487	rmd->counts = 0x01000000;
488	sc->TxMD = rmd+1;
489
490	/*
491	* Enable RX and TX
492	*/
493	st_le32( (tbase+memCSR5), IT_SETUP);
494	st_le32( (tbase+memCSR7), IT_SETUP);
495	st_le32( (unsigned int*)(tbase+memCSR6), CSR6_INIT \| CSR6_TXRX);
496
497	}
498
499	static void
500	dec21140_rxDaemon (void *arg)
501	{
502	volatile unsigned int *tbase;
503	struct ether_header *eh;
504	struct dec21140_softc dp = (struct dec21140_softc )&dec21140_softc[0];
505	struct ifnet *ifp = &dp->arpcom.ac_if;
506	struct mbuf *m;
507	volatile struct MD *rmd;
508	unsigned int len;
509	rtems_event_set events;
510
511	tbase = dec21140_softc[0].base ;
512	rmd = dec21140_softc[0].MDbase;
513
514	for (;;){
515
516	rtems_bsdnet_event_receive (INTERRUPT_EVENT,
517	RTEMS_WAIT\|RTEMS_EVENT_ANY,
518	RTEMS_NO_TIMEOUT,
519	&events);
520
521	while((rmd->status & 0x80000000) == 0){
522	/* pass on the packet in the mbuf */
523	len = (rmd->status >> 16) & 0x7ff;
524	m = (struct mbuf *)(rmd->m);
525	m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header);
526	eh = mtod (m, struct ether_header *);
527	m->m_data += sizeof(struct ether_header);
528	ether_input (ifp, eh, m);
529
530	/* get a new mbuf for the 21140 */
531	MGETHDR (m, M_WAIT, MT_DATA);
532	MCLGET (m, M_WAIT);
533	m->m_pkthdr.rcvif = ifp;
534	rmd->m = m;
535	rmd->buf1 = phys_to_bus(mtod(m, void *));
536
537	rmd->status = 0x80000000;
538
539	rmd=rmd->next;
540	}
541	}
542	}
543
544	static void
545	sendpacket (struct ifnet ifp, struct mbuf m)
546	{
547	struct dec21140_softc *dp = ifp->if_softc;
548	volatile struct MD *tmd;
549	volatile unsigned char *temp;
550	struct mbuf *n;
551	unsigned int len;
552	volatile unsigned int *tbase;
553
554	tbase = dp->base;
555	/*
556	* Waiting for Transmitter ready
557	*/
558	tmd = dec21140_softc[0].TxMD;
559	n = m;
560
561	while ((tmd->status & 0x80000000) != 0){
562	tmd=tmd->next;
563	}
564
565	len = 0;
566	temp = (volatile unsigned char *)(bus_to_phys(tmd->buf1));
567
568	for (;;){
569	len += m->m_len;
570	memcpy((void) temp, (char )m->m_data, m->m_len);
571	temp += m->m_len ;
572	if ((m = m->m_next) == NULL)
573	break;
574	}
575
576	if (len < ET_MINLEN) len = ET_MINLEN;
577	tmd->counts = 0xe1000000 \| (len & 0x7ff);
578	tmd->status = 0x80000000;
579
580	st_le32( (tbase+memCSR1), 0x1);
581
582	m_freem(n);
583	dec21140_softc[0].TxMD = tmd->next;
584	}
585
586	/*
587	* Driver transmit daemon
588	*/
589	void
590	dec21140_txDaemon (void *arg)
591	{
592	struct dec21140_softc sc = (struct dec21140_softc )arg;
593	struct ifnet *ifp = &sc->arpcom.ac_if;
594	struct mbuf *m;
595	rtems_event_set events;
596
597	for (;;) {
598	/*
599	* Wait for packet
600	*/
601
602	rtems_bsdnet_event_receive (START_TRANSMIT_EVENT, RTEMS_EVENT_ANY \| RTEMS_WAIT, RTEMS_NO_TIMEOUT, &events);
603
604	/*
605	* Send packets till queue is empty
606	*/
607	for (;;) {
608	/*
609	* Get the next mbuf chain to transmit.
610	*/
611	IF_DEQUEUE(&ifp->if_snd, m);
612	if (!m)
613	break;
614	sendpacket (ifp, m);
615	}
616	ifp->if_flags &= ~IFF_OACTIVE;
617	}
618	}
619
620
621	static void
622	dec21140_start (struct ifnet *ifp)
623	{
624	struct dec21140_softc *sc = ifp->if_softc;
625
626	rtems_event_send (sc->txDaemonTid, START_TRANSMIT_EVENT);
627	ifp->if_flags \|= IFF_OACTIVE;
628	}
629
630	/*
631	* Initialize and start the device
632	*/
633	static void
634	dec21140_init (void *arg)
635	{
636	struct dec21140_softc *sc = arg;
637	struct ifnet *ifp = &sc->arpcom.ac_if;
638
639	if (sc->txDaemonTid == 0) {
640
641	/*
642	* Set up DEC21140 hardware
643	*/
644	dec21140Enet_initialize_hardware (sc);
645
646	/*
647	* Start driver tasks
648	*/
649	sc->rxDaemonTid = rtems_bsdnet_newproc ("DCrx", 4096,
650	dec21140_rxDaemon, sc);
651	sc->txDaemonTid = rtems_bsdnet_newproc ("DCtx", 4096,
652	dec21140_txDaemon, sc);
653	}
654
655	/*
656	* Tell the world that we're running.
657	*/
658	ifp->if_flags \|= IFF_RUNNING;
659
660	}
661
662	/*
663	* Stop the device
664	*/
665	static void
666	dec21140_stop (struct dec21140_softc *sc)
667	{
668	volatile unsigned int *tbase;
669	struct ifnet *ifp = &sc->arpcom.ac_if;
670
671	ifp->if_flags &= ~IFF_RUNNING;
672
673	/*
674	* Stop the transmitter
675	*/
676	tbase=dec21140_softc[0].base ;
677	st_le32( (tbase+memCSR7), NO_IT);
678	st_le32( (tbase+memCSR6), CSR6_INIT);
679	free((void*)sc->bufferBase);
680	}
681
682
683	/*
684	* Show interface statistics
685	*/
686	static void
687	dec21140_stats (struct dec21140_softc *sc)
688	{
689	printf (" Rx Interrupts:%-8lu", sc->rxInterrupts);
690	printf (" Not First:%-8lu", sc->rxNotFirst);
691	printf (" Not Last:%-8lu\n", sc->rxNotLast);
692	printf (" Giant:%-8lu", sc->rxGiant);
693	printf (" Runt:%-8lu", sc->rxRunt);
694	printf (" Non-octet:%-8lu\n", sc->rxNonOctet);
695	printf (" Bad CRC:%-8lu", sc->rxBadCRC);
696	printf (" Overrun:%-8lu", sc->rxOverrun);
697	printf (" Collision:%-8lu\n", sc->rxCollision);
698
699	printf (" Tx Interrupts:%-8lu", sc->txInterrupts);
700	printf (" Deferred:%-8lu", sc->txDeferred);
701	printf (" Missed Hearbeat:%-8lu\n", sc->txHeartbeat);
702	printf (" No Carrier:%-8lu", sc->txLostCarrier);
703	printf ("Retransmit Limit:%-8lu", sc->txRetryLimit);
704	printf (" Late Collision:%-8lu\n", sc->txLateCollision);
705	printf (" Underrun:%-8lu", sc->txUnderrun);
706	printf (" Raw output wait:%-8lu\n", sc->txRawWait);
707	}
708
709	/*
710	* Driver ioctl handler
711	*/
712	static int
713	dec21140_ioctl (struct ifnet *ifp, int command, caddr_t data)
714	{
715	struct dec21140_softc *sc = ifp->if_softc;
716	int error = 0;
717
718	switch (command) {
719	case SIOCGIFADDR:
720	case SIOCSIFADDR:
721	ether_ioctl (ifp, command, data);
722	break;
723
724	case SIOCSIFFLAGS:
725	switch (ifp->if_flags & (IFF_UP \| IFF_RUNNING)) {
726	case IFF_RUNNING:
727	dec21140_stop (sc);
728	break;
729
730	case IFF_UP:
731	dec21140_init (sc);
732	break;
733
734	case IFF_UP \| IFF_RUNNING:
735	dec21140_stop (sc);
736	dec21140_init (sc);
737	break;
738
739	default:
740	break;
741	}
742	break;
743
744	case SIO_RTEMS_SHOW_STATS:
745	dec21140_stats (sc);
746	break;
747
748	/*
749	* FIXME: All sorts of multicast commands need to be added here!
750	*/
751	default:
752	error = EINVAL;
753	break;
754	}
755
756	return error;
757	}
758
759	/*
760	* Attach an DEC21140 driver to the system
761	*/
762	int
763	rtems_dec21140_driver_attach (struct rtems_bsdnet_ifconfig *config)
764	{
765	struct dec21140_softc *sc;
766	struct ifnet *ifp;
767	int mtu;
768	int i;
769
770	/*
771	* First, find a DEC board
772	*/
773	#if defined(__i386)
774	int signature;
775	int value;
776	char interrupt;
777	int diag;
778
779	if (pcib_init() == PCIB_ERR_NOTPRESENT)
780	rtems_panic("PCI BIOS not found !!");
781
782	/*
783	* First, find a DEC board
784	*/
785	if ((diag = pcib_find_by_devid(PCI_VENDOR_ID_DEC,
786	PCI_DEVICE_ID_DEC_TULIP_FAST,
787	0,
788	&signature)) != PCIB_ERR_SUCCESS)
789	rtems_panic("DEC PCI board not found !! (%d)\n", diag);
790	else {
791	printk("DEC PCI Device found\n");
792	}
793	#endif
794	#if defined(__PPC)
795	unsigned char ucSlotNumber, ucFnNumber;
796	unsigned int ulDeviceID, lvalue, tmp;
797	unsigned char cvalue;
798
799	for(ucSlotNumber=0;ucSlotNumber<PCI_MAX_DEVICES;ucSlotNumber++) {
800	for(ucFnNumber=0;ucFnNumber<PCI_MAX_FUNCTIONS;ucFnNumber++) {
801	(void)pci_read_config_dword(0,
802	ucSlotNumber,
803	ucFnNumber,
804	PCI_VENDOR_ID,
805	&ulDeviceID);
806	if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) {
807	/*
808	* This slot is empty
809	*/
810	continue;
811	}
812	if (ulDeviceID == ((PCI_DEVICE_ID_DEC_TULIP_FAST<<16) + PCI_VENDOR_ID_DEC))
813	break;
814	}
815	if (ulDeviceID == ((PCI_DEVICE_ID_DEC_TULIP_FAST<<16) + PCI_VENDOR_ID_DEC)){
816	printk("DEC Adapter found !!\n");
817	break;
818	}
819	}
820
821	if(ulDeviceID==PCI_INVALID_VENDORDEVICEID)
822	rtems_panic("DEC PCI board not found !!\n");
823	#endif
824	/*
825	* Find a free driver
826	*/
827	for (i = 0 ; i < NDECDRIVER ; i++) {
828	sc = &dec21140_softc[i];
829	ifp = &sc->arpcom.ac_if;
830	if (ifp->if_softc == NULL)
831	break;
832	}
833	if (i >= NDECDRIVER) {
834	printk ("Too many DEC drivers.\n");
835	return 0;
836	}
837
838	/*
839	* Process options
840	*/
841	#if defined(__i386)
842	pcib_conf_read32(signature, 16, &value);
843	sc->port = value & ~IO_MASK;
844
845	pcib_conf_read32(signature, 20, &value);
846	if (_CPU_is_paging_enabled())
847	_CPU_map_phys_address(&(sc->base),
848	(void *)(value & ~MEM_MASK),
849	DEC_REGISTER_SIZE ,
850	PTE_CACHE_DISABLE \| PTE_WRITABLE);
851	else
852	sc->base = (unsigned int *)(value & ~MEM_MASK);
853
854	pcib_conf_read8(signature, 60, &interrupt);
855	sc->irqInfo.name = (rtems_irq_symbolic_name)interrupt;
856	#endif
857	#if defined(__PPC)
858	(void)pci_read_config_dword(0,
859	ucSlotNumber,
860	ucFnNumber,
861	PCI_BASE_ADDRESS_0,
862	&lvalue);
863
864	sc->port = lvalue & (unsigned int)(~IO_MASK);
865
866	(void)pci_read_config_dword(0,
867	ucSlotNumber,
868	ucFnNumber,
869	PCI_BASE_ADDRESS_1 ,
870	&lvalue);
871
872
873	tmp = (unsigned int)(lvalue & (unsigned int)(~MEM_MASK))
874	+ (unsigned int)PREP_ISA_MEM_BASE;
875	sc->base = (unsigned int *)(tmp);
876
877	(void)pci_read_config_byte(0,
878	ucSlotNumber,
879	ucFnNumber,
880	PCI_INTERRUPT_LINE,
881	&cvalue);
882	sc->irqInfo.name = (rtems_irq_symbolic_name)cvalue;
883	#endif
884	if (config->hardware_address) {
885	memcpy (sc->arpcom.ac_enaddr, config->hardware_address,
886	ETHER_ADDR_LEN);
887	}
888	else {
889	memset (sc->arpcom.ac_enaddr, 0x08,ETHER_ADDR_LEN);
890	}
891	if (config->mtu)
892	mtu = config->mtu;
893	else
894	mtu = ETHERMTU;
895
896	sc->acceptBroadcast = !config->ignore_broadcast;
897
898	/*
899	* Set up network interface values
900	*/
901	ifp->if_softc = sc;
902	ifp->if_unit = i + 1;
903	ifp->if_name = "dc";
904	ifp->if_mtu = mtu;
905	ifp->if_init = dec21140_init;
906	ifp->if_ioctl = dec21140_ioctl;
907	ifp->if_start = dec21140_start;
908	ifp->if_output = ether_output;
909	ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX;
910	if (ifp->if_snd.ifq_maxlen == 0)
911	ifp->if_snd.ifq_maxlen = ifqmaxlen;
912
913	/*
914	* Attach the interface
915	*/
916	if_attach (ifp);
917	ether_ifattach (ifp);
918
919	return 1;
920	};
921	#endif /* DEC21140_SUPPORTED */
922

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