1 | /* |
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2 | * RTEMS driver for TULIP based Ethernet Controller |
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3 | * |
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4 | * Copyright (C) 1999 Emmanuel Raguet. raguet@crf.canon.fr |
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5 | * |
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6 | * The license and distribution terms for this file may be |
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7 | * found in found in the file LICENSE in this distribution or at |
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8 | * http://www.rtems.com/license/LICENSE. |
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9 | * |
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10 | * $Id$ |
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11 | * |
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12 | * ------------------------------------------------------------------------ |
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13 | * [22.05.2000,StWi/CWA] added support for the DEC/Intel 21143 chip |
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14 | * |
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15 | * Thanks go to Andrew Klossner who provided the vital information about the |
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16 | * Intel 21143 chip. FWIW: The 21143 additions to this driver were initially |
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17 | * tested with a PC386 BSP using a Kingston KNE100TX with 21143PD chip. |
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18 | * |
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19 | * The driver will automatically detect whether there is a 21140 or 21143 |
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20 | * network card in the system and activate support accordingly. It will |
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21 | * look for the 21140 first. If the 21140 is not found the driver will |
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22 | * look for the 21143. |
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23 | * |
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24 | * 2004-11-10, Joel/Richard - 21143 support works on MVME2100. |
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25 | * ------------------------------------------------------------------------ |
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26 | * |
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27 | * 2003-03-13, Greg Menke, gregory.menke@gsfc.nasa.gov |
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28 | * |
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29 | * Added support for up to 8 units (which is an arbitrary limit now), |
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30 | * consolidating their support into a single pair of rx/tx daemons and a |
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31 | * single ISR for all vectors servicing the DEC units. The driver now |
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32 | * simply uses whatever INTERRUPT_LINE the card supplies, requiring it |
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33 | * be configured either by the boot monitor or bspstart() hackery. |
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34 | * Tested on a MCP750 PPC based system with 2 DEC21140 boards. |
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35 | * |
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36 | * Also fixed a few bugs related to board configuration, start and stop. |
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37 | * |
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38 | */ |
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39 | |
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40 | #include <rtems.h> |
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41 | |
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42 | /* |
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43 | * This driver only supports architectures with the new style |
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44 | * exception processing. The following checks try to keep this |
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45 | * from being compiled on systems which can't support this driver. |
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46 | */ |
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47 | |
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48 | #if defined(__i386__) |
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49 | #define DEC21140_SUPPORTED |
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50 | #endif |
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51 | #if defined(__PPC__) && (defined(mpc604) || defined(mpc750) || defined(mpc603e)) |
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52 | #define DEC21140_SUPPORTED |
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53 | #endif |
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54 | |
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55 | #if defined(DEC21140_SUPPORTED) |
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56 | #include <bsp.h> |
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57 | #include <rtems/pci.h> |
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58 | |
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59 | #if defined(__PPC__) |
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60 | #include <libcpu/byteorder.h> |
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61 | #include <libcpu/io.h> |
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62 | #endif |
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63 | |
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64 | #if defined(__i386__) |
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65 | #include <libcpu/byteorder.h> |
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66 | #endif |
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67 | |
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68 | #include <stdlib.h> |
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69 | #include <stdio.h> |
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70 | #include <stdarg.h> |
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71 | #include <string.h> |
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72 | #include <errno.h> |
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73 | #include <rtems/error.h> |
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74 | #include <rtems/bspIo.h> |
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75 | #include <rtems/rtems_bsdnet.h> |
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76 | |
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77 | #include <sys/param.h> |
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78 | #include <sys/mbuf.h> |
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79 | |
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80 | #include <sys/socket.h> |
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81 | #include <sys/sockio.h> |
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82 | #include <net/if.h> |
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83 | #include <netinet/in.h> |
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84 | #include <netinet/if_ether.h> |
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85 | |
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86 | #include <bsp/irq.h> |
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87 | |
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88 | #ifdef malloc |
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89 | #undef malloc |
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90 | #endif |
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91 | #ifdef free |
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92 | #undef free |
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93 | #endif |
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94 | |
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95 | #define DEC_DEBUG |
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96 | |
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97 | /* note: the 21143 isn't really a DEC, it's an Intel chip */ |
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98 | #define PCI_INVALID_VENDORDEVICEID 0xffffffff |
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99 | #define PCI_VENDOR_ID_DEC 0x1011 |
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100 | #define PCI_DEVICE_ID_DEC_21140 0x0009 |
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101 | #define PCI_DEVICE_ID_DEC_21143 0x0019 |
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102 | |
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103 | #define DRIVER_PREFIX "dc" |
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104 | |
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105 | #define IO_MASK 0x3 |
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106 | #define MEM_MASK 0xF |
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107 | |
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108 | /* command and status registers, 32-bit access, only if IO-ACCESS */ |
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109 | #define ioCSR0 0x00 /* bus mode register */ |
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110 | #define ioCSR1 0x08 /* transmit poll demand */ |
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111 | #define ioCSR2 0x10 /* receive poll demand */ |
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112 | #define ioCSR3 0x18 /* receive list base address */ |
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113 | #define ioCSR4 0x20 /* transmit list base address */ |
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114 | #define ioCSR5 0x28 /* status register */ |
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115 | #define ioCSR6 0x30 /* operation mode register */ |
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116 | #define ioCSR7 0x38 /* interrupt mask register */ |
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117 | #define ioCSR8 0x40 /* missed frame counter */ |
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118 | #define ioCSR9 0x48 /* Ethernet ROM register */ |
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119 | #define ioCSR10 0x50 /* reserved */ |
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120 | #define ioCSR11 0x58 /* full-duplex register */ |
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121 | #define ioCSR12 0x60 /* SIA status register */ |
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122 | #define ioCSR13 0x68 |
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123 | #define ioCSR14 0x70 |
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124 | #define ioCSR15 0x78 /* SIA general register */ |
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125 | |
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126 | /* command and status registers, 32-bit access, only if MEMORY-ACCESS */ |
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127 | #define memCSR0 0x00 /* bus mode register */ |
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128 | #define memCSR1 0x02 /* transmit poll demand */ |
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129 | #define memCSR2 0x04 /* receive poll demand */ |
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130 | #define memCSR3 0x06 /* receive list base address */ |
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131 | #define memCSR4 0x08 /* transmit list base address */ |
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132 | #define memCSR5 0x0A /* status register */ |
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133 | #define memCSR6 0x0C /* operation mode register */ |
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134 | #define memCSR7 0x0E /* interrupt mask register */ |
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135 | #define memCSR8 0x10 /* missed frame counter */ |
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136 | #define memCSR9 0x12 /* Ethernet ROM register */ |
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137 | #define memCSR10 0x14 /* reserved */ |
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138 | #define memCSR11 0x16 /* full-duplex register */ |
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139 | #define memCSR12 0x18 /* SIA status register */ |
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140 | #define memCSR13 0x1A |
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141 | #define memCSR14 0x1C |
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142 | #define memCSR15 0x1E /* SIA general register */ |
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143 | |
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144 | #define DEC_REGISTER_SIZE 0x100 /* to reserve virtual memory */ |
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145 | |
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146 | |
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147 | |
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148 | |
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149 | #define RESET_CHIP 0x00000001 |
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150 | #if defined(__PPC__) |
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151 | #define CSR0_MODE 0x0030e002 /* 01b08000 */ |
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152 | #else |
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153 | #define CSR0_MODE 0x0020e002 /* 01b08000 */ |
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154 | #endif |
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155 | #define ROM_ADDRESS 0x00004800 |
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156 | #define CSR6_INIT 0x022cc000 /* 022c0000 020c0000 */ |
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157 | #define CSR6_TX 0x00002000 |
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158 | #define CSR6_TXRX 0x00002002 |
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159 | #define IT_SETUP 0x000100c0 /* 000100e0 */ |
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160 | #define CLEAR_IT 0xFFFFFFFF |
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161 | #define NO_IT 0x00000000 |
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162 | |
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163 | /* message descriptor entry */ |
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164 | struct MD { |
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165 | /* used by hardware */ |
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166 | volatile uint32_t status; |
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167 | volatile uint32_t counts; |
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168 | volatile uint32_t buf1, buf2; |
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169 | /* used by software */ |
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170 | volatile struct mbuf *m; |
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171 | volatile struct MD *next; |
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172 | } __attribute__ ((packed)); |
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173 | |
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174 | /* |
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175 | ** These buffers allocated for each unit, so ensure |
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176 | ** |
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177 | ** rtems_bsdnet_config.mbuf_bytecount |
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178 | ** rtems_bsdnet_config.mbuf_cluster_bytecount |
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179 | ** |
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180 | ** are adequately sized to provide enough clusters and mbufs for all the |
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181 | ** units. The default bsdnet configuration is sufficient for one dec |
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182 | ** unit, but will be nearing exhaustion with 2 or more. Although a |
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183 | ** little expensive in memory, the following configuration should |
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184 | ** eliminate all mbuf/cluster issues; |
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185 | ** |
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186 | ** rtems_bsdnet_config.mbuf_bytecount = 128*1024; |
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187 | ** rtems_bsdnet_config.mbuf_cluster_bytecount = 256*1024; |
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188 | */ |
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189 | |
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190 | #define NRXBUFS 16 /* number of receive buffers */ |
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191 | #define NTXBUFS 16 /* number of transmit buffers */ |
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192 | |
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193 | /* |
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194 | * Number of DEC boards supported by this driver |
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195 | */ |
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196 | #define NDECDRIVER 8 |
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197 | |
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198 | /* |
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199 | * Receive buffer size -- Allow for a full ethernet packet including CRC |
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200 | */ |
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201 | #define RBUF_SIZE 1536 |
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202 | |
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203 | #define ET_MINLEN 60 /* minimum message length */ |
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204 | |
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205 | /* |
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206 | ** Events, one per unit. The event is sent to the rx task from the isr |
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207 | ** or from the stack to the tx task whenever a unit needs service. The |
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208 | ** rx/tx tasks identify the requesting unit(s) by their particular |
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209 | ** events so only requesting units are serviced. |
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210 | */ |
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211 | |
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212 | static rtems_event_set unit_signals[NDECDRIVER]= { RTEMS_EVENT_1, |
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213 | RTEMS_EVENT_2, |
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214 | RTEMS_EVENT_3, |
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215 | RTEMS_EVENT_4, |
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216 | RTEMS_EVENT_5, |
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217 | RTEMS_EVENT_6, |
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218 | RTEMS_EVENT_7, |
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219 | RTEMS_EVENT_8 }; |
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220 | |
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221 | #if defined(__PPC__) |
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222 | #define phys_to_bus(address) ((unsigned int)((address)) + PCI_DRAM_OFFSET) |
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223 | #define bus_to_phys(address) ((unsigned int)((address)) - PCI_DRAM_OFFSET) |
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224 | #define CPU_CACHE_ALIGNMENT_FOR_BUFFER PPC_CACHE_ALIGNMENT |
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225 | #else |
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226 | extern void Wait_X_ms( unsigned int timeToWait ); |
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227 | #define phys_to_bus(address) ((unsigned int) ((address))) |
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228 | #define bus_to_phys(address) ((unsigned int) ((address))) |
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229 | #define rtems_bsp_delay_in_bus_cycles(cycle) Wait_X_ms( cycle/100 ) |
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230 | #define CPU_CACHE_ALIGNMENT_FOR_BUFFER PG_SIZE |
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231 | #endif |
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232 | |
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233 | #if (MCLBYTES < RBUF_SIZE) |
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234 | # error "Driver must have MCLBYTES > RBUF_SIZE" |
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235 | #endif |
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236 | |
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237 | /* |
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238 | * Per-device data |
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239 | */ |
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240 | struct dec21140_softc { |
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241 | |
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242 | struct arpcom arpcom; |
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243 | |
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244 | rtems_irq_connect_data irqInfo; |
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245 | rtems_event_set ioevent; |
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246 | |
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247 | int numRxbuffers, numTxbuffers; |
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248 | |
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249 | volatile struct MD *MDbase; |
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250 | volatile struct MD *nextRxMD; |
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251 | volatile unsigned char *bufferBase; |
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252 | int acceptBroadcast; |
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253 | |
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254 | volatile struct MD *TxMD; |
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255 | volatile struct MD *SentTxMD; |
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256 | int PendingTxCount; |
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257 | int TxSuspended; |
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258 | |
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259 | unsigned int port; |
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260 | volatile unsigned int *base; |
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261 | |
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262 | /* |
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263 | * Statistics |
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264 | */ |
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265 | unsigned long rxInterrupts; |
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266 | unsigned long rxNotFirst; |
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267 | unsigned long rxNotLast; |
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268 | unsigned long rxGiant; |
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269 | unsigned long rxNonOctet; |
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270 | unsigned long rxRunt; |
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271 | unsigned long rxBadCRC; |
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272 | unsigned long rxOverrun; |
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273 | unsigned long rxCollision; |
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274 | |
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275 | unsigned long txInterrupts; |
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276 | unsigned long txDeferred; |
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277 | unsigned long txHeartbeat; |
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278 | unsigned long txLateCollision; |
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279 | unsigned long txRetryLimit; |
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280 | unsigned long txUnderrun; |
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281 | unsigned long txLostCarrier; |
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282 | unsigned long txRawWait; |
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283 | }; |
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284 | |
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285 | static struct dec21140_softc dec21140_softc[NDECDRIVER]; |
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286 | static rtems_id rxDaemonTid; |
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287 | static rtems_id txDaemonTid; |
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288 | |
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289 | /* |
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290 | * This routine reads a word (16 bits) from the serial EEPROM. |
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291 | */ |
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292 | /* EEPROM_Ctrl bits. */ |
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293 | #define EE_SHIFT_CLK 0x02 /* EEPROM shift clock. */ |
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294 | #define EE_CS 0x01 /* EEPROM chip select. */ |
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295 | #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ |
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296 | #define EE_WRITE_0 0x01 |
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297 | #define EE_WRITE_1 0x05 |
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298 | #define EE_DATA_READ 0x08 /* EEPROM chip data out. */ |
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299 | #define EE_ENB (0x4800 | EE_CS) |
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300 | |
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301 | /* The EEPROM commands include the alway-set leading bit. */ |
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302 | #define EE_WRITE_CMD (5 << 6) |
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303 | #define EE_READ_CMD (6 << 6) |
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304 | #define EE_ERASE_CMD (7 << 6) |
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305 | |
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306 | static int eeget16(volatile unsigned int *ioaddr, int location) |
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307 | { |
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308 | int i; |
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309 | unsigned short retval = 0; |
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310 | int read_cmd = location | EE_READ_CMD; |
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311 | |
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312 | st_le32(ioaddr, EE_ENB & ~EE_CS); |
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313 | st_le32(ioaddr, EE_ENB); |
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314 | |
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315 | /* Shift the read command bits out. */ |
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316 | for (i = 10; i >= 0; i--) { |
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317 | short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; |
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318 | st_le32(ioaddr, EE_ENB | dataval); |
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319 | rtems_bsp_delay_in_bus_cycles(200); |
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320 | st_le32(ioaddr, EE_ENB | dataval | EE_SHIFT_CLK); |
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321 | rtems_bsp_delay_in_bus_cycles(200); |
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322 | st_le32(ioaddr, EE_ENB | dataval); /* Finish EEPROM a clock tick. */ |
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323 | rtems_bsp_delay_in_bus_cycles(200); |
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324 | } |
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325 | st_le32(ioaddr, EE_ENB); |
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326 | |
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327 | for (i = 16; i > 0; i--) { |
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328 | st_le32(ioaddr, EE_ENB | EE_SHIFT_CLK); |
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329 | rtems_bsp_delay_in_bus_cycles(200); |
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330 | retval = (retval << 1) | ((ld_le32(ioaddr) & EE_DATA_READ) ? 1 : 0); |
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331 | st_le32(ioaddr, EE_ENB); |
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332 | rtems_bsp_delay_in_bus_cycles(200); |
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333 | } |
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334 | |
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335 | /* Terminate the EEPROM access. */ |
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336 | st_le32(ioaddr, EE_ENB & ~EE_CS); |
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337 | return ( ((retval<<8)&0xff00) | ((retval>>8)&0xff) ); |
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338 | } |
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339 | |
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340 | static void no_op(const rtems_irq_connect_data* irq) |
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341 | { |
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342 | return; |
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343 | } |
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344 | |
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345 | static int dec21140IsOn(const rtems_irq_connect_data* irq) |
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346 | { |
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347 | return BSP_irq_enabled_at_i8259s (irq->name); |
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348 | } |
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349 | |
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350 | /* |
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351 | * DEC21140 interrupt handler |
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352 | */ |
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353 | static rtems_isr |
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354 | dec21140Enet_interrupt_handler ( struct dec21140_softc *sc ) |
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355 | { |
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356 | volatile uint32_t *tbase; |
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357 | uint32_t status; |
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358 | |
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359 | tbase = (uint32_t*)(sc->base); |
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360 | |
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361 | /* |
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362 | * Read status |
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363 | */ |
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364 | status = ld_le32(tbase+memCSR5); |
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365 | st_le32((tbase+memCSR5), status); |
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366 | |
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367 | /* |
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368 | * Frame received? |
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369 | */ |
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370 | if( status & 0x000000c0 ) |
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371 | { |
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372 | sc->rxInterrupts++; |
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373 | rtems_event_send(rxDaemonTid, sc->ioevent); |
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374 | } |
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375 | } |
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376 | |
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377 | static rtems_isr |
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378 | dec21140Enet_interrupt_handler_entry() |
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379 | { |
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380 | int i; |
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381 | |
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382 | /* |
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383 | ** Check all the initialized dec units for interrupt service |
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384 | */ |
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385 | |
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386 | for(i=0; i< NDECDRIVER; i++ ) |
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387 | { |
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388 | if( dec21140_softc[i].base ) |
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389 | dec21140Enet_interrupt_handler( &dec21140_softc[i] ); |
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390 | } |
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391 | } |
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392 | |
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393 | /* |
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394 | * Initialize the ethernet hardware |
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395 | */ |
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396 | static void |
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397 | dec21140Enet_initialize_hardware (struct dec21140_softc *sc) |
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398 | { |
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399 | int i,st; |
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400 | volatile unsigned int *tbase; |
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401 | volatile unsigned char *cp, *setup_frm, *eaddrs; |
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402 | volatile unsigned char *buffer; |
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403 | volatile struct MD *rmd; |
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404 | |
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405 | |
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406 | #ifdef DEC_DEBUG |
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407 | printk("dec2114x : %02x:%02x:%02x:%02x:%02x:%02x name '%s%d', io %x, mem %x, int %d\n", |
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408 | sc->arpcom.ac_enaddr[0], sc->arpcom.ac_enaddr[1], |
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409 | sc->arpcom.ac_enaddr[2], sc->arpcom.ac_enaddr[3], |
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410 | sc->arpcom.ac_enaddr[4], sc->arpcom.ac_enaddr[5], |
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411 | sc->arpcom.ac_if.if_name, sc->arpcom.ac_if.if_unit, |
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412 | sc->port, (unsigned) sc->base, sc->irqInfo.name ); |
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413 | #endif |
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414 | |
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415 | tbase = sc->base; |
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416 | |
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417 | /* |
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418 | * WARNING : First write in CSR6 |
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419 | * Then Reset the chip ( 1 in CSR0) |
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420 | */ |
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421 | st_le32( (tbase+memCSR6), CSR6_INIT); |
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422 | st_le32( (tbase+memCSR0), RESET_CHIP); |
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423 | rtems_bsp_delay_in_bus_cycles(200); |
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424 | |
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425 | st_le32( (tbase+memCSR7), NO_IT); |
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426 | |
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427 | /* |
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428 | * Init CSR0 |
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429 | */ |
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430 | st_le32( (tbase+memCSR0), CSR0_MODE); |
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431 | |
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432 | /* |
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433 | * Init RX ring |
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434 | */ |
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435 | cp = (volatile unsigned char *)malloc(((sc->numRxbuffers+sc->numTxbuffers)*sizeof(struct MD)) |
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436 | + (sc->numTxbuffers*RBUF_SIZE) |
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437 | + CPU_CACHE_ALIGNMENT_FOR_BUFFER); |
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438 | sc->bufferBase = cp; |
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439 | cp += (CPU_CACHE_ALIGNMENT_FOR_BUFFER - (int)cp) & (CPU_CACHE_ALIGNMENT_FOR_BUFFER - 1); |
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440 | #if defined(__i386__) |
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441 | #ifdef PCI_BRIDGE_DOES_NOT_ENSURE_CACHE_COHERENCY_FOR_DMA |
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442 | if (_CPU_is_paging_enabled()) |
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443 | _CPU_change_memory_mapping_attribute |
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444 | (NULL, cp, |
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445 | ((sc->numRxbuffers+sc->numTxbuffers)*sizeof(struct MD)) |
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446 | + (sc->numTxbuffers*RBUF_SIZE), |
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447 | PTE_CACHE_DISABLE | PTE_WRITABLE); |
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448 | #endif |
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449 | #endif |
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450 | rmd = (volatile struct MD*)cp; |
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451 | sc->MDbase = rmd; |
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452 | sc->nextRxMD = sc->MDbase; |
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453 | |
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454 | buffer = cp + ((sc->numRxbuffers+sc->numTxbuffers)*sizeof(struct MD)); |
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455 | st_le32( (tbase+memCSR3), (long)(phys_to_bus((long)(sc->MDbase)))); |
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456 | |
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457 | for (i=0 ; i<sc->numRxbuffers; i++) |
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458 | { |
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459 | struct mbuf *m; |
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460 | |
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461 | /* allocate an mbuf for each receive descriptor */ |
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462 | MGETHDR (m, M_WAIT, MT_DATA); |
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463 | MCLGET (m, M_WAIT); |
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464 | m->m_pkthdr.rcvif = &sc->arpcom.ac_if; |
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465 | rmd->m = m; |
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466 | |
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467 | rmd->buf2 = phys_to_bus(rmd+1); |
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468 | rmd->buf1 = phys_to_bus(mtod(m, void *)); |
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469 | rmd->status = 0x80000000; |
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470 | rmd->counts = 0xfdc00000 | (RBUF_SIZE); |
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471 | rmd->next = rmd+1; |
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472 | rmd++; |
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473 | } |
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474 | /* |
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475 | * mark last RX buffer. |
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476 | */ |
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477 | sc->MDbase [sc->numRxbuffers-1].buf2 = 0; |
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478 | sc->MDbase [sc->numRxbuffers-1].counts = 0xfec00000 | (RBUF_SIZE); |
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479 | sc->MDbase [sc->numRxbuffers-1].next = sc->MDbase; |
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480 | |
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481 | |
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482 | |
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483 | /* |
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484 | * Init TX ring |
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485 | */ |
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486 | st_le32( (tbase+memCSR4), (long)(phys_to_bus((long)(rmd))) ); |
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487 | for (i=0 ; i<sc->numTxbuffers; i++){ |
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488 | (rmd+i)->buf2 = phys_to_bus(rmd+i+1); |
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489 | (rmd+i)->buf1 = phys_to_bus(buffer + (i*RBUF_SIZE)); |
---|
490 | (rmd+i)->counts = 0x01000000; |
---|
491 | (rmd+i)->status = 0x0; |
---|
492 | (rmd+i)->next = rmd+i+1; |
---|
493 | (rmd+i)->m = 0; |
---|
494 | } |
---|
495 | |
---|
496 | /* |
---|
497 | * mark last TX buffer. |
---|
498 | */ |
---|
499 | (rmd+sc->numTxbuffers-1)->buf2 = phys_to_bus(rmd); |
---|
500 | (rmd+sc->numTxbuffers-1)->next = rmd; |
---|
501 | |
---|
502 | |
---|
503 | /* |
---|
504 | * Build setup frame |
---|
505 | */ |
---|
506 | setup_frm = (volatile unsigned char *)(bus_to_phys(rmd->buf1)); |
---|
507 | eaddrs = (unsigned char *)(sc->arpcom.ac_enaddr); |
---|
508 | /* Fill the buffer with our physical address. */ |
---|
509 | for (i = 1; i < 16; i++) { |
---|
510 | *setup_frm++ = eaddrs[0]; |
---|
511 | *setup_frm++ = eaddrs[1]; |
---|
512 | *setup_frm++ = eaddrs[0]; |
---|
513 | *setup_frm++ = eaddrs[1]; |
---|
514 | *setup_frm++ = eaddrs[2]; |
---|
515 | *setup_frm++ = eaddrs[3]; |
---|
516 | *setup_frm++ = eaddrs[2]; |
---|
517 | *setup_frm++ = eaddrs[3]; |
---|
518 | *setup_frm++ = eaddrs[4]; |
---|
519 | *setup_frm++ = eaddrs[5]; |
---|
520 | *setup_frm++ = eaddrs[4]; |
---|
521 | *setup_frm++ = eaddrs[5]; |
---|
522 | } |
---|
523 | |
---|
524 | /* Add the broadcast address when doing perfect filtering */ |
---|
525 | memset((void*) setup_frm, 0xff, 12); |
---|
526 | rmd->counts = 0x09000000 | 192 ; |
---|
527 | rmd->status = 0x80000000; |
---|
528 | st_le32( (tbase+memCSR6), CSR6_INIT | CSR6_TX); |
---|
529 | st_le32( (tbase+memCSR1), 1); |
---|
530 | |
---|
531 | while (rmd->status != 0x7fffffff); |
---|
532 | rmd->counts = 0x01000000; |
---|
533 | |
---|
534 | sc->TxMD = rmd+1; |
---|
535 | |
---|
536 | sc->irqInfo.hdl = (rtems_irq_hdl)dec21140Enet_interrupt_handler_entry; |
---|
537 | sc->irqInfo.on = no_op; |
---|
538 | sc->irqInfo.off = no_op; |
---|
539 | sc->irqInfo.isOn = dec21140IsOn; |
---|
540 | |
---|
541 | #ifdef DEC_DEBUG |
---|
542 | printk( "dec2114x: Installing IRQ %d\n", sc->irqInfo.name ); |
---|
543 | #endif |
---|
544 | #ifdef BSP_SHARED_HANDLER_SUPPORT |
---|
545 | st = BSP_install_rtems_shared_irq_handler( &sc->irqInfo ); |
---|
546 | #else |
---|
547 | st = BSP_install_rtems_irq_handler( &sc->irqInfo ); |
---|
548 | #endif |
---|
549 | |
---|
550 | if (!st) |
---|
551 | rtems_panic ("dec2114x : Interrupt name %d already in use\n", sc->irqInfo.name ); |
---|
552 | } |
---|
553 | |
---|
554 | static void |
---|
555 | dec21140_rxDaemon (void *arg) |
---|
556 | { |
---|
557 | volatile unsigned int *tbase; |
---|
558 | volatile struct MD *rmd; |
---|
559 | struct dec21140_softc *sc; |
---|
560 | struct ifnet *ifp; |
---|
561 | struct ether_header *eh; |
---|
562 | struct mbuf *m; |
---|
563 | unsigned int i,len; |
---|
564 | rtems_event_set events; |
---|
565 | |
---|
566 | for (;;) |
---|
567 | { |
---|
568 | |
---|
569 | rtems_bsdnet_event_receive( RTEMS_ALL_EVENTS, |
---|
570 | RTEMS_WAIT|RTEMS_EVENT_ANY, |
---|
571 | RTEMS_NO_TIMEOUT, |
---|
572 | &events); |
---|
573 | |
---|
574 | for(i=0; i< NDECDRIVER; i++ ) |
---|
575 | { |
---|
576 | sc = &dec21140_softc[i]; |
---|
577 | if( sc->base ) |
---|
578 | { |
---|
579 | if( events & sc->ioevent ) |
---|
580 | { |
---|
581 | ifp = &sc->arpcom.ac_if; |
---|
582 | tbase = sc->base; |
---|
583 | rmd = sc->nextRxMD; |
---|
584 | |
---|
585 | /* |
---|
586 | ** Read off all the packets we've received on this unit |
---|
587 | */ |
---|
588 | while((rmd->status & 0x80000000) == 0) |
---|
589 | { |
---|
590 | /* printk("unit %i rx\n", ifp->if_unit ); */ |
---|
591 | |
---|
592 | /* pass on the packet in the mbuf */ |
---|
593 | len = (rmd->status >> 16) & 0x7ff; |
---|
594 | m = (struct mbuf *)(rmd->m); |
---|
595 | m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header); |
---|
596 | eh = mtod (m, struct ether_header *); |
---|
597 | m->m_data += sizeof(struct ether_header); |
---|
598 | ether_input (ifp, eh, m); |
---|
599 | |
---|
600 | /* get a new mbuf for the 21140 */ |
---|
601 | MGETHDR (m, M_WAIT, MT_DATA); |
---|
602 | MCLGET (m, M_WAIT); |
---|
603 | m->m_pkthdr.rcvif = ifp; |
---|
604 | rmd->m = m; |
---|
605 | rmd->buf1 = phys_to_bus(mtod(m, void *)); |
---|
606 | |
---|
607 | /* mark the descriptor as ready to receive */ |
---|
608 | rmd->status = 0x80000000; |
---|
609 | |
---|
610 | rmd=rmd->next; |
---|
611 | } |
---|
612 | |
---|
613 | sc->nextRxMD = rmd; |
---|
614 | } |
---|
615 | } |
---|
616 | } |
---|
617 | |
---|
618 | } |
---|
619 | } |
---|
620 | |
---|
621 | static void |
---|
622 | sendpacket (struct ifnet *ifp, struct mbuf *m) |
---|
623 | { |
---|
624 | struct dec21140_softc *dp = ifp->if_softc; |
---|
625 | volatile struct MD *tmd; |
---|
626 | volatile unsigned char *temp; |
---|
627 | struct mbuf *n; |
---|
628 | unsigned int len; |
---|
629 | volatile unsigned int *tbase; |
---|
630 | |
---|
631 | tbase = dp->base; |
---|
632 | /* |
---|
633 | * Waiting for Transmitter ready |
---|
634 | */ |
---|
635 | |
---|
636 | tmd = dp->TxMD; |
---|
637 | n = m; |
---|
638 | |
---|
639 | while ((tmd->status & 0x80000000) != 0) |
---|
640 | { |
---|
641 | tmd=tmd->next; |
---|
642 | } |
---|
643 | |
---|
644 | len = 0; |
---|
645 | temp = (volatile unsigned char *)(bus_to_phys(tmd->buf1)); |
---|
646 | |
---|
647 | for (;;) |
---|
648 | { |
---|
649 | len += m->m_len; |
---|
650 | memcpy((void*) temp, (char *)m->m_data, m->m_len); |
---|
651 | temp += m->m_len ; |
---|
652 | if ((m = m->m_next) == NULL) |
---|
653 | break; |
---|
654 | } |
---|
655 | |
---|
656 | if (len < ET_MINLEN) len = ET_MINLEN; |
---|
657 | tmd->counts = 0xe1000000 | (len & 0x7ff); |
---|
658 | tmd->status = 0x80000000; |
---|
659 | |
---|
660 | st_le32( (tbase+memCSR1), 0x1); |
---|
661 | |
---|
662 | m_freem(n); |
---|
663 | |
---|
664 | dp->TxMD = tmd->next; |
---|
665 | } |
---|
666 | |
---|
667 | /* |
---|
668 | * Driver transmit daemon |
---|
669 | */ |
---|
670 | void |
---|
671 | dec21140_txDaemon (void *arg) |
---|
672 | { |
---|
673 | struct dec21140_softc *sc; |
---|
674 | struct ifnet *ifp; |
---|
675 | struct mbuf *m; |
---|
676 | int i; |
---|
677 | rtems_event_set events; |
---|
678 | |
---|
679 | for (;;) |
---|
680 | { |
---|
681 | /* |
---|
682 | * Wait for packets bound for any of the dec units |
---|
683 | */ |
---|
684 | rtems_bsdnet_event_receive( RTEMS_ALL_EVENTS, |
---|
685 | RTEMS_EVENT_ANY | RTEMS_WAIT, |
---|
686 | RTEMS_NO_TIMEOUT, &events); |
---|
687 | |
---|
688 | for(i=0; i< NDECDRIVER; i++ ) |
---|
689 | { |
---|
690 | sc = &dec21140_softc[i]; |
---|
691 | if( sc->base ) |
---|
692 | { |
---|
693 | if( events & sc->ioevent ) |
---|
694 | { |
---|
695 | ifp = &sc->arpcom.ac_if; |
---|
696 | |
---|
697 | /* |
---|
698 | * Send packets till queue is empty |
---|
699 | */ |
---|
700 | for(;;) |
---|
701 | { |
---|
702 | IF_DEQUEUE(&ifp->if_snd, m); |
---|
703 | if( !m ) break; |
---|
704 | /* printk("unit %i tx\n", ifp->if_unit ); */ |
---|
705 | sendpacket (ifp, m); |
---|
706 | } |
---|
707 | |
---|
708 | ifp->if_flags &= ~IFF_OACTIVE; |
---|
709 | } |
---|
710 | } |
---|
711 | } |
---|
712 | |
---|
713 | } |
---|
714 | } |
---|
715 | |
---|
716 | static void |
---|
717 | dec21140_start (struct ifnet *ifp) |
---|
718 | { |
---|
719 | struct dec21140_softc *sc = ifp->if_softc; |
---|
720 | rtems_event_send( txDaemonTid, sc->ioevent ); |
---|
721 | ifp->if_flags |= IFF_OACTIVE; |
---|
722 | } |
---|
723 | |
---|
724 | /* |
---|
725 | * Initialize and start the device |
---|
726 | */ |
---|
727 | static void |
---|
728 | dec21140_init (void *arg) |
---|
729 | { |
---|
730 | struct dec21140_softc *sc = arg; |
---|
731 | struct ifnet *ifp = &sc->arpcom.ac_if; |
---|
732 | volatile unsigned int *tbase; |
---|
733 | |
---|
734 | /* |
---|
735 | * Set up DEC21140 hardware if its not already been done |
---|
736 | */ |
---|
737 | if( !sc->irqInfo.hdl ) |
---|
738 | { |
---|
739 | dec21140Enet_initialize_hardware (sc); |
---|
740 | } |
---|
741 | |
---|
742 | /* |
---|
743 | * Enable RX and TX |
---|
744 | */ |
---|
745 | tbase = sc->base; |
---|
746 | st_le32( (tbase+memCSR5), IT_SETUP); |
---|
747 | st_le32( (tbase+memCSR7), IT_SETUP); |
---|
748 | st_le32( (unsigned int*)(tbase+memCSR6), CSR6_INIT | CSR6_TXRX); |
---|
749 | |
---|
750 | /* |
---|
751 | * Tell the world that we're running. |
---|
752 | */ |
---|
753 | ifp->if_flags |= IFF_RUNNING; |
---|
754 | } |
---|
755 | |
---|
756 | /* |
---|
757 | * Stop the device |
---|
758 | */ |
---|
759 | static void |
---|
760 | dec21140_stop (struct dec21140_softc *sc) |
---|
761 | { |
---|
762 | volatile unsigned int *tbase; |
---|
763 | struct ifnet *ifp = &sc->arpcom.ac_if; |
---|
764 | |
---|
765 | ifp->if_flags &= ~IFF_RUNNING; |
---|
766 | |
---|
767 | /* |
---|
768 | * Stop the transmitter |
---|
769 | */ |
---|
770 | tbase = sc->base; |
---|
771 | st_le32( (tbase+memCSR7), NO_IT); |
---|
772 | st_le32( (tbase+memCSR6), CSR6_INIT); |
---|
773 | |
---|
774 | /* free((void*)sc->bufferBase); */ |
---|
775 | } |
---|
776 | |
---|
777 | /* |
---|
778 | * Show interface statistics |
---|
779 | */ |
---|
780 | static void |
---|
781 | dec21140_stats (struct dec21140_softc *sc) |
---|
782 | { |
---|
783 | printf (" Rx Interrupts:%-8lu", sc->rxInterrupts); |
---|
784 | printf (" Not First:%-8lu", sc->rxNotFirst); |
---|
785 | printf (" Not Last:%-8lu\n", sc->rxNotLast); |
---|
786 | printf (" Giant:%-8lu", sc->rxGiant); |
---|
787 | printf (" Runt:%-8lu", sc->rxRunt); |
---|
788 | printf (" Non-octet:%-8lu\n", sc->rxNonOctet); |
---|
789 | printf (" Bad CRC:%-8lu", sc->rxBadCRC); |
---|
790 | printf (" Overrun:%-8lu", sc->rxOverrun); |
---|
791 | printf (" Collision:%-8lu\n", sc->rxCollision); |
---|
792 | |
---|
793 | printf (" Tx Interrupts:%-8lu", sc->txInterrupts); |
---|
794 | printf (" Deferred:%-8lu", sc->txDeferred); |
---|
795 | printf (" Missed Hearbeat:%-8lu\n", sc->txHeartbeat); |
---|
796 | printf (" No Carrier:%-8lu", sc->txLostCarrier); |
---|
797 | printf ("Retransmit Limit:%-8lu", sc->txRetryLimit); |
---|
798 | printf (" Late Collision:%-8lu\n", sc->txLateCollision); |
---|
799 | printf (" Underrun:%-8lu", sc->txUnderrun); |
---|
800 | printf (" Raw output wait:%-8lu\n", sc->txRawWait); |
---|
801 | } |
---|
802 | |
---|
803 | /* |
---|
804 | * Driver ioctl handler |
---|
805 | */ |
---|
806 | static int |
---|
807 | dec21140_ioctl (struct ifnet *ifp, ioctl_command_t command, caddr_t data) |
---|
808 | { |
---|
809 | struct dec21140_softc *sc = ifp->if_softc; |
---|
810 | int error = 0; |
---|
811 | |
---|
812 | switch (command) { |
---|
813 | case SIOCGIFADDR: |
---|
814 | case SIOCSIFADDR: |
---|
815 | ether_ioctl (ifp, command, data); |
---|
816 | break; |
---|
817 | |
---|
818 | case SIOCSIFFLAGS: |
---|
819 | switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { |
---|
820 | case IFF_RUNNING: |
---|
821 | dec21140_stop (sc); |
---|
822 | break; |
---|
823 | |
---|
824 | case IFF_UP: |
---|
825 | dec21140_init (sc); |
---|
826 | break; |
---|
827 | |
---|
828 | case IFF_UP | IFF_RUNNING: |
---|
829 | dec21140_stop (sc); |
---|
830 | dec21140_init (sc); |
---|
831 | break; |
---|
832 | |
---|
833 | default: |
---|
834 | break; |
---|
835 | } |
---|
836 | break; |
---|
837 | |
---|
838 | case SIO_RTEMS_SHOW_STATS: |
---|
839 | dec21140_stats (sc); |
---|
840 | break; |
---|
841 | |
---|
842 | /* |
---|
843 | * FIXME: All sorts of multicast commands need to be added here! |
---|
844 | */ |
---|
845 | default: |
---|
846 | error = EINVAL; |
---|
847 | break; |
---|
848 | } |
---|
849 | |
---|
850 | return error; |
---|
851 | } |
---|
852 | |
---|
853 | |
---|
854 | /* |
---|
855 | int iftap(struct ifnet *ifp, struct ether_header *eh, struct mbuf *m ) |
---|
856 | { |
---|
857 | int i; |
---|
858 | |
---|
859 | if( ifp->if_unit == 1 ) return 0; |
---|
860 | |
---|
861 | printf("unit %i, src ", ifp->if_unit ); |
---|
862 | for(i=0; i< ETHER_ADDR_LEN; i++) printf("%02x", (char) eh->ether_shost[i] ); |
---|
863 | printf(" dest "); |
---|
864 | for(i=0; i< ETHER_ADDR_LEN; i++) printf("%02x", (char) eh->ether_dhost[i] ); |
---|
865 | printf("\n"); |
---|
866 | |
---|
867 | return -1; |
---|
868 | } |
---|
869 | */ |
---|
870 | |
---|
871 | /* |
---|
872 | * Attach an DEC21140 driver to the system |
---|
873 | */ |
---|
874 | int |
---|
875 | rtems_dec21140_driver_attach (struct rtems_bsdnet_ifconfig *config, int attach) |
---|
876 | { |
---|
877 | struct dec21140_softc *sc; |
---|
878 | struct ifnet *ifp; |
---|
879 | char *unitName; |
---|
880 | int unitNumber; |
---|
881 | int mtu; |
---|
882 | unsigned char cvalue; |
---|
883 | #if defined(__i386__) |
---|
884 | uint32_t value; |
---|
885 | uint8_t interrupt; |
---|
886 | #endif |
---|
887 | int pbus, pdev, pfun; |
---|
888 | #if defined(__PPC__) |
---|
889 | int tmp; |
---|
890 | uint32_t lvalue; |
---|
891 | #endif |
---|
892 | |
---|
893 | /* |
---|
894 | * Get the instance number for the board we're going to configure |
---|
895 | * from the user. |
---|
896 | */ |
---|
897 | if( (unitNumber = rtems_bsdnet_parse_driver_name(config, &unitName)) == -1 ) |
---|
898 | { |
---|
899 | return 0; |
---|
900 | } |
---|
901 | if( strcmp(unitName, DRIVER_PREFIX) ) |
---|
902 | { |
---|
903 | printk("dec2114x : unit name '%s' not %s\n", unitName, DRIVER_PREFIX ); |
---|
904 | return 0; |
---|
905 | } |
---|
906 | |
---|
907 | /* |
---|
908 | * Find the board |
---|
909 | */ |
---|
910 | if ( pci_find_device(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21140, |
---|
911 | unitNumber-1, &pbus, &pdev, &pfun) == -1 ) { |
---|
912 | if ( pci_find_device(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21143, |
---|
913 | unitNumber-1, &pbus, &pdev, &pfun) != -1 ) { |
---|
914 | |
---|
915 | /* the 21143 chip must be enabled before it can be accessed */ |
---|
916 | #if defined(__i386__) |
---|
917 | pci_write_config_dword(pbus, pdev, pfun, 0x40, 0 ); |
---|
918 | #else |
---|
919 | pci_write_config_dword(pbus, pdev, pfun, 0x40, PCI_DEVICE_ID_DEC_21143); |
---|
920 | #endif |
---|
921 | |
---|
922 | } else { |
---|
923 | printk("dec2114x : device '%s' not found on PCI bus\n", config->name ); |
---|
924 | return 0; |
---|
925 | } |
---|
926 | } |
---|
927 | |
---|
928 | #ifdef DEC_DEBUG |
---|
929 | else { |
---|
930 | printk("dec21140 : found device '%s', bus 0x%02x, dev 0x%02x, func 0x%02x\n", |
---|
931 | config->name, pbus, pdev, pfun); |
---|
932 | } |
---|
933 | #endif |
---|
934 | |
---|
935 | if ((unitNumber < 1) || (unitNumber > NDECDRIVER)) |
---|
936 | { |
---|
937 | printk("dec2114x : unit %i is invalid, must be (1 <= n <= %d)\n", unitNumber); |
---|
938 | return 0; |
---|
939 | } |
---|
940 | |
---|
941 | sc = &dec21140_softc[unitNumber - 1]; |
---|
942 | ifp = &sc->arpcom.ac_if; |
---|
943 | if (ifp->if_softc != NULL) |
---|
944 | { |
---|
945 | printk("dec2114x : unit %i already in use.\n", unitNumber ); |
---|
946 | return 0; |
---|
947 | } |
---|
948 | |
---|
949 | |
---|
950 | /* |
---|
951 | ** Get this unit's rx/tx event |
---|
952 | */ |
---|
953 | sc->ioevent = unit_signals[unitNumber-1]; |
---|
954 | |
---|
955 | /* |
---|
956 | ** Save the buffer counts |
---|
957 | */ |
---|
958 | sc->numRxbuffers = (config->rbuf_count) ? config->rbuf_count : NRXBUFS; |
---|
959 | sc->numTxbuffers = (config->xbuf_count) ? config->xbuf_count : NTXBUFS; |
---|
960 | |
---|
961 | |
---|
962 | /* |
---|
963 | * Get card address spaces & retrieve its isr vector |
---|
964 | */ |
---|
965 | #if defined(__i386__) |
---|
966 | |
---|
967 | pci_read_config_dword(pbus, pdev, pfun, 16, &value); |
---|
968 | sc->port = value & ~IO_MASK; |
---|
969 | |
---|
970 | pci_read_config_dword(pbus, pdev, pfun, 20, &value); |
---|
971 | if (_CPU_is_paging_enabled()) |
---|
972 | _CPU_map_phys_address((void **) &(sc->base), |
---|
973 | (void *)(value & ~MEM_MASK), |
---|
974 | DEC_REGISTER_SIZE , |
---|
975 | PTE_CACHE_DISABLE | PTE_WRITABLE); |
---|
976 | else |
---|
977 | sc->base = (unsigned int *)(value & ~MEM_MASK); |
---|
978 | |
---|
979 | pci_read_config_byte(pbus, pdev, pfun, 60, &interrupt); |
---|
980 | cvalue = interrupt; |
---|
981 | #endif |
---|
982 | #if defined(__PPC__) |
---|
983 | (void)pci_read_config_dword(pbus, |
---|
984 | pdev, |
---|
985 | pfun, |
---|
986 | PCI_BASE_ADDRESS_0, |
---|
987 | &lvalue); |
---|
988 | |
---|
989 | sc->port = lvalue & (unsigned int)(~IO_MASK); |
---|
990 | |
---|
991 | (void)pci_read_config_dword(pbus, |
---|
992 | pdev, |
---|
993 | pfun, |
---|
994 | PCI_BASE_ADDRESS_1, |
---|
995 | &lvalue); |
---|
996 | |
---|
997 | tmp = (unsigned int)(lvalue & (unsigned int)(~MEM_MASK)) |
---|
998 | + (unsigned int)PCI_MEM_BASE; |
---|
999 | |
---|
1000 | sc->base = (unsigned int *)(tmp); |
---|
1001 | |
---|
1002 | pci_read_config_byte(pbus, |
---|
1003 | pdev, |
---|
1004 | pfun, |
---|
1005 | PCI_INTERRUPT_LINE, |
---|
1006 | &cvalue); |
---|
1007 | |
---|
1008 | #endif |
---|
1009 | |
---|
1010 | /* |
---|
1011 | ** Prep the board |
---|
1012 | */ |
---|
1013 | |
---|
1014 | pci_write_config_word(pbus, pdev, pfun, |
---|
1015 | PCI_COMMAND, |
---|
1016 | (uint16_t) ( PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER ) ); |
---|
1017 | |
---|
1018 | /* |
---|
1019 | ** Store the interrupt name, we'll use it later when we initialize |
---|
1020 | ** the board. |
---|
1021 | */ |
---|
1022 | memset(&sc->irqInfo,0,sizeof(rtems_irq_connect_data)); |
---|
1023 | sc->irqInfo.name = cvalue; |
---|
1024 | |
---|
1025 | |
---|
1026 | #ifdef DEC_DEBUG |
---|
1027 | printk("dec2114x : unit %d base address %08x.\n", unitNumber, sc->base ); |
---|
1028 | #endif |
---|
1029 | |
---|
1030 | |
---|
1031 | /* |
---|
1032 | ** Setup ethernet address |
---|
1033 | */ |
---|
1034 | if (config->hardware_address) { |
---|
1035 | memcpy (sc->arpcom.ac_enaddr, config->hardware_address, |
---|
1036 | ETHER_ADDR_LEN); |
---|
1037 | } |
---|
1038 | else { |
---|
1039 | union {char c[64]; unsigned short s[32];} rombuf; |
---|
1040 | int i; |
---|
1041 | |
---|
1042 | for (i=0; i<32; i++){ |
---|
1043 | rombuf.s[i] = eeget16( sc->base + memCSR9, i); |
---|
1044 | } |
---|
1045 | #if defined(__i386__) |
---|
1046 | for (i=0 ; i<(ETHER_ADDR_LEN/2); i++){ |
---|
1047 | sc->arpcom.ac_enaddr[2*i] = rombuf.c[20+2*i+1]; |
---|
1048 | sc->arpcom.ac_enaddr[2*i+1] = rombuf.c[20+2*i]; |
---|
1049 | } |
---|
1050 | #endif |
---|
1051 | #if defined(__PPC__) |
---|
1052 | memcpy (sc->arpcom.ac_enaddr, rombuf.c+20, ETHER_ADDR_LEN); |
---|
1053 | #endif |
---|
1054 | } |
---|
1055 | |
---|
1056 | if (config->mtu) |
---|
1057 | mtu = config->mtu; |
---|
1058 | else |
---|
1059 | mtu = ETHERMTU; |
---|
1060 | |
---|
1061 | sc->acceptBroadcast = !config->ignore_broadcast; |
---|
1062 | |
---|
1063 | /* |
---|
1064 | * Set up network interface values |
---|
1065 | */ |
---|
1066 | |
---|
1067 | /* ifp->if_tap = iftap; */ |
---|
1068 | |
---|
1069 | ifp->if_softc = sc; |
---|
1070 | ifp->if_unit = unitNumber; |
---|
1071 | ifp->if_name = unitName; |
---|
1072 | ifp->if_mtu = mtu; |
---|
1073 | ifp->if_init = dec21140_init; |
---|
1074 | ifp->if_ioctl = dec21140_ioctl; |
---|
1075 | ifp->if_start = dec21140_start; |
---|
1076 | ifp->if_output = ether_output; |
---|
1077 | ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX; |
---|
1078 | if (ifp->if_snd.ifq_maxlen == 0) |
---|
1079 | ifp->if_snd.ifq_maxlen = ifqmaxlen; |
---|
1080 | |
---|
1081 | /* |
---|
1082 | * Attach the interface |
---|
1083 | */ |
---|
1084 | if_attach (ifp); |
---|
1085 | ether_ifattach (ifp); |
---|
1086 | |
---|
1087 | #ifdef DEC_DEBUG |
---|
1088 | printk( "dec2114x : driver attached\n" ); |
---|
1089 | #endif |
---|
1090 | |
---|
1091 | /* |
---|
1092 | * Start driver tasks if this is the first dec unit initialized |
---|
1093 | */ |
---|
1094 | if (txDaemonTid == 0) |
---|
1095 | { |
---|
1096 | rxDaemonTid = rtems_bsdnet_newproc( "DCrx", 4096, |
---|
1097 | dec21140_rxDaemon, NULL); |
---|
1098 | |
---|
1099 | txDaemonTid = rtems_bsdnet_newproc( "DCtx", 4096, |
---|
1100 | dec21140_txDaemon, NULL); |
---|
1101 | #ifdef DEC_DEBUG |
---|
1102 | printk( "dec2114x : driver tasks created\n" ); |
---|
1103 | #endif |
---|
1104 | } |
---|
1105 | |
---|
1106 | return 1; |
---|
1107 | }; |
---|
1108 | |
---|
1109 | #endif /* DEC21140_SUPPORTED */ |
---|