source: rtems/c/src/lib/start/mips64orion/idt_csu.S @ f198c63

4.104.114.84.95
Last change on this file since f198c63 was f198c63, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 6, 1996 at 6:11:41 PM

new file for MIPS port by Craig Lebakken (lebakken@…) and
Derrick Ostertag (ostertag@…).

  • Property mode set to 100644
File size: 7.9 KB
Line 
1/*
2
3Based upon IDT provided code with the following release:
4
5This source code has been made available to you by IDT on an AS-IS
6basis. Anyone receiving this source is licensed under IDT copyrights
7to use it in any way he or she deems fit, including copying it,
8modifying it, compiling it, and redistributing it either with or
9without modifications.  No license under IDT patents or patent
10applications is to be implied by the copyright license.
11
12Any user of this software should understand that IDT cannot provide
13technical support for this software and will not be responsible for
14any consequences resulting from the use of this software.
15
16Any person who transfers this source code or any derivative work must
17include the IDT copyright notice, this paragraph, and the preceeding
18two paragraphs in the transferred software.
19
20COPYRIGHT IDT CORPORATION 1996
21LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
22
23*/
24
25/*************************************************************************
26**
27** Copyright 1991-95 Integrated Device Technology, Inc.
28**      All Rights Reserved
29**
30** idt_csu.S -- IDT stand alone startup code
31**
32**************************************************************************/
33#include <rtems/score/iregdef.h>
34#include <rtems/score/idtcpu.h>
35#include <rtems/score/idtmon.h>
36
37
38.extern _fbss,4           /* this is defined by the linker */
39.extern end,4             /* this is defined by the linker */
40
41.lcomm sim_mem_cfg_struct,12
42
43        .text
44
45
46#define TMP_STKSIZE  1024
47
48/**************************************************************************
49**
50**  start - Typicl standalone start up code required for R3000/R4000
51**
52**
53**      1)  Initialize the STATUS Register
54**              a) Clear parity error bit
55**              b) Set co_processor 1 usable bit ON
56**              c) Clear all IntMask Enables
57**              d) Set kernel/disabled mode
58**      2)  Initialize Cause Register
59**              a)  clear software interrupt bits       
60**      3)  Determine FPU installed or not
61**              if not, clear CoProcessor 1 usable bit
62**      4)  Clear bss area
63**      5)  MUST allocate temporary stack until memory size determined
64**          It MUST be uncached to prevent overwriting when caches are cleared
65**      6)  Install exception handlers
66**      7)  Determine memory and cache sizes
67**      8)  Establish permanent stack (cached or uncached as defined by bss)
68**      9)  Flush Instruction and Data caches
69**      10)  If there is a Translation Lookaside Buffer, Clear the TLB
70**      11)  Execute initialization code if the IDT/c library is to be used
71**
72**      12)  Jump to user's "main()"
73**      13)  Jump to promexit
74**
75**      IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally.
76**      This is used to mark code specific to R3xxx or R4xxx processors.
77**      IDT/C 6.x defines __mips to be the ISA level for which we're
78**      generating code. This is used to make sure the stack etc. is
79**      double word aligned, when using -mips3 (default) or -mips2,
80**      when compiling with IDT/C6.x
81**
82***************************************************************************/
83
84FRAME(start,sp,0,ra)
85
86        .set    noreorder
87#ifdef _R3000
88        li      v0,SR_PE|SR_CU1        /* reset parity error and set */
89                                        /* cp1 usable */
90#endif
91#ifdef _R4000
92#if __mips==3 || defined(R4650)
93        li      v0,SR_CU1|SR_DE|SR_FR   /* initally clear ERL, enable FPA 64bit regs*/
94                                        /* 4650: Need fr to be set anyway */
95#else
96        li      v0,SR_CU1|SR_DE         /* initally clear ERL, enable FPA 32bit regs*/
97#endif mips3
98#endif
99
100        mtc0    v0,C0_SR                /* clr IntMsks/ kernel/disabled mode */
101        nop
102        mtc0    zero,C0_CAUSE           /* clear software interrupts */
103        nop
104
105#ifdef _R4000
106        li      v0,CFG_C_NONCOHERENT    # initialise default cache mode
107        mtc0    v0,C0_CONFIG
108#endif
109
110/*
111**      check to see if an fpu is really plugged in
112*/
113        li      t3,0xaaaa5555           /*  put a's and 5's in t3       */
114        mtc1    t3,fp0                  /* try to write them into fp0   */     
115        mtc1    zero,fp1                /* try to write zero in fp      */
116        mfc1    t0,fp0
117        mfc1    t1,fp1
118        nop
119        bne     t0,t3,1f                /* branch if no match  */
120        nop
121        bne     t1,zero,1f              /* double check for positive id   */
122        nop
123        /* We have a FPU. clear fcsr */
124        ctc1    zero, fcr31
125        j       2f                      /* status register already correct  */
126        nop
1271:
128#ifdef _R3000
129        li      v0, SR_PE               /* reset parity error/NO cp1 usable */
130#endif
131
132#ifdef _R4000
133        li      v0,SR_DE                /* clear ERL and disable FPA */
134#endif
135
136        mtc0    v0, C0_SR               /* reset status register */
1372:
138        la      gp, _gp                 
139
140        la      v0,_fbss                /* clear bss before using it */
141        la      v1,end                  /* end of bss */
1423:      sw      zero,0(v0)
143        bltu    v0,v1,3b
144        add     v0,4
145
146
147/************************************************************************
148**
149**      Temporary Stack - needed to  handle stack saves until
150**                        memory size is determined and permanent stack set
151**
152**                        MUST be uncached to avoid confusion at cache
153**                             switching during memory sizing
154**
155*************************************************************************/
156#if __mips==3
157        /* For MIPS 3, we need to be sure that the stack is aligned on a
158         * double word boundary.
159         */
160        andi    t0, v0, 0x7
161        beqz    t0, 11f   /* Last three bits Zero, already aligned */
162        nop
163        add     v0, 4
16411:
165#endif
166
167        or      v0, K1BASE              /* switch to uncached */
168        add     v1, v0, TMP_STKSIZE     /* end of bss + length of tmp stack */
169        sub     v1, v1, (4*4)           /* overhead */
170        move    sp, v1                  /* set sp to top of stack */
1714:      sw      zero, 0(v0) 
172        bltu    v0, v1, 4b              /* clear out temp stack */
173        add     v0, 4
174       
175        jal     init_exc_vecs           /* install exception handlers */
176        nop                             /* MUST do before memory probes */
177
178        la      v0, 5f
179        li      v1, K1BASE              /* force into uncached space */
180        or      v0, v1                  /* during memory/cache probes */
181        j       v0
182        nop
1835:
184        la      a0, sim_mem_cfg_struct
185        jal     sim_mem_cfg             /* Make SIM call to get mem size */
186        nop
187        la      a0, sim_mem_cfg_struct
188        lw      a0, 0(a0)               /* Get memory size from struct */
189#ifdef _R3000
190        jal     config_Icache
191        nop
192        jal     config_Dcache           /* determine size of D & I caches */
193        nop     
194#endif
195#ifdef _R4000
196        jal     config_cache            /* determine size of D & I caches */
197        nop
198#endif
199
200        move    v0, a0                  /* mem_size */
201
202#if __mips==3
203        /* For MIPS 3, we need to be sure that the stack (and hence v0
204         * here) is aligned on a double word boundary.
205         */
206        andi    t0, v0, 0x7
207        beqz    t0, 12f   /* Last three bits Zero, already aligned */
208        nop
209        subu    v0, 4   /* mem_size was not aligned on doubleword bdry????*/
21012:
211#endif
212
213
214
215/**************************************************************************
216**
217**  Permanent Stack - now know top of memory, put permanent stack there
218**
219***************************************************************************/
220
221        la      t2, _fbss               /* cache mode as linked */
222        and     t2, 0xF0000000          /* isolate segment */
223        la      t1, 6f
224        j       t1                      /* back to original cache mode */
225        nop
2266:
227        or      v0, t2                  /* stack back to original cache mode */
228        addiu   v0,v0,-16               /* overhead */
229        move    sp, v0                  /* now replace count w top of memory */
230        move    v1, v0
231        subu    v1, P_STACKSIZE         /* clear requested stack size */
232
2337:      sw      zero, 0(v1)             /* clear P_STACKSIZE  stack */
234        bltu    v1,v0,7b
235        add     v1, 4
236        .set    reorder
237
238#ifdef _R3000
239        jal     flush_Icache   
240        jal     flush_Dcache            /* flush Data & Instruction caches */
241#endif
242#ifdef _R4000
243        jal     flush_cache_nowrite     /* flush Data & Instruction caches */
244#endif
245
246
247
248/**************************************************************************
249**
250**      If this chip supports a Translation Lookaside Buffer, clear it
251**
252***************************************************************************/
253
254        .set    noreorder
255        mfc0    t1,  C0_SR              /* look at Status Register */
256        nop
257        .set    reorder
258#ifdef _R3000
259        li      t2, SR_TS               /* TLB Shutdown bit */
260        and     t1,t2                   /* TLB Shutdown if 1 */
261        bnez    t1, 8f                  /* skip clearing if no TLB */   
262#endif
263
264#ifndef R4650
265        jal     init_tlb                /* clear the tlb */
266#endif
267
268
269/************************************************************************
270**
271**  Initialization required if using IDT/c or libc.a, standard C Lib
272**
273**  can SKIP if not necessary for application
274**
275************************************************************************/
2768:
277
278        jal     idtsim_init_sbrk
279        jal     idtsim_init_file
280/***********************  END I/O initialization **********************/
281
282
283        jal     main
284
285        jal     idtsim_promexit
286
287ENDFRAME(start)
288
289
290        .globl  sim_mem_cfg
291sim_mem_cfg:
292        .set noat
293        .set noreorder
294        li      AT, (0xbfc00000+((55)*8))
295        jr      AT
296        nop
297        .set at
298        .set reorder
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