1 | /* cpu_asm.s |
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2 | * |
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3 | * This file contains all assembly code for the Intel i386 implementation |
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4 | * of RDBG. |
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5 | * |
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6 | * $Id$ |
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7 | * |
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8 | */ |
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9 | |
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10 | #include <libcpu/cpu.h> |
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11 | #include <libcpu/io.h> |
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12 | #include <rtems/score/targopts.h> |
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13 | #include <asm.h> |
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14 | |
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15 | BEGIN_CODE |
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16 | |
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17 | /* |
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18 | * void copyback_data_cache_and_invalidate_instr_cache(addr, size) |
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19 | * |
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20 | * This routine performs a copy of the data cache |
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21 | * and invalidate the instruction cache |
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22 | */ |
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23 | |
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24 | .p2align 5 |
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25 | PUBLIC_VAR (copyback_data_cache_and_invalidate_instr_cache) |
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26 | |
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27 | SYM (copyback_data_cache_and_invalidate_instr_cache): |
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28 | /* r3 address to handle, r4 length in bytes */ |
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29 | addi r6, r0, PPC_CACHE_ALIGNMENT |
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30 | /* r5 = last address to handle */ |
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31 | add r5,r3,r4 |
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32 | /* r3 = cache_align(r3, PPC_CACHE_ALIGNMENT) |
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33 | subi r0,r6,1 |
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34 | andc r3,r3,r0 |
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35 | /* R4 = R3 = copy of first address */ |
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36 | mr r4,r3 |
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37 | /* |
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38 | * Copyback data cache |
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39 | */ |
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40 | 1: cmplw r4,r5 /* r4 >= r5 then done */ |
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41 | dcbst 0,r4 /* flush (data cache bloc store) */ |
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42 | add r4,r4,r6 /* r4 = next cache line addr */ |
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43 | blt 1b /* end r4 >= r5 then done */ |
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44 | sync /* Wait for all dcbst to complete on bus */ |
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45 | /* |
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46 | * invalidate instruction cache |
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47 | */ |
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48 | /* R4 = fisrt address */ |
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49 | mr r4,r3 |
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50 | 2: cmplw r4,r5 /* r4 >= r5 then done */ |
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51 | icbi 0,r4 /* invalidate (instruction cache bloc invalidate) */ |
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52 | add r4,r4,r6 /* r4 = next cache line addr */ |
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53 | blt 2b /* end r4 >= r5 then done */ |
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54 | sync /* Wait for all icbi to complete on bus */ |
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55 | isync |
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56 | blr |
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57 | |
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58 | |
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59 | /* |
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60 | * void enterRdbg(void) |
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61 | * |
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62 | * This function perform a call to the exception SYSTEM call |
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63 | * It is used : |
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64 | * 1 - in the user code, to simulate a Breakpoint. |
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65 | * (with justSaveContext = 0) |
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66 | * 2 - in the RDBG code, to push a ctx in the list. |
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67 | * (with justSaveContext = 1) |
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68 | * |
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69 | * In most of case, it will be use as described in 1. |
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70 | * The 2nd possibility will be used by RDBG to obtain |
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71 | * its own ctx |
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72 | */ |
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73 | |
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74 | PUBLIC_VAR (enterRdbg) |
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75 | |
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76 | SYM (enterRdbg): |
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77 | sc |
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78 | blr |
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79 | |
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80 | END_CODE |
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81 | |
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82 | END |
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