source: rtems/c/src/lib/librdbg/powerpc/mcp750/remdeb_f.x @ 981b99f

4.104.114.84.95
Last change on this file since 981b99f was 981b99f, checked in by Joel Sherrill <joel.sherrill@…>, on 08/10/99 at 16:41:44

Patch from Eric Valette <valette@…> and Emmanuel Raguet
<raguet@…>:

  • the dec21140 driver code has been hardened (various bug fixed) Emmanuel,
  • bug in the mcp750 init code have been fixed (interrupt stack/initial stack initialization), BSS correctly cleared (Eric V)
  • remote debugging over TCP/IP is nearly complete (berakpoints, backtrace, variables,...) (Eric V),
  • exception handling code has also been improved in order to fully support RDBG requirements (Eric V),
  • Property mode set to 100644
File size: 2.1 KB
Line 
1/*
2 **************************************************************************
3 *
4 * Component =   rdblib
5 * Synopsis  =   remdeb_f.x
6 *
7 **************************************************************************
8 * $Id$
9 **************************************************************************
10 */
11
12struct xdr_regs
13{
14  unsigned int  tabreg[40];
15};
16
17#ifdef RPC_HDR
18
19%/* now define register macros to apply to xdr_regs struct */
20%
21%#define R_PC           0
22%#define R_MSR          1
23%#define R_EXCEPNB      2
24%#define R_R0           3
25%#define R_R1    (R_R0 + 1)
26%#define R_R2    (R_R0 + 2)
27%#define R_R3    (R_R0 + 3)
28%#define R_R4    (R_R0 + 4)
29%#define R_R5    (R_R0 + 5)
30%#define R_R6    (R_R0 + 6)
31%#define R_R7    (R_R0 + 7)
32%#define R_R8    (R_R0 + 8)
33%#define R_R9    (R_R0 + 9)
34%#define R_R10   (R_R0 + 10)
35%#define R_R11   (R_R0 + 11)
36%#define R_R12   (R_R0 + 12)
37%#define R_R13   (R_R0 + 13)
38%#define R_R14   (R_R0 + 14)
39%#define R_R15   (R_R0 + 15)
40%#define R_R16   (R_R0 + 16)
41%#define R_R17   (R_R0 + 17)
42%#define R_R18   (R_R0 + 18)
43%#define R_R19   (R_R0 + 19)
44%#define R_R20   (R_R0 + 20)
45%#define R_R21   (R_R0 + 21)
46%#define R_R22   (R_R0 + 22)
47%#define R_R23   (R_R0 + 23)
48%#define R_R24   (R_R0 + 24)
49%#define R_R25   (R_R0 + 25)
50%#define R_R26   (R_R0 + 26)
51%#define R_R27   (R_R0 + 27)
52%#define R_R28   (R_R0 + 28)
53%#define R_R29   (R_R0 + 29)
54%#define R_R30   (R_R0 + 30)
55%#define R_R31   (R_R0 + 31)
56%#define R_CR    35
57%#define R_CTR   36
58%#define R_XER   37
59%#define R_LR    38
60%#define R_MQ    39
61%
62%#include <libcpu/raw_exception.h>
63%
64%#define REG_PC tabreg[R_PC]     /* PC register offset */
65%#define REG_SP tabreg[R_R1]    /* SP register offset */
66%#define REG_FP tabreg[R_R1]    /* SP register offset (no FP on PPC) */
67%#define BREAK_SIZE     4       /* Breakpoint occupies 4 bytes */
68%#define BREAK_ADJ      0       /* Nothing to subtract from address after bp */
69%#define IS_BREAK(l)    ((l) == 0x7d8d6808)
70%#define SET_BREAK(l)   (0x7d8d6808)
71%#define ORG_BREAK(c,p) (p)
72%#define IS_STEP(regs)  (regs.tabreg[R_EXCEPNB] == ASM_TRACE_VECTOR) /* Was step and not break */
73%#define TARGET_PROC_TYPE  3
74
75#endif
76
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