| 1 | /* cpu_asm.s |
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| 2 | * |
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| 3 | * This file contains the basic algorithms for all assembly code used |
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| 4 | * in an specific CPU port of RTEMS. These algorithms must be implemented |
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| 5 | * in assembly language. |
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| 6 | * |
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| 7 | * COPYRIGHT (c) 1989-2007. |
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| 8 | * On-Line Applications Research Corporation (OAR). |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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| 12 | * http://www.rtems.com/license/LICENSE. |
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| 13 | * |
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| 14 | * Ported to ERC32 implementation of the SPARC by On-Line Applications |
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| 15 | * Research Corporation (OAR) under contract to the European Space |
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| 16 | * Agency (ESA). |
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| 17 | * |
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| 18 | * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. |
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| 19 | * European Space Agency. |
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| 20 | * |
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| 21 | * Ported to Niagara and UltraSPARC III (US3) implementations of the SPARC-v9. |
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| 22 | * Niagara and US3 modifications of respective RTEMS file: |
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| 23 | * COPYRIGHT (c) 2010. Gedare Bloom. |
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| 24 | * |
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| 25 | * $Id$ |
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| 26 | */ |
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| 27 | |
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| 28 | #include <rtems/asm.h> |
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| 29 | #include <rtems/score/percpu.h> |
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| 30 | |
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| 31 | |
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| 32 | /* |
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| 33 | * The assembler needs to be told that we know what to do with |
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| 34 | * the global registers. |
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| 35 | */ |
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| 36 | .register %g2, #scratch |
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| 37 | .register %g3, #scratch |
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| 38 | .register %g6, #scratch |
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| 39 | .register %g7, #scratch |
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| 40 | |
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| 41 | |
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| 42 | /* |
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| 43 | * void _ISR_Handler() |
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| 44 | * |
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| 45 | * This routine provides the RTEMS interrupt management. |
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| 46 | * |
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| 47 | * We enter this handler from the 8 instructions in the trap table with |
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| 48 | * the following registers assumed to be set as shown: |
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| 49 | * |
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| 50 | * g4 = tstate (old l0) |
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| 51 | * g2 = trap type (vector) (old l3) |
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| 52 | * |
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| 53 | * NOTE: By an executive defined convention: |
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| 54 | * if trap type is between 0 and 511 it is an asynchronous trap |
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| 55 | * if trap type is between 512 and 1023 it is an asynchonous trap |
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| 56 | */ |
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| 57 | |
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| 58 | .align 4 |
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| 59 | PUBLIC(_ISR_Handler) |
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| 60 | SYM(_ISR_Handler): |
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| 61 | |
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| 62 | /* |
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| 63 | * The ISR is called at TL = 1. |
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| 64 | * On sun4u we use the alternate globals set. |
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| 65 | * |
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| 66 | * On entry: |
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| 67 | * g4 = tstate (from trap table) |
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| 68 | * g2 = trap vector # |
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| 69 | * |
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| 70 | * In either case, note that trap handlers share a register window with |
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| 71 | * the interrupted context, unless we explicitly enter a new window. This |
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| 72 | * differs from Sparc v8, in which a dedicated register window is saved |
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| 73 | * for trap handling. This means we have to avoid overwriting any registers |
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| 74 | * that we don't save. |
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| 75 | * |
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| 76 | */ |
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| 77 | |
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| 78 | |
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| 79 | /* |
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| 80 | * save some or all context on stack |
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| 81 | */ |
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| 82 | |
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| 83 | /* |
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| 84 | * Save the state of the interrupted task -- especially the global |
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| 85 | * registers -- in the Interrupt Stack Frame. Note that the ISF |
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| 86 | * includes a regular minimum stack frame which will be used if |
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| 87 | * needed by register window overflow and underflow handlers. |
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| 88 | * |
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| 89 | * This is slightly wasteful, since the stack already has the window |
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| 90 | * overflow space reserved, but there is no obvious way to ensure |
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| 91 | * we can store the interrupted state and still handle window |
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| 92 | * spill/fill correctly, since there is no room for the ISF. |
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| 93 | * |
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| 94 | */ |
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| 95 | |
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| 96 | /* this is for debugging purposes, make sure that TL = 1, otherwise |
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| 97 | * things might get dicey */ |
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| 98 | rdpr %tl, %g1 |
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| 99 | cmp %g1, 1 |
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| 100 | be 1f |
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| 101 | nop |
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| 102 | |
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| 103 | 0: ba 0b |
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| 104 | nop |
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| 105 | |
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| 106 | 1: |
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| 107 | /* first store the sp of the interrupted task temporarily in g1 */ |
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| 108 | mov %sp, %g1 |
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| 109 | |
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| 110 | sub %sp, CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE, %sp |
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| 111 | ! make space for Stack_Frame||ISF |
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| 112 | |
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| 113 | /* save tstate, tpc, tnpc, pil */ |
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| 114 | stx %g4, [%sp + STACK_BIAS + ISF_TSTATE_OFFSET] |
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| 115 | rdpr %pil, %g3 |
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| 116 | rdpr %tpc, %g4 |
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| 117 | rdpr %tnpc, %g5 |
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| 118 | stx %g3, [%sp + STACK_BIAS + ISF_PIL_OFFSET] |
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| 119 | stx %g4, [%sp + STACK_BIAS + ISF_TPC_OFFSET] |
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| 120 | stx %g5, [%sp + STACK_BIAS + ISF_TNPC_OFFSET] |
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| 121 | stx %g2, [%sp + STACK_BIAS + ISF_TVEC_NUM] |
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| 122 | |
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| 123 | rd %y, %g4 ! save y |
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| 124 | stx %g4, [%sp + STACK_BIAS + ISF_Y_OFFSET] |
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| 125 | |
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| 126 | ! save interrupted frame's output regs |
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| 127 | stx %o0, [%sp + STACK_BIAS + ISF_O0_OFFSET] ! save o0 |
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| 128 | stx %o1, [%sp + STACK_BIAS + ISF_O1_OFFSET] ! save o1 |
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| 129 | stx %o2, [%sp + STACK_BIAS + ISF_O2_OFFSET] ! save o2 |
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| 130 | stx %o3, [%sp + STACK_BIAS + ISF_O3_OFFSET] ! save o3 |
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| 131 | stx %o4, [%sp + STACK_BIAS + ISF_O4_OFFSET] ! save o4 |
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| 132 | stx %o5, [%sp + STACK_BIAS + ISF_O5_OFFSET] ! save o5 |
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| 133 | stx %g1, [%sp + STACK_BIAS + ISF_O6_SP_OFFSET] ! save o6/sp |
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| 134 | stx %o7, [%sp + STACK_BIAS + ISF_O7_OFFSET] ! save o7 |
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| 135 | |
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| 136 | mov %g1, %o5 ! hold the old sp here for now |
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| 137 | mov %g2, %o1 ! we'll need trap # later |
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| 138 | |
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| 139 | /* switch to TL[0] */ |
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| 140 | wrpr %g0, 0, %tl |
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| 141 | |
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| 142 | /* switch to normal globals */ |
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| 143 | #if defined (SUN4U) |
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| 144 | /* the assignment to pstate below will mask out the AG bit */ |
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| 145 | #elif defined (SUN4V) |
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| 146 | wrpr %g0, 0, %gl |
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| 147 | #endif |
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| 148 | /* get pstate to known state */ |
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| 149 | wrpr %g0, SPARC_PSTATE_PRIV_MASK | SPARC_PSTATE_PEF_MASK, %pstate |
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| 150 | |
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| 151 | ! save globals |
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| 152 | stx %g1, [%sp + STACK_BIAS + ISF_G1_OFFSET] ! save g1 |
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| 153 | stx %g2, [%sp + STACK_BIAS + ISF_G2_OFFSET] ! save g2 |
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| 154 | stx %g3, [%sp + STACK_BIAS + ISF_G3_OFFSET] ! save g3 |
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| 155 | stx %g4, [%sp + STACK_BIAS + ISF_G4_OFFSET] ! save g4 |
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| 156 | stx %g5, [%sp + STACK_BIAS + ISF_G5_OFFSET] ! save g5 |
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| 157 | stx %g6, [%sp + STACK_BIAS + ISF_G6_OFFSET] ! save g6 |
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| 158 | stx %g7, [%sp + STACK_BIAS + ISF_G7_OFFSET] ! save g7 |
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| 159 | |
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| 160 | |
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| 161 | mov %o1, %g2 ! get the trap # |
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| 162 | mov %o5, %g7 ! store the interrupted %sp (preserve) |
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| 163 | mov %sp, %o1 ! 2nd arg to ISR Handler = address of ISF |
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| 164 | |
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| 165 | /* |
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| 166 | * Increment ISR nest level and Thread dispatch disable level. |
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| 167 | * |
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| 168 | * Register usage for this section: (note, these are used later) |
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| 169 | * |
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| 170 | * g3 = _Thread_Dispatch_disable_level pointer |
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| 171 | * g5 = _Thread_Dispatch_disable_level value (uint32_t) |
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| 172 | * g6 = _ISR_Nest_level pointer |
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| 173 | * g4 = _ISR_Nest_level value (uint32_t) |
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| 174 | * o5 = temp |
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| 175 | * |
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| 176 | * NOTE: It is assumed that g6 - g7 will be preserved until the ISR |
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| 177 | * nest and thread dispatch disable levels are unnested. |
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| 178 | */ |
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| 179 | |
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| 180 | setx SYM(_Thread_Dispatch_disable_level), %o5, %g3 |
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| 181 | lduw [%g3], %g5 |
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| 182 | setx ISR_NEST_LEVEL, %o5, %g6 |
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| 183 | lduw [%g6], %g4 |
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| 184 | |
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| 185 | add %g5, 1, %g5 |
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| 186 | stuw %g5, [%g3] |
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| 187 | |
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| 188 | add %g4, 1, %g4 |
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| 189 | stuw %g4, [%g6] |
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| 190 | |
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| 191 | /* |
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| 192 | * If ISR nest level was zero (now 1), then switch stack. |
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| 193 | */ |
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| 194 | |
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| 195 | subcc %g4, 1, %g4 ! outermost interrupt handler? |
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| 196 | bnz dont_switch_stacks ! No, then do not switch stacks |
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| 197 | |
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| 198 | setx SYM(INTERRUPT_STACK_HIGH), %o5, %g1 |
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| 199 | ldx [%g1], %sp |
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| 200 | |
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| 201 | /* |
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| 202 | * Adjust the stack for the stack bias |
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| 203 | */ |
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| 204 | sub %sp, STACK_BIAS, %sp |
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| 205 | |
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| 206 | /* |
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| 207 | * Make sure we have a place on the stack for the window overflow |
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| 208 | * trap handler to write into. At this point it is safe to |
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| 209 | * enable traps again. |
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| 210 | */ |
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| 211 | |
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| 212 | sub %sp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp |
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| 213 | |
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| 214 | dont_switch_stacks: |
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| 215 | /* |
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| 216 | * Check if we have an external interrupt (trap 0x41 - 0x4f). If so, |
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| 217 | * set the PIL to mask off interrupts with lower priority. |
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| 218 | * |
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| 219 | * The original PIL is not modified since it will be restored |
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| 220 | * when the interrupt handler returns. |
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| 221 | */ |
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| 222 | |
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| 223 | and %g2, 0x0ff, %g1 ! is bottom byte of vector number [0x41,0x4f]? |
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| 224 | |
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| 225 | subcc %g1, 0x41, %g0 |
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| 226 | bl dont_fix_pil |
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| 227 | subcc %g1, 0x4f, %g0 |
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| 228 | bg dont_fix_pil |
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| 229 | nop |
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| 230 | wrpr %g0, %g1, %pil |
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| 231 | |
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| 232 | dont_fix_pil: |
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| 233 | /* We need to be careful about enabling traps here. |
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| 234 | * |
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| 235 | * We already stored off the tstate, tpc, and tnpc, and switched to |
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| 236 | * TL = 0, so it should be safe. |
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| 237 | */ |
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| 238 | |
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| 239 | /* zero out g4 so that ofw calls work */ |
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| 240 | mov %g0, %g4 |
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| 241 | |
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| 242 | ! **** ENABLE TRAPS **** |
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| 243 | wrpr %g0, SPARC_PSTATE_PRIV_MASK | SPARC_PSTATE_PEF_MASK | \ |
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| 244 | SPARC_PSTATE_IE_MASK, %pstate |
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| 245 | |
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| 246 | /* |
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| 247 | * Vector to user's handler. |
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| 248 | * |
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| 249 | * NOTE: TBR may no longer have vector number in it since |
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| 250 | * we just enabled traps. It is definitely in g2. |
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| 251 | */ |
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| 252 | setx SYM(_ISR_Vector_table), %o5, %g1 |
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| 253 | ldx [%g1], %g1 |
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| 254 | and %g2, 0x1FF, %o5 ! remove synchronous trap indicator |
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| 255 | sll %o5, 3, %o5 ! o5 = offset into table |
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| 256 | ldx [%g1 + %o5], %g1 ! g1 = _ISR_Vector_table[ vector ] |
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| 257 | |
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| 258 | |
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| 259 | ! o1 = 2nd arg = address of the ISF |
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| 260 | ! WAS LOADED WHEN ISF WAS SAVED!!! |
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| 261 | mov %g2, %o0 ! o0 = 1st arg = vector number |
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| 262 | call %g1, 0 |
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| 263 | nop ! delay slot |
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| 264 | |
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| 265 | /* |
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| 266 | * Redisable traps so we can finish up the interrupt processing. |
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| 267 | * This is a conservative place to do this. |
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| 268 | */ |
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| 269 | ! **** DISABLE TRAPS **** |
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| 270 | wrpr %g0, SPARC_PSTATE_PRIV_MASK, %pstate |
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| 271 | |
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| 272 | /* |
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| 273 | * We may safely use any of the %o and %g registers, because |
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| 274 | * we saved them earlier (and any other interrupt that uses |
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| 275 | * them will also save them). Right now, the state of those |
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| 276 | * registers are as follows: |
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| 277 | * %o registers: unknown (user's handler may have destroyed) |
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| 278 | * %g1,g4,g5: scratch |
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| 279 | * %g2: unknown: was trap vector |
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| 280 | * %g3: uknown: was _Thread_Dispatch_Disable_level pointer |
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| 281 | * %g6: _ISR_Nest_level |
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| 282 | * %g7: interrupted task's sp |
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| 283 | */ |
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| 284 | |
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| 285 | /* |
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| 286 | * Increment ISR nest level and Thread dispatch disable level. |
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| 287 | * |
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| 288 | * Register usage for this section: (note: as used above) |
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| 289 | * |
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| 290 | * g3 = _Thread_Dispatch_disable_level pointer |
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| 291 | * g5 = _Thread_Dispatch_disable_level value |
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| 292 | * g6 = _ISR_Nest_level pointer |
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| 293 | * g4 = _ISR_Nest_level value |
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| 294 | * o5 = temp |
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| 295 | */ |
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| 296 | |
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| 297 | /* We have to re-load the values from memory, because there are |
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| 298 | * not enough registers that we know will be preserved across the |
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| 299 | * user's handler. If this is a problem, we can create a register |
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| 300 | * window for _ISR_Handler. |
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| 301 | */ |
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| 302 | |
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| 303 | setx SYM(_Thread_Dispatch_disable_level), %o5, %g3 |
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| 304 | lduw [%g3],%g5 |
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| 305 | lduw [%g6],%g4 |
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| 306 | sub %g5, 1, %g5 |
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| 307 | stuw %g5, [%g3] |
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| 308 | sub %g4, 1, %g4 |
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| 309 | stuw %g4, [%g6] |
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| 310 | |
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| 311 | orcc %g4, %g0, %g0 ! ISRs still nested? |
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| 312 | bnz dont_restore_stack ! Yes then don't restore stack yet |
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| 313 | nop |
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| 314 | |
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| 315 | /* |
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| 316 | * This is the outermost interrupt handler. Need to get off the |
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| 317 | * CPU Interrupt Stack and back to the tasks stack. |
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| 318 | * |
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| 319 | * The following subtract should get us back on the interrupted |
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| 320 | * tasks stack and add enough room to invoke the dispatcher. |
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| 321 | * When we enable traps, we are mostly back in the context |
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| 322 | * of the task and subsequent interrupts can operate normally. |
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| 323 | * |
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| 324 | * Now %sp points to the bottom of the ISF. |
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| 325 | * |
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| 326 | */ |
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| 327 | |
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| 328 | sub %g7, CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE, %sp |
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| 329 | |
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| 330 | dont_restore_stack: |
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| 331 | |
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| 332 | /* |
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| 333 | * If dispatching is disabled (includes nested interrupt case), |
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| 334 | * then do a "simple" exit. |
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| 335 | */ |
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| 336 | |
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| 337 | orcc %g5, %g0, %g0 ! Is dispatching disabled? |
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| 338 | bnz simple_return ! Yes, then do a "simple" exit |
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| 339 | ! NOTE: Use the delay slot |
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| 340 | mov %g0, %g4 ! clear g4 for ofw |
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| 341 | |
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| 342 | ! Are we dispatching from a previous ISR in the interrupted thread? |
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| 343 | setx SYM(_CPU_ISR_Dispatch_disable), %o5, %g5 |
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| 344 | lduw [%g5], %o5 |
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| 345 | orcc %o5, %g0, %g0 ! Is this thread already doing an ISR? |
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| 346 | bnz simple_return ! Yes, then do a "simple" exit |
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| 347 | nop |
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| 348 | |
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| 349 | setx DISPATCH_NEEDED, %o5, %g7 |
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| 350 | |
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| 351 | |
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| 352 | /* |
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| 353 | * If a context switch is necessary, then do fudge stack to |
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| 354 | * return to the interrupt dispatcher. |
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| 355 | */ |
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| 356 | |
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| 357 | ldub [%g7], %o5 |
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| 358 | |
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| 359 | orcc %o5, %g0, %g0 ! Is thread switch necessary? |
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| 360 | bz simple_return ! no, then do a simple return. otherwise fallthru |
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| 361 | nop |
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| 362 | |
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| 363 | /* |
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| 364 | * Invoke interrupt dispatcher. |
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| 365 | */ |
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| 366 | PUBLIC(_ISR_Dispatch) |
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| 367 | SYM(_ISR_Dispatch): |
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| 368 | ! Set ISR dispatch nesting prevention flag |
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| 369 | mov 1, %o1 |
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| 370 | setx SYM(_CPU_ISR_Dispatch_disable), %o5, %o2 |
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| 371 | stuw %o1, [%o2] |
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| 372 | |
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| 373 | |
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| 374 | ! **** ENABLE TRAPS **** |
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| 375 | wrpr %g0, SPARC_PSTATE_PRIV_MASK | SPARC_PSTATE_PEF_MASK | \ |
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| 376 | SPARC_PSTATE_IE_MASK, %pstate |
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| 377 | isr_dispatch: |
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| 378 | call SYM(_Thread_Dispatch), 0 |
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| 379 | nop |
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| 380 | |
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| 381 | /* |
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| 382 | * We invoked _Thread_Dispatch in a state similar to the interrupted |
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| 383 | * task. In order to safely be able to tinker with the register |
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| 384 | * windows and get the task back to its pre-interrupt state, |
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| 385 | * we need to disable interrupts. |
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| 386 | */ |
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| 387 | mov 2, %g4 ! syscall (disable interrupts) |
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| 388 | ta 0 ! syscall (disable interrupts) |
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| 389 | mov 0, %g4 |
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| 390 | |
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| 391 | /* |
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| 392 | * While we had ISR dispatching disabled in this thread, |
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| 393 | * did we miss anything. If so, then we need to do another |
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| 394 | * _Thread_Dispatch before leaving this ISR Dispatch context. |
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| 395 | */ |
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| 396 | |
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| 397 | setx DISPATCH_NEEDED, %o5, %o1 |
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| 398 | ldub [%o1], %o2 |
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| 399 | |
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| 400 | orcc %o2, %g0, %g0 ! Is thread switch necessary? |
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| 401 | bz allow_nest_again ! No, then clear out and return |
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| 402 | nop |
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| 403 | |
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| 404 | ! Yes, then invoke the dispatcher |
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| 405 | dispatchAgain: |
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| 406 | mov 3, %g4 ! syscall (enable interrupts) |
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| 407 | ta 0 ! syscall (enable interrupts) |
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| 408 | ba isr_dispatch |
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| 409 | mov 0, %g4 |
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| 410 | |
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| 411 | allow_nest_again: |
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| 412 | |
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| 413 | ! Zero out ISR stack nesting prevention flag |
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| 414 | setx SYM(_CPU_ISR_Dispatch_disable), %o5, %o1 |
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| 415 | stuw %g0,[%o1] |
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| 416 | |
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| 417 | /* |
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| 418 | * The CWP in place at this point may be different from |
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| 419 | * that which was in effect at the beginning of the ISR if we |
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| 420 | * have been context switched between the beginning of this invocation |
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| 421 | * of _ISR_Handler and this point. Thus the CWP and WIM should |
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| 422 | * not be changed back to their values at ISR entry time. Any |
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| 423 | * changes to the PSR must preserve the CWP. |
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| 424 | */ |
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| 425 | |
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| 426 | simple_return: |
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| 427 | flushw ! get register windows to a 'clean' state |
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| 428 | |
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| 429 | ! **** DISABLE TRAPS **** |
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| 430 | wrpr %g0, SPARC_PSTATE_PRIV_MASK, %pstate |
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| 431 | |
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| 432 | ldx [%sp + STACK_BIAS + ISF_Y_OFFSET], %o1 ! restore y |
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| 433 | wr %o1, 0, %y |
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| 434 | |
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| 435 | ldx [%sp + STACK_BIAS + ISF_TSTATE_OFFSET], %g1 |
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| 436 | |
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| 437 | ! see if cwp is proper (tstate.cwp == cwp) |
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| 438 | and %g1, 0x1F, %g6 |
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| 439 | rdpr %cwp, %g7 |
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| 440 | cmp %g6, %g7 |
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| 441 | bz good_window |
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| 442 | nop |
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| 443 | |
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| 444 | /* |
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| 445 | * Fix the CWP. Need the cwp to be the proper cwp that |
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| 446 | * gets restored when returning from the trap via retry/done. Do |
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| 447 | * this before reloading the task's output regs. Basically fake a |
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| 448 | * window spill/fill. |
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| 449 | * |
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| 450 | * Is this necessary on sun4v? Why not just re-write |
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| 451 | * tstate.cwp to be equal to the current cwp? |
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| 452 | */ |
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| 453 | mov %sp, %g1 |
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| 454 | stx %l0, [%sp + STACK_BIAS + CPU_STACK_FRAME_L0_OFFSET] |
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| 455 | stx %l1, [%sp + STACK_BIAS + CPU_STACK_FRAME_L1_OFFSET] |
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| 456 | stx %l2, [%sp + STACK_BIAS + CPU_STACK_FRAME_L2_OFFSET] |
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| 457 | stx %l3, [%sp + STACK_BIAS + CPU_STACK_FRAME_L3_OFFSET] |
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| 458 | stx %l4, [%sp + STACK_BIAS + CPU_STACK_FRAME_L4_OFFSET] |
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| 459 | stx %l5, [%sp + STACK_BIAS + CPU_STACK_FRAME_L5_OFFSET] |
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| 460 | stx %l6, [%sp + STACK_BIAS + CPU_STACK_FRAME_L6_OFFSET] |
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| 461 | stx %l7, [%sp + STACK_BIAS + CPU_STACK_FRAME_L7_OFFSET] |
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| 462 | stx %i0, [%sp + STACK_BIAS + CPU_STACK_FRAME_I0_OFFSET] |
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| 463 | stx %i1, [%sp + STACK_BIAS + CPU_STACK_FRAME_I1_OFFSET] |
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| 464 | stx %i2, [%sp + STACK_BIAS + CPU_STACK_FRAME_I2_OFFSET] |
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| 465 | stx %i3, [%sp + STACK_BIAS + CPU_STACK_FRAME_I3_OFFSET] |
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| 466 | stx %i4, [%sp + STACK_BIAS + CPU_STACK_FRAME_I4_OFFSET] |
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| 467 | stx %i5, [%sp + STACK_BIAS + CPU_STACK_FRAME_I5_OFFSET] |
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| 468 | stx %i6, [%sp + STACK_BIAS + CPU_STACK_FRAME_I6_FP_OFFSET] |
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| 469 | stx %i7, [%sp + STACK_BIAS + CPU_STACK_FRAME_I7_OFFSET] |
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| 470 | wrpr %g0, %g6, %cwp |
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| 471 | mov %g1, %sp |
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| 472 | ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_L0_OFFSET], %l0 |
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| 473 | ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_L1_OFFSET], %l1 |
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| 474 | ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_L2_OFFSET], %l2 |
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| 475 | ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_L3_OFFSET], %l3 |
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| 476 | ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_L4_OFFSET], %l4 |
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| 477 | ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_L5_OFFSET], %l5 |
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| 478 | ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_L6_OFFSET], %l6 |
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| 479 | ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_L7_OFFSET], %l7 |
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| 480 | ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_I0_OFFSET], %i0 |
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| 481 | ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_I1_OFFSET], %i1 |
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| 482 | ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_I2_OFFSET], %i2 |
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| 483 | ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_I3_OFFSET], %i3 |
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| 484 | ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_I4_OFFSET], %i4 |
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| 485 | ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_I5_OFFSET], %i5 |
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| 486 | ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_I6_FP_OFFSET], %i6 |
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| 487 | ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_I7_OFFSET], %i7 |
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| 488 | |
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| 489 | |
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| 490 | good_window: |
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| 491 | |
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| 492 | |
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| 493 | /* |
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| 494 | * Restore tasks global and out registers |
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| 495 | */ |
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| 496 | |
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| 497 | ldx [%sp + STACK_BIAS + ISF_G1_OFFSET], %g1 ! restore g1 |
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| 498 | ldx [%sp + STACK_BIAS + ISF_G2_OFFSET], %g2 ! restore g2 |
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| 499 | ldx [%sp + STACK_BIAS + ISF_G3_OFFSET], %g3 ! restore g3 |
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| 500 | ldx [%sp + STACK_BIAS + ISF_G4_OFFSET], %g4 ! restore g4 |
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| 501 | ldx [%sp + STACK_BIAS + ISF_G5_OFFSET], %g5 ! restore g5 |
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| 502 | ldx [%sp + STACK_BIAS + ISF_G6_OFFSET], %g6 ! restore g6 |
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| 503 | ldx [%sp + STACK_BIAS + ISF_G7_OFFSET], %g7 ! restore g7 |
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| 504 | |
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| 505 | ! Assume the interrupted context is in TL 0 with GL 0 / normal globals. |
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| 506 | ! When tstate is restored at done/retry, the interrupted context is restored. |
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| 507 | ! return to TL[1], GL[1], and restore TSTATE, TPC, and TNPC |
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| 508 | wrpr %g0, 1, %tl |
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| 509 | |
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| 510 | ! return to GL=1 or AG |
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| 511 | #if defined(SUN4U) |
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| 512 | rdpr %pstate, %o1 |
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| 513 | or %o1, SPARC_PSTATE_AG_MASK, %o1 |
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| 514 | wrpr %o1, %g0, %pstate ! go to AG. |
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| 515 | #elif defined(SUN4V) |
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| 516 | wrpr %g0, 1, %gl |
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| 517 | #endif |
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| 518 | |
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| 519 | ! now we can use global registers (at gl=1 or AG) |
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| 520 | ldx [%sp + STACK_BIAS + ISF_PIL_OFFSET], %g3 |
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| 521 | ldx [%sp + STACK_BIAS + ISF_TPC_OFFSET], %g4 |
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| 522 | ldx [%sp + STACK_BIAS + ISF_TNPC_OFFSET], %g5 |
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| 523 | ldx [%sp + STACK_BIAS + ISF_TSTATE_OFFSET], %g1 |
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| 524 | ldx [%sp + STACK_BIAS + ISF_TVEC_NUM], %g2 |
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| 525 | wrpr %g0, %g3, %pil |
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| 526 | wrpr %g0, %g4, %tpc |
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| 527 | wrpr %g0, %g5, %tnpc |
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| 528 | |
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| 529 | wrpr %g0, %g1, %tstate |
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| 530 | |
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| 531 | ldx [%sp + STACK_BIAS + ISF_O0_OFFSET], %o0 ! restore o0 |
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| 532 | ldx [%sp + STACK_BIAS + ISF_O1_OFFSET], %o1 ! restore o1 |
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| 533 | ldx [%sp + STACK_BIAS + ISF_O2_OFFSET], %o2 ! restore o2 |
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| 534 | ldx [%sp + STACK_BIAS + ISF_O3_OFFSET], %o3 ! restore o3 |
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| 535 | ldx [%sp + STACK_BIAS + ISF_O4_OFFSET], %o4 ! restore o4 |
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| 536 | ldx [%sp + STACK_BIAS + ISF_O5_OFFSET], %o5 ! restore o5 |
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| 537 | ! sp is restored later |
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| 538 | ldx [%sp + STACK_BIAS + ISF_O7_OFFSET], %o7 ! restore o7 |
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| 539 | |
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| 540 | ldx [%sp + STACK_BIAS + ISF_O6_SP_OFFSET], %o6 ! restore o6/sp |
|---|
| 541 | |
|---|
| 542 | /* |
|---|
| 543 | * Determine whether to re-execute the trapping instruction |
|---|
| 544 | * (asynchronous trap) or to skip the trapping instruction |
|---|
| 545 | * (synchronous trap). |
|---|
| 546 | */ |
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| 547 | |
|---|
| 548 | andcc %g2, SPARC_SYNCHRONOUS_TRAP_BIT_MASK, %g0 |
|---|
| 549 | ! Is this a synchronous trap? |
|---|
| 550 | be not_synch ! No, then skip trapping instruction |
|---|
| 551 | mov 0, %g4 |
|---|
| 552 | retry ! re-execute trapping instruction |
|---|
| 553 | not_synch: |
|---|
| 554 | done ! skip trapping instruction |
|---|
| 555 | |
|---|
| 556 | /* end of file */ |
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