source: rtems/c/src/lib/libcpu/sparc64/shared/score/interrupt.S @ c499856

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Last change on this file since c499856 was c499856, checked in by Chris Johns <chrisj@…>, on Mar 20, 2014 at 9:10:47 PM

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1/*  cpu_asm.s
2 *
3 *  This file contains the basic algorithms for all assembly code used
4 *  in an specific CPU port of RTEMS.  These algorithms must be implemented
5 *  in assembly language.
6 *
7 *  COPYRIGHT (c) 1989-2007.
8 *  On-Line Applications Research Corporation (OAR).
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.rtems.org/license/LICENSE.
13 *
14 *  Ported to ERC32 implementation of the SPARC by On-Line Applications
15 *  Research Corporation (OAR) under contract to the European Space
16 *  Agency (ESA).
17 *
18 *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
19 *  European Space Agency.
20 *
21 *  Ported to Niagara and UltraSPARC III (US3) implementations of the SPARC-v9.
22 *  Niagara and US3 modifications of respective RTEMS file:
23 *    COPYRIGHT (c) 2010. Gedare Bloom.
24 */
25
26#include <rtems/asm.h>
27#include <rtems/score/percpu.h>
28
29
30/*
31 *  The assembler needs to be told that we know what to do with
32 *  the global registers.
33 */
34.register %g2, #scratch
35.register %g3, #scratch
36.register %g6, #scratch
37.register %g7, #scratch
38
39
40    /*
41     *  void _ISR_Handler()
42     *
43     *  This routine provides the RTEMS interrupt management.
44     *
45     *  We enter this handler from the 8 instructions in the trap table with
46     *  the following registers assumed to be set as shown:
47     *
48     *    g4 = tstate (old l0)
49     *    g2 = trap type (vector) (old l3)
50     *
51     *  NOTE: By an executive defined convention:
52     *    if trap type is between 0 and 511 it is an asynchronous trap
53     *    if trap type is between 512 and 1023 it is an asynchonous trap
54     */
55
56  .align 4
57PUBLIC(_ISR_Handler)
58  SYM(_ISR_Handler):
59
60    /*
61     * The ISR is called at TL = 1.
62     * On sun4u we use the alternate globals set.     
63     *
64     * On entry:
65     *   g4 = tstate (from trap table)
66     *   g2 = trap vector #
67     *
68     * In either case, note that trap handlers share a register window with
69     * the interrupted context, unless we explicitly enter a new window. This
70     * differs from Sparc v8, in which a dedicated register window is saved
71     * for trap handling.  This means we have to avoid overwriting any registers
72     * that we don't save.
73     *
74     */
75
76
77    /*
78     *  save some or all context on stack
79     */
80
81    /*
82     *  Save the state of the interrupted task -- especially the global
83     *  registers -- in the Interrupt Stack Frame.  Note that the ISF
84     *  includes a regular minimum stack frame which will be used if
85     *  needed by register window overflow and underflow handlers.
86     *
87     *  This is slightly wasteful, since the stack already has the window
88     *  overflow space reserved, but there is no obvious way to ensure
89     *  we can store the interrupted state and still handle window
90     *  spill/fill correctly, since there is no room for the ISF.
91     *
92     */
93
94    /* this is for debugging purposes, make sure that TL = 1, otherwise
95     * things might get dicey */
96    rdpr %tl, %g1
97    cmp %g1, 1
98    be 1f
99    nop
100
101    0: ba 0b
102    nop
103
104    1:
105    /* first store the sp of the interrupted task temporarily in g1 */
106    mov   %sp, %g1
107
108    sub     %sp, CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE, %sp
109    ! make space for Stack_Frame||ISF
110
111    /* save tstate, tpc, tnpc, pil */
112    stx   %g4, [%sp + STACK_BIAS + ISF_TSTATE_OFFSET] 
113    rdpr  %pil, %g3
114    rdpr  %tpc, %g4
115    rdpr  %tnpc, %g5
116    stx   %g3, [%sp + STACK_BIAS + ISF_PIL_OFFSET]
117    stx   %g4, [%sp + STACK_BIAS + ISF_TPC_OFFSET]
118    stx   %g5, [%sp + STACK_BIAS + ISF_TNPC_OFFSET]
119    stx   %g2, [%sp + STACK_BIAS + ISF_TVEC_OFFSET]
120
121    rd  %y, %g4        ! save y
122    stx   %g4, [%sp + STACK_BIAS + ISF_Y_OFFSET]
123
124    ! save interrupted frame's output regs
125    stx     %o0, [%sp + STACK_BIAS + ISF_O0_OFFSET]     ! save o0
126    stx     %o1, [%sp + STACK_BIAS + ISF_O1_OFFSET]     ! save o1
127    stx     %o2, [%sp + STACK_BIAS + ISF_O2_OFFSET]     ! save o2
128    stx     %o3, [%sp + STACK_BIAS + ISF_O3_OFFSET]     ! save o3
129    stx     %o4, [%sp + STACK_BIAS + ISF_O4_OFFSET]     ! save o4
130    stx     %o5, [%sp + STACK_BIAS + ISF_O5_OFFSET]     ! save o5
131    stx     %g1, [%sp + STACK_BIAS + ISF_O6_SP_OFFSET]  ! save o6/sp
132    stx     %o7, [%sp + STACK_BIAS + ISF_O7_OFFSET]     ! save o7
133
134    mov  %g1, %o5    ! hold the old sp here for now
135    mov  %g2, %o1    ! we'll need trap # later
136
137    /* switch to TL[0] */
138    wrpr  %g0, 0, %tl
139
140    /* switch to normal globals */
141#if defined (SUN4U)
142    /* the assignment to pstate below will mask out the AG bit */
143#elif defined (SUN4V)
144    wrpr  %g0, 0, %gl
145#endif
146    /* get pstate to known state */
147    wrpr  %g0, SPARC_PSTATE_PRIV_MASK | SPARC_PSTATE_PEF_MASK, %pstate
148
149    ! save globals
150    stx     %g1, [%sp + STACK_BIAS + ISF_G1_OFFSET]     ! save g1
151    stx     %g2, [%sp + STACK_BIAS + ISF_G2_OFFSET]     ! save g2
152    stx     %g3, [%sp + STACK_BIAS + ISF_G3_OFFSET]     ! save g3
153    stx     %g4, [%sp + STACK_BIAS + ISF_G4_OFFSET]     ! save g4
154    stx     %g5, [%sp + STACK_BIAS + ISF_G5_OFFSET]     ! save g5
155    stx     %g6, [%sp + STACK_BIAS + ISF_G6_OFFSET]     ! save g6
156    stx     %g7, [%sp + STACK_BIAS + ISF_G7_OFFSET]     ! save g7
157
158
159  mov  %o1, %g2  ! get the trap #
160  mov  %o5, %g7  ! store the interrupted %sp (preserve)
161  mov  %sp, %o1  ! 2nd arg to ISR Handler = address of ISF
162  add  %o1, STACK_BIAS, %o1 ! need to adjust for stack bias, 2nd arg = ISF
163
164  /*
165   *  Increment ISR nest level and Thread dispatch disable level.
166   *
167   *  Register usage for this section: (note, these are used later)
168   *
169   *    g3 = _Thread_Dispatch_disable_level pointer
170   *    g5 = _Thread_Dispatch_disable_level value (uint32_t)
171   *    g6 = _ISR_Nest_level pointer
172   *    g4 = _ISR_Nest_level value (uint32_t)
173   *    o5 = temp
174   *
175   *  NOTE: It is assumed that g6 - g7 will be preserved until the ISR
176   *        nest and thread dispatch disable levels are unnested.
177   */
178
179  setx  THREAD_DISPATCH_DISABLE_LEVEL, %o5, %g3
180  lduw  [%g3], %g5
181  setx  ISR_NEST_LEVEL, %o5, %g6
182  lduw  [%g6], %g4
183
184  add      %g5, 1, %g5
185  stuw     %g5, [%g3]
186
187  add      %g4, 1, %g4
188  stuw     %g4, [%g6]
189
190  /*
191   *  If ISR nest level was zero (now 1), then switch stack.
192   */
193
194  subcc    %g4, 1, %g4             ! outermost interrupt handler?
195  bnz      dont_switch_stacks      ! No, then do not switch stacks
196
197  setx  SYM(INTERRUPT_STACK_HIGH), %o5, %g1
198  ldx  [%g1], %sp
199
200  /*
201   * Adjust the stack for the stack bias
202   */
203  sub     %sp, STACK_BIAS, %sp
204
205  /*
206   *  Make sure we have a place on the stack for the window overflow
207   *  trap handler to write into.  At this point it is safe to
208   *  enable traps again.
209   */
210
211  sub      %sp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
212
213  dont_switch_stacks:
214  /*
215   *  Check if we have an external interrupt (trap 0x41 - 0x4f). If so,
216   *  set the PIL to mask off interrupts with lower priority.
217   *
218   *  The original PIL is not modified since it will be restored
219   *  when the interrupt handler returns.
220   */
221
222  and      %g2, 0x0ff, %g1 ! is bottom byte of vector number [0x41,0x4f]?
223
224  subcc    %g1, 0x41, %g0
225  bl       dont_fix_pil
226  subcc    %g1, 0x4f, %g0
227  bg       dont_fix_pil
228  nop
229  wrpr     %g0, %g1, %pil
230
231  dont_fix_pil:
232  /* We need to be careful about enabling traps here.
233   *
234   * We already stored off the tstate, tpc, and tnpc, and switched to
235   * TL = 0, so it should be safe.
236   */
237
238  /* zero out g4 so that ofw calls work */
239  mov  %g0, %g4
240
241  ! **** ENABLE TRAPS ****
242  wrpr  %g0, SPARC_PSTATE_PRIV_MASK | SPARC_PSTATE_PEF_MASK | \
243    SPARC_PSTATE_IE_MASK, %pstate
244
245    /*
246     *  Vector to user's handler.
247     *
248     *  NOTE: TBR may no longer have vector number in it since
249     *        we just enabled traps.  It is definitely in g2.
250     */
251    setx  SYM(_ISR_Vector_table), %o5, %g1
252    ldx      [%g1], %g1
253    and      %g2, 0x1FF, %o5        ! remove synchronous trap indicator
254    sll      %o5, 3, %o5            ! o5 = offset into table
255    ldx      [%g1 + %o5], %g1       ! g1 = _ISR_Vector_table[ vector ]
256
257
258    ! o1 = 2nd arg = address of the ISF
259    !   WAS LOADED WHEN ISF WAS SAVED!!!
260    mov      %g2, %o0               ! o0 = 1st arg = vector number
261    call     %g1, 0
262    nop                             ! delay slot
263
264    /*
265     *  Redisable traps so we can finish up the interrupt processing.
266     *  This is a conservative place to do this.
267     */
268    ! **** DISABLE TRAPS ****
269    wrpr  %g0, SPARC_PSTATE_PRIV_MASK, %pstate
270
271    /*
272     * We may safely use any of the %o and %g registers, because
273     * we saved them earlier (and any other interrupt that uses
274     * them will also save them).  Right now, the state of those
275     * registers are as follows:
276     *  %o registers: unknown (user's handler may have destroyed)
277     *  %g1,g4,g5: scratch
278     *  %g2: unknown: was trap vector
279     *  %g3: uknown: was _Thread_Dispatch_Disable_level pointer
280     *  %g6: _ISR_Nest_level
281     *  %g7: interrupted task's sp
282     */
283
284    /*
285     *  Increment ISR nest level and Thread dispatch disable level.
286     *
287     *  Register usage for this section: (note: as used above)
288     *
289     *    g3 = _Thread_Dispatch_disable_level pointer
290     *    g5 = _Thread_Dispatch_disable_level value
291     *    g6 = _ISR_Nest_level pointer
292     *    g4 = _ISR_Nest_level value
293     *    o5 = temp
294     */
295
296    /* We have to re-load the values from memory, because there are
297     * not enough registers that we know will be preserved across the
298     * user's handler. If this is a problem, we can create a register
299     * window for _ISR_Handler.
300     */
301
302    setx  THREAD_DISPATCH_DISABLE_LEVEL, %o5, %g3
303    lduw  [%g3],%g5
304    lduw  [%g6],%g4
305    sub   %g5, 1, %g5
306    stuw  %g5, [%g3]
307    sub   %g4, 1, %g4
308    stuw  %g4, [%g6]
309
310    orcc  %g4, %g0, %g0           ! ISRs still nested?
311    bnz   dont_restore_stack      ! Yes then don't restore stack yet
312    nop
313
314    /*
315     *  This is the outermost interrupt handler. Need to get off the
316     *  CPU Interrupt Stack and back to the tasks stack.
317     *
318     *  The following subtract should get us back on the interrupted
319     *  tasks stack and add enough room to invoke the dispatcher.
320     *  When we enable traps, we are mostly back in the context
321     *  of the task and subsequent interrupts can operate normally.
322     *
323     *  Now %sp points to the bottom of the ISF.
324     * 
325     */
326
327    sub      %g7,   CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE, %sp
328
329    dont_restore_stack:
330
331    /*
332     *  If dispatching is disabled (includes nested interrupt case),
333     *  then do a "simple" exit.
334     */
335
336    orcc     %g5, %g0, %g0   ! Is dispatching disabled?
337    bnz      simple_return   ! Yes, then do a "simple" exit
338    ! NOTE: Use the delay slot
339    mov      %g0, %g4  ! clear g4 for ofw
340
341    ! Are we dispatching from a previous ISR in the interrupted thread?
342    setx  SYM(_CPU_ISR_Dispatch_disable), %o5, %g5
343    lduw     [%g5], %o5
344    orcc     %o5, %g0, %g0   ! Is this thread already doing an ISR?
345    bnz      simple_return   ! Yes, then do a "simple" exit
346    nop
347
348    setx    DISPATCH_NEEDED, %o5, %g7
349
350
351    /*
352     *  If a context switch is necessary, then do fudge stack to
353     *  return to the interrupt dispatcher.
354     */
355
356    ldub     [%g7], %o5
357
358    orcc     %o5, %g0, %g0   ! Is thread switch necessary?
359    bz       simple_return   ! no, then do a simple return. otherwise fallthru
360    nop
361
362    /*
363     *  Invoke interrupt dispatcher.
364     */
365PUBLIC(_ISR_Dispatch)
366  SYM(_ISR_Dispatch):
367    ! Set ISR dispatch nesting prevention flag
368      mov      1, %o1
369      setx     SYM(_CPU_ISR_Dispatch_disable), %o5, %o2
370      stuw     %o1, [%o2]
371
372
373      !  **** ENABLE TRAPS ****
374      wrpr  %g0, SPARC_PSTATE_PRIV_MASK | SPARC_PSTATE_PEF_MASK | \
375        SPARC_PSTATE_IE_MASK, %pstate
376        isr_dispatch:
377        call    SYM(_Thread_Dispatch), 0
378        nop
379
380        /*
381         *  We invoked _Thread_Dispatch in a state similar to the interrupted
382         *  task.  In order to safely be able to tinker with the register
383         *  windows and get the task back to its pre-interrupt state,
384         *  we need to disable interrupts.
385         */
386      mov   2, %g4        ! syscall (disable interrupts)
387      ta    0             ! syscall (disable interrupts)
388      mov   0, %g4
389
390  /*
391   *  While we had ISR dispatching disabled in this thread,
392   *  did we miss anything.  If so, then we need to do another
393   *  _Thread_Dispatch before leaving this ISR Dispatch context.
394   */
395
396  setx     DISPATCH_NEEDED, %o5, %o1
397  ldub     [%o1], %o2
398
399  orcc     %o2, %g0, %g0   ! Is thread switch necessary?
400  bz       allow_nest_again ! No, then clear out and return
401  nop
402
403  ! Yes, then invoke the dispatcher
404dispatchAgain:
405  mov      3, %g4        ! syscall (enable interrupts)
406  ta       0             ! syscall (enable interrupts)
407  ba       isr_dispatch
408  mov      0, %g4
409
410  allow_nest_again:
411
412  ! Zero out ISR stack nesting prevention flag
413  setx    SYM(_CPU_ISR_Dispatch_disable), %o5, %o1
414  stuw    %g0,[%o1]
415
416  /*
417   *  The CWP in place at this point may be different from
418   *  that which was in effect at the beginning of the ISR if we
419   *  have been context switched between the beginning of this invocation
420   *  of _ISR_Handler and this point.  Thus the CWP and WIM should
421   *  not be changed back to their values at ISR entry time.  Any
422   *  changes to the PSR must preserve the CWP.
423   */
424
425  simple_return:
426  flushw          ! get register windows to a 'clean' state
427
428  ! **** DISABLE TRAPS ****
429  wrpr    %g0, SPARC_PSTATE_PRIV_MASK, %pstate
430
431  ldx     [%sp + STACK_BIAS + ISF_Y_OFFSET], %o1      ! restore y
432  wr      %o1, 0, %y
433
434  ldx  [%sp + STACK_BIAS + ISF_TSTATE_OFFSET], %g1
435
436! see if cwp is proper (tstate.cwp == cwp)
437  and  %g1, 0x1F, %g6
438  rdpr  %cwp, %g7
439  cmp  %g6, %g7
440  bz  good_window
441  nop
442
443  /*
444   * Fix the CWP. Need the cwp to be the proper cwp that
445   * gets restored when returning from the trap via retry/done. Do
446   * this before reloading the task's output regs. Basically fake a
447   * window spill/fill.
448   *
449   * Is this necessary on sun4v? Why not just re-write
450   * tstate.cwp to be equal to the current cwp?
451   */
452  mov  %sp, %g1
453  stx  %l0, [%sp + STACK_BIAS + CPU_STACK_FRAME_L0_OFFSET]
454  stx  %l1, [%sp + STACK_BIAS + CPU_STACK_FRAME_L1_OFFSET]
455  stx  %l2, [%sp + STACK_BIAS + CPU_STACK_FRAME_L2_OFFSET]
456  stx  %l3, [%sp + STACK_BIAS + CPU_STACK_FRAME_L3_OFFSET]
457  stx  %l4, [%sp + STACK_BIAS + CPU_STACK_FRAME_L4_OFFSET]
458  stx  %l5, [%sp + STACK_BIAS + CPU_STACK_FRAME_L5_OFFSET]
459  stx  %l6, [%sp + STACK_BIAS + CPU_STACK_FRAME_L6_OFFSET]
460  stx  %l7, [%sp + STACK_BIAS + CPU_STACK_FRAME_L7_OFFSET]
461  stx  %i0, [%sp + STACK_BIAS + CPU_STACK_FRAME_I0_OFFSET]
462  stx  %i1, [%sp + STACK_BIAS + CPU_STACK_FRAME_I1_OFFSET]
463  stx  %i2, [%sp + STACK_BIAS + CPU_STACK_FRAME_I2_OFFSET]
464  stx  %i3, [%sp + STACK_BIAS + CPU_STACK_FRAME_I3_OFFSET]
465  stx  %i4, [%sp + STACK_BIAS + CPU_STACK_FRAME_I4_OFFSET]
466  stx  %i5, [%sp + STACK_BIAS + CPU_STACK_FRAME_I5_OFFSET]
467  stx  %i6, [%sp + STACK_BIAS + CPU_STACK_FRAME_I6_FP_OFFSET]
468  stx  %i7, [%sp + STACK_BIAS + CPU_STACK_FRAME_I7_OFFSET]
469  wrpr  %g0, %g6, %cwp
470  mov  %g1, %sp
471  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_L0_OFFSET], %l0
472  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_L1_OFFSET], %l1
473  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_L2_OFFSET], %l2
474  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_L3_OFFSET], %l3
475  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_L4_OFFSET], %l4
476  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_L5_OFFSET], %l5
477  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_L6_OFFSET], %l6
478  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_L7_OFFSET], %l7
479  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_I0_OFFSET], %i0
480  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_I1_OFFSET], %i1
481  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_I2_OFFSET], %i2
482  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_I3_OFFSET], %i3
483  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_I4_OFFSET], %i4
484  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_I5_OFFSET], %i5
485  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_I6_FP_OFFSET], %i6
486  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_I7_OFFSET], %i7
487
488
489  good_window:
490
491
492  /*
493   *  Restore tasks global and out registers
494   */
495
496  ldx     [%sp + STACK_BIAS + ISF_G1_OFFSET], %g1    ! restore g1
497  ldx     [%sp + STACK_BIAS + ISF_G2_OFFSET], %g2    ! restore g2
498  ldx     [%sp + STACK_BIAS + ISF_G3_OFFSET], %g3    ! restore g3
499  ldx     [%sp + STACK_BIAS + ISF_G4_OFFSET], %g4    ! restore g4
500  ldx     [%sp + STACK_BIAS + ISF_G5_OFFSET], %g5    ! restore g5
501  ldx     [%sp + STACK_BIAS + ISF_G6_OFFSET], %g6    ! restore g6
502  ldx     [%sp + STACK_BIAS + ISF_G7_OFFSET], %g7    ! restore g7
503
504  ! Assume the interrupted context is in TL 0 with GL 0 / normal globals.
505  ! When tstate is restored at done/retry, the interrupted context is restored.
506  ! return to TL[1], GL[1], and restore TSTATE, TPC, and TNPC
507  wrpr  %g0, 1, %tl
508
509  ! return to GL=1 or AG
510#if defined(SUN4U)
511    rdpr  %pstate, %o1
512    or  %o1, SPARC_PSTATE_AG_MASK, %o1
513    wrpr  %o1, %g0, %pstate                 ! go to AG.
514#elif defined(SUN4V)
515  wrpr  %g0, 1, %gl
516#endif
517
518! now we can use global registers (at gl=1 or AG)
519  ldx   [%sp + STACK_BIAS + ISF_PIL_OFFSET], %g3
520  ldx   [%sp + STACK_BIAS + ISF_TPC_OFFSET], %g4
521  ldx   [%sp + STACK_BIAS + ISF_TNPC_OFFSET], %g5
522  ldx   [%sp + STACK_BIAS + ISF_TSTATE_OFFSET], %g1
523  ldx   [%sp + STACK_BIAS + ISF_TVEC_OFFSET], %g2
524  wrpr  %g0, %g3, %pil
525  wrpr  %g0, %g4, %tpc
526  wrpr  %g0, %g5, %tnpc
527
528  wrpr    %g0, %g1, %tstate
529
530  ldx     [%sp + STACK_BIAS + ISF_O0_OFFSET], %o0    ! restore o0
531  ldx     [%sp + STACK_BIAS + ISF_O1_OFFSET], %o1    ! restore o1
532  ldx     [%sp + STACK_BIAS + ISF_O2_OFFSET], %o2    ! restore o2
533  ldx     [%sp + STACK_BIAS + ISF_O3_OFFSET], %o3    ! restore o3
534  ldx     [%sp + STACK_BIAS + ISF_O4_OFFSET], %o4    ! restore o4
535  ldx     [%sp + STACK_BIAS + ISF_O5_OFFSET], %o5    ! restore o5
536  ! sp is restored later
537  ldx     [%sp + STACK_BIAS + ISF_O7_OFFSET], %o7    ! restore o7
538
539  ldx     [%sp + STACK_BIAS + ISF_O6_SP_OFFSET], %o6 ! restore o6/sp
540
541  /*
542   *  Determine whether to re-execute the trapping instruction
543   *  (asynchronous trap) or to skip the trapping instruction
544   *  (synchronous trap).
545   */
546
547  andcc   %g2, SPARC_SYNCHRONOUS_TRAP_BIT_MASK, %g0
548  ! Is this a synchronous trap?
549  be  not_synch             ! No, then skip trapping instruction
550  mov  0, %g4
551  retry        ! re-execute trapping instruction
552  not_synch:
553  done        ! skip trapping instruction
554
555/* end of file */
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