source: rtems/c/src/lib/libcpu/sparc64/shared/score/interrupt.S @ 71d97c9

4.115
Last change on this file since 71d97c9 was 71d97c9, checked in by Gedare Bloom <gedare@…>, on Dec 8, 2014 at 6:16:37 PM

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1/*  cpu_asm.s
2 *
3 *  This file contains the basic algorithms for all assembly code used
4 *  in an specific CPU port of RTEMS.  These algorithms must be implemented
5 *  in assembly language.
6 *
7 *  COPYRIGHT (c) 1989-2007. On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.rtems.org/license/LICENSE.
12 *
13 *  Ported to ERC32 implementation of the SPARC by On-Line Applications
14 *  Research Corporation (OAR) under contract to the European Space
15 *  Agency (ESA).
16 *
17 *  ERC32 modifications of respective RTEMS file:
18 *  COPYRIGHT (c) 1995. European Space Agency.
19 *
20 *  Ported to Niagara and UltraSPARC III (US3) implementations of the SPARC-v9.
21 *  Niagara and US3 modifications of respective RTEMS file:
22 *  COPYRIGHT (c) 2010. Gedare Bloom.
23 */
24
25#include <rtems/asm.h>
26#include <rtems/score/percpu.h>
27
28
29/*
30 *  The assembler needs to be told that we know what to do with
31 *  the global registers.
32 */
33.register %g2, #scratch
34.register %g3, #scratch
35.register %g6, #scratch
36.register %g7, #scratch
37
38
39    /*
40     *  void _ISR_Handler()
41     *
42     *  This routine provides the RTEMS interrupt management.
43     *
44     *  We enter this handler from the 8 instructions in the trap table with
45     *  the following registers assumed to be set as shown:
46     *
47     *    g4 = tstate (old l0)
48     *    g2 = trap type (vector) (old l3)
49     *
50     *  NOTE: By an executive defined convention:
51     *    if trap type is between 0 and 511 it is an asynchronous trap
52     *    if trap type is between 512 and 1023 it is an asynchonous trap
53     */
54
55  .align 4
56PUBLIC(_ISR_Handler)
57  SYM(_ISR_Handler):
58
59    /*
60     * The ISR is called at TL = 1.
61     * On sun4u we use the alternate globals set.     
62     *
63     * On entry:
64     *   g4 = tstate (from trap table)
65     *   g2 = trap vector #
66     *
67     * In either case, note that trap handlers share a register window with
68     * the interrupted context, unless we explicitly enter a new window. This
69     * differs from Sparc v8, in which a dedicated register window is saved
70     * for trap handling.  This means we have to avoid overwriting any registers
71     * that we don't save.
72     *
73     */
74
75
76    /*
77     *  save some or all context on stack
78     */
79
80    /*
81     *  Save the state of the interrupted task -- especially the global
82     *  registers -- in the Interrupt Stack Frame.  Note that the ISF
83     *  includes a regular minimum stack frame which will be used if
84     *  needed by register window overflow and underflow handlers.
85     *
86     *  This is slightly wasteful, since the stack already has the window
87     *  overflow space reserved, but there is no obvious way to ensure
88     *  we can store the interrupted state and still handle window
89     *  spill/fill correctly, since there is no room for the ISF.
90     *
91     */
92
93    /* this is for debugging purposes, make sure that TL = 1, otherwise
94     * things might get dicey */
95    rdpr %tl, %g1
96    cmp %g1, 1
97    be 1f
98    nop
99
100    0: ba 0b
101    nop
102
103    1:
104    /* first store the sp of the interrupted task temporarily in g1 */
105    mov   %sp, %g1
106
107    sub     %sp, CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE, %sp
108    ! make space for Stack_Frame||ISF
109
110    /* save tstate, tpc, tnpc, pil */
111    stx   %g4, [%sp + STACK_BIAS + ISF_TSTATE_OFFSET] 
112    rdpr  %pil, %g3
113    rdpr  %tpc, %g4
114    rdpr  %tnpc, %g5
115    stx   %g3, [%sp + STACK_BIAS + ISF_PIL_OFFSET]
116    stx   %g4, [%sp + STACK_BIAS + ISF_TPC_OFFSET]
117    stx   %g5, [%sp + STACK_BIAS + ISF_TNPC_OFFSET]
118    stx   %g2, [%sp + STACK_BIAS + ISF_TVEC_OFFSET]
119
120    rd  %y, %g4        ! save y
121    stx   %g4, [%sp + STACK_BIAS + ISF_Y_OFFSET]
122
123    ! save interrupted frame's output regs
124    stx     %o0, [%sp + STACK_BIAS + ISF_O0_OFFSET]     ! save o0
125    stx     %o1, [%sp + STACK_BIAS + ISF_O1_OFFSET]     ! save o1
126    stx     %o2, [%sp + STACK_BIAS + ISF_O2_OFFSET]     ! save o2
127    stx     %o3, [%sp + STACK_BIAS + ISF_O3_OFFSET]     ! save o3
128    stx     %o4, [%sp + STACK_BIAS + ISF_O4_OFFSET]     ! save o4
129    stx     %o5, [%sp + STACK_BIAS + ISF_O5_OFFSET]     ! save o5
130    stx     %g1, [%sp + STACK_BIAS + ISF_O6_SP_OFFSET]  ! save o6/sp
131    stx     %o7, [%sp + STACK_BIAS + ISF_O7_OFFSET]     ! save o7
132
133    mov  %g1, %o5    ! hold the old sp here for now
134    mov  %g2, %o1    ! we'll need trap # later
135
136    /* switch to TL[0] */
137    wrpr  %g0, 0, %tl
138
139    /* switch to normal globals */
140#if defined (SUN4U)
141    /* the assignment to pstate below will mask out the AG bit */
142#elif defined (SUN4V)
143    wrpr  %g0, 0, %gl
144#endif
145    /* get pstate to known state */
146    wrpr  %g0, SPARC_PSTATE_PRIV_MASK | SPARC_PSTATE_PEF_MASK, %pstate
147
148    ! save globals
149    stx     %g1, [%sp + STACK_BIAS + ISF_G1_OFFSET]     ! save g1
150    stx     %g2, [%sp + STACK_BIAS + ISF_G2_OFFSET]     ! save g2
151    stx     %g3, [%sp + STACK_BIAS + ISF_G3_OFFSET]     ! save g3
152    stx     %g4, [%sp + STACK_BIAS + ISF_G4_OFFSET]     ! save g4
153    stx     %g5, [%sp + STACK_BIAS + ISF_G5_OFFSET]     ! save g5
154    stx     %g6, [%sp + STACK_BIAS + ISF_G6_OFFSET]     ! save g6
155    stx     %g7, [%sp + STACK_BIAS + ISF_G7_OFFSET]     ! save g7
156
157
158  mov  %o1, %g2  ! get the trap #
159  mov  %o5, %g7  ! store the interrupted %sp (preserve)
160  mov  %sp, %o1  ! 2nd arg to ISR Handler = address of ISF
161  add  %o1, STACK_BIAS, %o1 ! need to adjust for stack bias, 2nd arg = ISF
162
163  /*
164   *  Increment ISR nest level and Thread dispatch disable level.
165   *
166   *  Register usage for this section: (note, these are used later)
167   *
168   *    g3 = _Thread_Dispatch_disable_level pointer
169   *    g5 = _Thread_Dispatch_disable_level value (uint32_t)
170   *    g6 = _ISR_Nest_level pointer
171   *    g4 = _ISR_Nest_level value (uint32_t)
172   *    o5 = temp
173   *
174   *  NOTE: It is assumed that g6 - g7 will be preserved until the ISR
175   *        nest and thread dispatch disable levels are unnested.
176   */
177
178  setx  THREAD_DISPATCH_DISABLE_LEVEL, %o5, %g3
179  lduw  [%g3], %g5
180  setx  ISR_NEST_LEVEL, %o5, %g6
181  lduw  [%g6], %g4
182
183  add      %g5, 1, %g5
184  stuw     %g5, [%g3]
185
186  add      %g4, 1, %g4
187  stuw     %g4, [%g6]
188
189  /*
190   *  If ISR nest level was zero (now 1), then switch stack.
191   */
192
193  subcc    %g4, 1, %g4             ! outermost interrupt handler?
194  bnz      dont_switch_stacks      ! No, then do not switch stacks
195
196  setx  SYM(INTERRUPT_STACK_HIGH), %o5, %g1
197  ldx  [%g1], %sp
198
199  /*
200   * Adjust the stack for the stack bias
201   */
202  sub     %sp, STACK_BIAS, %sp
203
204  /*
205   *  Make sure we have a place on the stack for the window overflow
206   *  trap handler to write into.  At this point it is safe to
207   *  enable traps again.
208   */
209
210  sub      %sp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
211
212  dont_switch_stacks:
213  /*
214   *  Check if we have an external interrupt (trap 0x41 - 0x4f). If so,
215   *  set the PIL to mask off interrupts with lower priority.
216   *
217   *  The original PIL is not modified since it will be restored
218   *  when the interrupt handler returns.
219   */
220
221  and      %g2, 0x0ff, %g1 ! is bottom byte of vector number [0x41,0x4f]?
222
223  subcc    %g1, 0x41, %g0
224  bl       dont_fix_pil
225  subcc    %g1, 0x4f, %g0
226  bg       dont_fix_pil
227  nop
228  wrpr     %g0, %g1, %pil
229
230  dont_fix_pil:
231  /* We need to be careful about enabling traps here.
232   *
233   * We already stored off the tstate, tpc, and tnpc, and switched to
234   * TL = 0, so it should be safe.
235   */
236
237  /* zero out g4 so that ofw calls work */
238  mov  %g0, %g4
239
240  ! **** ENABLE TRAPS ****
241  wrpr  %g0, SPARC_PSTATE_PRIV_MASK | SPARC_PSTATE_PEF_MASK | \
242    SPARC_PSTATE_IE_MASK, %pstate
243
244    /*
245     *  Vector to user's handler.
246     *
247     *  NOTE: TBR may no longer have vector number in it since
248     *        we just enabled traps.  It is definitely in g2.
249     */
250    setx  SYM(_ISR_Vector_table), %o5, %g1
251    and      %g2, 0x1FF, %o5        ! remove synchronous trap indicator
252    sll      %o5, 3, %o5            ! o5 = offset into table
253    ldx      [%g1 + %o5], %g1       ! g1 = _ISR_Vector_table[ vector ]
254
255
256    ! o1 = 2nd arg = address of the ISF
257    !   WAS LOADED WHEN ISF WAS SAVED!!!
258    mov      %g2, %o0               ! o0 = 1st arg = vector number
259    call     %g1, 0
260    nop                             ! delay slot
261
262    /*
263     *  Redisable traps so we can finish up the interrupt processing.
264     *  This is a conservative place to do this.
265     */
266    ! **** DISABLE TRAPS ****
267    wrpr  %g0, SPARC_PSTATE_PRIV_MASK, %pstate
268
269    /*
270     * We may safely use any of the %o and %g registers, because
271     * we saved them earlier (and any other interrupt that uses
272     * them will also save them).  Right now, the state of those
273     * registers are as follows:
274     *  %o registers: unknown (user's handler may have destroyed)
275     *  %g1,g4,g5: scratch
276     *  %g2: unknown: was trap vector
277     *  %g3: uknown: was _Thread_Dispatch_Disable_level pointer
278     *  %g6: _ISR_Nest_level
279     *  %g7: interrupted task's sp
280     */
281
282    /*
283     *  Increment ISR nest level and Thread dispatch disable level.
284     *
285     *  Register usage for this section: (note: as used above)
286     *
287     *    g3 = _Thread_Dispatch_disable_level pointer
288     *    g5 = _Thread_Dispatch_disable_level value
289     *    g6 = _ISR_Nest_level pointer
290     *    g4 = _ISR_Nest_level value
291     *    o5 = temp
292     */
293
294    /* We have to re-load the values from memory, because there are
295     * not enough registers that we know will be preserved across the
296     * user's handler. If this is a problem, we can create a register
297     * window for _ISR_Handler.
298     */
299
300    setx  THREAD_DISPATCH_DISABLE_LEVEL, %o5, %g3
301    lduw  [%g3],%g5
302    lduw  [%g6],%g4
303    sub   %g5, 1, %g5
304    stuw  %g5, [%g3]
305    sub   %g4, 1, %g4
306    stuw  %g4, [%g6]
307
308    orcc  %g4, %g0, %g0           ! ISRs still nested?
309    bnz   dont_restore_stack      ! Yes then don't restore stack yet
310    nop
311
312    /*
313     *  This is the outermost interrupt handler. Need to get off the
314     *  CPU Interrupt Stack and back to the tasks stack.
315     *
316     *  The following subtract should get us back on the interrupted
317     *  tasks stack and add enough room to invoke the dispatcher.
318     *  When we enable traps, we are mostly back in the context
319     *  of the task and subsequent interrupts can operate normally.
320     *
321     *  Now %sp points to the bottom of the ISF.
322     * 
323     */
324
325    sub      %g7,   CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE, %sp
326
327    dont_restore_stack:
328
329    /*
330     *  If dispatching is disabled (includes nested interrupt case),
331     *  then do a "simple" exit.
332     */
333
334    orcc     %g5, %g0, %g0   ! Is dispatching disabled?
335    bnz      simple_return   ! Yes, then do a "simple" exit
336    ! NOTE: Use the delay slot
337    mov      %g0, %g4  ! clear g4 for ofw
338
339    ! Are we dispatching from a previous ISR in the interrupted thread?
340    setx  SYM(_CPU_ISR_Dispatch_disable), %o5, %g5
341    lduw     [%g5], %o5
342    orcc     %o5, %g0, %g0   ! Is this thread already doing an ISR?
343    bnz      simple_return   ! Yes, then do a "simple" exit
344    nop
345
346    setx    DISPATCH_NEEDED, %o5, %g7
347
348
349    /*
350     *  If a context switch is necessary, then do fudge stack to
351     *  return to the interrupt dispatcher.
352     */
353
354    ldub     [%g7], %o5
355
356    orcc     %o5, %g0, %g0   ! Is thread switch necessary?
357    bz       simple_return   ! no, then do a simple return. otherwise fallthru
358    nop
359
360    /*
361     *  Invoke interrupt dispatcher.
362     */
363PUBLIC(_ISR_Dispatch)
364  SYM(_ISR_Dispatch):
365    ! Set ISR dispatch nesting prevention flag
366      mov      1, %o1
367      setx     SYM(_CPU_ISR_Dispatch_disable), %o5, %o2
368      stuw     %o1, [%o2]
369
370
371      !  **** ENABLE TRAPS ****
372      wrpr  %g0, SPARC_PSTATE_PRIV_MASK | SPARC_PSTATE_PEF_MASK | \
373        SPARC_PSTATE_IE_MASK, %pstate
374        isr_dispatch:
375        call    SYM(_Thread_Dispatch), 0
376        nop
377
378        /*
379         *  We invoked _Thread_Dispatch in a state similar to the interrupted
380         *  task.  In order to safely be able to tinker with the register
381         *  windows and get the task back to its pre-interrupt state,
382         *  we need to disable interrupts.
383         */
384      mov   2, %g4        ! syscall (disable interrupts)
385      ta    0             ! syscall (disable interrupts)
386      mov   0, %g4
387
388  /*
389   *  While we had ISR dispatching disabled in this thread,
390   *  did we miss anything.  If so, then we need to do another
391   *  _Thread_Dispatch before leaving this ISR Dispatch context.
392   */
393
394  setx     DISPATCH_NEEDED, %o5, %o1
395  ldub     [%o1], %o2
396
397  orcc     %o2, %g0, %g0   ! Is thread switch necessary?
398  bz       allow_nest_again ! No, then clear out and return
399  nop
400
401  ! Yes, then invoke the dispatcher
402dispatchAgain:
403  mov      3, %g4        ! syscall (enable interrupts)
404  ta       0             ! syscall (enable interrupts)
405  ba       isr_dispatch
406  mov      0, %g4
407
408  allow_nest_again:
409
410  ! Zero out ISR stack nesting prevention flag
411  setx    SYM(_CPU_ISR_Dispatch_disable), %o5, %o1
412  stuw    %g0,[%o1]
413
414  /*
415   *  The CWP in place at this point may be different from
416   *  that which was in effect at the beginning of the ISR if we
417   *  have been context switched between the beginning of this invocation
418   *  of _ISR_Handler and this point.  Thus the CWP and WIM should
419   *  not be changed back to their values at ISR entry time.  Any
420   *  changes to the PSR must preserve the CWP.
421   */
422
423  simple_return:
424  flushw          ! get register windows to a 'clean' state
425
426  ! **** DISABLE TRAPS ****
427  wrpr    %g0, SPARC_PSTATE_PRIV_MASK, %pstate
428
429  ldx     [%sp + STACK_BIAS + ISF_Y_OFFSET], %o1      ! restore y
430  wr      %o1, 0, %y
431
432  ldx  [%sp + STACK_BIAS + ISF_TSTATE_OFFSET], %g1
433
434! see if cwp is proper (tstate.cwp == cwp)
435  and  %g1, 0x1F, %g6
436  rdpr  %cwp, %g7
437  cmp  %g6, %g7
438  bz  good_window
439  nop
440
441  /*
442   * Fix the CWP. Need the cwp to be the proper cwp that
443   * gets restored when returning from the trap via retry/done. Do
444   * this before reloading the task's output regs. Basically fake a
445   * window spill/fill.
446   *
447   * Is this necessary on sun4v? Why not just re-write
448   * tstate.cwp to be equal to the current cwp?
449   */
450  mov  %sp, %g1
451  stx  %l0, [%sp + STACK_BIAS + CPU_STACK_FRAME_L0_OFFSET]
452  stx  %l1, [%sp + STACK_BIAS + CPU_STACK_FRAME_L1_OFFSET]
453  stx  %l2, [%sp + STACK_BIAS + CPU_STACK_FRAME_L2_OFFSET]
454  stx  %l3, [%sp + STACK_BIAS + CPU_STACK_FRAME_L3_OFFSET]
455  stx  %l4, [%sp + STACK_BIAS + CPU_STACK_FRAME_L4_OFFSET]
456  stx  %l5, [%sp + STACK_BIAS + CPU_STACK_FRAME_L5_OFFSET]
457  stx  %l6, [%sp + STACK_BIAS + CPU_STACK_FRAME_L6_OFFSET]
458  stx  %l7, [%sp + STACK_BIAS + CPU_STACK_FRAME_L7_OFFSET]
459  stx  %i0, [%sp + STACK_BIAS + CPU_STACK_FRAME_I0_OFFSET]
460  stx  %i1, [%sp + STACK_BIAS + CPU_STACK_FRAME_I1_OFFSET]
461  stx  %i2, [%sp + STACK_BIAS + CPU_STACK_FRAME_I2_OFFSET]
462  stx  %i3, [%sp + STACK_BIAS + CPU_STACK_FRAME_I3_OFFSET]
463  stx  %i4, [%sp + STACK_BIAS + CPU_STACK_FRAME_I4_OFFSET]
464  stx  %i5, [%sp + STACK_BIAS + CPU_STACK_FRAME_I5_OFFSET]
465  stx  %i6, [%sp + STACK_BIAS + CPU_STACK_FRAME_I6_FP_OFFSET]
466  stx  %i7, [%sp + STACK_BIAS + CPU_STACK_FRAME_I7_OFFSET]
467  wrpr  %g0, %g6, %cwp
468  mov  %g1, %sp
469  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_L0_OFFSET], %l0
470  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_L1_OFFSET], %l1
471  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_L2_OFFSET], %l2
472  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_L3_OFFSET], %l3
473  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_L4_OFFSET], %l4
474  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_L5_OFFSET], %l5
475  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_L6_OFFSET], %l6
476  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_L7_OFFSET], %l7
477  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_I0_OFFSET], %i0
478  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_I1_OFFSET], %i1
479  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_I2_OFFSET], %i2
480  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_I3_OFFSET], %i3
481  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_I4_OFFSET], %i4
482  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_I5_OFFSET], %i5
483  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_I6_FP_OFFSET], %i6
484  ldx  [%sp + STACK_BIAS + CPU_STACK_FRAME_I7_OFFSET], %i7
485
486
487  good_window:
488
489
490  /*
491   *  Restore tasks global and out registers
492   */
493
494  ldx     [%sp + STACK_BIAS + ISF_G1_OFFSET], %g1    ! restore g1
495  ldx     [%sp + STACK_BIAS + ISF_G2_OFFSET], %g2    ! restore g2
496  ldx     [%sp + STACK_BIAS + ISF_G3_OFFSET], %g3    ! restore g3
497  ldx     [%sp + STACK_BIAS + ISF_G4_OFFSET], %g4    ! restore g4
498  ldx     [%sp + STACK_BIAS + ISF_G5_OFFSET], %g5    ! restore g5
499  ldx     [%sp + STACK_BIAS + ISF_G6_OFFSET], %g6    ! restore g6
500  ldx     [%sp + STACK_BIAS + ISF_G7_OFFSET], %g7    ! restore g7
501
502  ! Assume the interrupted context is in TL 0 with GL 0 / normal globals.
503  ! When tstate is restored at done/retry, the interrupted context is restored.
504  ! return to TL[1], GL[1], and restore TSTATE, TPC, and TNPC
505  wrpr  %g0, 1, %tl
506
507  ! return to GL=1 or AG
508#if defined(SUN4U)
509    rdpr  %pstate, %o1
510    or  %o1, SPARC_PSTATE_AG_MASK, %o1
511    wrpr  %o1, %g0, %pstate                 ! go to AG.
512#elif defined(SUN4V)
513  wrpr  %g0, 1, %gl
514#endif
515
516! now we can use global registers (at gl=1 or AG)
517  ldx   [%sp + STACK_BIAS + ISF_PIL_OFFSET], %g3
518  ldx   [%sp + STACK_BIAS + ISF_TPC_OFFSET], %g4
519  ldx   [%sp + STACK_BIAS + ISF_TNPC_OFFSET], %g5
520  ldx   [%sp + STACK_BIAS + ISF_TSTATE_OFFSET], %g1
521  ldx   [%sp + STACK_BIAS + ISF_TVEC_OFFSET], %g2
522  wrpr  %g0, %g3, %pil
523  wrpr  %g0, %g4, %tpc
524  wrpr  %g0, %g5, %tnpc
525
526  wrpr    %g0, %g1, %tstate
527
528  ldx     [%sp + STACK_BIAS + ISF_O0_OFFSET], %o0    ! restore o0
529  ldx     [%sp + STACK_BIAS + ISF_O1_OFFSET], %o1    ! restore o1
530  ldx     [%sp + STACK_BIAS + ISF_O2_OFFSET], %o2    ! restore o2
531  ldx     [%sp + STACK_BIAS + ISF_O3_OFFSET], %o3    ! restore o3
532  ldx     [%sp + STACK_BIAS + ISF_O4_OFFSET], %o4    ! restore o4
533  ldx     [%sp + STACK_BIAS + ISF_O5_OFFSET], %o5    ! restore o5
534  ! sp is restored later
535  ldx     [%sp + STACK_BIAS + ISF_O7_OFFSET], %o7    ! restore o7
536
537  ldx     [%sp + STACK_BIAS + ISF_O6_SP_OFFSET], %o6 ! restore o6/sp
538
539  /*
540   *  Determine whether to re-execute the trapping instruction
541   *  (asynchronous trap) or to skip the trapping instruction
542   *  (synchronous trap).
543   */
544
545  andcc   %g2, SPARC_SYNCHRONOUS_TRAP_BIT_MASK, %g0
546  ! Is this a synchronous trap?
547  be  not_synch             ! No, then skip trapping instruction
548  mov  0, %g4
549  retry        ! re-execute trapping instruction
550  not_synch:
551  done        ! skip trapping instruction
552
553/* end of file */
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