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interrupt.S @ 03b7789

4.115

Last change on this file since 03b7789 was 03b7789, checked in by Sebastian Huber <sebastian.huber@…>, on 04/26/14 at 13:09:10
score: Statically initialize _ISR_Vector_table
Property mode set to `100644`
File size: 18.1 KB

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[c56982c]	1	/* cpu_asm.s
	2	*
	3	* This file contains the basic algorithms for all assembly code used
	4	* in an specific CPU port of RTEMS. These algorithms must be implemented
	5	* in assembly language.
	6	*
	7	* COPYRIGHT (c) 1989-2007.
	8	* On-Line Applications Research Corporation (OAR).
	9	*
	10	* The license and distribution terms for this file may be
	11	* found in the file LICENSE in this distribution or at
[c499856]	12	* http://www.rtems.org/license/LICENSE.
[c56982c]	13	*
	14	* Ported to ERC32 implementation of the SPARC by On-Line Applications
	15	* Research Corporation (OAR) under contract to the European Space
	16	* Agency (ESA).
	17	*
	18	* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
	19	* European Space Agency.
	20	*
	21	* Ported to Niagara and UltraSPARC III (US3) implementations of the SPARC-v9.
	22	* Niagara and US3 modifications of respective RTEMS file:
	23	* COPYRIGHT (c) 2010. Gedare Bloom.
	24	*/
	25
	26	#include <rtems/asm.h>
[646e7b0d]	27	#include <rtems/score/percpu.h>
[c56982c]	28
	29
	30	/*
	31	* The assembler needs to be told that we know what to do with
	32	* the global registers.
	33	*/
	34	.register %g2, #scratch
	35	.register %g3, #scratch
	36	.register %g6, #scratch
	37	.register %g7, #scratch
	38
	39
	40	/*
	41	* void _ISR_Handler()
	42	*
	43	* This routine provides the RTEMS interrupt management.
	44	*
	45	* We enter this handler from the 8 instructions in the trap table with
	46	* the following registers assumed to be set as shown:
	47	*
	48	* g4 = tstate (old l0)
	49	* g2 = trap type (vector) (old l3)
	50	*
	51	* NOTE: By an executive defined convention:
	52	* if trap type is between 0 and 511 it is an asynchronous trap
	53	* if trap type is between 512 and 1023 it is an asynchonous trap
	54	*/
	55
	56	.align 4
	57	PUBLIC(_ISR_Handler)
	58	SYM(_ISR_Handler):
	59
	60	/*
	61	* The ISR is called at TL = 1.
	62	* On sun4u we use the alternate globals set.
	63	*
	64	* On entry:
	65	* g4 = tstate (from trap table)
	66	* g2 = trap vector #
	67	*
	68	* In either case, note that trap handlers share a register window with
	69	* the interrupted context, unless we explicitly enter a new window. This
	70	* differs from Sparc v8, in which a dedicated register window is saved
	71	* for trap handling. This means we have to avoid overwriting any registers
	72	* that we don't save.
	73	*
	74	*/
	75
	76
	77	/*
	78	* save some or all context on stack
	79	*/
	80
	81	/*
	82	* Save the state of the interrupted task -- especially the global
	83	* registers -- in the Interrupt Stack Frame. Note that the ISF
	84	* includes a regular minimum stack frame which will be used if
	85	* needed by register window overflow and underflow handlers.
	86	*
	87	* This is slightly wasteful, since the stack already has the window
	88	* overflow space reserved, but there is no obvious way to ensure
	89	* we can store the interrupted state and still handle window
	90	* spill/fill correctly, since there is no room for the ISF.
	91	*
	92	*/
	93
	94	/* this is for debugging purposes, make sure that TL = 1, otherwise
	95	* things might get dicey */
	96	rdpr %tl, %g1
	97	cmp %g1, 1
	98	be 1f
	99	nop
	100
	101	0: ba 0b
	102	nop
	103
	104	1:
	105	/* first store the sp of the interrupted task temporarily in g1 */
	106	mov %sp, %g1
	107
	108	sub %sp, CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE, %sp
	109	! make space for Stack_Frame\|\|ISF
	110
	111	/* save tstate, tpc, tnpc, pil */
	112	stx %g4, [%sp + STACK_BIAS + ISF_TSTATE_OFFSET]
	113	rdpr %pil, %g3
	114	rdpr %tpc, %g4
	115	rdpr %tnpc, %g5
	116	stx %g3, [%sp + STACK_BIAS + ISF_PIL_OFFSET]
	117	stx %g4, [%sp + STACK_BIAS + ISF_TPC_OFFSET]
	118	stx %g5, [%sp + STACK_BIAS + ISF_TNPC_OFFSET]
[67baf60]	119	stx %g2, [%sp + STACK_BIAS + ISF_TVEC_OFFSET]
[c56982c]	120
	121	rd %y, %g4 ! save y
	122	stx %g4, [%sp + STACK_BIAS + ISF_Y_OFFSET]
	123
	124	! save interrupted frame's output regs
	125	stx %o0, [%sp + STACK_BIAS + ISF_O0_OFFSET] ! save o0
	126	stx %o1, [%sp + STACK_BIAS + ISF_O1_OFFSET] ! save o1
	127	stx %o2, [%sp + STACK_BIAS + ISF_O2_OFFSET] ! save o2
	128	stx %o3, [%sp + STACK_BIAS + ISF_O3_OFFSET] ! save o3
	129	stx %o4, [%sp + STACK_BIAS + ISF_O4_OFFSET] ! save o4
	130	stx %o5, [%sp + STACK_BIAS + ISF_O5_OFFSET] ! save o5
	131	stx %g1, [%sp + STACK_BIAS + ISF_O6_SP_OFFSET] ! save o6/sp
	132	stx %o7, [%sp + STACK_BIAS + ISF_O7_OFFSET] ! save o7
	133
	134	mov %g1, %o5 ! hold the old sp here for now
	135	mov %g2, %o1 ! we'll need trap # later
	136
	137	/* switch to TL[0] */
	138	wrpr %g0, 0, %tl
	139
	140	/* switch to normal globals */
	141	#if defined (SUN4U)
	142	/* the assignment to pstate below will mask out the AG bit */
	143	#elif defined (SUN4V)
	144	wrpr %g0, 0, %gl
	145	#endif
	146	/* get pstate to known state */
	147	wrpr %g0, SPARC_PSTATE_PRIV_MASK \| SPARC_PSTATE_PEF_MASK, %pstate
	148
	149	! save globals
	150	stx %g1, [%sp + STACK_BIAS + ISF_G1_OFFSET] ! save g1
	151	stx %g2, [%sp + STACK_BIAS + ISF_G2_OFFSET] ! save g2
	152	stx %g3, [%sp + STACK_BIAS + ISF_G3_OFFSET] ! save g3
	153	stx %g4, [%sp + STACK_BIAS + ISF_G4_OFFSET] ! save g4
	154	stx %g5, [%sp + STACK_BIAS + ISF_G5_OFFSET] ! save g5
	155	stx %g6, [%sp + STACK_BIAS + ISF_G6_OFFSET] ! save g6
	156	stx %g7, [%sp + STACK_BIAS + ISF_G7_OFFSET] ! save g7
	157
	158
	159	mov %o1, %g2 ! get the trap #
	160	mov %o5, %g7 ! store the interrupted %sp (preserve)
	161	mov %sp, %o1 ! 2nd arg to ISR Handler = address of ISF
[05e75a4b]	162	add %o1, STACK_BIAS, %o1 ! need to adjust for stack bias, 2nd arg = ISF
[c56982c]	163
	164	/*
	165	* Increment ISR nest level and Thread dispatch disable level.
	166	*
	167	* Register usage for this section: (note, these are used later)
	168	*
	169	* g3 = _Thread_Dispatch_disable_level pointer
	170	* g5 = _Thread_Dispatch_disable_level value (uint32_t)
	171	* g6 = _ISR_Nest_level pointer
	172	* g4 = _ISR_Nest_level value (uint32_t)
	173	* o5 = temp
	174	*
	175	* NOTE: It is assumed that g6 - g7 will be preserved until the ISR
	176	* nest and thread dispatch disable levels are unnested.
	177	*/
	178
[d19cce29]	179	setx THREAD_DISPATCH_DISABLE_LEVEL, %o5, %g3
[c56982c]	180	lduw [%g3], %g5
[646e7b0d]	181	setx ISR_NEST_LEVEL, %o5, %g6
[c56982c]	182	lduw [%g6], %g4
	183
	184	add %g5, 1, %g5
	185	stuw %g5, [%g3]
	186
	187	add %g4, 1, %g4
	188	stuw %g4, [%g6]
	189
	190	/*
	191	* If ISR nest level was zero (now 1), then switch stack.
	192	*/
	193
	194	subcc %g4, 1, %g4 ! outermost interrupt handler?
	195	bnz dont_switch_stacks ! No, then do not switch stacks
	196
[2c4d3879]	197	setx SYM(INTERRUPT_STACK_HIGH), %o5, %g1
[c56982c]	198	ldx [%g1], %sp
	199
	200	/*
	201	* Adjust the stack for the stack bias
	202	*/
	203	sub %sp, STACK_BIAS, %sp
	204
	205	/*
	206	* Make sure we have a place on the stack for the window overflow
	207	* trap handler to write into. At this point it is safe to
	208	* enable traps again.
	209	*/
	210
	211	sub %sp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
	212
	213	dont_switch_stacks:
	214	/*
	215	* Check if we have an external interrupt (trap 0x41 - 0x4f). If so,
	216	* set the PIL to mask off interrupts with lower priority.
	217	*
	218	* The original PIL is not modified since it will be restored
	219	* when the interrupt handler returns.
	220	*/
	221
	222	and %g2, 0x0ff, %g1 ! is bottom byte of vector number [0x41,0x4f]?
	223
	224	subcc %g1, 0x41, %g0
	225	bl dont_fix_pil
	226	subcc %g1, 0x4f, %g0
	227	bg dont_fix_pil
	228	nop
	229	wrpr %g0, %g1, %pil
	230
	231	dont_fix_pil:
	232	/* We need to be careful about enabling traps here.
	233	*
	234	* We already stored off the tstate, tpc, and tnpc, and switched to
	235	* TL = 0, so it should be safe.
	236	*/
	237
	238	/* zero out g4 so that ofw calls work */
	239	mov %g0, %g4
	240
	241	! ** ENABLE TRAPS **
	242	wrpr %g0, SPARC_PSTATE_PRIV_MASK \| SPARC_PSTATE_PEF_MASK \| \
	243	SPARC_PSTATE_IE_MASK, %pstate
	244
	245	/*
	246	* Vector to user's handler.
	247	*
	248	* NOTE: TBR may no longer have vector number in it since
	249	* we just enabled traps. It is definitely in g2.
	250	*/
	251	setx SYM(_ISR_Vector_table), %o5, %g1
	252	and %g2, 0x1FF, %o5 ! remove synchronous trap indicator
	253	sll %o5, 3, %o5 ! o5 = offset into table
	254	ldx [%g1 + %o5], %g1 ! g1 = _ISR_Vector_table[ vector ]
	255
	256
	257	! o1 = 2nd arg = address of the ISF
	258	! WAS LOADED WHEN ISF WAS SAVED!!!
	259	mov %g2, %o0 ! o0 = 1st arg = vector number
	260	call %g1, 0
	261	nop ! delay slot
	262
	263	/*
	264	* Redisable traps so we can finish up the interrupt processing.
	265	* This is a conservative place to do this.
	266	*/
	267	! ** DISABLE TRAPS **
	268	wrpr %g0, SPARC_PSTATE_PRIV_MASK, %pstate
	269
	270	/*
	271	* We may safely use any of the %o and %g registers, because
	272	* we saved them earlier (and any other interrupt that uses
	273	* them will also save them). Right now, the state of those
	274	* registers are as follows:
	275	* %o registers: unknown (user's handler may have destroyed)
	276	* %g1,g4,g5: scratch
	277	* %g2: unknown: was trap vector
	278	* %g3: uknown: was _Thread_Dispatch_Disable_level pointer
	279	* %g6: _ISR_Nest_level
	280	* %g7: interrupted task's sp
	281	*/
	282
	283	/*
	284	* Increment ISR nest level and Thread dispatch disable level.
	285	*
	286	* Register usage for this section: (note: as used above)
	287	*
	288	* g3 = _Thread_Dispatch_disable_level pointer
	289	* g5 = _Thread_Dispatch_disable_level value
	290	* g6 = _ISR_Nest_level pointer
	291	* g4 = _ISR_Nest_level value
	292	* o5 = temp
	293	*/
	294
	295	/* We have to re-load the values from memory, because there are
	296	* not enough registers that we know will be preserved across the
	297	* user's handler. If this is a problem, we can create a register
	298	* window for _ISR_Handler.
	299	*/
	300
[d19cce29]	301	setx THREAD_DISPATCH_DISABLE_LEVEL, %o5, %g3
[c56982c]	302	lduw [%g3],%g5
	303	lduw [%g6],%g4
	304	sub %g5, 1, %g5
	305	stuw %g5, [%g3]
	306	sub %g4, 1, %g4
	307	stuw %g4, [%g6]
	308
	309	orcc %g4, %g0, %g0 ! ISRs still nested?
	310	bnz dont_restore_stack ! Yes then don't restore stack yet
	311	nop
	312
	313	/*
	314	* This is the outermost interrupt handler. Need to get off the
	315	* CPU Interrupt Stack and back to the tasks stack.
	316	*
	317	* The following subtract should get us back on the interrupted
	318	* tasks stack and add enough room to invoke the dispatcher.
	319	* When we enable traps, we are mostly back in the context
	320	* of the task and subsequent interrupts can operate normally.
	321	*
	322	* Now %sp points to the bottom of the ISF.
	323	*
	324	*/
	325
	326	sub %g7, CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE, %sp
	327
	328	dont_restore_stack:
	329
	330	/*
	331	* If dispatching is disabled (includes nested interrupt case),
	332	* then do a "simple" exit.
	333	*/
	334
	335	orcc %g5, %g0, %g0 ! Is dispatching disabled?
	336	bnz simple_return ! Yes, then do a "simple" exit
	337	! NOTE: Use the delay slot
	338	mov %g0, %g4 ! clear g4 for ofw
	339
	340	! Are we dispatching from a previous ISR in the interrupted thread?
	341	setx SYM(_CPU_ISR_Dispatch_disable), %o5, %g5
	342	lduw [%g5], %o5
	343	orcc %o5, %g0, %g0 ! Is this thread already doing an ISR?
	344	bnz simple_return ! Yes, then do a "simple" exit
	345	nop
	346
[646e7b0d]	347	setx DISPATCH_NEEDED, %o5, %g7
[c56982c]	348
	349
	350	/*
	351	* If a context switch is necessary, then do fudge stack to
	352	* return to the interrupt dispatcher.
	353	*/
	354
	355	ldub [%g7], %o5
	356
	357	orcc %o5, %g0, %g0 ! Is thread switch necessary?
[ce3bfb7]	358	bz simple_return ! no, then do a simple return. otherwise fallthru
[c56982c]	359	nop
	360
	361	/*
	362	* Invoke interrupt dispatcher.
	363	*/
	364	PUBLIC(_ISR_Dispatch)
	365	SYM(_ISR_Dispatch):
	366	! Set ISR dispatch nesting prevention flag
	367	mov 1, %o1
	368	setx SYM(_CPU_ISR_Dispatch_disable), %o5, %o2
	369	stuw %o1, [%o2]
	370
	371
	372	! ** ENABLE TRAPS **
	373	wrpr %g0, SPARC_PSTATE_PRIV_MASK \| SPARC_PSTATE_PEF_MASK \| \
	374	SPARC_PSTATE_IE_MASK, %pstate
	375	isr_dispatch:
	376	call SYM(_Thread_Dispatch), 0
	377	nop
	378
	379	/*
	380	* We invoked _Thread_Dispatch in a state similar to the interrupted
	381	* task. In order to safely be able to tinker with the register
	382	* windows and get the task back to its pre-interrupt state,
	383	* we need to disable interrupts.
	384	*/
	385	mov 2, %g4 ! syscall (disable interrupts)
	386	ta 0 ! syscall (disable interrupts)
	387	mov 0, %g4
	388
	389	/*
	390	* While we had ISR dispatching disabled in this thread,
	391	* did we miss anything. If so, then we need to do another
	392	* _Thread_Dispatch before leaving this ISR Dispatch context.
	393	*/
	394
[646e7b0d]	395	setx DISPATCH_NEEDED, %o5, %o1
[c56982c]	396	ldub [%o1], %o2
	397
	398	orcc %o2, %g0, %g0 ! Is thread switch necessary?
	399	bz allow_nest_again ! No, then clear out and return
	400	nop
	401
	402	! Yes, then invoke the dispatcher
[646e7b0d]	403	dispatchAgain:
[c56982c]	404	mov 3, %g4 ! syscall (enable interrupts)
	405	ta 0 ! syscall (enable interrupts)
	406	ba isr_dispatch
	407	mov 0, %g4
	408
	409	allow_nest_again:
	410
	411	! Zero out ISR stack nesting prevention flag
	412	setx SYM(_CPU_ISR_Dispatch_disable), %o5, %o1
	413	stuw %g0,[%o1]
	414
	415	/*
	416	* The CWP in place at this point may be different from
	417	* that which was in effect at the beginning of the ISR if we
	418	* have been context switched between the beginning of this invocation
	419	* of _ISR_Handler and this point. Thus the CWP and WIM should
	420	* not be changed back to their values at ISR entry time. Any
	421	* changes to the PSR must preserve the CWP.
	422	*/
	423
	424	simple_return:
	425	flushw ! get register windows to a 'clean' state
	426
	427	! ** DISABLE TRAPS **
	428	wrpr %g0, SPARC_PSTATE_PRIV_MASK, %pstate
	429
	430	ldx [%sp + STACK_BIAS + ISF_Y_OFFSET], %o1 ! restore y
	431	wr %o1, 0, %y
	432
	433	ldx [%sp + STACK_BIAS + ISF_TSTATE_OFFSET], %g1
	434
	435	! see if cwp is proper (tstate.cwp == cwp)
	436	and %g1, 0x1F, %g6
	437	rdpr %cwp, %g7
	438	cmp %g6, %g7
	439	bz good_window
	440	nop
	441
	442	/*
	443	* Fix the CWP. Need the cwp to be the proper cwp that
	444	* gets restored when returning from the trap via retry/done. Do
	445	* this before reloading the task's output regs. Basically fake a
	446	* window spill/fill.
	447	*
	448	* Is this necessary on sun4v? Why not just re-write
	449	* tstate.cwp to be equal to the current cwp?
	450	*/
	451	mov %sp, %g1
	452	stx %l0, [%sp + STACK_BIAS + CPU_STACK_FRAME_L0_OFFSET]
	453	stx %l1, [%sp + STACK_BIAS + CPU_STACK_FRAME_L1_OFFSET]
	454	stx %l2, [%sp + STACK_BIAS + CPU_STACK_FRAME_L2_OFFSET]
	455	stx %l3, [%sp + STACK_BIAS + CPU_STACK_FRAME_L3_OFFSET]
	456	stx %l4, [%sp + STACK_BIAS + CPU_STACK_FRAME_L4_OFFSET]
	457	stx %l5, [%sp + STACK_BIAS + CPU_STACK_FRAME_L5_OFFSET]
	458	stx %l6, [%sp + STACK_BIAS + CPU_STACK_FRAME_L6_OFFSET]
	459	stx %l7, [%sp + STACK_BIAS + CPU_STACK_FRAME_L7_OFFSET]
	460	stx %i0, [%sp + STACK_BIAS + CPU_STACK_FRAME_I0_OFFSET]
	461	stx %i1, [%sp + STACK_BIAS + CPU_STACK_FRAME_I1_OFFSET]
	462	stx %i2, [%sp + STACK_BIAS + CPU_STACK_FRAME_I2_OFFSET]
	463	stx %i3, [%sp + STACK_BIAS + CPU_STACK_FRAME_I3_OFFSET]
	464	stx %i4, [%sp + STACK_BIAS + CPU_STACK_FRAME_I4_OFFSET]
	465	stx %i5, [%sp + STACK_BIAS + CPU_STACK_FRAME_I5_OFFSET]
	466	stx %i6, [%sp + STACK_BIAS + CPU_STACK_FRAME_I6_FP_OFFSET]
	467	stx %i7, [%sp + STACK_BIAS + CPU_STACK_FRAME_I7_OFFSET]
	468	wrpr %g0, %g6, %cwp
	469	mov %g1, %sp
	470	ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_L0_OFFSET], %l0
	471	ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_L1_OFFSET], %l1
	472	ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_L2_OFFSET], %l2
	473	ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_L3_OFFSET], %l3
	474	ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_L4_OFFSET], %l4
	475	ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_L5_OFFSET], %l5
	476	ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_L6_OFFSET], %l6
	477	ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_L7_OFFSET], %l7
	478	ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_I0_OFFSET], %i0
	479	ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_I1_OFFSET], %i1
	480	ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_I2_OFFSET], %i2
	481	ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_I3_OFFSET], %i3
	482	ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_I4_OFFSET], %i4
	483	ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_I5_OFFSET], %i5
	484	ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_I6_FP_OFFSET], %i6
	485	ldx [%sp + STACK_BIAS + CPU_STACK_FRAME_I7_OFFSET], %i7
	486
	487
	488	good_window:
	489
	490
	491	/*
	492	* Restore tasks global and out registers
	493	*/
	494
	495	ldx [%sp + STACK_BIAS + ISF_G1_OFFSET], %g1 ! restore g1
	496	ldx [%sp + STACK_BIAS + ISF_G2_OFFSET], %g2 ! restore g2
	497	ldx [%sp + STACK_BIAS + ISF_G3_OFFSET], %g3 ! restore g3
	498	ldx [%sp + STACK_BIAS + ISF_G4_OFFSET], %g4 ! restore g4
	499	ldx [%sp + STACK_BIAS + ISF_G5_OFFSET], %g5 ! restore g5
	500	ldx [%sp + STACK_BIAS + ISF_G6_OFFSET], %g6 ! restore g6
	501	ldx [%sp + STACK_BIAS + ISF_G7_OFFSET], %g7 ! restore g7
	502
[ce3bfb7]	503	! Assume the interrupted context is in TL 0 with GL 0 / normal globals.
	504	! When tstate is restored at done/retry, the interrupted context is restored.
[c56982c]	505	! return to TL[1], GL[1], and restore TSTATE, TPC, and TNPC
	506	wrpr %g0, 1, %tl
	507
	508	! return to GL=1 or AG
	509	#if defined(SUN4U)
[ce3bfb7]	510	rdpr %pstate, %o1
	511	or %o1, SPARC_PSTATE_AG_MASK, %o1
	512	wrpr %o1, %g0, %pstate ! go to AG.
[c56982c]	513	#elif defined(SUN4V)
	514	wrpr %g0, 1, %gl
	515	#endif
	516
	517	! now we can use global registers (at gl=1 or AG)
	518	ldx [%sp + STACK_BIAS + ISF_PIL_OFFSET], %g3
	519	ldx [%sp + STACK_BIAS + ISF_TPC_OFFSET], %g4
	520	ldx [%sp + STACK_BIAS + ISF_TNPC_OFFSET], %g5
	521	ldx [%sp + STACK_BIAS + ISF_TSTATE_OFFSET], %g1
[67baf60]	522	ldx [%sp + STACK_BIAS + ISF_TVEC_OFFSET], %g2
[c56982c]	523	wrpr %g0, %g3, %pil
	524	wrpr %g0, %g4, %tpc
	525	wrpr %g0, %g5, %tnpc
	526
	527	wrpr %g0, %g1, %tstate
	528
	529	ldx [%sp + STACK_BIAS + ISF_O0_OFFSET], %o0 ! restore o0
	530	ldx [%sp + STACK_BIAS + ISF_O1_OFFSET], %o1 ! restore o1
	531	ldx [%sp + STACK_BIAS + ISF_O2_OFFSET], %o2 ! restore o2
	532	ldx [%sp + STACK_BIAS + ISF_O3_OFFSET], %o3 ! restore o3
	533	ldx [%sp + STACK_BIAS + ISF_O4_OFFSET], %o4 ! restore o4
	534	ldx [%sp + STACK_BIAS + ISF_O5_OFFSET], %o5 ! restore o5
	535	! sp is restored later
	536	ldx [%sp + STACK_BIAS + ISF_O7_OFFSET], %o7 ! restore o7
	537
	538	ldx [%sp + STACK_BIAS + ISF_O6_SP_OFFSET], %o6 ! restore o6/sp
	539
	540	/*
	541	* Determine whether to re-execute the trapping instruction
	542	* (asynchronous trap) or to skip the trapping instruction
	543	* (synchronous trap).
	544	*/
	545
	546	andcc %g2, SPARC_SYNCHRONOUS_TRAP_BIT_MASK, %g0
	547	! Is this a synchronous trap?
	548	be not_synch ! No, then skip trapping instruction
	549	mov 0, %g4
	550	retry ! re-execute trapping instruction
	551	not_synch:
	552	done ! skip trapping instruction
	553
	554	/* end of file */

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