1 | /* |
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2 | * SPARC-v9 Dependent Source |
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3 | * |
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4 | * COPYRIGHT (c) 1989-2007. |
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5 | * On-Line Applications Research Corporation (OAR). |
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6 | * |
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7 | * This file is based on the SPARC cpu.c file. Modifications are made to |
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8 | * provide support for the SPARC-v9. |
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9 | * COPYRIGHT (c) 2010. Gedare Bloom. |
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10 | * |
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11 | * The license and distribution terms for this file may be |
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12 | * found in the file LICENSE in this distribution or at |
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13 | * http://www.rtems.org/license/LICENSE. |
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14 | */ |
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15 | |
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16 | #include <rtems/system.h> |
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17 | #include <rtems/asm.h> |
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18 | #include <rtems/score/isr.h> |
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19 | #include <rtems/rtems/cache.h> |
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20 | |
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21 | /* |
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22 | * This initializes the set of opcodes placed in each trap |
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23 | * table entry. The routine which installs a handler is responsible |
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24 | * for filling in the fields for the _handler address and the _vector |
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25 | * trap type. |
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26 | * |
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27 | * The constants following this structure are masks for the fields which |
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28 | * must be filled in when the handler is installed. |
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29 | */ |
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30 | |
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31 | /* 64-bit registers complicate this. Also, in sparc v9, |
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32 | * each trap level gets its own set of global registers, but |
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33 | * does not get its own dedicated register window. so we avoid |
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34 | * using the local registers in the trap handler. |
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35 | */ |
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36 | const CPU_Trap_table_entry _CPU_Trap_slot_template = { |
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37 | 0x89508000, /* rdpr %tstate, %g4 */ |
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38 | 0x05000000, /* sethi %hh(_handler), %g2 */ |
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39 | 0x8410a000, /* or %g2, %hm(_handler), %g2 */ |
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40 | 0x8528b020, /* sllx %g2, 32, %g2 */ |
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41 | 0x07000000, /* sethi %hi(_handler), %g3 */ |
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42 | 0x8610c002, /* or %g3, %g2, %g3 */ |
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43 | 0x81c0e000, /* jmp %g3 + %lo(_handler) */ |
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44 | 0x84102000 /* mov _vector, %g2 */ |
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45 | }; |
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46 | |
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47 | |
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48 | /*PAGE |
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49 | * |
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50 | * _CPU_ISR_Get_level |
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51 | * |
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52 | * Input Parameters: NONE |
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53 | * |
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54 | * Output Parameters: |
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55 | * returns the current interrupt level (PIL field of the PSR) |
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56 | */ |
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57 | |
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58 | uint32_t _CPU_ISR_Get_level( void ) |
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59 | { |
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60 | uint32_t level; |
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61 | |
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62 | sparc64_get_interrupt_level( level ); |
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63 | |
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64 | return level; |
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65 | } |
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66 | |
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67 | /*PAGE |
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68 | * |
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69 | * _CPU_ISR_install_raw_handler |
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70 | * |
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71 | * This routine installs the specified handler as a "raw" non-executive |
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72 | * supported trap handler (a.k.a. interrupt service routine). |
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73 | * |
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74 | * Input Parameters: |
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75 | * vector - trap table entry number plus synchronous |
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76 | * vs. asynchronous information |
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77 | * new_handler - address of the handler to be installed |
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78 | * old_handler - pointer to an address of the handler previously installed |
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79 | * |
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80 | * Output Parameters: NONE |
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81 | * *new_handler - address of the handler previously installed |
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82 | * |
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83 | * NOTE: |
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84 | * |
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85 | * On the SPARC v9, there are really only 512 vectors. However, the executive |
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86 | * has no easy, fast, reliable way to determine which traps are synchronous |
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87 | * and which are asynchronous. By default, traps return to the |
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88 | * instruction which caused the interrupt. So if you install a software |
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89 | * trap handler as an executive interrupt handler (which is desirable since |
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90 | * RTEMS takes care of window and register issues), then the executive needs |
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91 | * to know that the return address is to the trap rather than the instruction |
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92 | * following the trap. |
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93 | * |
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94 | * So vectors 0 through 511 are treated as regular asynchronous traps which |
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95 | * provide the "correct" return address. Vectors 512 through 1023 are assumed |
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96 | * by the executive to be synchronous and to require that the return be to the |
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97 | * trapping instruction. |
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98 | * |
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99 | * If you use this mechanism to install a trap handler which must reexecute |
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100 | * the instruction which caused the trap, then it should be installed as |
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101 | * a synchronous trap. This will avoid the executive changing the return |
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102 | * address. |
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103 | */ |
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104 | /* Verified this is working properly from sparc64_install_isr_entries */ |
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105 | void _CPU_ISR_install_raw_handler( |
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106 | uint32_t vector, |
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107 | proc_ptr new_handler, |
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108 | proc_ptr *old_handler |
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109 | ) |
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110 | { |
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111 | uint32_t real_vector; |
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112 | CPU_Trap_table_entry *tba; |
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113 | CPU_Trap_table_entry *slot; |
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114 | uint64_t u64_tba; |
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115 | uint64_t u64_handler; |
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116 | |
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117 | /* |
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118 | * Get the "real" trap number for this vector ignoring the synchronous |
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119 | * versus asynchronous indicator included with our vector numbers. |
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120 | */ |
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121 | |
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122 | real_vector = SPARC_REAL_TRAP_NUMBER( vector ); |
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123 | |
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124 | /* |
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125 | * Get the current base address of the trap table and calculate a pointer |
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126 | * to the slot we are interested in. |
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127 | */ |
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128 | |
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129 | sparc64_get_tba( u64_tba ); |
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130 | |
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131 | /* u32_tbr &= 0xfffff000; */ |
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132 | u64_tba &= 0xffffffffffff8000; /* keep only trap base address */ |
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133 | |
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134 | tba = (CPU_Trap_table_entry *) u64_tba; |
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135 | |
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136 | /* use array indexing to fill in lower bits -- require |
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137 | * CPU_Trap_table_entry to be full-sized. */ |
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138 | slot = &tba[ real_vector ]; |
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139 | |
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140 | /* |
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141 | * Get the address of the old_handler from the trap table. |
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142 | * |
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143 | * NOTE: The old_handler returned will be bogus if it does not follow |
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144 | * the RTEMS model. |
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145 | */ |
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146 | |
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147 | /* shift amount to shift of hi bits (31:10) */ |
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148 | #define HI_BITS_SHIFT 10 |
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149 | |
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150 | /* shift amount of hm bits (41:32) */ |
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151 | #define HM_BITS_SHIFT 32 |
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152 | |
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153 | /* shift amount of hh bits (63:42) */ |
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154 | #define HH_BITS_SHIFT 42 |
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155 | |
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156 | /* We're only interested in bits 0-9 of the immediate field*/ |
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157 | #define IMM_MASK 0x000003FF |
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158 | |
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159 | if ( slot->rdpr_tstate_g4 == _CPU_Trap_slot_template.rdpr_tstate_g4 ) { |
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160 | u64_handler = |
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161 | (((uint64_t)((slot->sethi_of_hh_handler_to_g2 << HI_BITS_SHIFT) | |
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162 | (slot->or_g2_hm_handler_to_g2 & IMM_MASK))) << HM_BITS_SHIFT) | |
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163 | ((slot->sethi_of_handler_to_g3 << HI_BITS_SHIFT) | |
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164 | (slot->jmp_to_low_of_handler_plus_g3 & IMM_MASK)); |
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165 | *old_handler = (proc_ptr) u64_handler; |
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166 | } else |
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167 | *old_handler = 0; |
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168 | |
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169 | /* |
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170 | * Copy the template to the slot and then fix it. |
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171 | */ |
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172 | |
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173 | *slot = _CPU_Trap_slot_template; |
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174 | |
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175 | u64_handler = (uint64_t) new_handler; |
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176 | |
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177 | /* mask for extracting %hh */ |
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178 | #define HH_BITS_MASK 0xFFFFFC0000000000 |
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179 | |
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180 | /* mask for extracting %hm */ |
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181 | #define HM_BITS_MASK 0x000003FF00000000 |
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182 | |
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183 | /* mask for extracting %hi */ |
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184 | #define HI_BITS_MASK 0x00000000FFFFFC00 |
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185 | |
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186 | /* mask for extracting %lo */ |
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187 | #define LO_BITS_MASK 0x00000000000003FF |
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188 | |
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189 | |
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190 | slot->mov_vector_g2 |= vector; |
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191 | slot->sethi_of_hh_handler_to_g2 |= |
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192 | (u64_handler & HH_BITS_MASK) >> HH_BITS_SHIFT; |
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193 | slot->or_g2_hm_handler_to_g2 |= |
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194 | (u64_handler & HM_BITS_MASK) >> HM_BITS_SHIFT; |
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195 | slot->sethi_of_handler_to_g3 |= |
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196 | (u64_handler & HI_BITS_MASK) >> HI_BITS_SHIFT; |
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197 | slot->jmp_to_low_of_handler_plus_g3 |= (u64_handler & LO_BITS_MASK); |
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198 | |
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199 | /* need to flush icache after this !!! */ |
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200 | |
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201 | /* need to flush icache in case old trap handler is in cache */ |
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202 | rtems_cache_invalidate_entire_instruction(); |
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203 | |
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204 | } |
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205 | |
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206 | /*PAGE |
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207 | * |
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208 | * _CPU_ISR_install_vector |
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209 | * |
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210 | * This kernel routine installs the RTEMS handler for the |
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211 | * specified vector. |
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212 | * |
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213 | * Input parameters: |
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214 | * vector - interrupt vector number |
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215 | * new_handler - replacement ISR for this vector number |
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216 | * old_handler - pointer to former ISR for this vector number |
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217 | * |
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218 | * Output parameters: |
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219 | * *old_handler - former ISR for this vector number |
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220 | * |
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221 | */ |
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222 | |
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223 | void _CPU_ISR_install_vector( |
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224 | uint64_t vector, |
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225 | proc_ptr new_handler, |
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226 | proc_ptr *old_handler |
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227 | ) |
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228 | { |
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229 | uint64_t real_vector; |
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230 | proc_ptr ignored; |
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231 | |
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232 | /* |
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233 | * Get the "real" trap number for this vector ignoring the synchronous |
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234 | * versus asynchronous indicator included with our vector numbers. |
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235 | */ |
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236 | real_vector = SPARC_REAL_TRAP_NUMBER( vector ); |
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237 | /* |
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238 | * Return the previous ISR handler. |
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239 | */ |
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240 | |
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241 | *old_handler = _ISR_Vector_table[ vector ]; |
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242 | |
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243 | /* |
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244 | * Install the wrapper so this ISR can be invoked properly. |
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245 | */ |
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246 | |
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247 | _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); |
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248 | |
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249 | /* |
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250 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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251 | * be used by the _ISR_Handler so the user gets control. |
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252 | */ |
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253 | |
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254 | _ISR_Vector_table[ real_vector ] = new_handler; |
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255 | } |
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