source: rtems/c/src/lib/libcpu/sparc64/shared/score/cpu.c @ 71d97c9

4.115
Last change on this file since 71d97c9 was 71d97c9, checked in by Gedare Bloom <gedare@…>, on Dec 8, 2014 at 6:16:37 PM

sparc64: put each copyright on one line

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1/*
2 *  SPARC-v9 Dependent Source
3 */
4
5/*
6 *  COPYRIGHT (c) 1989-2007. On-Line Applications Research Corporation (OAR).
7 *
8 *  This file is based on the SPARC cpu.c file. Modifications are made to
9 *  provide support for the SPARC-v9.
10 *  COPYRIGHT (c) 2010. Gedare Bloom.
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.org/license/LICENSE.
15 */
16
17#include <rtems/system.h>
18#include <rtems/asm.h>
19#include <rtems/score/isr.h>
20#include <rtems/rtems/cache.h>
21
22/*
23 *  This initializes the set of opcodes placed in each trap
24 *  table entry.  The routine which installs a handler is responsible
25 *  for filling in the fields for the _handler address and the _vector
26 *  trap type.
27 *
28 *  The constants following this structure are masks for the fields which
29 *  must be filled in when the handler is installed.
30 */
31
32/*  64-bit registers complicate this. Also, in sparc v9,
33 *      each trap level gets its own set of global registers, but
34 *      does not get its own dedicated register window. so we avoid
35 *      using the local registers in the trap handler.
36 */
37const CPU_Trap_table_entry _CPU_Trap_slot_template = {
38  0x89508000,   /* rdpr   %tstate, %g4       */
39  0x05000000,   /* sethi %hh(_handler), %g2  */
40  0x8410a000,   /* or     %g2, %hm(_handler), %g2 */
41  0x8528b020,   /* sllx   %g2, 32, %g2 */
42  0x07000000,   /* sethi  %hi(_handler), %g3 */
43  0x8610c002,   /* or     %g3, %g2, %g3 */
44  0x81c0e000, /* jmp   %g3 + %lo(_handler) */
45  0x84102000  /* mov   _vector, %g2        */
46};
47
48
49/*
50 *  _CPU_ISR_Get_level
51 *
52 *  Input Parameters: NONE
53 *
54 *  Output Parameters:
55 *    returns the current interrupt level (PIL field of the PSR)
56 */
57uint32_t   _CPU_ISR_Get_level( void )
58{
59  uint32_t   level;
60
61  sparc64_get_interrupt_level( level );
62
63  return level;
64}
65
66/*
67 *  _CPU_ISR_install_raw_handler
68 *
69 *  This routine installs the specified handler as a "raw" non-executive
70 *  supported trap handler (a.k.a. interrupt service routine).
71 *
72 *  Input Parameters:
73 *    vector      - trap table entry number plus synchronous
74 *                    vs. asynchronous information
75 *    new_handler - address of the handler to be installed
76 *    old_handler - pointer to an address of the handler previously installed
77 *
78 *  Output Parameters: NONE
79 *    *new_handler - address of the handler previously installed
80 *
81 *  NOTE:
82 *
83 *  On the SPARC v9, there are really only 512 vectors.  However, the executive
84 *  has no easy, fast, reliable way to determine which traps are synchronous
85 *  and which are asynchronous.  By default, traps return to the
86 *  instruction which caused the interrupt.  So if you install a software
87 *  trap handler as an executive interrupt handler (which is desirable since
88 *  RTEMS takes care of window and register issues), then the executive needs
89 *  to know that the return address is to the trap rather than the instruction
90 *  following the trap.
91 *
92 *  So vectors 0 through 511 are treated as regular asynchronous traps which
93 *  provide the "correct" return address.  Vectors 512 through 1023 are assumed
94 *  by the executive to be synchronous and to require that the return be to the
95 *  trapping instruction.
96 *
97 *  If you use this mechanism to install a trap handler which must reexecute
98 *  the instruction which caused the trap, then it should be installed as
99 *  a synchronous trap.  This will avoid the executive changing the return
100 *  address.
101 */
102void _CPU_ISR_install_raw_handler(
103  uint32_t    vector,
104  proc_ptr    new_handler,
105  proc_ptr   *old_handler
106)
107{
108  uint32_t               real_vector;
109  CPU_Trap_table_entry  *tba;
110  CPU_Trap_table_entry  *slot;
111  uint64_t               u64_tba;
112  uint64_t               u64_handler;
113
114  /*
115   *  Get the "real" trap number for this vector ignoring the synchronous
116   *  versus asynchronous indicator included with our vector numbers.
117   */
118
119  real_vector = SPARC_REAL_TRAP_NUMBER( vector );
120
121  /*
122   *  Get the current base address of the trap table and calculate a pointer
123   *  to the slot we are interested in.
124   */
125
126  sparc64_get_tba( u64_tba );
127
128/*  u32_tbr &= 0xfffff000; */
129  u64_tba &= 0xffffffffffff8000;  /* keep only trap base address */
130
131  tba = (CPU_Trap_table_entry *) u64_tba;
132
133  /* use array indexing to fill in lower bits -- require
134   * CPU_Trap_table_entry to be full-sized. */
135  slot = &tba[ real_vector ];
136
137  /*
138   *  Get the address of the old_handler from the trap table.
139   *
140   *  NOTE: The old_handler returned will be bogus if it does not follow
141   *        the RTEMS model.
142   */
143
144  /* shift amount to shift of hi bits (31:10) */
145#define HI_BITS_SHIFT  10
146
147  /* shift amount of hm bits (41:32) */
148#define HM_BITS_SHIFT  32
149
150  /* shift amount of hh bits (63:42) */
151#define HH_BITS_SHIFT  42
152
153  /* We're only interested in bits 0-9 of the immediate field*/
154#define IMM_MASK    0x000003FF
155
156  if ( slot->rdpr_tstate_g4 == _CPU_Trap_slot_template.rdpr_tstate_g4 ) {
157    u64_handler =
158      (((uint64_t)((slot->sethi_of_hh_handler_to_g2 << HI_BITS_SHIFT) |
159      (slot->or_g2_hm_handler_to_g2 & IMM_MASK))) << HM_BITS_SHIFT) |
160      ((slot->sethi_of_handler_to_g3 << HI_BITS_SHIFT) |
161      (slot->jmp_to_low_of_handler_plus_g3 & IMM_MASK));
162    *old_handler = (proc_ptr) u64_handler;
163  } else
164    *old_handler = 0;
165
166  /*
167   *  Copy the template to the slot and then fix it.
168   */
169
170  *slot = _CPU_Trap_slot_template;
171
172  u64_handler = (uint64_t) new_handler;
173
174  /* mask for extracting %hh */
175#define HH_BITS_MASK   0xFFFFFC0000000000
176
177  /* mask for extracting %hm */
178#define HM_BITS_MASK   0x000003FF00000000
179
180  /* mask for extracting %hi */
181#define HI_BITS_MASK   0x00000000FFFFFC00
182
183  /* mask for extracting %lo */
184#define LO_BITS_MASK   0x00000000000003FF
185
186
187  slot->mov_vector_g2 |= vector;
188  slot->sethi_of_hh_handler_to_g2 |=
189    (u64_handler & HH_BITS_MASK) >> HH_BITS_SHIFT;
190  slot->or_g2_hm_handler_to_g2 |=
191    (u64_handler & HM_BITS_MASK) >> HM_BITS_SHIFT;
192  slot->sethi_of_handler_to_g3 |=
193    (u64_handler & HI_BITS_MASK) >> HI_BITS_SHIFT;
194  slot->jmp_to_low_of_handler_plus_g3 |= (u64_handler & LO_BITS_MASK);
195
196  /* need to flush icache after this !!! */
197
198  /* need to flush icache in case old trap handler is in cache */
199  rtems_cache_invalidate_entire_instruction();
200
201}
202
203/*
204 *  _CPU_ISR_install_vector
205 *
206 *  This kernel routine installs the RTEMS handler for the
207 *  specified vector.
208 *
209 *  Input parameters:
210 *    vector       - interrupt vector number
211 *    new_handler  - replacement ISR for this vector number
212 *    old_handler  - pointer to former ISR for this vector number
213 *
214 *  Output parameters:
215 *    *old_handler - former ISR for this vector number
216 */
217void _CPU_ISR_install_vector(
218  uint64_t    vector,
219  proc_ptr    new_handler,
220  proc_ptr   *old_handler
221)
222{
223   uint64_t   real_vector;
224   proc_ptr   ignored;
225
226  /*
227   *  Get the "real" trap number for this vector ignoring the synchronous
228   *  versus asynchronous indicator included with our vector numbers.
229   */
230   real_vector = SPARC_REAL_TRAP_NUMBER( vector );
231   /*
232    *  Return the previous ISR handler.
233    */
234
235   *old_handler = _ISR_Vector_table[ vector ];
236
237   /*
238    *  Install the wrapper so this ISR can be invoked properly.
239    */
240
241   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
242
243   /*
244    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
245    *  be used by the _ISR_Handler so the user gets control.
246    */
247
248    _ISR_Vector_table[ real_vector ] = new_handler;
249}
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