source: rtems/c/src/lib/libcpu/sparc64/ChangeLog @ 646e7b0d

4.115
Last change on this file since 646e7b0d was 646e7b0d, checked in by Joel Sherrill <joel.sherrill@…>, on 06/29/10 at 00:39:44

2010-06-28 Joel Sherrill <joel.sherrill@…>

PR 1573/cpukit

  • shared/score/interrupt.S: Add a per cpu data structure which contains the information required by RTEMS for each CPU core. This encapsulates information such as thread executing, heir, idle and dispatch needed.
  • Property mode set to 100644
File size: 2.0 KB
Line 
12010-06-28      Joel Sherrill <joel.sherrill@oarcorp.com>
2
3        PR 1573/cpukit
4        * shared/score/interrupt.S: Add a per cpu data structure which contains
5        the information required by RTEMS for each CPU core. This
6        encapsulates information such as thread executing, heir, idle and
7        dispatch needed.
8
92010-06-17      Joel Sherrill <joel.sherrill@oarcorp.com>
10
11        * .cvsignore, ChangeLog, Makefile.am, configure.ac, preinstall.am,
12        shared/cache/cache.c, shared/cache/cache_.h,
13        shared/interrupts/installisrentries.c, shared/score/cpu.c,
14        shared/score/interrupt.S, shared/syscall/sparc64-syscall.S,
15        shared/syscall/sparc64-syscall.h: New files.
16
172010-05-13  Gedare Bloom <gedare@gwmail.gwu.edu>
18
19        * sun4u/syscall/sparc-syscall.S: disable/enable interrupts directly.
20
212010-05-10  Gedare Bloom <gedare@gwmail.gwu.edu>
22
23        * shared/score/cpu.c, Makefile.am: Moved cpu.c from sun4v/score
24        * configure.ac: m5sim is no longer part of shared. sun4u option added.
25
262010-05-10  Gedare Bloom <gedare@gwmail.gwu.edu>
27
28        * sun4u/: New model specific subdir.
29        * sun4u/score/, sun4u/syscall/: Copied from sun4v.
30
312010-05-03  Gedare Bloom <gedare@gwmail.gwu.edu>
32
33        * m5sim/syscall/sparc-syscall.h, m5sim/syscall/sparc-syscall.S:
34        Renamed files from syscall.h and syscall.S
35
362010-05-03  Gedare Bloom <gedare@gwmail.gwu.edu>
37
38        * sun4v/syscall/syscall.S: Explicitly enable IE bit when using
39        SYS_irqset.
40        * m5sim/score/cpu.c: install raw handler and isr get level are nops
41
422010-05-02  Gedare Bloom <gedare@gwmail.gwu.edu>
43
44        * m5sim/score m5sim/syscall: new subdirs
45        * m5sim/syscall/syscall.h m5sim/syscall/syscall.S: New files.
46
472010-05-02  Gedare Bloom <gedare@gwmail.gwu.edu>
48
49        * sun4v/score/cpu_asm.S: Remove context switch code.
50
512010-05-02  Gedare Bloom <gedare@gwmail.gwu.edu>
52
53        * shared/, shared/cache, shared/interrupts: Moved cache and
54        interrupts into shared folder.
55
562010-05-02  Gedare Bloom <gedare@gwmail.gwu.edu>
57
58        * sun4v, sun4v/score/cpu_asm.S, sun4v/score/cpu.c: Copied from
59        score/cpu/sparc64
60
612010-05-02  Gedare Bloom <gedare@gwmail.gwu.edu>
62
63        * ChangeLog: New file.
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