source: rtems/c/src/lib/libcpu/sparc/include/erc32.h @ 9700578

4.104.114.84.95
Last change on this file since 9700578 was 9700578, checked in by Joel Sherrill <joel.sherrill@…>, on 10/30/95 at 21:54:45

SPARC port passes all tests
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1/*  erc32.h
2 *
3 *  This include file contains information pertaining to the ERC32.
4 *  The ERC32 is a custom SPARC V7 implementation based on the Cypress
5 *  601/602 chipset.  This CPU has a number of on-board peripherals and
6 *  was developed by the European Space Agency to target space applications.
7 *
8 *  NOTE:  Other than where absolutely required, this version currently
9 *         supports only the peripherals and bits used by the basic board
10 *         support package. This includes at least significant pieces of
11 *         the following items:
12 *
13 *           + UART Channels A and B
14 *           + General Purpose Timer
15 *           + Real Time Clock
16 *           + Watchdog Timer (so it can be disabled)
17 *           + Control Register (so powerdown mode can be enabled)
18 *           + Memory Control Register
19 *           + Interrupt Control
20 *
21 *  $Id$
22 */
23 
24#ifndef _INCLUDE_ERC32_h
25#define _INCLUDE_ERC32_h
26
27#include <rtems/score/sparc.h>
28 
29#ifdef __cplusplus
30extern "C" {
31#endif
32
33/*
34 *  Interrupt Sources
35 *
36 *  The interrupt source numbers directly map to the trap type and to
37 *  the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask,
38 *  and the Interrupt Pending Registers.
39 */
40
41#define ERC32_INTERRUPT_MASKED_ERRORS             1
42#define ERC32_INTERRUPT_EXTERNAL_1                2
43#define ERC32_INTERRUPT_EXTERNAL_2                3
44#define ERC32_INTERRUPT_UART_A_RX_TX              4
45#define ERC32_INTERRUPT_UART_B_RX_TX              5
46#define ERC32_INTERRUPT_CORRECTABLE_MEMORY_ERROR  6
47#define ERC32_INTERRUPT_UART_ERROR                7
48#define ERC32_INTERRUPT_DMA_ACCESS_ERROR          8
49#define ERC32_INTERRUPT_DMA_TIMEOUT               9
50#define ERC32_INTERRUPT_EXTERNAL_3               10
51#define ERC32_INTERRUPT_EXTERNAL_4               11
52#define ERC32_INTERRUPT_GENERAL_PURPOSE_TIMER    12
53#define ERC32_INTERRUPT_REAL_TIME_CLOCK          13
54#define ERC32_INTERRUPT_EXTERNAL_5               14
55#define ERC32_INTERRUPT_WATCHDOG_TIMEOUT         15
56
57#ifndef ASM
58
59/*
60 *  Trap Types for on-chip peripherals
61 *
62 *  Source: Table 8 - Interrupt Trap Type and Default Priority Assignments
63 *
64 *  NOTE: The priority level for each source corresponds to the least
65 *        significant nibble of the trap type.
66 */
67
68#define ERC32_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10)
69
70#define ERC32_TRAP_SOURCE( _trap ) ((_trap) - 0x10)
71
72#define ERC32_Is_MEC_Trap( _trap ) \
73  ( (_trap) >= ERC32_TRAP_TYPE( ERC32_INTERRUPT_MASKED_ERRORS ) && \
74    (_trap) <= ERC32_TRAP_TYPE( ERC32_INTERRUPT_WATCHDOG_TIMEOUT ) )
75
76/*
77 *  Structure for ERC32 memory mapped registers. 
78 *
79 *  Source: Section 3.25.2 - Register Address Map
80 *
81 *  NOTE:  There is only one of these structures per CPU, its base address
82 *         is 0x01f80000, and the variable MEC is placed there by the
83 *         linkcmds file.
84 */
85
86typedef struct {
87  volatile unsigned32  Control;                              /* offset 0x00 */
88  volatile unsigned32  Software_Reset;                       /* offset 0x04 */
89  volatile unsigned32  Power_Down;                           /* offset 0x08 */
90  volatile unsigned32  Unimplemented_0;                      /* offset 0x0c */
91  volatile unsigned32  Memory_Configuration;                 /* offset 0x10 */
92  volatile unsigned32  IO_Configuration;                     /* offset 0x14 */
93  volatile unsigned32  Wait_State_Configuration;             /* offset 0x18 */
94  volatile unsigned32  Unimplemented_1;                      /* offset 0x1c */
95  volatile unsigned32  Memory_Access_0;                      /* offset 0x20 */
96  volatile unsigned32  Memory_Access_1;                      /* offset 0x24 */
97  volatile unsigned32  Unimplemented_2[ 7 ];                 /* offset 0x28 */
98  volatile unsigned32  Interrupt_Shape;                      /* offset 0x44 */
99  volatile unsigned32  Interrupt_Pending;                    /* offset 0x48 */
100  volatile unsigned32  Interrupt_Mask;                       /* offset 0x4c */
101  volatile unsigned32  Interrupt_Clear;                      /* offset 0x50 */
102  volatile unsigned32  Interrupt_Force;                      /* offset 0x54 */
103  volatile unsigned32  Unimplemented_3[ 2 ];                 /* offset 0x58 */
104                                                             /* offset 0x60 */
105  volatile unsigned32  Watchdog_Program_and_Timeout_Acknowledge;
106  volatile unsigned32  Watchdog_Trap_Door_Set;               /* offset 0x64 */
107  volatile unsigned32  Unimplemented_4[ 6 ];                 /* offset 0x68 */
108  volatile unsigned32  Real_Time_Clock_Counter;              /* offset 0x80 */
109  volatile unsigned32  Real_Time_Clock_Scalar;               /* offset 0x84 */
110  volatile unsigned32  General_Purpose_Timer_Counter;        /* offset 0x88 */
111  volatile unsigned32  General_Purpose_Timer_Scalar;         /* offset 0x8c */
112  volatile unsigned32  Unimplemented_5[ 2 ];                 /* offset 0x90 */
113  volatile unsigned32  Timer_Control;                        /* offset 0x98 */
114  volatile unsigned32  Unimplemented_6;                      /* offset 0x9c */
115  volatile unsigned32  System_Fault_Status;                  /* offset 0xa0 */
116  volatile unsigned32  First_Failing_Address;                /* offset 0xa4 */
117  volatile unsigned32  First_Failing_Data;                   /* offset 0xa8 */
118  volatile unsigned32  First_Failing_Syndrome_and_Check_Bits;/* offset 0xac */
119  volatile unsigned32  Error_and_Reset_Status;               /* offset 0xb0 */
120  volatile unsigned32  Error_Mask;                           /* offset 0xb4 */
121  volatile unsigned32  Unimplemented_7[ 2 ];                 /* offset 0xb8 */
122  volatile unsigned32  Debug_Control;                        /* offset 0xc0 */
123  volatile unsigned32  Breakpoint;                           /* offset 0xc4 */
124  volatile unsigned32  Watchpoint;                           /* offset 0xc8 */
125  volatile unsigned32  Unimplemented_8;                      /* offset 0xcc */
126  volatile unsigned32  Test_Control;                         /* offset 0xd0 */
127  volatile unsigned32  Test_Data;                            /* offset 0xd4 */
128  volatile unsigned32  Unimplemented_9[ 2 ];                 /* offset 0xd8 */
129  volatile unsigned32  UART_Channel_A;                       /* offset 0xe0 */
130  volatile unsigned32  UART_Channel_B;                       /* offset 0xe4 */
131  volatile unsigned32  UART_Status;                          /* offset 0xe8 */
132} ERC32_Register_Map;
133
134#endif
135
136/*
137 *  The following constants are intended to be used ONLY in assembly
138 *  language files.
139 *
140 *  NOTE:  The intended style of usage is to load the address of MEC
141 *         into a register and then use these as displacements from
142 *         that register.
143 */
144
145#ifdef ASM
146
147#define  ERC32_MEC_CONTROL_OFFSET                                  0x00
148#define  ERC32_MEC_SOFTWARE_RESET_OFFSET                           0x04
149#define  ERC32_MEC_POWER_DOWN_OFFSET                               0x08
150#define  ERC32_MEC_UNIMPLEMENTED_0_OFFSET                          0x0C
151#define  ERC32_MEC_MEMORY_CONFIGURATION_OFFSET                     0x10
152#define  ERC32_MEC_IO_CONFIGURATION_OFFSET                         0x14
153#define  ERC32_MEC_WAIT_STATE_CONFIGURATION_OFFSET                 0x18
154#define  ERC32_MEC_UNIMPLEMENTED_1_OFFSET                          0x1C
155#define  ERC32_MEC_MEMORY_ACCESS_0_OFFSET                          0x20
156#define  ERC32_MEC_MEMORY_ACCESS_1_OFFSET                          0x24
157#define  ERC32_MEC_UNIMPLEMENTED_2_OFFSET                          0x28
158#define  ERC32_MEC_INTERRUPT_SHAPE_OFFSET                          0x44
159#define  ERC32_MEC_INTERRUPT_PENDING_OFFSET                        0x48
160#define  ERC32_MEC_INTERRUPT_MASK_OFFSET                           0x4C
161#define  ERC32_MEC_INTERRUPT_CLEAR_OFFSET                          0x50
162#define  ERC32_MEC_INTERRUPT_FORCE_OFFSET                          0x54
163#define  ERC32_MEC_UNIMPLEMENTED_3_OFFSET                          0x58
164#define  ERC32_MEC_WATCHDOG_PROGRAM_AND_TIMEOUT_ACKNOWLEDGE_OFFSET 0x60
165#define  ERC32_MEC_WATCHDOG_TRAP_DOOR_SET_OFFSET                   0x64
166#define  ERC32_MEC_UNIMPLEMENTED_4_OFFSET                          0x6C
167#define  ERC32_MEC_REAL_TIME_CLOCK_COUNTER_OFFSET                  0x80
168#define  ERC32_MEC_REAL_TIME_CLOCK_SCALAR_OFFSET                   0x84
169#define  ERC32_MEC_GENERAL_PURPOSE_TIMER_COUNTER_OFFSET            0x88
170#define  ERC32_MEC_GENERAL_PURPOSE_TIMER_SCALAR_OFFSET             0x8C
171#define  ERC32_MEC_UNIMPLEMENTED_5_OFFSET                          0x90
172#define  ERC32_MEC_TIMER_CONTROL_OFFSET                            0x98
173#define  ERC32_MEC_UNIMPLEMENTED_6_OFFSET                          0x9C
174#define  ERC32_MEC_SYSTEM_FAULT_STATUS_OFFSET                      0xA0
175#define  ERC32_MEC_FIRST_FAILING_ADDRESS_OFFSET                    0xA4
176#define  ERC32_MEC_FIRST_FAILING_DATA_OFFSET                       0xA8
177#define  ERC32_MEC_FIRST_FAILING_SYNDROME_AND_CHECK_BITS_OFFSET    0xAC
178#define  ERC32_MEC_ERROR_AND_RESET_STATUS_OFFSET                   0xB0
179#define  ERC32_MEC_ERROR_MASK_OFFSET                               0xB4
180#define  ERC32_MEC_UNIMPLEMENTED_7_OFFSET                          0xB8
181#define  ERC32_MEC_DEBUG_CONTROL_OFFSET                            0xC0
182#define  ERC32_MEC_BREAKPOINT_OFFSET                               0xC4
183#define  ERC32_MEC_WATCHPOINT_OFFSET                               0xC8
184#define  ERC32_MEC_UNIMPLEMENTED_8_OFFSET                          0xCC
185#define  ERC32_MEC_TEST_CONTROL_OFFSET                             0xD0
186#define  ERC32_MEC_TEST_DATA_OFFSET                                0xD4
187#define  ERC32_MEC_UNIMPLEMENTED_9_OFFSET                          0xD8
188#define  ERC32_MEC_UART_CHANNEL_A_OFFSET                           0xE0
189#define  ERC32_MEC_UART_CHANNEL_B_OFFSET                           0xE4
190#define  ERC32_MEC_UART_STATUS_OFFSET                              0xE8
191
192#endif
193
194/*
195 *  The following defines the bits in the Configuration Register.
196 */
197
198#define ERC32_CONFIGURATION_POWER_DOWN_MASK               0x00000001
199#define ERC32_CONFIGURATION_POWER_DOWN_ALLOWED            0x00000001
200#define ERC32_CONFIGURATION_POWER_DOWN_DISABLED           0x00000000
201
202#define ERC32_CONFIGURATION_SOFTWARE_RESET_MASK           0x00000002
203#define ERC32_CONFIGURATION_SOFTWARE_RESET_ALLOWED        0x00000002
204#define ERC32_CONFIGURATION_SOFTWARE_RESET_DISABLED       0x00000000
205
206#define ERC32_CONFIGURATION_BUS_TIMEOUT_MASK              0x00000004
207#define ERC32_CONFIGURATION_BUS_TIMEOUT_ENABLED           0x00000004
208#define ERC32_CONFIGURATION_BUS_TIMEOUT_DISABLED          0x00000000
209
210#define ERC32_CONFIGURATION_ACCESS_PROTECTION_MASK        0x00000008
211#define ERC32_CONFIGURATION_ACCESS_PROTECTION_ENABLED     0x00000008
212#define ERC32_CONFIGURATION_ACCESS_PROTECTION_DISABLED    0x00000000
213
214
215/*
216 *  The following defines the bits in the Memory Configuration Register.
217 */
218
219#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_MASK  0x00001C00
220#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_256K  ( 0 << 10 )
221#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_512K  ( 1 << 10 )
222#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_1MB   ( 2 << 10 )
223#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_2MB   ( 3 << 10 )
224#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_4MB   ( 4 << 10 )
225#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_8MB   ( 5 << 10 )
226#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_16MB  ( 6 << 10 )
227#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_32MB  ( 7 << 10 )
228
229#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_MASK  0x001C0000
230#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4K    ( 0 << 18 )
231#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8K    ( 1 << 18 )
232#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16K   ( 2 << 18 )
233#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_32K   ( 3 << 18 )
234#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_64K   ( 4 << 18 )
235#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K  ( 5 << 18 )
236#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K  ( 6 << 18 )
237#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K  ( 7 << 18 )
238 
239/*
240 *  The following defines the bits in the Timer Control Register.
241 */
242
243#define ERC32_MEC_TIMER_CONTROL_GCR    0x00000001  /* 1 = reload at 0 */
244                                               /* 0 = stop at 0 */
245#define ERC32_MEC_TIMER_CONTROL_GCL    0x00000002  /* 1 = load and start */
246                                               /* 0 = no function */
247#define ERC32_MEC_TIMER_CONTROL_GSE    0x00000004  /* 1 = enable counting */
248                                               /* 0 = hold scalar and counter */
249#define ERC32_MEC_TIMER_CONTROL_GSL    0x00000008  /* 1 = load scalar and start */
250                                               /* 0 = no function */
251
252#define ERC32_MEC_TIMER_CONTROL_RTCCR  0x00000100  /* 1 = reload at 0 */
253                                               /* 0 = stop at 0 */
254#define ERC32_MEC_TIMER_CONTROL_RTCCL  0x00000200  /* 1 = load and start */
255                                               /* 0 = no function */
256#define ERC32_MEC_TIMER_CONTROL_RTCSE  0x00000400  /* 1 = enable counting */
257                                               /* 0 = hold scalar and counter */
258#define ERC32_MEC_TIMER_CONTROL_RTCSL  0x00000800  /* 1 = load scalar and start */
259                                               /* 0 = no function */
260
261/*
262 *  The following defines the bits in the UART Control Registers.
263 *
264 *  NOTE: Same bits in UART channels A and B.
265 */
266
267#define ERC32_MEC_UART_CONTROL_RTD  0x000000FF /* RX/TX data */
268#define ERC32_MEC_UART_CONTROL_DR   0x00000100 /* RX Data Ready */
269#define ERC32_MEC_UART_CONTROL_TSE  0x00000200 /* TX Send Empty */
270                                               /*   (i.e. no data to send) */
271#define ERC32_MEC_UART_CONTROL_THE  0x00000400 /* TX Hold Empty */
272                                               /*   (i.e. ready to load) */
273 
274/*
275 *  The following defines the bits in the MEC UART Control Registers.
276 */
277
278#define ERC32_MEC_UART_STATUS_DR   0x00000001 /* Data Ready */
279#define ERC32_MEC_UART_STATUS_TSE  0x00000002 /* TX Send Register Empty */
280#define ERC32_MEC_UART_STATUS_THE  0x00000004 /* TX Hold Register Empty */
281#define ERC32_MEC_UART_STATUS_FE   0x00000010 /* RX Framing Error */
282#define ERC32_MEC_UART_STATUS_PE   0x00000020 /* RX Parity Error */
283#define ERC32_MEC_UART_STATUS_OE   0x00000040 /* RX Overrun Error */
284#define ERC32_MEC_UART_STATUS_CU   0x00000080 /* Clear Errors */
285#define ERC32_MEC_UART_STATUS_TXE  0x00000006 /* TX Empty */
286
287#define ERC32_MEC_UART_STATUS_DRA   (ERC32_MEC_UART_STATUS_DR  << 0)
288#define ERC32_MEC_UART_STATUS_TSEA  (ERC32_MEC_UART_STATUS_TSE << 0)
289#define ERC32_MEC_UART_STATUS_THEA  (ERC32_MEC_UART_STATUS_THE << 0)
290#define ERC32_MEC_UART_STATUS_FEA   (ERC32_MEC_UART_STATUS_FE  << 0)
291#define ERC32_MEC_UART_STATUS_PEA   (ERC32_MEC_UART_STATUS_PE  << 0)
292#define ERC32_MEC_UART_STATUS_OEA   (ERC32_MEC_UART_STATUS_OE  << 0)
293#define ERC32_MEC_UART_STATUS_CUA   (ERC32_MEC_UART_STATUS_CU  << 0)
294#define ERC32_MEC_UART_STATUS_TXEA  (ERC32_MEC_UART_STATUS_TXE << 0)
295
296#define ERC32_MEC_UART_STATUS_DRB   (ERC32_MEC_UART_STATUS_DR  << 16)
297#define ERC32_MEC_UART_STATUS_TSEB  (ERC32_MEC_UART_STATUS_TSE << 16)
298#define ERC32_MEC_UART_STATUS_THEB  (ERC32_MEC_UART_STATUS_THE << 16)
299#define ERC32_MEC_UART_STATUS_FEB   (ERC32_MEC_UART_STATUS_FE  << 16)
300#define ERC32_MEC_UART_STATUS_PEB   (ERC32_MEC_UART_STATUS_PE  << 16)
301#define ERC32_MEC_UART_STATUS_OEB   (ERC32_MEC_UART_STATUS_OE  << 16)
302#define ERC32_MEC_UART_STATUS_CUB   (ERC32_MEC_UART_STATUS_CU  << 16)
303#define ERC32_MEC_UART_STATUS_TXEB  (ERC32_MEC_UART_STATUS_TXE << 16)
304
305#ifndef ASM
306
307/*
308 *  This is used to manipulate the on-chip registers.
309 *
310 *  The following symbol must be defined in the linkcmds file and point
311 *  to the correct location.
312 */
313
314extern ERC32_Register_Map ERC32_MEC;
315 
316/*
317 *  Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask,
318 *  and the Interrupt Pending Registers.
319 *
320 *  NOTE: For operations which are not atomic, this code disables interrupts
321 *        to guarantee there are no intervening accesses to the same register.
322 *        The operations which read the register, modify the value and then
323 *        store the result back are vulnerable.
324 */
325
326#define ERC32_Clear_interrupt( _source ) \
327  do { \
328    ERC32_MEC.Interrupt_Clear = (1 << (_source)); \
329  } while (0)
330
331#define ERC32_Force_interrupt( _source ) \
332  do { \
333    ERC32_MEC.Interrupt_Force = (1 << (_source)); \
334  } while (0)
335 
336#define ERC32_Is_interrupt_pending( _source ) \
337  (ERC32_MEC.Interrupt_Pending & (1 << (_source)))
338 
339#define ERC32_Is_interrupt_masked( _source ) \
340  (ERC32_MEC.Interrupt_Masked & (1 << (_source)))
341 
342#define ERC32_Mask_interrupt( _source ) \
343  do { \
344    unsigned32 _level; \
345    \
346    sparc_disable_interrupts( _level ); \
347      ERC32_MEC.Interrupt_Mask |= (1 << (_source)); \
348    sparc_enable_interrupts( _level ); \
349  } while (0)
350 
351#define ERC32_Unmask_interrupt( _source ) \
352  do { \
353    unsigned32 _level; \
354    \
355    sparc_disable_interrupts( _level ); \
356      ERC32_MEC.Interrupt_Mask &= ~(1 << (_source)); \
357    sparc_enable_interrupts( _level ); \
358  } while (0)
359
360#define ERC32_Disable_interrupt( _source, _previous ) \
361  do { \
362    unsigned32 _level; \
363    unsigned32 _mask = 1 << (_source); \
364    \
365    sparc_disable_interrupts( _level ); \
366      (_previous) = ERC32_MEC.Interrupt_Mask; \
367      ERC32_MEC.Interrupt_Mask = _previous | _mask; \
368    sparc_enable_interrupts( _level ); \
369    (_previous) &= ~_mask; \
370  } while (0)
371 
372#define ERC32_Restore_interrupt( _source, _previous ) \
373  do { \
374    unsigned32 _level; \
375    unsigned32 _mask = 1 << (_source); \
376    \
377    sparc_disable_interrupts( _level ); \
378      ERC32_MEC.Interrupt_Mask = \
379        (ERC32_MEC.Interrupt_Mask & ~_mask) | (_previous); \
380    sparc_enable_interrupts( _level ); \
381  } while (0)
382
383/*
384 *  The following macros attempt to hide the fact that the General Purpose
385 *  Timer and Real Time Clock Timer share the Timer Control Register.  Because
386 *  the Timer Control Register is write only, we must mirror it in software
387 *  and insure that writes to one timer do not alter the current settings
388 *  and status of the other timer.
389 *
390 *  This code promotes the view that the two timers are completely independent.
391 *  By exclusively using the routines below to access the Timer Control
392 *  Register, the application can view the system as having a General Purpose
393 *  Timer Control Register and a Real Time Clock Timer Control Register
394 *  rather than the single shared value.
395 *
396 *  Each logical timer control register is organized as follows:
397 *
398 *    D0 - Counter Reload
399 *          1 = reload counter at zero and restart
400 *          0 = stop counter at zero
401 *
402 *    D1 - Counter Load
403 *          1 = load counter with preset value and restart
404 *          0 = no function
405 *
406 *    D2 - Enable
407 *          1 = enable counting
408 *          0 = hold scaler and counter
409 *
410 *    D2 - Scaler Load
411 *          1 = load scalar with preset value and restart
412 *          0 = no function
413 *
414 *  To insure the management of the mirror is atomic, we disable interrupts
415 *  around updates.
416 */
417
418#define ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO     0x00000001
419#define ERC32_MEC_TIMER_COUNTER_STOP_AT_ZERO       0x00000000
420
421#define ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER       0x00000002
422
423#define ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING    0x00000004
424#define ERC32_MEC_TIMER_COUNTER_DISABLE_COUNTING   0x00000000
425
426#define ERC32_MEC_TIMER_COUNTER_LOAD_SCALER        0x00000008
427
428#define ERC32_MEC_TIMER_COUNTER_RELOAD_MASK        0x00000001
429#define ERC32_MEC_TIMER_COUNTER_ENABLE_MASK        0x00000004
430
431#define ERC32_MEC_TIMER_COUNTER_DEFINED_MASK       0x0000000F
432#define ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK  0x00000005
433
434extern unsigned32 _ERC32_MEC_Timer_Control_Mirror;
435
436/*
437 *  This macros manipulate the General Purpose Timer portion of the
438 *  Timer Control register and promote the view that there are actually
439 *  two independent Timer Control Registers.
440 */
441
442#define ERC32_MEC_Set_General_Purpose_Timer_Control( _value ) \
443  do { \
444    unsigned32 _level; \
445    unsigned32 _control; \
446    unsigned32 __value; \
447    \
448    __value = ((_value) & 0x0f); \
449    sparc_disable_interrupts( _level ); \
450      _control = _ERC32_MEC_Timer_Control_Mirror; \
451      _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK << 8; \
452      _ERC32_MEC_Timer_Control_Mirror = _control | _value; \
453      _control &= (ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK << 8); \
454      _control |= __value; \
455      /* printf( "GPT 0x%x 0x%x 0x%x\n", _value, __value, _control );  */ \
456      ERC32_MEC.Timer_Control = _control; \
457    sparc_enable_interrupts( _level ); \
458  } while ( 0 )
459
460#define ERC32_MEC_Get_General_Purpose_Timer_Control( _value ) \
461  do { \
462    (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \
463  } while ( 0 )
464
465/*
466 *  This macros manipulate the Real Timer Clock Timer portion of the
467 *  Timer Control register and promote the view that there are actually
468 *  two independent Timer Control Registers.
469 */
470 
471#define ERC32_MEC_Set_Real_Time_Clock_Timer_Control( _value ) \
472  do { \
473    unsigned32 _level; \
474    unsigned32 _control; \
475    unsigned32 __value; \
476    \
477    __value = ((_value) & 0x0f) << 8; \
478    sparc_disable_interrupts( _level ); \
479      _control = _ERC32_MEC_Timer_Control_Mirror; \
480      _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK; \
481      _ERC32_MEC_Timer_Control_Mirror = _control | _value; \
482      _control &= ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK; \
483      _control |= __value; \
484      /* printf( "RTC 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \
485      ERC32_MEC.Timer_Control = _control; \
486    sparc_enable_interrupts( _level ); \
487  } while ( 0 )
488 
489#define ERC32_MEC_Get_Real_Time_Clock_Timer_Control( _value ) \
490  do { \
491    (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \
492  } while ( 0 )
493
494
495#endif /* !ASM */
496
497#ifdef __cplusplus
498}
499#endif
500 
501#endif /* !_INCLUDE_ERC32_h */
502/* end of include file */
503
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