[9700578] | 1 | /* erc32.h |
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| 2 | * |
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| 3 | * This include file contains information pertaining to the ERC32. |
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| 4 | * The ERC32 is a custom SPARC V7 implementation based on the Cypress |
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| 5 | * 601/602 chipset. This CPU has a number of on-board peripherals and |
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| 6 | * was developed by the European Space Agency to target space applications. |
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| 7 | * |
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| 8 | * NOTE: Other than where absolutely required, this version currently |
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| 9 | * supports only the peripherals and bits used by the basic board |
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| 10 | * support package. This includes at least significant pieces of |
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| 11 | * the following items: |
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| 12 | * |
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| 13 | * + UART Channels A and B |
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| 14 | * + General Purpose Timer |
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| 15 | * + Real Time Clock |
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| 16 | * + Watchdog Timer (so it can be disabled) |
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| 17 | * + Control Register (so powerdown mode can be enabled) |
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| 18 | * + Memory Control Register |
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| 19 | * + Interrupt Control |
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| 20 | * |
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[c4808ca] | 21 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. |
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| 22 | * On-Line Applications Research Corporation (OAR). |
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| 23 | * All rights assigned to U.S. Government, 1994. |
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| 24 | * |
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| 25 | * This material may be reproduced by or for the U.S. Government pursuant |
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| 26 | * to the copyright license under the clause at DFARS 252.227-7013. This |
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| 27 | * notice must appear in all copies of this file and its derivatives. |
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| 28 | * |
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| 29 | * Ported to ERC32 implementation of the SPARC by On-Line Applications |
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| 30 | * Research Corporation (OAR) under contract to the European Space |
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| 31 | * Agency (ESA). |
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| 32 | * |
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| 33 | * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. |
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| 34 | * European Space Agency. |
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| 35 | * |
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[9700578] | 36 | * $Id$ |
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| 37 | */ |
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| 38 | |
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| 39 | #ifndef _INCLUDE_ERC32_h |
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| 40 | #define _INCLUDE_ERC32_h |
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| 41 | |
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| 42 | #include <rtems/score/sparc.h> |
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| 43 | |
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| 44 | #ifdef __cplusplus |
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| 45 | extern "C" { |
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| 46 | #endif |
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| 47 | |
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| 48 | /* |
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| 49 | * Interrupt Sources |
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| 50 | * |
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| 51 | * The interrupt source numbers directly map to the trap type and to |
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| 52 | * the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask, |
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| 53 | * and the Interrupt Pending Registers. |
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| 54 | */ |
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| 55 | |
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| 56 | #define ERC32_INTERRUPT_MASKED_ERRORS 1 |
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| 57 | #define ERC32_INTERRUPT_EXTERNAL_1 2 |
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| 58 | #define ERC32_INTERRUPT_EXTERNAL_2 3 |
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| 59 | #define ERC32_INTERRUPT_UART_A_RX_TX 4 |
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| 60 | #define ERC32_INTERRUPT_UART_B_RX_TX 5 |
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| 61 | #define ERC32_INTERRUPT_CORRECTABLE_MEMORY_ERROR 6 |
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| 62 | #define ERC32_INTERRUPT_UART_ERROR 7 |
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| 63 | #define ERC32_INTERRUPT_DMA_ACCESS_ERROR 8 |
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| 64 | #define ERC32_INTERRUPT_DMA_TIMEOUT 9 |
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| 65 | #define ERC32_INTERRUPT_EXTERNAL_3 10 |
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| 66 | #define ERC32_INTERRUPT_EXTERNAL_4 11 |
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| 67 | #define ERC32_INTERRUPT_GENERAL_PURPOSE_TIMER 12 |
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| 68 | #define ERC32_INTERRUPT_REAL_TIME_CLOCK 13 |
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| 69 | #define ERC32_INTERRUPT_EXTERNAL_5 14 |
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| 70 | #define ERC32_INTERRUPT_WATCHDOG_TIMEOUT 15 |
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| 71 | |
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| 72 | #ifndef ASM |
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| 73 | |
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| 74 | /* |
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| 75 | * Trap Types for on-chip peripherals |
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| 76 | * |
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| 77 | * Source: Table 8 - Interrupt Trap Type and Default Priority Assignments |
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| 78 | * |
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| 79 | * NOTE: The priority level for each source corresponds to the least |
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| 80 | * significant nibble of the trap type. |
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| 81 | */ |
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| 82 | |
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| 83 | #define ERC32_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10) |
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| 84 | |
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| 85 | #define ERC32_TRAP_SOURCE( _trap ) ((_trap) - 0x10) |
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| 86 | |
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| 87 | #define ERC32_Is_MEC_Trap( _trap ) \ |
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| 88 | ( (_trap) >= ERC32_TRAP_TYPE( ERC32_INTERRUPT_MASKED_ERRORS ) && \ |
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| 89 | (_trap) <= ERC32_TRAP_TYPE( ERC32_INTERRUPT_WATCHDOG_TIMEOUT ) ) |
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| 90 | |
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| 91 | /* |
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| 92 | * Structure for ERC32 memory mapped registers. |
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| 93 | * |
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| 94 | * Source: Section 3.25.2 - Register Address Map |
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| 95 | * |
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| 96 | * NOTE: There is only one of these structures per CPU, its base address |
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| 97 | * is 0x01f80000, and the variable MEC is placed there by the |
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| 98 | * linkcmds file. |
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| 99 | */ |
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| 100 | |
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| 101 | typedef struct { |
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| 102 | volatile unsigned32 Control; /* offset 0x00 */ |
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| 103 | volatile unsigned32 Software_Reset; /* offset 0x04 */ |
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| 104 | volatile unsigned32 Power_Down; /* offset 0x08 */ |
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| 105 | volatile unsigned32 Unimplemented_0; /* offset 0x0c */ |
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| 106 | volatile unsigned32 Memory_Configuration; /* offset 0x10 */ |
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| 107 | volatile unsigned32 IO_Configuration; /* offset 0x14 */ |
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| 108 | volatile unsigned32 Wait_State_Configuration; /* offset 0x18 */ |
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| 109 | volatile unsigned32 Unimplemented_1; /* offset 0x1c */ |
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| 110 | volatile unsigned32 Memory_Access_0; /* offset 0x20 */ |
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| 111 | volatile unsigned32 Memory_Access_1; /* offset 0x24 */ |
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| 112 | volatile unsigned32 Unimplemented_2[ 7 ]; /* offset 0x28 */ |
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| 113 | volatile unsigned32 Interrupt_Shape; /* offset 0x44 */ |
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| 114 | volatile unsigned32 Interrupt_Pending; /* offset 0x48 */ |
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| 115 | volatile unsigned32 Interrupt_Mask; /* offset 0x4c */ |
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| 116 | volatile unsigned32 Interrupt_Clear; /* offset 0x50 */ |
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| 117 | volatile unsigned32 Interrupt_Force; /* offset 0x54 */ |
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| 118 | volatile unsigned32 Unimplemented_3[ 2 ]; /* offset 0x58 */ |
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| 119 | /* offset 0x60 */ |
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| 120 | volatile unsigned32 Watchdog_Program_and_Timeout_Acknowledge; |
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| 121 | volatile unsigned32 Watchdog_Trap_Door_Set; /* offset 0x64 */ |
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| 122 | volatile unsigned32 Unimplemented_4[ 6 ]; /* offset 0x68 */ |
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| 123 | volatile unsigned32 Real_Time_Clock_Counter; /* offset 0x80 */ |
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| 124 | volatile unsigned32 Real_Time_Clock_Scalar; /* offset 0x84 */ |
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| 125 | volatile unsigned32 General_Purpose_Timer_Counter; /* offset 0x88 */ |
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| 126 | volatile unsigned32 General_Purpose_Timer_Scalar; /* offset 0x8c */ |
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| 127 | volatile unsigned32 Unimplemented_5[ 2 ]; /* offset 0x90 */ |
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| 128 | volatile unsigned32 Timer_Control; /* offset 0x98 */ |
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| 129 | volatile unsigned32 Unimplemented_6; /* offset 0x9c */ |
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| 130 | volatile unsigned32 System_Fault_Status; /* offset 0xa0 */ |
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| 131 | volatile unsigned32 First_Failing_Address; /* offset 0xa4 */ |
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| 132 | volatile unsigned32 First_Failing_Data; /* offset 0xa8 */ |
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| 133 | volatile unsigned32 First_Failing_Syndrome_and_Check_Bits;/* offset 0xac */ |
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| 134 | volatile unsigned32 Error_and_Reset_Status; /* offset 0xb0 */ |
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| 135 | volatile unsigned32 Error_Mask; /* offset 0xb4 */ |
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| 136 | volatile unsigned32 Unimplemented_7[ 2 ]; /* offset 0xb8 */ |
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| 137 | volatile unsigned32 Debug_Control; /* offset 0xc0 */ |
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| 138 | volatile unsigned32 Breakpoint; /* offset 0xc4 */ |
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| 139 | volatile unsigned32 Watchpoint; /* offset 0xc8 */ |
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| 140 | volatile unsigned32 Unimplemented_8; /* offset 0xcc */ |
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| 141 | volatile unsigned32 Test_Control; /* offset 0xd0 */ |
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| 142 | volatile unsigned32 Test_Data; /* offset 0xd4 */ |
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| 143 | volatile unsigned32 Unimplemented_9[ 2 ]; /* offset 0xd8 */ |
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| 144 | volatile unsigned32 UART_Channel_A; /* offset 0xe0 */ |
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| 145 | volatile unsigned32 UART_Channel_B; /* offset 0xe4 */ |
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| 146 | volatile unsigned32 UART_Status; /* offset 0xe8 */ |
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| 147 | } ERC32_Register_Map; |
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| 148 | |
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| 149 | #endif |
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| 150 | |
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| 151 | /* |
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| 152 | * The following constants are intended to be used ONLY in assembly |
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| 153 | * language files. |
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| 154 | * |
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| 155 | * NOTE: The intended style of usage is to load the address of MEC |
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| 156 | * into a register and then use these as displacements from |
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| 157 | * that register. |
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| 158 | */ |
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| 159 | |
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| 160 | #ifdef ASM |
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| 161 | |
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| 162 | #define ERC32_MEC_CONTROL_OFFSET 0x00 |
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| 163 | #define ERC32_MEC_SOFTWARE_RESET_OFFSET 0x04 |
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| 164 | #define ERC32_MEC_POWER_DOWN_OFFSET 0x08 |
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| 165 | #define ERC32_MEC_UNIMPLEMENTED_0_OFFSET 0x0C |
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| 166 | #define ERC32_MEC_MEMORY_CONFIGURATION_OFFSET 0x10 |
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| 167 | #define ERC32_MEC_IO_CONFIGURATION_OFFSET 0x14 |
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| 168 | #define ERC32_MEC_WAIT_STATE_CONFIGURATION_OFFSET 0x18 |
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| 169 | #define ERC32_MEC_UNIMPLEMENTED_1_OFFSET 0x1C |
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| 170 | #define ERC32_MEC_MEMORY_ACCESS_0_OFFSET 0x20 |
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| 171 | #define ERC32_MEC_MEMORY_ACCESS_1_OFFSET 0x24 |
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| 172 | #define ERC32_MEC_UNIMPLEMENTED_2_OFFSET 0x28 |
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| 173 | #define ERC32_MEC_INTERRUPT_SHAPE_OFFSET 0x44 |
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| 174 | #define ERC32_MEC_INTERRUPT_PENDING_OFFSET 0x48 |
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| 175 | #define ERC32_MEC_INTERRUPT_MASK_OFFSET 0x4C |
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| 176 | #define ERC32_MEC_INTERRUPT_CLEAR_OFFSET 0x50 |
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| 177 | #define ERC32_MEC_INTERRUPT_FORCE_OFFSET 0x54 |
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| 178 | #define ERC32_MEC_UNIMPLEMENTED_3_OFFSET 0x58 |
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| 179 | #define ERC32_MEC_WATCHDOG_PROGRAM_AND_TIMEOUT_ACKNOWLEDGE_OFFSET 0x60 |
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| 180 | #define ERC32_MEC_WATCHDOG_TRAP_DOOR_SET_OFFSET 0x64 |
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| 181 | #define ERC32_MEC_UNIMPLEMENTED_4_OFFSET 0x6C |
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| 182 | #define ERC32_MEC_REAL_TIME_CLOCK_COUNTER_OFFSET 0x80 |
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| 183 | #define ERC32_MEC_REAL_TIME_CLOCK_SCALAR_OFFSET 0x84 |
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| 184 | #define ERC32_MEC_GENERAL_PURPOSE_TIMER_COUNTER_OFFSET 0x88 |
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| 185 | #define ERC32_MEC_GENERAL_PURPOSE_TIMER_SCALAR_OFFSET 0x8C |
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| 186 | #define ERC32_MEC_UNIMPLEMENTED_5_OFFSET 0x90 |
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| 187 | #define ERC32_MEC_TIMER_CONTROL_OFFSET 0x98 |
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| 188 | #define ERC32_MEC_UNIMPLEMENTED_6_OFFSET 0x9C |
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| 189 | #define ERC32_MEC_SYSTEM_FAULT_STATUS_OFFSET 0xA0 |
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| 190 | #define ERC32_MEC_FIRST_FAILING_ADDRESS_OFFSET 0xA4 |
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| 191 | #define ERC32_MEC_FIRST_FAILING_DATA_OFFSET 0xA8 |
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| 192 | #define ERC32_MEC_FIRST_FAILING_SYNDROME_AND_CHECK_BITS_OFFSET 0xAC |
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| 193 | #define ERC32_MEC_ERROR_AND_RESET_STATUS_OFFSET 0xB0 |
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| 194 | #define ERC32_MEC_ERROR_MASK_OFFSET 0xB4 |
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| 195 | #define ERC32_MEC_UNIMPLEMENTED_7_OFFSET 0xB8 |
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| 196 | #define ERC32_MEC_DEBUG_CONTROL_OFFSET 0xC0 |
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| 197 | #define ERC32_MEC_BREAKPOINT_OFFSET 0xC4 |
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| 198 | #define ERC32_MEC_WATCHPOINT_OFFSET 0xC8 |
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| 199 | #define ERC32_MEC_UNIMPLEMENTED_8_OFFSET 0xCC |
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| 200 | #define ERC32_MEC_TEST_CONTROL_OFFSET 0xD0 |
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| 201 | #define ERC32_MEC_TEST_DATA_OFFSET 0xD4 |
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| 202 | #define ERC32_MEC_UNIMPLEMENTED_9_OFFSET 0xD8 |
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| 203 | #define ERC32_MEC_UART_CHANNEL_A_OFFSET 0xE0 |
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| 204 | #define ERC32_MEC_UART_CHANNEL_B_OFFSET 0xE4 |
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| 205 | #define ERC32_MEC_UART_STATUS_OFFSET 0xE8 |
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| 206 | |
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| 207 | #endif |
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| 208 | |
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| 209 | /* |
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| 210 | * The following defines the bits in the Configuration Register. |
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| 211 | */ |
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| 212 | |
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| 213 | #define ERC32_CONFIGURATION_POWER_DOWN_MASK 0x00000001 |
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| 214 | #define ERC32_CONFIGURATION_POWER_DOWN_ALLOWED 0x00000001 |
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| 215 | #define ERC32_CONFIGURATION_POWER_DOWN_DISABLED 0x00000000 |
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| 216 | |
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| 217 | #define ERC32_CONFIGURATION_SOFTWARE_RESET_MASK 0x00000002 |
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| 218 | #define ERC32_CONFIGURATION_SOFTWARE_RESET_ALLOWED 0x00000002 |
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| 219 | #define ERC32_CONFIGURATION_SOFTWARE_RESET_DISABLED 0x00000000 |
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| 220 | |
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| 221 | #define ERC32_CONFIGURATION_BUS_TIMEOUT_MASK 0x00000004 |
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| 222 | #define ERC32_CONFIGURATION_BUS_TIMEOUT_ENABLED 0x00000004 |
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| 223 | #define ERC32_CONFIGURATION_BUS_TIMEOUT_DISABLED 0x00000000 |
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| 224 | |
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| 225 | #define ERC32_CONFIGURATION_ACCESS_PROTECTION_MASK 0x00000008 |
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| 226 | #define ERC32_CONFIGURATION_ACCESS_PROTECTION_ENABLED 0x00000008 |
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| 227 | #define ERC32_CONFIGURATION_ACCESS_PROTECTION_DISABLED 0x00000000 |
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| 228 | |
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| 229 | |
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| 230 | /* |
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| 231 | * The following defines the bits in the Memory Configuration Register. |
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| 232 | */ |
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| 233 | |
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| 234 | #define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001C00 |
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| 235 | #define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_256K ( 0 << 10 ) |
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| 236 | #define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_512K ( 1 << 10 ) |
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| 237 | #define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_1MB ( 2 << 10 ) |
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| 238 | #define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_2MB ( 3 << 10 ) |
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| 239 | #define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_4MB ( 4 << 10 ) |
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| 240 | #define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_8MB ( 5 << 10 ) |
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| 241 | #define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_16MB ( 6 << 10 ) |
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| 242 | #define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_32MB ( 7 << 10 ) |
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| 243 | |
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| 244 | #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x001C0000 |
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| 245 | #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4K ( 0 << 18 ) |
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| 246 | #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8K ( 1 << 18 ) |
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| 247 | #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16K ( 2 << 18 ) |
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| 248 | #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_32K ( 3 << 18 ) |
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| 249 | #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_64K ( 4 << 18 ) |
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| 250 | #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K ( 5 << 18 ) |
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| 251 | #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K ( 6 << 18 ) |
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| 252 | #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K ( 7 << 18 ) |
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| 253 | |
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| 254 | /* |
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| 255 | * The following defines the bits in the Timer Control Register. |
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| 256 | */ |
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| 257 | |
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| 258 | #define ERC32_MEC_TIMER_CONTROL_GCR 0x00000001 /* 1 = reload at 0 */ |
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| 259 | /* 0 = stop at 0 */ |
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| 260 | #define ERC32_MEC_TIMER_CONTROL_GCL 0x00000002 /* 1 = load and start */ |
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| 261 | /* 0 = no function */ |
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| 262 | #define ERC32_MEC_TIMER_CONTROL_GSE 0x00000004 /* 1 = enable counting */ |
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| 263 | /* 0 = hold scalar and counter */ |
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| 264 | #define ERC32_MEC_TIMER_CONTROL_GSL 0x00000008 /* 1 = load scalar and start */ |
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| 265 | /* 0 = no function */ |
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| 266 | |
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| 267 | #define ERC32_MEC_TIMER_CONTROL_RTCCR 0x00000100 /* 1 = reload at 0 */ |
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| 268 | /* 0 = stop at 0 */ |
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| 269 | #define ERC32_MEC_TIMER_CONTROL_RTCCL 0x00000200 /* 1 = load and start */ |
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| 270 | /* 0 = no function */ |
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| 271 | #define ERC32_MEC_TIMER_CONTROL_RTCSE 0x00000400 /* 1 = enable counting */ |
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| 272 | /* 0 = hold scalar and counter */ |
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| 273 | #define ERC32_MEC_TIMER_CONTROL_RTCSL 0x00000800 /* 1 = load scalar and start */ |
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| 274 | /* 0 = no function */ |
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| 275 | |
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| 276 | /* |
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| 277 | * The following defines the bits in the UART Control Registers. |
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| 278 | * |
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| 279 | * NOTE: Same bits in UART channels A and B. |
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| 280 | */ |
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| 281 | |
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| 282 | #define ERC32_MEC_UART_CONTROL_RTD 0x000000FF /* RX/TX data */ |
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| 283 | #define ERC32_MEC_UART_CONTROL_DR 0x00000100 /* RX Data Ready */ |
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| 284 | #define ERC32_MEC_UART_CONTROL_TSE 0x00000200 /* TX Send Empty */ |
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| 285 | /* (i.e. no data to send) */ |
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| 286 | #define ERC32_MEC_UART_CONTROL_THE 0x00000400 /* TX Hold Empty */ |
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| 287 | /* (i.e. ready to load) */ |
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| 288 | |
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| 289 | /* |
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| 290 | * The following defines the bits in the MEC UART Control Registers. |
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| 291 | */ |
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| 292 | |
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| 293 | #define ERC32_MEC_UART_STATUS_DR 0x00000001 /* Data Ready */ |
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| 294 | #define ERC32_MEC_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */ |
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| 295 | #define ERC32_MEC_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */ |
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| 296 | #define ERC32_MEC_UART_STATUS_FE 0x00000010 /* RX Framing Error */ |
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| 297 | #define ERC32_MEC_UART_STATUS_PE 0x00000020 /* RX Parity Error */ |
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| 298 | #define ERC32_MEC_UART_STATUS_OE 0x00000040 /* RX Overrun Error */ |
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| 299 | #define ERC32_MEC_UART_STATUS_CU 0x00000080 /* Clear Errors */ |
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| 300 | #define ERC32_MEC_UART_STATUS_TXE 0x00000006 /* TX Empty */ |
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| 301 | |
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| 302 | #define ERC32_MEC_UART_STATUS_DRA (ERC32_MEC_UART_STATUS_DR << 0) |
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| 303 | #define ERC32_MEC_UART_STATUS_TSEA (ERC32_MEC_UART_STATUS_TSE << 0) |
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| 304 | #define ERC32_MEC_UART_STATUS_THEA (ERC32_MEC_UART_STATUS_THE << 0) |
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| 305 | #define ERC32_MEC_UART_STATUS_FEA (ERC32_MEC_UART_STATUS_FE << 0) |
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| 306 | #define ERC32_MEC_UART_STATUS_PEA (ERC32_MEC_UART_STATUS_PE << 0) |
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| 307 | #define ERC32_MEC_UART_STATUS_OEA (ERC32_MEC_UART_STATUS_OE << 0) |
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| 308 | #define ERC32_MEC_UART_STATUS_CUA (ERC32_MEC_UART_STATUS_CU << 0) |
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| 309 | #define ERC32_MEC_UART_STATUS_TXEA (ERC32_MEC_UART_STATUS_TXE << 0) |
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| 310 | |
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| 311 | #define ERC32_MEC_UART_STATUS_DRB (ERC32_MEC_UART_STATUS_DR << 16) |
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| 312 | #define ERC32_MEC_UART_STATUS_TSEB (ERC32_MEC_UART_STATUS_TSE << 16) |
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| 313 | #define ERC32_MEC_UART_STATUS_THEB (ERC32_MEC_UART_STATUS_THE << 16) |
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| 314 | #define ERC32_MEC_UART_STATUS_FEB (ERC32_MEC_UART_STATUS_FE << 16) |
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| 315 | #define ERC32_MEC_UART_STATUS_PEB (ERC32_MEC_UART_STATUS_PE << 16) |
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| 316 | #define ERC32_MEC_UART_STATUS_OEB (ERC32_MEC_UART_STATUS_OE << 16) |
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| 317 | #define ERC32_MEC_UART_STATUS_CUB (ERC32_MEC_UART_STATUS_CU << 16) |
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| 318 | #define ERC32_MEC_UART_STATUS_TXEB (ERC32_MEC_UART_STATUS_TXE << 16) |
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| 319 | |
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| 320 | #ifndef ASM |
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| 321 | |
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| 322 | /* |
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| 323 | * This is used to manipulate the on-chip registers. |
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| 324 | * |
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| 325 | * The following symbol must be defined in the linkcmds file and point |
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| 326 | * to the correct location. |
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| 327 | */ |
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| 328 | |
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| 329 | extern ERC32_Register_Map ERC32_MEC; |
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| 330 | |
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| 331 | /* |
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| 332 | * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask, |
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| 333 | * and the Interrupt Pending Registers. |
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| 334 | * |
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| 335 | * NOTE: For operations which are not atomic, this code disables interrupts |
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| 336 | * to guarantee there are no intervening accesses to the same register. |
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| 337 | * The operations which read the register, modify the value and then |
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| 338 | * store the result back are vulnerable. |
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| 339 | */ |
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| 340 | |
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| 341 | #define ERC32_Clear_interrupt( _source ) \ |
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| 342 | do { \ |
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| 343 | ERC32_MEC.Interrupt_Clear = (1 << (_source)); \ |
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| 344 | } while (0) |
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| 345 | |
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| 346 | #define ERC32_Force_interrupt( _source ) \ |
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| 347 | do { \ |
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[66e519c1] | 348 | unsigned32 _level; \ |
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| 349 | \ |
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| 350 | sparc_disable_interrupts( _level ); \ |
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| 351 | ERC32_MEC.Test_Control = ERC32_MEC.Test_Control | 0x80000; \ |
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| 352 | sparc_enable_interrupts( _level ); \ |
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[9700578] | 353 | ERC32_MEC.Interrupt_Force = (1 << (_source)); \ |
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| 354 | } while (0) |
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| 355 | |
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| 356 | #define ERC32_Is_interrupt_pending( _source ) \ |
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| 357 | (ERC32_MEC.Interrupt_Pending & (1 << (_source))) |
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| 358 | |
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| 359 | #define ERC32_Is_interrupt_masked( _source ) \ |
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| 360 | (ERC32_MEC.Interrupt_Masked & (1 << (_source))) |
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| 361 | |
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| 362 | #define ERC32_Mask_interrupt( _source ) \ |
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| 363 | do { \ |
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| 364 | unsigned32 _level; \ |
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| 365 | \ |
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| 366 | sparc_disable_interrupts( _level ); \ |
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| 367 | ERC32_MEC.Interrupt_Mask |= (1 << (_source)); \ |
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| 368 | sparc_enable_interrupts( _level ); \ |
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| 369 | } while (0) |
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| 370 | |
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| 371 | #define ERC32_Unmask_interrupt( _source ) \ |
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| 372 | do { \ |
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| 373 | unsigned32 _level; \ |
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| 374 | \ |
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| 375 | sparc_disable_interrupts( _level ); \ |
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| 376 | ERC32_MEC.Interrupt_Mask &= ~(1 << (_source)); \ |
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| 377 | sparc_enable_interrupts( _level ); \ |
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| 378 | } while (0) |
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| 379 | |
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| 380 | #define ERC32_Disable_interrupt( _source, _previous ) \ |
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| 381 | do { \ |
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| 382 | unsigned32 _level; \ |
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| 383 | unsigned32 _mask = 1 << (_source); \ |
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| 384 | \ |
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| 385 | sparc_disable_interrupts( _level ); \ |
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| 386 | (_previous) = ERC32_MEC.Interrupt_Mask; \ |
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| 387 | ERC32_MEC.Interrupt_Mask = _previous | _mask; \ |
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| 388 | sparc_enable_interrupts( _level ); \ |
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| 389 | (_previous) &= ~_mask; \ |
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| 390 | } while (0) |
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| 391 | |
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| 392 | #define ERC32_Restore_interrupt( _source, _previous ) \ |
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| 393 | do { \ |
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| 394 | unsigned32 _level; \ |
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| 395 | unsigned32 _mask = 1 << (_source); \ |
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| 396 | \ |
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| 397 | sparc_disable_interrupts( _level ); \ |
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| 398 | ERC32_MEC.Interrupt_Mask = \ |
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| 399 | (ERC32_MEC.Interrupt_Mask & ~_mask) | (_previous); \ |
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| 400 | sparc_enable_interrupts( _level ); \ |
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| 401 | } while (0) |
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| 402 | |
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| 403 | /* |
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| 404 | * The following macros attempt to hide the fact that the General Purpose |
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| 405 | * Timer and Real Time Clock Timer share the Timer Control Register. Because |
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| 406 | * the Timer Control Register is write only, we must mirror it in software |
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| 407 | * and insure that writes to one timer do not alter the current settings |
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| 408 | * and status of the other timer. |
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| 409 | * |
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| 410 | * This code promotes the view that the two timers are completely independent. |
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| 411 | * By exclusively using the routines below to access the Timer Control |
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| 412 | * Register, the application can view the system as having a General Purpose |
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| 413 | * Timer Control Register and a Real Time Clock Timer Control Register |
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| 414 | * rather than the single shared value. |
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| 415 | * |
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| 416 | * Each logical timer control register is organized as follows: |
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| 417 | * |
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| 418 | * D0 - Counter Reload |
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| 419 | * 1 = reload counter at zero and restart |
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| 420 | * 0 = stop counter at zero |
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| 421 | * |
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| 422 | * D1 - Counter Load |
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| 423 | * 1 = load counter with preset value and restart |
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| 424 | * 0 = no function |
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| 425 | * |
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| 426 | * D2 - Enable |
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| 427 | * 1 = enable counting |
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| 428 | * 0 = hold scaler and counter |
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| 429 | * |
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| 430 | * D2 - Scaler Load |
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| 431 | * 1 = load scalar with preset value and restart |
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| 432 | * 0 = no function |
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| 433 | * |
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| 434 | * To insure the management of the mirror is atomic, we disable interrupts |
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| 435 | * around updates. |
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| 436 | */ |
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| 437 | |
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| 438 | #define ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000001 |
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| 439 | #define ERC32_MEC_TIMER_COUNTER_STOP_AT_ZERO 0x00000000 |
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| 440 | |
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| 441 | #define ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER 0x00000002 |
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| 442 | |
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| 443 | #define ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING 0x00000004 |
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| 444 | #define ERC32_MEC_TIMER_COUNTER_DISABLE_COUNTING 0x00000000 |
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| 445 | |
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| 446 | #define ERC32_MEC_TIMER_COUNTER_LOAD_SCALER 0x00000008 |
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| 447 | |
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| 448 | #define ERC32_MEC_TIMER_COUNTER_RELOAD_MASK 0x00000001 |
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| 449 | #define ERC32_MEC_TIMER_COUNTER_ENABLE_MASK 0x00000004 |
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| 450 | |
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| 451 | #define ERC32_MEC_TIMER_COUNTER_DEFINED_MASK 0x0000000F |
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| 452 | #define ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000005 |
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| 453 | |
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| 454 | extern unsigned32 _ERC32_MEC_Timer_Control_Mirror; |
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| 455 | |
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| 456 | /* |
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| 457 | * This macros manipulate the General Purpose Timer portion of the |
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| 458 | * Timer Control register and promote the view that there are actually |
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| 459 | * two independent Timer Control Registers. |
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| 460 | */ |
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| 461 | |
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| 462 | #define ERC32_MEC_Set_General_Purpose_Timer_Control( _value ) \ |
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| 463 | do { \ |
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| 464 | unsigned32 _level; \ |
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| 465 | unsigned32 _control; \ |
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| 466 | unsigned32 __value; \ |
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| 467 | \ |
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| 468 | __value = ((_value) & 0x0f); \ |
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| 469 | sparc_disable_interrupts( _level ); \ |
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| 470 | _control = _ERC32_MEC_Timer_Control_Mirror; \ |
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| 471 | _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK << 8; \ |
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| 472 | _ERC32_MEC_Timer_Control_Mirror = _control | _value; \ |
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| 473 | _control &= (ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK << 8); \ |
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| 474 | _control |= __value; \ |
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| 475 | /* printf( "GPT 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \ |
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| 476 | ERC32_MEC.Timer_Control = _control; \ |
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| 477 | sparc_enable_interrupts( _level ); \ |
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| 478 | } while ( 0 ) |
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| 479 | |
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| 480 | #define ERC32_MEC_Get_General_Purpose_Timer_Control( _value ) \ |
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| 481 | do { \ |
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| 482 | (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \ |
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| 483 | } while ( 0 ) |
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| 484 | |
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| 485 | /* |
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| 486 | * This macros manipulate the Real Timer Clock Timer portion of the |
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| 487 | * Timer Control register and promote the view that there are actually |
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| 488 | * two independent Timer Control Registers. |
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| 489 | */ |
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| 490 | |
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| 491 | #define ERC32_MEC_Set_Real_Time_Clock_Timer_Control( _value ) \ |
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| 492 | do { \ |
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| 493 | unsigned32 _level; \ |
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| 494 | unsigned32 _control; \ |
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| 495 | unsigned32 __value; \ |
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| 496 | \ |
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| 497 | __value = ((_value) & 0x0f) << 8; \ |
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| 498 | sparc_disable_interrupts( _level ); \ |
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| 499 | _control = _ERC32_MEC_Timer_Control_Mirror; \ |
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| 500 | _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK; \ |
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| 501 | _ERC32_MEC_Timer_Control_Mirror = _control | _value; \ |
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| 502 | _control &= ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK; \ |
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| 503 | _control |= __value; \ |
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| 504 | /* printf( "RTC 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \ |
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| 505 | ERC32_MEC.Timer_Control = _control; \ |
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| 506 | sparc_enable_interrupts( _level ); \ |
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| 507 | } while ( 0 ) |
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| 508 | |
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| 509 | #define ERC32_MEC_Get_Real_Time_Clock_Timer_Control( _value ) \ |
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| 510 | do { \ |
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| 511 | (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \ |
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| 512 | } while ( 0 ) |
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| 513 | |
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| 514 | |
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| 515 | #endif /* !ASM */ |
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| 516 | |
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| 517 | #ifdef __cplusplus |
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| 518 | } |
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| 519 | #endif |
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| 520 | |
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| 521 | #endif /* !_INCLUDE_ERC32_h */ |
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| 522 | /* end of include file */ |
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| 523 | |
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