source: rtems/c/src/lib/libcpu/shared/src/cache_manager.c @ d2978ee9

4.104.114.84.95
Last change on this file since d2978ee9 was d2978ee9, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 10, 2000 at 2:09:51 PM

2000-08-10 Charles-Antoine Gauthier <charles.gauthier@…>

  • shared/src/cache_manager.c (rtems_cache_flush_multiple_data_lines, rtems_cache_invalidate_multiple_data_lines): Do not operate on the entire address space when flushing zero bytes.
  • Property mode set to 100644
File size: 7.1 KB
Line 
1/*
2 *  Cache Manager
3 *
4 *  COPYRIGHT (c) 1989-1999.
5 *  On-Line Applications Research Corporation (OAR).
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.OARcorp.com/rtems/license.html.
10 *
11 * 
12 *  The functions in this file implement the API to the RTEMS Cache Manager and
13 *  are divided into data cache and instruction cache functions. Data cache
14 *  functions only have bodies if a data cache is supported. Instruction
15 *  cache functions only have bodies if an instruction cache is supported.
16 *  Support for a particular cache exists only if CPU_x_CACHE_ALIGNMENT is
17 *  defined, where x E {DATA, INSTRUCTION}. These definitions are found in
18 *  the Cache Manager Wrapper header files, often
19 * 
20 *  rtems/c/src/lib/libcpu/CPU/cache_.h
21 * 
22 *  The functions below are implemented with CPU dependent inline routines
23 *  found in the cache.c files for each CPU. In the event that a CPU does
24 *  not support a specific function for a cache it has, the CPU dependent
25 *  routine does nothing (but does exist).
26 * 
27 *  At this point, the Cache Manager makes no considerations, and provides no
28 *  support for BSP specific issues such as a secondary cache. In such a system,
29 *  the CPU dependent routines would have to be modified, or a BSP layer added
30 *  to this Manager.
31 */
32
33#include <rtems.h>
34#include <sys/types.h>
35#include <libcpu/cache.h>
36#include "cache_.h"
37
38
39/*
40 * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE A DATA CACHE
41 */
42
43/*
44 * This function is called to flush the data cache by performing cache
45 * copybacks. It must determine how many cache lines need to be copied
46 * back and then perform the copybacks.
47 */
48void
49rtems_cache_flush_multiple_data_lines( const void * d_addr, size_t n_bytes )
50{
51#if defined(CPU_DATA_CACHE_ALIGNMENT)
52  const void * final_address;
53
54 /*
55  * Set d_addr to the beginning of the cache line; final_address indicates
56  * the last address_t which needs to be pushed. Increment d_addr and push
57  * the resulting line until final_address is passed.
58  */
59
60  if( n_bytes == 0 )
61    /* Do nothing if number of bytes to flush is zero */
62    return;
63   
64  final_address = (void *)((size_t)d_addr + n_bytes - 1);
65  d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1));
66  while( d_addr <= final_address )  {
67    _CPU_cache_flush_1_data_line( d_addr );
68    d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT);
69  }
70#endif
71}
72
73
74/*
75 * This function is responsible for performing a data cache invalidate.
76 * It must determine how many cache lines need to be invalidated and then
77 * perform the invalidations.
78 */
79
80void
81rtems_cache_invalidate_multiple_data_lines( const void * d_addr, size_t n_bytes )
82{
83#if defined(CPU_DATA_CACHE_ALIGNMENT)
84  const void * final_address;
85
86 /*
87  * Set d_addr to the beginning of the cache line; final_address indicates
88  * the last address_t which needs to be invalidated. Increment d_addr and
89  * invalidate the resulting line until final_address is passed.
90  */
91
92  if( n_bytes == 0 )
93    /* Do nothing if number of bytes to invalidate is zero */
94    return;
95   
96  final_address = (void *)((size_t)d_addr + n_bytes - 1);
97  d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1));
98  while( final_address > d_addr ) {
99    _CPU_cache_invalidate_1_data_line( d_addr );
100    d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT);
101  }
102#endif
103}
104
105
106/*
107 * This function is responsible for performing a data cache flush.
108 * It flushes the entire cache.
109 */
110void
111rtems_cache_flush_entire_data( void )
112{
113#if defined(CPU_DATA_CACHE_ALIGNMENT)
114   /*
115    * Call the CPU-specific routine
116    */
117   _CPU_cache_flush_entire_data();
118#endif
119}
120
121
122/*
123 * This function is responsible for performing a data cache
124 * invalidate. It invalidates the entire cache.
125 */
126void
127rtems_cache_invalidate_entire_data( void )
128{
129#if defined(CPU_DATA_CACHE_ALIGNMENT)
130 /*
131  * Call the CPU-specific routine
132  */
133
134 _CPU_cache_invalidate_entire_data();
135#endif
136}
137
138
139/*
140 * This function returns the data cache granularity.
141 */
142int
143rtems_cache_get_data_line_size( void )
144{
145#if defined(CPU_DATA_CACHE_ALIGNMENT)
146  return CPU_DATA_CACHE_ALIGNMENT;
147#else
148  return 0;
149#endif
150}
151
152
153/*
154 * This function freezes the data cache; cache lines
155 * are not replaced.
156 */
157void
158rtems_cache_freeze_data( void )
159{
160#if defined(CPU_DATA_CACHE_ALIGNMENT)
161  _CPU_cache_freeze_data();
162#endif
163}
164
165
166/*
167 * This function unfreezes the instruction cache.
168 */
169void rtems_cache_unfreeze_data( void )
170{
171#if defined(CPU_DATA_CACHE_ALIGNMENT)
172  _CPU_cache_unfreeze_data();
173#endif
174}
175
176
177/* Turn on the data cache. */
178void
179rtems_cache_enable_data( void )
180{
181#if defined(CPU_DATA_CACHE_ALIGNMENT)
182  _CPU_cache_enable_data();
183#endif
184}
185
186
187/* Turn off the data cache. */
188void
189rtems_cache_disable_data( void )
190{
191#if defined(CPU_DATA_CACHE_ALIGNMENT)
192  _CPU_cache_disable_data();
193#endif
194}
195
196
197
198/*
199 * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE AN INSTRUCTION CACHE
200 */
201
202/*
203 * This function is responsible for performing an instruction cache
204 * invalidate. It must determine how many cache lines need to be invalidated
205 * and then perform the invalidations.
206 */
207void
208rtems_cache_invalidate_multiple_instruction_lines( const void * i_addr, size_t n_bytes )
209{
210#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
211  const void * final_address;
212
213 /*
214  * Set i_addr to the beginning of the cache line; final_address indicates
215  * the last address_t which needs to be invalidated. Increment i_addr and
216  * invalidate the resulting line until final_address is passed.
217  */
218
219  if( n_bytes == 0 )
220    /* Do nothing if number of bytes to invalidate is zero */
221    return;
222   
223  final_address = (void *)((size_t)i_addr + n_bytes - 1);
224  i_addr = (void *)((size_t)i_addr & ~(CPU_INSTRUCTION_CACHE_ALIGNMENT - 1));
225  while( final_address > i_addr ) {
226    _CPU_cache_invalidate_1_instruction_line( i_addr );
227    i_addr = (void *)((size_t)i_addr + CPU_INSTRUCTION_CACHE_ALIGNMENT);
228  }
229#endif
230}
231
232
233/*
234 * This function is responsible for performing an instruction cache
235 * invalidate. It invalidates the entire cache.
236 */
237void
238rtems_cache_invalidate_entire_instruction( void )
239{
240#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
241 /*
242  * Call the CPU-specific routine
243  */
244
245 _CPU_cache_invalidate_entire_instruction();
246#endif
247}
248
249
250/*
251 * This function returns the instruction cache granularity.
252 */
253int
254rtems_cache_get_instruction_line_size( void )
255{
256#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
257  return CPU_INSTRUCTION_CACHE_ALIGNMENT;
258#else
259  return 0;
260#endif
261}
262
263
264/*
265 * This function freezes the instruction cache; cache lines
266 * are not replaced.
267 */
268void
269rtems_cache_freeze_instruction( void )
270{
271#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
272  _CPU_cache_freeze_instruction();
273#endif
274}
275
276
277/*
278 * This function unfreezes the instruction cache.
279 */
280void rtems_cache_unfreeze_instruction( void )
281{
282#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
283  _CPU_cache_unfreeze_instruction();
284#endif
285}
286
287
288/* Turn on the instruction cache. */
289void
290rtems_cache_enable_instruction( void )
291{
292#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
293  _CPU_cache_enable_instruction();
294#endif
295}
296
297
298/* Turn off the instruction cache. */
299void
300rtems_cache_disable_instruction( void )
301{
302#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
303  _CPU_cache_disable_instruction();
304#endif
305}
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