source: rtems/c/src/lib/libcpu/shared/src/cache_manager.c @ cf1f72e

4.104.114.84.95
Last change on this file since cf1f72e was cf1f72e, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 13, 2000 at 9:53:38 PM

Moved i386 and m68k cache management code to libcpu. Everything
now is an implementation of the prototypes in rtems/rtems/cache.h.
The libcpu/i386/wrapup directory is no longer needed.
The PowerPC needs this done to it.

  • Property mode set to 100644
File size: 6.7 KB
Line 
1/*
2 *  Cache Manager
3 *
4 *  COPYRIGHT (c) 1989-1999.
5 *  On-Line Applications Research Corporation (OAR).
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.OARcorp.com/rtems/license.html.
10 *
11 * 
12 *  The functions in this file implement the API to the RTEMS Cache Manager and
13 *  are divided into data cache and instruction cache functions. Data cache
14 *  functions are only declared if a data cache is supported. Instruction
15 *  cache functions are only declared if an instruction cache is supported.
16 *  Support for a particular cache exists only if _CPU_x_CACHE_ALIGNMENT is
17 *  defined, where x E {DATA, INST}. These definitions are found in the CPU
18 *  dependent source files in the supercore, often
19 * 
20 *  rtems/c/src/exec/score/cpu/CPU/rtems/score/CPU.h
21 * 
22 *  The functions below are implemented with CPU dependent inline routines
23 *  also found in the above file. In the event that a CPU does not support a
24 *  specific function, the CPU dependent routine does nothing (but does exist).
25 * 
26 *  At this point, the Cache Manager makes no considerations, and provides no
27 *  support for BSP specific issues such as a secondary cache. In such a system,
28 *  the CPU dependent routines would have to be modified, or a BSP layer added
29 *  to this Manager.
30 */
31
32#include <rtems.h>
33#include <sys/types.h>
34#include <libcpu/cache.h>
35#include "cache_.h"
36
37
38/*
39 * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE A DATA CACHE
40 */
41
42/*
43 * This function is called to flush the data cache by performing cache
44 * copybacks. It must determine how many cache lines need to be copied
45 * back and then perform the copybacks.
46 */
47void
48rtems_flush_multiple_data_cache_lines( const void * d_addr, size_t n_bytes )
49{
50#if defined(_CPU_DATA_CACHE_ALIGNMENT)
51  const void * final_address;
52
53 /*
54  * Set d_addr to the beginning of the cache line; final_address indicates
55  * the last address_t which needs to be pushed. Increment d_addr and push
56  * the resulting line until final_address is passed.
57  */
58
59  final_address = (void *)((size_t)d_addr + n_bytes - 1);
60  d_addr = (void *)((size_t)d_addr & ~(_CPU_DATA_CACHE_ALIGNMENT - 1));
61  while( d_addr <= final_address )  {
62    _CPU_flush_1_data_cache_line( d_addr );
63    d_addr = (void *)((size_t)d_addr + _CPU_DATA_CACHE_ALIGNMENT);
64  }
65#endif
66}
67
68
69/*
70 * This function is responsible for performing a data cache invalidate.
71 * It must determine how many cache lines need to be invalidated and then
72 * perform the invalidations.
73 */
74
75void
76rtems_invalidate_multiple_data_cache_lines( const void * d_addr, size_t n_bytes )
77{
78#if defined(_CPU_DATA_CACHE_ALIGNMENT)
79  const void * final_address;
80
81 /*
82  * Set d_addr to the beginning of the cache line; final_address indicates
83  * the last address_t which needs to be invalidated. Increment d_addr and
84  * invalidate the resulting line until final_address is passed.
85  */
86
87  final_address = (void *)((size_t)d_addr + n_bytes - 1);
88  d_addr = (void *)((size_t)d_addr & ~(_CPU_DATA_CACHE_ALIGNMENT - 1));
89  while( final_address > d_addr ) {
90    _CPU_invalidate_1_data_cache_line( d_addr );
91    d_addr = (void *)((size_t)d_addr + _CPU_DATA_CACHE_ALIGNMENT);
92  }
93#endif
94}
95
96
97/*
98 * This function is responsible for performing a data cache flush.
99 * It flushes the entire cache.
100 */
101void
102rtems_flush_entire_data_cache( void )
103{
104#if defined(_CPU_DATA_CACHE_ALIGNMENT)
105   /*
106    * Call the CPU-specific routine
107    */
108   _CPU_flush_entire_data_cache();
109#endif
110}
111
112
113/*
114 * This function is responsible for performing a data cache
115 * invalidate. It invalidates the entire cache.
116 */
117void
118rtems_invalidate_entire_data_cache( void )
119{
120#if defined(_CPU_DATA_CACHE_ALIGNMENT)
121 /*
122  * Call the CPU-specific routine
123  */
124
125 _CPU_invalidate_entire_data_cache();
126#endif
127}
128
129
130/*
131 * This function returns the data cache granularity.
132 */
133int
134rtems_get_data_cache_line_size( void )
135{
136#if defined(_CPU_DATA_CACHE_ALIGNMENT)
137  return _CPU_DATA_CACHE_ALIGNMENT;
138#else
139  return 0;
140#endif
141}
142
143
144/*
145 * This function freezes the data cache; cache lines
146 * are not replaced.
147 */
148void
149rtems_freeze_data_cache( void )
150{
151#if defined(_CPU_DATA_CACHE_ALIGNMENT)
152  _CPU_freeze_data_cache();
153#endif
154}
155
156
157/*
158 * This function unfreezes the instruction cache.
159 */
160void rtems_unfreeze_data_cache( void )
161{
162#if defined(_CPU_DATA_CACHE_ALIGNMENT)
163  _CPU_unfreeze_data_cache();
164#endif
165}
166
167
168/* Turn on the data cache. */
169void
170rtems_enable_data_cache( void )
171{
172#if defined(_CPU_DATA_CACHE_ALIGNMENT)
173  _CPU_enable_data_cache();
174#endif
175}
176
177
178/* Turn off the data cache. */
179void
180rtems_disable_data_cache( void )
181{
182#if defined(_CPU_DATA_CACHE_ALIGNMENT)
183  _CPU_disable_data_cache();
184#endif
185}
186
187
188
189/*
190 * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE AN INSTRUCTION CACHE
191 */
192
193/*
194 * This function is responsible for performing an instruction cache
195 * invalidate. It must determine how many cache lines need to be invalidated
196 * and then perform the invalidations.
197 */
198void
199rtems_invalidate_multiple_inst_cache_lines( const void * i_addr, size_t n_bytes )
200{
201#if defined(_CPU_INST_CACHE_ALIGNMENT)
202  const void * final_address;
203
204 /*
205  * Set i_addr to the beginning of the cache line; final_address indicates
206  * the last address_t which needs to be invalidated. Increment i_addr and
207  * invalidate the resulting line until final_address is passed.
208  */
209
210  final_address = (void *)((size_t)i_addr + n_bytes - 1);
211  i_addr = (void *)((size_t)i_addr & ~(_CPU_INST_CACHE_ALIGNMENT - 1));
212  while( final_address > i_addr ) {
213    _CPU_invalidate_1_inst_cache_line( i_addr );
214    i_addr = (void *)((size_t)i_addr + _CPU_INST_CACHE_ALIGNMENT);
215  }
216#endif
217}
218
219
220/*
221 * This function is responsible for performing an instruction cache
222 * invalidate. It invalidates the entire cache.
223 */
224void
225rtems_invalidate_entire_inst_cache( void )
226{
227#if defined(_CPU_INST_CACHE_ALIGNMENT)
228 /*
229  * Call the CPU-specific routine
230  */
231
232 _CPU_invalidate_entire_inst_cache();
233#endif
234}
235
236
237/*
238 * This function returns the instruction cache granularity.
239 */
240int
241rtems_get_inst_cache_line_size( void )
242{
243#if defined(_CPU_INST_CACHE_ALIGNMENT)
244  return _CPU_INST_CACHE_ALIGNMENT;
245#else
246  return 0;
247#endif
248}
249
250
251/*
252 * This function freezes the instruction cache; cache lines
253 * are not replaced.
254 */
255void
256rtems_freeze_inst_cache( void )
257{
258#if defined(_CPU_INST_CACHE_ALIGNMENT)
259  _CPU_freeze_inst_cache();
260#endif
261}
262
263
264/*
265 * This function unfreezes the instruction cache.
266 */
267void rtems_unfreeze_inst_cache( void )
268{
269#if defined(_CPU_INST_CACHE_ALIGNMENT)
270  _CPU_unfreeze_inst_cache();
271#endif
272}
273
274
275/* Turn on the instruction cache. */
276void
277rtems_enable_inst_cache( void )
278{
279#if defined(_CPU_INST_CACHE_ALIGNMENT)
280  _CPU_enable_inst_cache();
281#endif
282}
283
284
285/* Turn off the instruction cache. */
286void
287rtems_disable_inst_cache( void )
288{
289#if defined(_CPU_INST_CACHE_ALIGNMENT)
290  _CPU_disable_inst_cache();
291#endif
292}
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