source: rtems/c/src/lib/libcpu/shared/src/cache_manager.c @ 5e77d129

4.104.114.84.95
Last change on this file since 5e77d129 was 5e77d129, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 14, 2000 at 8:32:44 PM

Patch from John Cotton <john.cotton@…> to correct cache
routine naming to follow RTEMS package/object.method rule.
This patch also eliminated calls to the obsolete routine
m68k_enable_caching.

  • Property mode set to 100644
File size: 6.8 KB
Line 
1/*
2 *  Cache Manager
3 *
4 *  COPYRIGHT (c) 1989-1999.
5 *  On-Line Applications Research Corporation (OAR).
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.OARcorp.com/rtems/license.html.
10 *
11 * 
12 *  The functions in this file implement the API to the RTEMS Cache Manager and
13 *  are divided into data cache and instruction cache functions. Data cache
14 *  functions only have bodies if a data cache is supported. Instruction
15 *  cache functions only have bodies if an instruction cache is supported.
16 *  Support for a particular cache exists only if CPU_x_CACHE_ALIGNMENT is
17 *  defined, where x E {DATA, INSTRUCTION}. These definitions are found in
18 *  the Cache Manager Wrapper header files, often
19 * 
20 *  rtems/c/src/lib/libcpu/CPU/cache_.h
21 * 
22 *  The functions below are implemented with CPU dependent inline routines
23 *  found in the cache.c files for each CPU. In the event that a CPU does
24 *  not support a specific function for a cache it has, the CPU dependent
25 *  routine does nothing (but does exist).
26 * 
27 *  At this point, the Cache Manager makes no considerations, and provides no
28 *  support for BSP specific issues such as a secondary cache. In such a system,
29 *  the CPU dependent routines would have to be modified, or a BSP layer added
30 *  to this Manager.
31 */
32
33#include <rtems.h>
34#include <sys/types.h>
35#include <libcpu/cache.h>
36#include "cache_.h"
37
38
39/*
40 * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE A DATA CACHE
41 */
42
43/*
44 * This function is called to flush the data cache by performing cache
45 * copybacks. It must determine how many cache lines need to be copied
46 * back and then perform the copybacks.
47 */
48void
49rtems_cache_flush_multiple_data_lines( const void * d_addr, size_t n_bytes )
50{
51#if defined(CPU_DATA_CACHE_ALIGNMENT)
52  const void * final_address;
53
54 /*
55  * Set d_addr to the beginning of the cache line; final_address indicates
56  * the last address_t which needs to be pushed. Increment d_addr and push
57  * the resulting line until final_address is passed.
58  */
59
60  final_address = (void *)((size_t)d_addr + n_bytes - 1);
61  d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1));
62  while( d_addr <= final_address )  {
63    _CPU_cache_flush_1_data_line( d_addr );
64    d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT);
65  }
66#endif
67}
68
69
70/*
71 * This function is responsible for performing a data cache invalidate.
72 * It must determine how many cache lines need to be invalidated and then
73 * perform the invalidations.
74 */
75
76void
77rtems_cache_invalidate_multiple_data_lines( const void * d_addr, size_t n_bytes )
78{
79#if defined(CPU_DATA_CACHE_ALIGNMENT)
80  const void * final_address;
81
82 /*
83  * Set d_addr to the beginning of the cache line; final_address indicates
84  * the last address_t which needs to be invalidated. Increment d_addr and
85  * invalidate the resulting line until final_address is passed.
86  */
87
88  final_address = (void *)((size_t)d_addr + n_bytes - 1);
89  d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1));
90  while( final_address > d_addr ) {
91    _CPU_cache_invalidate_1_data_line( d_addr );
92    d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT);
93  }
94#endif
95}
96
97
98/*
99 * This function is responsible for performing a data cache flush.
100 * It flushes the entire cache.
101 */
102void
103rtems_cache_flush_entire_data( void )
104{
105#if defined(CPU_DATA_CACHE_ALIGNMENT)
106   /*
107    * Call the CPU-specific routine
108    */
109   _CPU_cache_flush_entire_data();
110#endif
111}
112
113
114/*
115 * This function is responsible for performing a data cache
116 * invalidate. It invalidates the entire cache.
117 */
118void
119rtems_cache_invalidate_entire_data( void )
120{
121#if defined(CPU_DATA_CACHE_ALIGNMENT)
122 /*
123  * Call the CPU-specific routine
124  */
125
126 _CPU_cache_invalidate_entire_data();
127#endif
128}
129
130
131/*
132 * This function returns the data cache granularity.
133 */
134int
135rtems_cache_get_data_line_size( void )
136{
137#if defined(CPU_DATA_CACHE_ALIGNMENT)
138  return CPU_DATA_CACHE_ALIGNMENT;
139#else
140  return 0;
141#endif
142}
143
144
145/*
146 * This function freezes the data cache; cache lines
147 * are not replaced.
148 */
149void
150rtems_cache_freeze_data( void )
151{
152#if defined(CPU_DATA_CACHE_ALIGNMENT)
153  _CPU_cache_freeze_data();
154#endif
155}
156
157
158/*
159 * This function unfreezes the instruction cache.
160 */
161void rtems_cache_unfreeze_data( void )
162{
163#if defined(CPU_DATA_CACHE_ALIGNMENT)
164  _CPU_cache_unfreeze_data();
165#endif
166}
167
168
169/* Turn on the data cache. */
170void
171rtems_cache_enable_data( void )
172{
173#if defined(CPU_DATA_CACHE_ALIGNMENT)
174  _CPU_cache_enable_data();
175#endif
176}
177
178
179/* Turn off the data cache. */
180void
181rtems_cache_disable_data( void )
182{
183#if defined(CPU_DATA_CACHE_ALIGNMENT)
184  _CPU_cache_disable_data();
185#endif
186}
187
188
189
190/*
191 * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE AN INSTRUCTION CACHE
192 */
193
194/*
195 * This function is responsible for performing an instruction cache
196 * invalidate. It must determine how many cache lines need to be invalidated
197 * and then perform the invalidations.
198 */
199void
200rtems_cache_invalidate_multiple_instruction_lines( const void * i_addr, size_t n_bytes )
201{
202#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
203  const void * final_address;
204
205 /*
206  * Set i_addr to the beginning of the cache line; final_address indicates
207  * the last address_t which needs to be invalidated. Increment i_addr and
208  * invalidate the resulting line until final_address is passed.
209  */
210
211  final_address = (void *)((size_t)i_addr + n_bytes - 1);
212  i_addr = (void *)((size_t)i_addr & ~(CPU_INSTRUCTION_CACHE_ALIGNMENT - 1));
213  while( final_address > i_addr ) {
214    _CPU_cache_invalidate_1_instruction_line( i_addr );
215    i_addr = (void *)((size_t)i_addr + CPU_INSTRUCTION_CACHE_ALIGNMENT);
216  }
217#endif
218}
219
220
221/*
222 * This function is responsible for performing an instruction cache
223 * invalidate. It invalidates the entire cache.
224 */
225void
226rtems_cache_invalidate_entire_instruction( void )
227{
228#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
229 /*
230  * Call the CPU-specific routine
231  */
232
233 _CPU_cache_invalidate_entire_instruction();
234#endif
235}
236
237
238/*
239 * This function returns the instruction cache granularity.
240 */
241int
242rtems_cache_get_instruction_line_size( void )
243{
244#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
245  return CPU_INSTRUCTION_CACHE_ALIGNMENT;
246#else
247  return 0;
248#endif
249}
250
251
252/*
253 * This function freezes the instruction cache; cache lines
254 * are not replaced.
255 */
256void
257rtems_cache_freeze_instruction( void )
258{
259#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
260  _CPU_cache_freeze_instruction();
261#endif
262}
263
264
265/*
266 * This function unfreezes the instruction cache.
267 */
268void rtems_cache_unfreeze_instruction( void )
269{
270#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
271  _CPU_cache_unfreeze_instruction();
272#endif
273}
274
275
276/* Turn on the instruction cache. */
277void
278rtems_cache_enable_instruction( void )
279{
280#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
281  _CPU_cache_enable_instruction();
282#endif
283}
284
285
286/* Turn off the instruction cache. */
287void
288rtems_cache_disable_instruction( void )
289{
290#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
291  _CPU_cache_disable_instruction();
292#endif
293}
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