[cf1f72e] | 1 | /* |
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[8ef3818] | 2 | * Cache Manager |
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| 3 | * |
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| 4 | * COPYRIGHT (c) 1989-1999. |
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| 5 | * On-Line Applications Research Corporation (OAR). |
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| 6 | * |
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| 7 | * The license and distribution terms for this file may be |
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| 8 | * found in the file LICENSE in this distribution or at |
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| 9 | * http://www.OARcorp.com/rtems/license.html. |
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| 10 | * |
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| 11 | * |
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[cf1f72e] | 12 | * The functions in this file implement the API to the RTEMS Cache Manager and |
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[8ef3818] | 13 | * are divided into data cache and instruction cache functions. Data cache |
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[5e77d129] | 14 | * functions only have bodies if a data cache is supported. Instruction |
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| 15 | * cache functions only have bodies if an instruction cache is supported. |
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| 16 | * Support for a particular cache exists only if CPU_x_CACHE_ALIGNMENT is |
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| 17 | * defined, where x E {DATA, INSTRUCTION}. These definitions are found in |
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| 18 | * the Cache Manager Wrapper header files, often |
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[8ef3818] | 19 | * |
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[5e77d129] | 20 | * rtems/c/src/lib/libcpu/CPU/cache_.h |
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[8ef3818] | 21 | * |
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| 22 | * The functions below are implemented with CPU dependent inline routines |
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[5e77d129] | 23 | * found in the cache.c files for each CPU. In the event that a CPU does |
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| 24 | * not support a specific function for a cache it has, the CPU dependent |
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| 25 | * routine does nothing (but does exist). |
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[8ef3818] | 26 | * |
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| 27 | * At this point, the Cache Manager makes no considerations, and provides no |
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| 28 | * support for BSP specific issues such as a secondary cache. In such a system, |
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| 29 | * the CPU dependent routines would have to be modified, or a BSP layer added |
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| 30 | * to this Manager. |
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| 31 | */ |
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| 32 | |
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[cf1f72e] | 33 | #include <rtems.h> |
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[8ef3818] | 34 | #include <sys/types.h> |
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[cf1f72e] | 35 | #include <libcpu/cache.h> |
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| 36 | #include "cache_.h" |
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[8ef3818] | 37 | |
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| 38 | |
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| 39 | /* |
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[cf1f72e] | 40 | * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE A DATA CACHE |
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[8ef3818] | 41 | */ |
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| 42 | |
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| 43 | /* |
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| 44 | * This function is called to flush the data cache by performing cache |
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| 45 | * copybacks. It must determine how many cache lines need to be copied |
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| 46 | * back and then perform the copybacks. |
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| 47 | */ |
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| 48 | void |
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[5e77d129] | 49 | rtems_cache_flush_multiple_data_lines( const void * d_addr, size_t n_bytes ) |
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[8ef3818] | 50 | { |
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[5e77d129] | 51 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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[cf1f72e] | 52 | const void * final_address; |
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| 53 | |
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| 54 | /* |
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| 55 | * Set d_addr to the beginning of the cache line; final_address indicates |
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| 56 | * the last address_t which needs to be pushed. Increment d_addr and push |
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| 57 | * the resulting line until final_address is passed. |
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| 58 | */ |
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| 59 | |
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[d2978ee9] | 60 | if( n_bytes == 0 ) |
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| 61 | /* Do nothing if number of bytes to flush is zero */ |
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| 62 | return; |
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| 63 | |
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[cf1f72e] | 64 | final_address = (void *)((size_t)d_addr + n_bytes - 1); |
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[5e77d129] | 65 | d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1)); |
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[cf1f72e] | 66 | while( d_addr <= final_address ) { |
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[5e77d129] | 67 | _CPU_cache_flush_1_data_line( d_addr ); |
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| 68 | d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT); |
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[cf1f72e] | 69 | } |
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| 70 | #endif |
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[8ef3818] | 71 | } |
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| 72 | |
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| 73 | |
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| 74 | /* |
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| 75 | * This function is responsible for performing a data cache invalidate. |
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| 76 | * It must determine how many cache lines need to be invalidated and then |
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| 77 | * perform the invalidations. |
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| 78 | */ |
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[cf1f72e] | 79 | |
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[8ef3818] | 80 | void |
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[5e77d129] | 81 | rtems_cache_invalidate_multiple_data_lines( const void * d_addr, size_t n_bytes ) |
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[8ef3818] | 82 | { |
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[5e77d129] | 83 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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[cf1f72e] | 84 | const void * final_address; |
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| 85 | |
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| 86 | /* |
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| 87 | * Set d_addr to the beginning of the cache line; final_address indicates |
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| 88 | * the last address_t which needs to be invalidated. Increment d_addr and |
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| 89 | * invalidate the resulting line until final_address is passed. |
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| 90 | */ |
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| 91 | |
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[d2978ee9] | 92 | if( n_bytes == 0 ) |
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| 93 | /* Do nothing if number of bytes to invalidate is zero */ |
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| 94 | return; |
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| 95 | |
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[cf1f72e] | 96 | final_address = (void *)((size_t)d_addr + n_bytes - 1); |
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[5e77d129] | 97 | d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1)); |
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[ec45e86] | 98 | while( final_address >= d_addr ) { |
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[5e77d129] | 99 | _CPU_cache_invalidate_1_data_line( d_addr ); |
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| 100 | d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT); |
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[cf1f72e] | 101 | } |
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| 102 | #endif |
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[8ef3818] | 103 | } |
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| 104 | |
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| 105 | |
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| 106 | /* |
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| 107 | * This function is responsible for performing a data cache flush. |
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| 108 | * It flushes the entire cache. |
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| 109 | */ |
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| 110 | void |
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[5e77d129] | 111 | rtems_cache_flush_entire_data( void ) |
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[8ef3818] | 112 | { |
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[5e77d129] | 113 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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[8ef3818] | 114 | /* |
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| 115 | * Call the CPU-specific routine |
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| 116 | */ |
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[5e77d129] | 117 | _CPU_cache_flush_entire_data(); |
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[cf1f72e] | 118 | #endif |
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[8ef3818] | 119 | } |
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| 120 | |
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| 121 | |
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| 122 | /* |
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| 123 | * This function is responsible for performing a data cache |
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| 124 | * invalidate. It invalidates the entire cache. |
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| 125 | */ |
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| 126 | void |
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[5e77d129] | 127 | rtems_cache_invalidate_entire_data( void ) |
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[8ef3818] | 128 | { |
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[5e77d129] | 129 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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[cf1f72e] | 130 | /* |
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| 131 | * Call the CPU-specific routine |
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| 132 | */ |
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| 133 | |
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[5e77d129] | 134 | _CPU_cache_invalidate_entire_data(); |
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[cf1f72e] | 135 | #endif |
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[8ef3818] | 136 | } |
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| 137 | |
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| 138 | |
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| 139 | /* |
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| 140 | * This function returns the data cache granularity. |
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| 141 | */ |
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| 142 | int |
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[5e77d129] | 143 | rtems_cache_get_data_line_size( void ) |
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[8ef3818] | 144 | { |
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[5e77d129] | 145 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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| 146 | return CPU_DATA_CACHE_ALIGNMENT; |
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[cf1f72e] | 147 | #else |
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| 148 | return 0; |
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| 149 | #endif |
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[8ef3818] | 150 | } |
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| 151 | |
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| 152 | |
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| 153 | /* |
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| 154 | * This function freezes the data cache; cache lines |
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| 155 | * are not replaced. |
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| 156 | */ |
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| 157 | void |
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[5e77d129] | 158 | rtems_cache_freeze_data( void ) |
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[8ef3818] | 159 | { |
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[5e77d129] | 160 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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| 161 | _CPU_cache_freeze_data(); |
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[cf1f72e] | 162 | #endif |
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[8ef3818] | 163 | } |
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| 164 | |
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| 165 | |
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| 166 | /* |
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| 167 | * This function unfreezes the instruction cache. |
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| 168 | */ |
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[5e77d129] | 169 | void rtems_cache_unfreeze_data( void ) |
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[8ef3818] | 170 | { |
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[5e77d129] | 171 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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| 172 | _CPU_cache_unfreeze_data(); |
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[cf1f72e] | 173 | #endif |
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[8ef3818] | 174 | } |
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| 175 | |
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| 176 | |
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| 177 | /* Turn on the data cache. */ |
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| 178 | void |
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[5e77d129] | 179 | rtems_cache_enable_data( void ) |
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[8ef3818] | 180 | { |
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[5e77d129] | 181 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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| 182 | _CPU_cache_enable_data(); |
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[cf1f72e] | 183 | #endif |
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[8ef3818] | 184 | } |
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| 185 | |
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| 186 | |
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| 187 | /* Turn off the data cache. */ |
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| 188 | void |
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[5e77d129] | 189 | rtems_cache_disable_data( void ) |
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[8ef3818] | 190 | { |
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[5e77d129] | 191 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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| 192 | _CPU_cache_disable_data(); |
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[8ef3818] | 193 | #endif |
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[cf1f72e] | 194 | } |
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[8ef3818] | 195 | |
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| 196 | |
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| 197 | |
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| 198 | /* |
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[cf1f72e] | 199 | * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE AN INSTRUCTION CACHE |
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[8ef3818] | 200 | */ |
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| 201 | |
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| 202 | /* |
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| 203 | * This function is responsible for performing an instruction cache |
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| 204 | * invalidate. It must determine how many cache lines need to be invalidated |
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| 205 | * and then perform the invalidations. |
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| 206 | */ |
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| 207 | void |
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[5e77d129] | 208 | rtems_cache_invalidate_multiple_instruction_lines( const void * i_addr, size_t n_bytes ) |
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[8ef3818] | 209 | { |
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[cb88748] | 210 | #if CPU_INSTRUCTION_CACHE_ALIGNMENT |
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[cf1f72e] | 211 | const void * final_address; |
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| 212 | |
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| 213 | /* |
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| 214 | * Set i_addr to the beginning of the cache line; final_address indicates |
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| 215 | * the last address_t which needs to be invalidated. Increment i_addr and |
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| 216 | * invalidate the resulting line until final_address is passed. |
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| 217 | */ |
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| 218 | |
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[d2978ee9] | 219 | if( n_bytes == 0 ) |
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| 220 | /* Do nothing if number of bytes to invalidate is zero */ |
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| 221 | return; |
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| 222 | |
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[cf1f72e] | 223 | final_address = (void *)((size_t)i_addr + n_bytes - 1); |
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[5e77d129] | 224 | i_addr = (void *)((size_t)i_addr & ~(CPU_INSTRUCTION_CACHE_ALIGNMENT - 1)); |
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[cf1f72e] | 225 | while( final_address > i_addr ) { |
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[5e77d129] | 226 | _CPU_cache_invalidate_1_instruction_line( i_addr ); |
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| 227 | i_addr = (void *)((size_t)i_addr + CPU_INSTRUCTION_CACHE_ALIGNMENT); |
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[cf1f72e] | 228 | } |
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| 229 | #endif |
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[8ef3818] | 230 | } |
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| 231 | |
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| 232 | |
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| 233 | /* |
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| 234 | * This function is responsible for performing an instruction cache |
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| 235 | * invalidate. It invalidates the entire cache. |
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| 236 | */ |
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| 237 | void |
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[5e77d129] | 238 | rtems_cache_invalidate_entire_instruction( void ) |
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[8ef3818] | 239 | { |
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[5e77d129] | 240 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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[cf1f72e] | 241 | /* |
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| 242 | * Call the CPU-specific routine |
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| 243 | */ |
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| 244 | |
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[5e77d129] | 245 | _CPU_cache_invalidate_entire_instruction(); |
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[cf1f72e] | 246 | #endif |
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[8ef3818] | 247 | } |
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| 248 | |
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| 249 | |
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| 250 | /* |
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| 251 | * This function returns the instruction cache granularity. |
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| 252 | */ |
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| 253 | int |
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[5e77d129] | 254 | rtems_cache_get_instruction_line_size( void ) |
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[8ef3818] | 255 | { |
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[5e77d129] | 256 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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| 257 | return CPU_INSTRUCTION_CACHE_ALIGNMENT; |
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[cf1f72e] | 258 | #else |
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| 259 | return 0; |
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| 260 | #endif |
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[8ef3818] | 261 | } |
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| 262 | |
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| 263 | |
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| 264 | /* |
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| 265 | * This function freezes the instruction cache; cache lines |
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| 266 | * are not replaced. |
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| 267 | */ |
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| 268 | void |
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[5e77d129] | 269 | rtems_cache_freeze_instruction( void ) |
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[8ef3818] | 270 | { |
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[5e77d129] | 271 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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| 272 | _CPU_cache_freeze_instruction(); |
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[cf1f72e] | 273 | #endif |
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[8ef3818] | 274 | } |
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| 275 | |
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| 276 | |
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| 277 | /* |
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| 278 | * This function unfreezes the instruction cache. |
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| 279 | */ |
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[5e77d129] | 280 | void rtems_cache_unfreeze_instruction( void ) |
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[8ef3818] | 281 | { |
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[5e77d129] | 282 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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| 283 | _CPU_cache_unfreeze_instruction(); |
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[cf1f72e] | 284 | #endif |
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[8ef3818] | 285 | } |
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| 286 | |
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| 287 | |
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| 288 | /* Turn on the instruction cache. */ |
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| 289 | void |
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[5e77d129] | 290 | rtems_cache_enable_instruction( void ) |
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[8ef3818] | 291 | { |
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[5e77d129] | 292 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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| 293 | _CPU_cache_enable_instruction(); |
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[cf1f72e] | 294 | #endif |
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[8ef3818] | 295 | } |
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| 296 | |
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| 297 | |
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| 298 | /* Turn off the instruction cache. */ |
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| 299 | void |
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[5e77d129] | 300 | rtems_cache_disable_instruction( void ) |
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[8ef3818] | 301 | { |
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[5e77d129] | 302 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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| 303 | _CPU_cache_disable_instruction(); |
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[8ef3818] | 304 | #endif |
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[cf1f72e] | 305 | } |
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