[cf1f72e] | 1 | /* |
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[8ef3818] | 2 | * Cache Manager |
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| 3 | * |
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| 4 | * COPYRIGHT (c) 1989-1999. |
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| 5 | * On-Line Applications Research Corporation (OAR). |
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| 6 | * |
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| 7 | * The license and distribution terms for this file may be |
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| 8 | * found in the file LICENSE in this distribution or at |
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[c499856] | 9 | * http://www.rtems.org/license/LICENSE. |
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[8ef3818] | 10 | * |
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[359e537] | 11 | * |
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[cf1f72e] | 12 | * The functions in this file implement the API to the RTEMS Cache Manager and |
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[8ef3818] | 13 | * are divided into data cache and instruction cache functions. Data cache |
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[5e77d129] | 14 | * functions only have bodies if a data cache is supported. Instruction |
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| 15 | * cache functions only have bodies if an instruction cache is supported. |
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| 16 | * Support for a particular cache exists only if CPU_x_CACHE_ALIGNMENT is |
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| 17 | * defined, where x E {DATA, INSTRUCTION}. These definitions are found in |
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| 18 | * the Cache Manager Wrapper header files, often |
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[359e537] | 19 | * |
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[5e77d129] | 20 | * rtems/c/src/lib/libcpu/CPU/cache_.h |
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[359e537] | 21 | * |
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[2bd440e] | 22 | * The cache implementation header file can define |
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[4bf2a6aa] | 23 | * |
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| 24 | * #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS |
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| 25 | * |
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[2bd440e] | 26 | * if it provides cache maintenance functions which operate on multiple lines. |
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[4bf2a6aa] | 27 | * Otherwise a generic loop with single line operations will be used. It is |
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| 28 | * strongly recommended to provide the implementation in terms of static |
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| 29 | * inline functions for performance reasons. |
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[2bd440e] | 30 | * |
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[8ef3818] | 31 | * The functions below are implemented with CPU dependent inline routines |
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[5e77d129] | 32 | * found in the cache.c files for each CPU. In the event that a CPU does |
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| 33 | * not support a specific function for a cache it has, the CPU dependent |
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| 34 | * routine does nothing (but does exist). |
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[359e537] | 35 | * |
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[8ef3818] | 36 | * At this point, the Cache Manager makes no considerations, and provides no |
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| 37 | * support for BSP specific issues such as a secondary cache. In such a system, |
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| 38 | * the CPU dependent routines would have to be modified, or a BSP layer added |
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| 39 | * to this Manager. |
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| 40 | */ |
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| 41 | |
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[cf1f72e] | 42 | #include <rtems.h> |
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| 43 | #include "cache_.h" |
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[ddbc3f8d] | 44 | |
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[26c142e5] | 45 | #if defined(RTEMS_SMP) |
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[ddbc3f8d] | 46 | |
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[26c142e5] | 47 | #include <rtems/score/smpimpl.h> |
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[ddbc3f8d] | 48 | |
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| 49 | typedef struct { |
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| 50 | const void *addr; |
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| 51 | size_t size; |
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[26c142e5] | 52 | } smp_cache_area; |
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[ddbc3f8d] | 53 | |
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[26c142e5] | 54 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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[ddbc3f8d] | 55 | |
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[26c142e5] | 56 | static void smp_cache_data_flush(void *arg) |
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[ddbc3f8d] | 57 | { |
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[26c142e5] | 58 | smp_cache_area *area = arg; |
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[ddbc3f8d] | 59 | |
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[26c142e5] | 60 | rtems_cache_flush_multiple_data_lines(area->addr, area->size); |
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[ddbc3f8d] | 61 | } |
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| 62 | |
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[26c142e5] | 63 | static void smp_cache_data_inv(void *arg) |
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[ddbc3f8d] | 64 | { |
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[26c142e5] | 65 | smp_cache_area *area = arg; |
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[ddbc3f8d] | 66 | |
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[26c142e5] | 67 | rtems_cache_invalidate_multiple_data_lines(area->addr, area->size); |
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[ddbc3f8d] | 68 | } |
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| 69 | |
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[26c142e5] | 70 | static void smp_cache_data_flush_all(void *arg) |
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[ddbc3f8d] | 71 | { |
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[26c142e5] | 72 | rtems_cache_flush_entire_data(); |
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| 73 | } |
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[ddbc3f8d] | 74 | |
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[26c142e5] | 75 | static void smp_cache_data_inv_all(void *arg) |
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| 76 | { |
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| 77 | rtems_cache_invalidate_entire_data(); |
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[ddbc3f8d] | 78 | } |
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[26c142e5] | 79 | |
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| 80 | #endif /* defined(CPU_DATA_CACHE_ALIGNMENT) */ |
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[ddbc3f8d] | 81 | |
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| 82 | void |
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| 83 | rtems_cache_flush_multiple_data_lines_processor_set( |
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| 84 | const void *addr, |
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| 85 | size_t size, |
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| 86 | const size_t setsize, |
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| 87 | const cpu_set_t *set |
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| 88 | ) |
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| 89 | { |
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| 90 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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[26c142e5] | 91 | smp_cache_area area = { addr, size }; |
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| 92 | |
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| 93 | _SMP_Multicast_action( setsize, set, smp_cache_data_flush, &area ); |
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[ddbc3f8d] | 94 | #endif |
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| 95 | } |
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| 96 | |
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| 97 | void |
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| 98 | rtems_cache_invalidate_multiple_data_lines_processor_set( |
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| 99 | const void *addr, |
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| 100 | size_t size, |
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| 101 | const size_t setsize, |
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| 102 | const cpu_set_t *set |
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| 103 | ) |
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| 104 | { |
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| 105 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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[26c142e5] | 106 | smp_cache_area area = { addr, size }; |
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| 107 | |
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| 108 | _SMP_Multicast_action( setsize, set, smp_cache_data_inv, &area ); |
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[ddbc3f8d] | 109 | #endif |
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| 110 | } |
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| 111 | |
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| 112 | void |
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| 113 | rtems_cache_flush_entire_data_processor_set( |
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| 114 | const size_t setsize, |
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| 115 | const cpu_set_t *set |
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| 116 | ) |
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| 117 | { |
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| 118 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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[26c142e5] | 119 | _SMP_Multicast_action( setsize, set, smp_cache_data_flush_all, NULL ); |
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[ddbc3f8d] | 120 | #endif |
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| 121 | } |
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| 122 | |
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| 123 | void |
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| 124 | rtems_cache_invalidate_entire_data_processor_set( |
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| 125 | const size_t setsize, |
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| 126 | const cpu_set_t *set |
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| 127 | ) |
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| 128 | { |
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| 129 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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[26c142e5] | 130 | _SMP_Multicast_action( setsize, set, smp_cache_data_inv_all, NULL ); |
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[ddbc3f8d] | 131 | #endif |
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| 132 | } |
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[26c142e5] | 133 | |
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| 134 | #endif /* defined(RTEMS_SMP) */ |
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[8ef3818] | 135 | |
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| 136 | /* |
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[cf1f72e] | 137 | * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE A DATA CACHE |
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[8ef3818] | 138 | */ |
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| 139 | |
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| 140 | /* |
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| 141 | * This function is called to flush the data cache by performing cache |
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| 142 | * copybacks. It must determine how many cache lines need to be copied |
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| 143 | * back and then perform the copybacks. |
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| 144 | */ |
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| 145 | void |
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[5e77d129] | 146 | rtems_cache_flush_multiple_data_lines( const void * d_addr, size_t n_bytes ) |
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[8ef3818] | 147 | { |
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[5e77d129] | 148 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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[2bd440e] | 149 | #if defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS) |
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| 150 | _CPU_cache_flush_data_range( d_addr, n_bytes ); |
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| 151 | #else |
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[cf1f72e] | 152 | const void * final_address; |
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| 153 | |
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| 154 | /* |
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| 155 | * Set d_addr to the beginning of the cache line; final_address indicates |
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| 156 | * the last address_t which needs to be pushed. Increment d_addr and push |
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| 157 | * the resulting line until final_address is passed. |
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| 158 | */ |
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| 159 | |
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[d2978ee9] | 160 | if( n_bytes == 0 ) |
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| 161 | /* Do nothing if number of bytes to flush is zero */ |
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| 162 | return; |
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[359e537] | 163 | |
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[cf1f72e] | 164 | final_address = (void *)((size_t)d_addr + n_bytes - 1); |
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[5e77d129] | 165 | d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1)); |
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[cf1f72e] | 166 | while( d_addr <= final_address ) { |
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[5e77d129] | 167 | _CPU_cache_flush_1_data_line( d_addr ); |
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| 168 | d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT); |
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[cf1f72e] | 169 | } |
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| 170 | #endif |
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[2bd440e] | 171 | #endif |
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[8ef3818] | 172 | } |
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| 173 | |
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| 174 | |
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| 175 | /* |
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| 176 | * This function is responsible for performing a data cache invalidate. |
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| 177 | * It must determine how many cache lines need to be invalidated and then |
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| 178 | * perform the invalidations. |
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| 179 | */ |
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[cf1f72e] | 180 | |
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[8ef3818] | 181 | void |
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[5e77d129] | 182 | rtems_cache_invalidate_multiple_data_lines( const void * d_addr, size_t n_bytes ) |
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[8ef3818] | 183 | { |
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[5e77d129] | 184 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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[2bd440e] | 185 | #if defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS) |
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| 186 | _CPU_cache_invalidate_data_range( d_addr, n_bytes ); |
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| 187 | #else |
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[cf1f72e] | 188 | const void * final_address; |
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| 189 | |
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| 190 | /* |
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| 191 | * Set d_addr to the beginning of the cache line; final_address indicates |
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| 192 | * the last address_t which needs to be invalidated. Increment d_addr and |
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| 193 | * invalidate the resulting line until final_address is passed. |
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| 194 | */ |
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| 195 | |
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[d2978ee9] | 196 | if( n_bytes == 0 ) |
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| 197 | /* Do nothing if number of bytes to invalidate is zero */ |
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| 198 | return; |
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[359e537] | 199 | |
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[cf1f72e] | 200 | final_address = (void *)((size_t)d_addr + n_bytes - 1); |
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[5e77d129] | 201 | d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1)); |
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[ec45e86] | 202 | while( final_address >= d_addr ) { |
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[5e77d129] | 203 | _CPU_cache_invalidate_1_data_line( d_addr ); |
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| 204 | d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT); |
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[cf1f72e] | 205 | } |
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| 206 | #endif |
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[2bd440e] | 207 | #endif |
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[8ef3818] | 208 | } |
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| 209 | |
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| 210 | |
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| 211 | /* |
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| 212 | * This function is responsible for performing a data cache flush. |
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| 213 | * It flushes the entire cache. |
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| 214 | */ |
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| 215 | void |
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[5e77d129] | 216 | rtems_cache_flush_entire_data( void ) |
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[8ef3818] | 217 | { |
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[5e77d129] | 218 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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[8ef3818] | 219 | /* |
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| 220 | * Call the CPU-specific routine |
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| 221 | */ |
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[5e77d129] | 222 | _CPU_cache_flush_entire_data(); |
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[cf1f72e] | 223 | #endif |
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[8ef3818] | 224 | } |
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| 225 | |
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| 226 | |
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| 227 | /* |
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| 228 | * This function is responsible for performing a data cache |
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| 229 | * invalidate. It invalidates the entire cache. |
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| 230 | */ |
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| 231 | void |
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[5e77d129] | 232 | rtems_cache_invalidate_entire_data( void ) |
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[8ef3818] | 233 | { |
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[5e77d129] | 234 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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[cf1f72e] | 235 | /* |
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| 236 | * Call the CPU-specific routine |
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| 237 | */ |
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| 238 | |
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[5e77d129] | 239 | _CPU_cache_invalidate_entire_data(); |
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[cf1f72e] | 240 | #endif |
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[8ef3818] | 241 | } |
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| 242 | |
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| 243 | |
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| 244 | /* |
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| 245 | * This function returns the data cache granularity. |
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| 246 | */ |
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[e7549ff4] | 247 | size_t |
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[5e77d129] | 248 | rtems_cache_get_data_line_size( void ) |
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[8ef3818] | 249 | { |
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[5e77d129] | 250 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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| 251 | return CPU_DATA_CACHE_ALIGNMENT; |
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[cf1f72e] | 252 | #else |
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| 253 | return 0; |
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| 254 | #endif |
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[8ef3818] | 255 | } |
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| 256 | |
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| 257 | |
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[e1d7bf0] | 258 | size_t |
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| 259 | rtems_cache_get_data_cache_size( uint32_t level ) |
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| 260 | { |
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| 261 | #if defined(CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS) |
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| 262 | return _CPU_cache_get_data_cache_size( level ); |
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| 263 | #else |
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| 264 | return 0; |
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| 265 | #endif |
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| 266 | } |
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| 267 | |
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[8ef3818] | 268 | /* |
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| 269 | * This function freezes the data cache; cache lines |
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| 270 | * are not replaced. |
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| 271 | */ |
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| 272 | void |
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[5e77d129] | 273 | rtems_cache_freeze_data( void ) |
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[8ef3818] | 274 | { |
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[5e77d129] | 275 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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| 276 | _CPU_cache_freeze_data(); |
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[cf1f72e] | 277 | #endif |
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[8ef3818] | 278 | } |
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| 279 | |
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| 280 | |
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| 281 | /* |
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| 282 | * This function unfreezes the instruction cache. |
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| 283 | */ |
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[5e77d129] | 284 | void rtems_cache_unfreeze_data( void ) |
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[8ef3818] | 285 | { |
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[5e77d129] | 286 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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| 287 | _CPU_cache_unfreeze_data(); |
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[cf1f72e] | 288 | #endif |
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[8ef3818] | 289 | } |
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| 290 | |
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| 291 | |
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| 292 | /* Turn on the data cache. */ |
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| 293 | void |
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[5e77d129] | 294 | rtems_cache_enable_data( void ) |
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[8ef3818] | 295 | { |
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[5e77d129] | 296 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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| 297 | _CPU_cache_enable_data(); |
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[cf1f72e] | 298 | #endif |
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[8ef3818] | 299 | } |
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| 300 | |
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| 301 | |
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| 302 | /* Turn off the data cache. */ |
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| 303 | void |
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[5e77d129] | 304 | rtems_cache_disable_data( void ) |
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[8ef3818] | 305 | { |
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[5e77d129] | 306 | #if defined(CPU_DATA_CACHE_ALIGNMENT) |
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| 307 | _CPU_cache_disable_data(); |
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[8ef3818] | 308 | #endif |
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[cf1f72e] | 309 | } |
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[8ef3818] | 310 | |
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| 311 | |
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| 312 | |
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| 313 | /* |
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[cf1f72e] | 314 | * THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE AN INSTRUCTION CACHE |
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[8ef3818] | 315 | */ |
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| 316 | |
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[26c142e5] | 317 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) \ |
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| 318 | && defined(RTEMS_SMP) \ |
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| 319 | && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING) |
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| 320 | |
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| 321 | static void smp_cache_inst_inv(void *arg) |
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| 322 | { |
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| 323 | smp_cache_area *area = arg; |
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[ddbc3f8d] | 324 | |
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[26c142e5] | 325 | _CPU_cache_invalidate_instruction_range(area->addr, area->size); |
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| 326 | } |
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| 327 | |
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| 328 | static void smp_cache_inst_inv_all(void *arg) |
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| 329 | { |
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| 330 | _CPU_cache_invalidate_entire_instruction(); |
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| 331 | } |
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| 332 | |
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| 333 | #endif |
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[ddbc3f8d] | 334 | |
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[8ef3818] | 335 | /* |
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| 336 | * This function is responsible for performing an instruction cache |
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| 337 | * invalidate. It must determine how many cache lines need to be invalidated |
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| 338 | * and then perform the invalidations. |
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| 339 | */ |
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[ddbc3f8d] | 340 | |
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[26c142e5] | 341 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) \ |
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| 342 | && !defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS) |
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[ddbc3f8d] | 343 | static void |
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[26c142e5] | 344 | _CPU_cache_invalidate_instruction_range( |
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[ddbc3f8d] | 345 | const void * i_addr, |
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| 346 | size_t n_bytes |
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| 347 | ) |
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[8ef3818] | 348 | { |
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[cf1f72e] | 349 | const void * final_address; |
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| 350 | |
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| 351 | /* |
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| 352 | * Set i_addr to the beginning of the cache line; final_address indicates |
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| 353 | * the last address_t which needs to be invalidated. Increment i_addr and |
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| 354 | * invalidate the resulting line until final_address is passed. |
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| 355 | */ |
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| 356 | |
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[d2978ee9] | 357 | if( n_bytes == 0 ) |
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| 358 | /* Do nothing if number of bytes to invalidate is zero */ |
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| 359 | return; |
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[359e537] | 360 | |
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[cf1f72e] | 361 | final_address = (void *)((size_t)i_addr + n_bytes - 1); |
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[5e77d129] | 362 | i_addr = (void *)((size_t)i_addr & ~(CPU_INSTRUCTION_CACHE_ALIGNMENT - 1)); |
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[fc6a0ae] | 363 | while( final_address >= i_addr ) { |
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[5e77d129] | 364 | _CPU_cache_invalidate_1_instruction_line( i_addr ); |
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| 365 | i_addr = (void *)((size_t)i_addr + CPU_INSTRUCTION_CACHE_ALIGNMENT); |
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[cf1f72e] | 366 | } |
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[ddbc3f8d] | 367 | } |
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| 368 | #endif |
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| 369 | |
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| 370 | void |
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| 371 | rtems_cache_invalidate_multiple_instruction_lines( |
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| 372 | const void * i_addr, |
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| 373 | size_t n_bytes |
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| 374 | ) |
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| 375 | { |
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| 376 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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| 377 | #if defined(RTEMS_SMP) && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING) |
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[26c142e5] | 378 | smp_cache_area area = { i_addr, n_bytes }; |
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[ddbc3f8d] | 379 | |
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[26c142e5] | 380 | _SMP_Multicast_action( 0, NULL, smp_cache_inst_inv, &area ); |
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[ddbc3f8d] | 381 | #else |
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[26c142e5] | 382 | _CPU_cache_invalidate_instruction_range( i_addr, n_bytes ); |
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[cf1f72e] | 383 | #endif |
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[2bd440e] | 384 | #endif |
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[8ef3818] | 385 | } |
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| 386 | |
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| 387 | |
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| 388 | /* |
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| 389 | * This function is responsible for performing an instruction cache |
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| 390 | * invalidate. It invalidates the entire cache. |
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| 391 | */ |
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| 392 | void |
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[5e77d129] | 393 | rtems_cache_invalidate_entire_instruction( void ) |
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[8ef3818] | 394 | { |
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[5e77d129] | 395 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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[ddbc3f8d] | 396 | #if defined(RTEMS_SMP) && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING) |
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[26c142e5] | 397 | _SMP_Multicast_action( 0, NULL, smp_cache_inst_inv_all, NULL ); |
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[ddbc3f8d] | 398 | #else |
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[5e77d129] | 399 | _CPU_cache_invalidate_entire_instruction(); |
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[cf1f72e] | 400 | #endif |
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[ddbc3f8d] | 401 | #endif |
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[8ef3818] | 402 | } |
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| 403 | |
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| 404 | |
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| 405 | /* |
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| 406 | * This function returns the instruction cache granularity. |
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| 407 | */ |
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[e7549ff4] | 408 | size_t |
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[5e77d129] | 409 | rtems_cache_get_instruction_line_size( void ) |
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[8ef3818] | 410 | { |
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[5e77d129] | 411 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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| 412 | return CPU_INSTRUCTION_CACHE_ALIGNMENT; |
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[cf1f72e] | 413 | #else |
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| 414 | return 0; |
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| 415 | #endif |
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[8ef3818] | 416 | } |
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| 417 | |
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| 418 | |
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[e1d7bf0] | 419 | size_t |
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| 420 | rtems_cache_get_instruction_cache_size( uint32_t level ) |
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| 421 | { |
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| 422 | #if defined(CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS) |
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| 423 | return _CPU_cache_get_instruction_cache_size( level ); |
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| 424 | #else |
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| 425 | return 0; |
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| 426 | #endif |
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| 427 | } |
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| 428 | |
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| 429 | |
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[8ef3818] | 430 | /* |
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| 431 | * This function freezes the instruction cache; cache lines |
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| 432 | * are not replaced. |
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| 433 | */ |
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| 434 | void |
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[5e77d129] | 435 | rtems_cache_freeze_instruction( void ) |
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[8ef3818] | 436 | { |
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[5e77d129] | 437 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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| 438 | _CPU_cache_freeze_instruction(); |
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[cf1f72e] | 439 | #endif |
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[8ef3818] | 440 | } |
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| 441 | |
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| 442 | |
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| 443 | /* |
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| 444 | * This function unfreezes the instruction cache. |
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| 445 | */ |
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[5e77d129] | 446 | void rtems_cache_unfreeze_instruction( void ) |
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[8ef3818] | 447 | { |
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[5e77d129] | 448 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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| 449 | _CPU_cache_unfreeze_instruction(); |
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[cf1f72e] | 450 | #endif |
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[8ef3818] | 451 | } |
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| 452 | |
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| 453 | |
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| 454 | /* Turn on the instruction cache. */ |
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| 455 | void |
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[5e77d129] | 456 | rtems_cache_enable_instruction( void ) |
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[8ef3818] | 457 | { |
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[5e77d129] | 458 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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| 459 | _CPU_cache_enable_instruction(); |
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[cf1f72e] | 460 | #endif |
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[8ef3818] | 461 | } |
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| 462 | |
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| 463 | |
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| 464 | /* Turn off the instruction cache. */ |
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| 465 | void |
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[5e77d129] | 466 | rtems_cache_disable_instruction( void ) |
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[8ef3818] | 467 | { |
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[5e77d129] | 468 | #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) |
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| 469 | _CPU_cache_disable_instruction(); |
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[8ef3818] | 470 | #endif |
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[cf1f72e] | 471 | } |
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