[ba71076] | 1 | /* |
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| 2 | * timer driver for the Hitachi SH 7750 |
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| 3 | * |
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| 4 | * This file manages the benchmark timer used by the RTEMS Timing Test |
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| 5 | * Suite. Each measured time period is demarcated by calls to |
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| 6 | * Timer_initialize() and Read_timer(). Read_timer() usually returns |
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| 7 | * the number of microseconds since Timer_initialize() exitted. |
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| 8 | * |
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| 9 | * NOTE: It is important that the timer start/stop overhead be |
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| 10 | * determined when porting or modifying this code. |
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| 11 | * |
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| 12 | * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia |
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| 13 | * Author: Victor V. Vengerov <vvv@oktet.ru> |
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| 14 | * |
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| 15 | * COPYRIGHT (c) 1998. |
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| 16 | * On-Line Applications Research Corporation (OAR). |
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| 17 | * |
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| 18 | * The license and distribution terms for this file may be |
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| 19 | * found in the file LICENSE in this distribution or at |
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| 20 | * http://www.OARcorp.com/rtems/license.html. |
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| 21 | * |
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| 22 | * $Id$ |
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| 23 | */ |
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| 24 | |
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| 25 | #include <rtems.h> |
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| 26 | |
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| 27 | #include <rtems/score/sh_io.h> |
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| 28 | #include <rtems/score/iosh7750.h> |
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| 29 | |
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| 30 | #ifndef TIMER_PRIO |
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| 31 | #define TIMER_PRIO 15 |
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| 32 | #endif |
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| 33 | |
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| 34 | /* Timer prescaler division ratio */ |
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| 35 | #define TIMER_PRESCALER 4 |
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| 36 | #define TCR1_TPSC SH7750_TCR_TPSC_DIV4 |
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| 37 | |
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| 38 | #define TIMER_VECTOR SH7750_EVT_TO_NUM(SH7750_EVT_TUNI1) |
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| 39 | |
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| 40 | rtems_isr timerisr(); |
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| 41 | |
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| 42 | static rtems_unsigned32 Timer_interrupts; |
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| 43 | |
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| 44 | /* Counter should be divided to this value to obtain time in microseconds */ |
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| 45 | static rtems_unsigned32 microseconds_divider; |
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| 46 | |
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| 47 | /* Interrupt period in microseconds */ |
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| 48 | static rtems_unsigned32 microseconds_per_int; |
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| 49 | |
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| 50 | rtems_boolean Timer_driver_Find_average_overhead; |
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| 51 | |
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| 52 | /* Timer_initialize -- |
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| 53 | * Initialize Timer 1 to operate as a RTEMS benchmark timer: |
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| 54 | * - determine timer clock frequency |
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| 55 | * - install timer interrupt handler |
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| 56 | * - configure the Timer 1 hardware |
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| 57 | * - start the timer |
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| 58 | * |
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| 59 | * PARAMETERS: |
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| 60 | * none |
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| 61 | * |
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| 62 | * RETURNS: |
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| 63 | * none |
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| 64 | */ |
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| 65 | void |
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| 66 | Timer_initialize(void) |
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| 67 | { |
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| 68 | rtems_unsigned8 temp8; |
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| 69 | rtems_unsigned16 temp16; |
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| 70 | rtems_interrupt_level level; |
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| 71 | rtems_isr *ignored; |
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| 72 | int cpudiv = 1; |
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| 73 | int tidiv = 1; |
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| 74 | |
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| 75 | Timer_interrupts = 0; |
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| 76 | _CPU_ISR_Disable(level); |
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| 77 | |
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| 78 | /* Get CPU frequency divider from clock unit */ |
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| 79 | switch (read16(SH7750_FRQCR) & SH7750_FRQCR_IFC) |
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| 80 | { |
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| 81 | case SH7750_FRQCR_IFCDIV1: |
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| 82 | cpudiv = 1; |
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| 83 | break; |
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| 84 | |
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| 85 | case SH7750_FRQCR_IFCDIV2: |
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| 86 | cpudiv = 2; |
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| 87 | break; |
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| 88 | |
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| 89 | case SH7750_FRQCR_IFCDIV3: |
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| 90 | cpudiv = 3; |
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| 91 | break; |
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| 92 | |
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| 93 | case SH7750_FRQCR_IFCDIV4: |
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| 94 | cpudiv = 4; |
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| 95 | break; |
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| 96 | |
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| 97 | case SH7750_FRQCR_IFCDIV6: |
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| 98 | cpudiv = 6; |
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| 99 | break; |
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| 100 | |
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| 101 | case SH7750_FRQCR_IFCDIV8: |
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| 102 | cpudiv = 8; |
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| 103 | break; |
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| 104 | |
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| 105 | default: |
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| 106 | rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED); |
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| 107 | } |
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| 108 | |
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| 109 | /* Get peripheral module frequency divider from clock unit */ |
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| 110 | switch (read16(SH7750_FRQCR) & SH7750_FRQCR_PFC) |
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| 111 | { |
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| 112 | case SH7750_FRQCR_PFCDIV2: |
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| 113 | tidiv = 2 * TIMER_PRESCALER; |
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| 114 | break; |
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| 115 | |
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| 116 | case SH7750_FRQCR_PFCDIV3: |
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| 117 | tidiv = 3 * TIMER_PRESCALER; |
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| 118 | break; |
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| 119 | |
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| 120 | case SH7750_FRQCR_PFCDIV4: |
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| 121 | tidiv = 4 * TIMER_PRESCALER; |
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| 122 | break; |
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| 123 | |
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| 124 | case SH7750_FRQCR_PFCDIV6: |
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| 125 | tidiv = 6 * TIMER_PRESCALER; |
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| 126 | break; |
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| 127 | |
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| 128 | case SH7750_FRQCR_PFCDIV8: |
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| 129 | tidiv = 8 * TIMER_PRESCALER; |
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| 130 | break; |
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| 131 | |
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| 132 | default: |
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| 133 | rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED); |
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| 134 | } |
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| 135 | |
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| 136 | microseconds_divider = |
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| 137 | rtems_cpu_configuration_get_clicks_per_second() * cpudiv / |
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| 138 | (tidiv * 1000000); |
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| 139 | microseconds_per_int = 0xFFFFFFFF / microseconds_divider; |
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| 140 | |
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| 141 | /* |
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| 142 | * Hardware specific initialization |
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| 143 | */ |
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| 144 | |
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| 145 | /* Stop the Timer 0 */ |
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| 146 | temp8 = read8(SH7750_TSTR); |
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| 147 | temp8 &= ~SH7750_TSTR_STR1; |
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| 148 | write8(temp8, SH7750_TSTR); |
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| 149 | |
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| 150 | /* Establish interrupt handler */ |
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| 151 | _CPU_ISR_install_raw_handler( TIMER_VECTOR, timerisr, &ignored ); |
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| 152 | |
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| 153 | /* Reset timer constant and counter */ |
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| 154 | write32(0xFFFFFFFF, SH7750_TCOR1); |
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| 155 | write32(0xFFFFFFFF, SH7750_TCNT1); |
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| 156 | |
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| 157 | /* Select timer mode */ |
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| 158 | write16( |
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| 159 | SH7750_TCR_UNIE | /* Enable Underflow Interrupt */ |
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| 160 | SH7750_TCR_CKEG_RAISE | /* Count on rising edge */ |
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| 161 | TCR1_TPSC, /* Timer prescaler ratio */ |
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| 162 | SH7750_TCR1); |
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| 163 | |
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| 164 | /* Set timer interrupt priority */ |
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| 165 | temp16 = read16(SH7750_IPRA); |
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| 166 | temp16 = (temp16 & ~SH7750_IPRA_TMU1) | (TIMER_PRIO << SH7750_IPRA_TMU1_S); |
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| 167 | write16(temp16, SH7750_IPRA); |
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| 168 | |
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| 169 | |
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| 170 | _CPU_ISR_Enable(level); |
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| 171 | |
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| 172 | /* Start the Timer 1 */ |
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| 173 | temp8 = read8(SH7750_TSTR); |
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| 174 | temp8 |= SH7750_TSTR_STR1; |
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| 175 | write8(temp8, SH7750_TSTR); |
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| 176 | |
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| 177 | } |
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| 178 | |
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| 179 | /* |
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| 180 | * The following controls the behavior of Read_timer(). |
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| 181 | * |
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| 182 | * AVG_OVERHEAD is the overhead for starting and stopping the timer. It |
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| 183 | * is usually deducted from the number returned. |
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| 184 | * |
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| 185 | * LEAST_VALID is the lowest number this routine should trust. Numbers |
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| 186 | * below this are "noise" and zero is returned. |
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| 187 | */ |
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| 188 | |
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| 189 | #define AVG_OVERHEAD 0 /* It typically takes X.X microseconds */ |
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| 190 | /* (Y countdowns) to start/stop the timer. */ |
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| 191 | /* This value is in microseconds. */ |
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| 192 | #define LEAST_VALID 0 /* 20 */ /* Don't trust a clicks value lower than this */ |
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| 193 | |
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| 194 | /* Read_timer -- |
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| 195 | * Read timer value in microsecond units since timer start. |
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| 196 | * |
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| 197 | * PARAMETERS: |
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| 198 | * none |
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| 199 | * |
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| 200 | * RETURNS: |
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| 201 | * number of microseconds since timer has been started |
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| 202 | */ |
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| 203 | int |
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| 204 | Read_timer(void) |
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| 205 | { |
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| 206 | rtems_unsigned32 clicks; |
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| 207 | rtems_unsigned32 ints; |
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| 208 | rtems_unsigned32 total ; |
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| 209 | rtems_interrupt_level level; |
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| 210 | rtems_unsigned32 tcr; |
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| 211 | |
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| 212 | |
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| 213 | _CPU_ISR_Disable(level); |
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| 214 | |
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| 215 | clicks = 0xFFFFFFFF - read32(SH7750_TCNT1); |
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| 216 | tcr = read32(SH7750_TCR1); |
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| 217 | ints = Timer_interrupts; |
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| 218 | |
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| 219 | _CPU_ISR_Enable(level); |
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| 220 | |
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| 221 | /* Handle the case when timer overflowed but interrupt was not processed */ |
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| 222 | if ((clicks > 0xFF000000) && ((tcr & SH7750_TCR_UNF) != 0)) |
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| 223 | { |
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| 224 | ints++; |
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| 225 | } |
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| 226 | |
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| 227 | total = microseconds_per_int * ints + (clicks / microseconds_divider); |
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| 228 | |
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| 229 | if ( Timer_driver_Find_average_overhead ) |
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| 230 | return total; /* in microsecond units */ |
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| 231 | else |
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| 232 | { |
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| 233 | if ( total < LEAST_VALID ) |
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| 234 | return 0; /* below timer resolution */ |
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| 235 | /* |
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| 236 | * Somehow convert total into microseconds |
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| 237 | */ |
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| 238 | return (total - AVG_OVERHEAD) ; |
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| 239 | } |
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| 240 | } |
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| 241 | |
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| 242 | /* Empty_function -- |
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| 243 | * Empty function call used in loops to measure basic cost of looping |
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| 244 | * in Timing Test Suite. |
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| 245 | * |
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| 246 | * PARAMETERS: |
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| 247 | * none |
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| 248 | * |
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| 249 | * RETURNS: |
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| 250 | * RTEMS_SUCCESSFUL |
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| 251 | */ |
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| 252 | rtems_status_code |
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| 253 | Empty_function( void ) |
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| 254 | { |
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| 255 | return RTEMS_SUCCESSFUL; |
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| 256 | } |
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| 257 | |
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| 258 | /* Set_find_average_overhead -- |
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| 259 | * This routine is invoked by the "Check Timer" (tmck) test in the |
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| 260 | * RTEMS Timing Test Suite. It makes the Read_timer routine not |
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| 261 | * subtract the overhead required to initialize and read the benchmark |
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| 262 | * timer. |
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| 263 | * |
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| 264 | * PARAMETERS: |
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| 265 | * find_flag - boolean flag, TRUE if overhead must not be subtracted. |
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| 266 | * |
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| 267 | * RETURNS: |
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| 268 | * none |
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| 269 | */ |
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| 270 | void |
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| 271 | Set_find_average_overhead(rtems_boolean find_flag) |
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| 272 | { |
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| 273 | Timer_driver_Find_average_overhead = find_flag; |
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| 274 | } |
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| 275 | |
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| 276 | /* timerisr -- |
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| 277 | * Timer interrupt handler routine. This function invoked on timer |
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| 278 | * underflow event; once per 2^32 clocks. It should reset the timer |
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| 279 | * event and increment timer interrupts counter. |
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| 280 | */ |
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| 281 | void |
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| 282 | timerisr(void) |
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| 283 | { |
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| 284 | unsigned8 temp8; |
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| 285 | |
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| 286 | /* reset the flags of the status register */ |
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| 287 | temp8 = read8(SH7750_TCR1) & ~SH7750_TCR_UNF; |
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| 288 | write8(temp8, SH7750_TCR1); |
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| 289 | |
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| 290 | Timer_interrupts += 1; |
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| 291 | } |
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