1 | /* |
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2 | * This file contains the basic algorithms for all assembly code used |
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3 | * in an specific CPU port of RTEMS. These algorithms must be implemented |
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4 | * in assembly language |
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5 | * |
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6 | * NOTE: This port uses a C file with inline assembler instructions |
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7 | * |
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8 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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9 | * Bernd Becker (becker@faw.uni-ulm.de) |
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10 | * |
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11 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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12 | * |
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13 | * This program is distributed in the hope that it will be useful, |
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14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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16 | * |
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17 | * |
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18 | * COPYRIGHT (c) 1998. |
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19 | * On-Line Applications Research Corporation (OAR). |
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20 | * |
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21 | * The license and distribution terms for this file may be |
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22 | * found in the file LICENSE in this distribution or at |
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23 | * http://www.OARcorp.com/rtems/license.html. |
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24 | * |
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25 | * $Id$ |
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26 | * |
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27 | * This material may be reproduced by or for the U.S. Government pursuant |
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28 | * to the copyright license under the clause at DFARS 252.227-7013. This |
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29 | * notice must appear in all copies of this file and its derivatives. |
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30 | * |
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31 | */ |
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32 | |
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33 | /* |
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34 | * This is supposed to be an assembly file. This means that system.h |
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35 | * and cpu.h should not be included in a "real" cpu_asm file. An |
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36 | * implementation in assembly should include "cpu_asm.h" |
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37 | */ |
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38 | |
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39 | #include <rtems/system.h> |
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40 | #include <rtems/score/cpu.h> |
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41 | #include <rtems/score/isr.h> |
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42 | #include <rtems/score/thread.h> |
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43 | #include <rtems/score/sh.h> |
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44 | #include <rtems/score/ispsh7750.h> |
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45 | #include <rtems/score/iosh7750.h> |
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46 | #include <rtems/score/sh4_regs.h> |
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47 | #include <rtems/score/sh_io.h> |
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48 | |
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49 | /* from cpu_isps.c */ |
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50 | extern proc_ptr _Hardware_isr_Table[]; |
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51 | |
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52 | #if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
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53 | unsigned long *_old_stack_ptr; |
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54 | #endif |
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55 | |
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56 | register unsigned long *stack_ptr asm("r15"); |
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57 | |
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58 | /* |
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59 | * _CPU_Context_save_fp_context |
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60 | * |
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61 | * This routine is responsible for saving the FP context |
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62 | * at *fp_context_ptr. If the point to load the FP context |
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63 | * from is changed then the pointer is modified by this routine. |
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64 | * |
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65 | * Sometimes a macro implementation of this is in cpu.h which dereferences |
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66 | * the ** and a similarly named routine in this file is passed something |
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67 | * like a (Context_Control_fp *). The general rule on making this decision |
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68 | * is to avoid writing assembly language. |
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69 | */ |
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70 | |
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71 | void _CPU_Context_save_fp( |
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72 | void **fp_context_ptr /* r4 */ |
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73 | ) |
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74 | { |
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75 | #if SH_HAS_FPU |
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76 | |
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77 | asm volatile(" |
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78 | mov.l @%0,r4 |
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79 | add %1,r4 |
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80 | sts.l fpscr,@-r4 |
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81 | sts.l fpul,@-r4 |
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82 | lds %2,fpscr |
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83 | fmov dr14,@-r4 |
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84 | fmov dr12,@-r4 |
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85 | fmov dr10,@-r4 |
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86 | fmov dr8,@-r4 |
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87 | fmov dr6,@-r4 |
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88 | fmov dr4,@-r4 |
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89 | fmov dr2,@-r4 |
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90 | fmov dr0,@-r4 |
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91 | " |
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92 | #ifdef SH4_USE_X_REGISTERS |
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93 | " |
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94 | lds %3,fpscr |
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95 | fmov xd14,@-r4 |
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96 | fmov xd12,@-r4 |
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97 | fmov xd10,@-r4 |
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98 | fmov xd8,@-r4 |
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99 | fmov xd6,@-r4 |
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100 | fmov xd4,@-r4 |
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101 | fmov xd2,@-r4 |
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102 | fmov xd0,@-r4 |
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103 | " |
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104 | #endif |
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105 | "lds %4,fpscr |
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106 | " |
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107 | : |
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108 | : "r"(fp_context_ptr), "r"(sizeof(Context_Control_fp)), |
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109 | "r"(SH4_FPSCR_SZ), "r"(SH4_FPSCR_PR | SH4_FPSCR_SZ), "r"(SH4_FPSCR_PR) |
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110 | : "r4", "r0"); |
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111 | |
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112 | #endif |
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113 | } |
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114 | |
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115 | /* |
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116 | * _CPU_Context_restore_fp_context |
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117 | * |
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118 | * This routine is responsible for restoring the FP context |
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119 | * at *fp_context_ptr. If the point to load the FP context |
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120 | * from is changed then the pointer is modified by this routine. |
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121 | * |
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122 | * Sometimes a macro implementation of this is in cpu.h which dereferences |
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123 | * the ** and a similarly named routine in this file is passed something |
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124 | * like a (Context_Control_fp *). The general rule on making this decision |
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125 | * is to avoid writing assembly language. |
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126 | */ |
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127 | |
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128 | void _CPU_Context_restore_fp( |
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129 | void **fp_context_ptr /* r4 */ |
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130 | ) |
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131 | { |
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132 | #if SH_HAS_FPU |
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133 | |
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134 | asm volatile(" |
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135 | mov.l @%0,r4 |
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136 | " |
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137 | #ifdef SH4_USE_X_REGISTERS |
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138 | " |
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139 | lds %1,fpscr |
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140 | fmov @r4+,xd0 |
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141 | fmov @r4+,xd2 |
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142 | fmov @r4+,xd4 |
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143 | fmov @r4+,xd6 |
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144 | fmov @r4+,xd8 |
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145 | fmov @r4+,xd10 |
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146 | fmov @r4+,xd12 |
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147 | fmov @r4+,xd14 |
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148 | " |
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149 | #endif |
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150 | " |
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151 | lds %2,fpscr |
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152 | fmov @r4+,dr0 |
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153 | fmov @r4+,dr2 |
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154 | fmov @r4+,dr4 |
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155 | fmov @r4+,dr6 |
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156 | fmov @r4+,dr8 |
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157 | fmov @r4+,dr10 |
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158 | fmov @r4+,dr12 |
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159 | fmov @r4+,dr14 |
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160 | lds.l @r4+,fpul |
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161 | lds.l @r4+,fpscr |
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162 | " : |
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163 | : "r"(fp_context_ptr), "r"(SH4_FPSCR_PR | SH4_FPSCR_SZ), "r"(SH4_FPSCR_SZ) |
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164 | : "r4", "r0"); |
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165 | |
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166 | #endif |
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167 | } |
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168 | |
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169 | /* _CPU_Context_switch |
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170 | * |
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171 | * This routine performs a normal non-FP context switch. |
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172 | */ |
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173 | |
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174 | /* within __CPU_Context_switch: |
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175 | * _CPU_Context_switch |
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176 | * _CPU_Context_restore |
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177 | * |
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178 | * This routine is generally used only to restart self in an |
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179 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
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180 | * |
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181 | * NOTE: It should be safe not to store r4, r5 |
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182 | * |
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183 | * NOTE: It is doubtful if r0 is really needed to be stored |
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184 | * |
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185 | * NOTE: gbr is added, but should not be necessary, as it is |
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186 | * only used globally in this port. |
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187 | */ |
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188 | |
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189 | /* |
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190 | * FIXME: This is an ugly hack, but we wanted to avoid recalculating |
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191 | * the offset each time Context_Control is changed |
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192 | */ |
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193 | void __CPU_Context_switch( |
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194 | Context_Control *run, /* r4 */ |
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195 | Context_Control *heir /* r5 */ |
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196 | ) |
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197 | { |
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198 | |
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199 | asm volatile(" |
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200 | .global __CPU_Context_switch |
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201 | __CPU_Context_switch: |
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202 | |
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203 | add %0,r4 |
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204 | |
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205 | stc.l sr,@-r4 |
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206 | stc.l gbr,@-r4 |
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207 | mov.l r0,@-r4 |
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208 | mov.l r1,@-r4 |
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209 | mov.l r2,@-r4 |
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210 | mov.l r3,@-r4 |
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211 | |
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212 | mov.l r6,@-r4 |
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213 | mov.l r7,@-r4 |
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214 | mov.l r8,@-r4 |
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215 | mov.l r9,@-r4 |
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216 | mov.l r10,@-r4 |
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217 | mov.l r11,@-r4 |
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218 | mov.l r12,@-r4 |
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219 | mov.l r13,@-r4 |
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220 | mov.l r14,@-r4 |
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221 | sts.l pr,@-r4 |
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222 | sts.l mach,@-r4 |
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223 | sts.l macl,@-r4 |
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224 | mov.l r15,@-r4 |
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225 | |
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226 | mov r5, r4" |
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227 | :: "I" (sizeof(Context_Control)) |
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228 | ); |
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229 | |
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230 | asm volatile(" |
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231 | .global __CPU_Context_restore |
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232 | __CPU_Context_restore: |
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233 | mov.l @r4+,r15 |
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234 | lds.l @r4+,macl |
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235 | lds.l @r4+,mach |
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236 | lds.l @r4+,pr |
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237 | mov.l @r4+,r14 |
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238 | mov.l @r4+,r13 |
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239 | mov.l @r4+,r12 |
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240 | mov.l @r4+,r11 |
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241 | mov.l @r4+,r10 |
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242 | mov.l @r4+,r9 |
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243 | mov.l @r4+,r8 |
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244 | mov.l @r4+,r7 |
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245 | mov.l @r4+,r6 |
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246 | |
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247 | mov.l @r4+,r3 |
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248 | mov.l @r4+,r2 |
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249 | mov.l @r4+,r1 |
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250 | mov.l @r4+,r0 |
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251 | ldc.l @r4+,gbr |
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252 | ldc.l @r4+,sr |
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253 | |
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254 | rts |
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255 | nop" ); |
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256 | } |
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257 | |
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258 | /* |
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259 | * This routine provides the RTEMS interrupt management. |
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260 | */ |
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261 | |
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262 | void __ISR_Handler( unsigned32 vector) |
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263 | { |
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264 | register unsigned32 level; |
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265 | |
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266 | _CPU_ISR_Disable( level ); |
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267 | |
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268 | _Thread_Dispatch_disable_level++; |
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269 | |
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270 | #if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
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271 | if( _ISR_Nest_level == 0 ) |
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272 | { |
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273 | /* Install irq stack */ |
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274 | _old_stack_ptr = stack_ptr; |
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275 | stack_ptr = _CPU_Interrupt_stack_high; |
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276 | } |
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277 | |
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278 | #endif |
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279 | |
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280 | _ISR_Nest_level++; |
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281 | |
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282 | _CPU_ISR_Enable( level ); |
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283 | |
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284 | /* call isp */ |
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285 | if( _ISR_Vector_table[ vector]) |
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286 | (*_ISR_Vector_table[ vector ])( vector ); |
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287 | |
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288 | _CPU_ISR_Disable( level ); |
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289 | |
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290 | _ISR_Nest_level--; |
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291 | |
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292 | #if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
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293 | |
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294 | if( _ISR_Nest_level == 0 ) |
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295 | /* restore old stack pointer */ |
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296 | stack_ptr = _old_stack_ptr; |
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297 | #endif |
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298 | |
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299 | _Thread_Dispatch_disable_level--; |
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300 | |
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301 | _CPU_ISR_Enable( level ); |
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302 | |
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303 | if ( _Thread_Dispatch_disable_level == 0 ) |
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304 | { |
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305 | if(( _Context_Switch_necessary) || (! _ISR_Signals_to_thread_executing)) |
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306 | { |
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307 | _ISR_Signals_to_thread_executing = FALSE; |
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308 | _Thread_Dispatch(); |
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309 | } |
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310 | } |
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311 | } |
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