source: rtems/c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c @ ba71076

4.104.114.84.95
Last change on this file since ba71076 was ba71076, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 12, 2001 at 1:19:08 PM

2001-10-11 Alexandra Kossovsky <sasha@…>

  • clock/Makefile.am, clock/ckinit.c, clock/.cvsignore, Makefile.am, include/Makefile.am, include/iosh7750.h, include/ipl.h, include/ispsh7750.h, include/sh4_regs.h, include/sh4uart.h, include/sh7750_regs.h, include/.cvsignore, sci/Makefile.am, sci/console.c, sci/sh4uart.c, sci/.cvsignore, score/Makefile.am, score/cpu_asm.c, score/ispsh7750.c, score/.cvsignore, timer/Makefile.am, timer/timer.c, timer/.cvsignore, configure.ac, .cvsignore, ChangeLog?: New files. Reviewed and updated to latest automake and autoconf standards by Ralf Corsepius <corsepiu@…>.
  • Property mode set to 100644
File size: 6.9 KB
Line 
1/*
2 *  This file contains the basic algorithms for all assembly code used
3 *  in an specific CPU port of RTEMS.  These algorithms must be implemented
4 *  in assembly language
5 *
6 *  NOTE:  This port uses a C file with inline assembler instructions
7 *
8 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
9 *           Bernd Becker (becker@faw.uni-ulm.de)
10 *
11 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
12 *
13 *  This program is distributed in the hope that it will be useful,
14 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
15 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
16 *
17 *
18 *  COPYRIGHT (c) 1998.
19 *  On-Line Applications Research Corporation (OAR).
20 *  Copyright assigned to U.S. Government, 1994.
21 *
22 *  The license and distribution terms for this file may be
23 *  found in the file LICENSE in this distribution or at
24 *  http://www.OARcorp.com/rtems/license.html.
25 *
26 *  $Id$
27 *
28 *  This material may be reproduced by or for the U.S. Government pursuant
29 *  to the copyright license under the clause at DFARS 252.227-7013.  This
30 *  notice must appear in all copies of this file and its derivatives.
31 *
32 */
33
34/*
35 *  This is supposed to be an assembly file.  This means that system.h
36 *  and cpu.h should not be included in a "real" cpu_asm file.  An
37 *  implementation in assembly should include "cpu_asm.h"
38 */
39
40#include <rtems/system.h>
41#include <rtems/score/cpu.h>
42#include <rtems/score/isr.h>
43#include <rtems/score/thread.h>
44#include <rtems/score/sh.h>
45#include <rtems/score/ispsh7750.h>
46#include <rtems/score/iosh7750.h>
47#include <rtems/score/sh4_regs.h>
48#include <rtems/score/sh_io.h>
49
50/* from cpu_isps.c */
51extern proc_ptr         _Hardware_isr_Table[];
52
53#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
54  unsigned long    *_old_stack_ptr;
55#endif
56
57register unsigned long  *stack_ptr asm("r15"); 
58
59/*
60 *  _CPU_Context_save_fp_context
61 *
62 *  This routine is responsible for saving the FP context
63 *  at *fp_context_ptr.  If the point to load the FP context
64 *  from is changed then the pointer is modified by this routine.
65 *
66 *  Sometimes a macro implementation of this is in cpu.h which dereferences
67 *  the ** and a similarly named routine in this file is passed something
68 *  like a (Context_Control_fp *).  The general rule on making this decision
69 *  is to avoid writing assembly language.
70 */
71
72void _CPU_Context_save_fp(
73  void **fp_context_ptr     /* r4 */
74)
75{
76#if SH_HAS_FPU
77 
78asm volatile("
79    mov.l   @%0,r4   
80    add     %1,r4
81    sts.l   fpscr,@-r4
82    sts.l   fpul,@-r4
83    lds     %2,fpscr
84    fmov    dr14,@-r4
85    fmov    dr12,@-r4
86    fmov    dr10,@-r4
87    fmov    dr8,@-r4
88    fmov    dr6,@-r4
89    fmov    dr4,@-r4
90    fmov    dr2,@-r4
91    fmov    dr0,@-r4
92    "
93#ifdef SH4_USE_X_REGISTERS
94    "
95    lds     %3,fpscr
96    fmov    xd14,@-r4
97    fmov    xd12,@-r4
98    fmov    xd10,@-r4
99    fmov    xd8,@-r4
100    fmov    xd6,@-r4
101    fmov    xd4,@-r4
102    fmov    xd2,@-r4
103    fmov    xd0,@-r4
104    "
105#endif
106   "lds     %4,fpscr
107   "
108    : 
109    : "r"(fp_context_ptr), "r"(sizeof(Context_Control_fp)), 
110      "r"(SH4_FPSCR_SZ), "r"(SH4_FPSCR_PR | SH4_FPSCR_SZ), "r"(SH4_FPSCR_PR)
111    : "r4", "r0");
112
113#endif
114}
115
116/*
117 *  _CPU_Context_restore_fp_context
118 *
119 *  This routine is responsible for restoring the FP context
120 *  at *fp_context_ptr.  If the point to load the FP context
121 *  from is changed then the pointer is modified by this routine.
122 *
123 *  Sometimes a macro implementation of this is in cpu.h which dereferences
124 *  the ** and a similarly named routine in this file is passed something
125 *  like a (Context_Control_fp *).  The general rule on making this decision
126 *  is to avoid writing assembly language.
127 */
128
129void _CPU_Context_restore_fp(
130  void **fp_context_ptr     /* r4 */
131)
132{
133#if SH_HAS_FPU
134
135asm volatile("
136    mov.l   @%0,r4   
137    "
138#ifdef SH4_USE_X_REGISTERS
139    "
140    lds     %1,fpscr
141    fmov    @r4+,xd0
142    fmov    @r4+,xd2
143    fmov    @r4+,xd4
144    fmov    @r4+,xd6
145    fmov    @r4+,xd8
146    fmov    @r4+,xd10
147    fmov    @r4+,xd12
148    fmov    @r4+,xd14
149    "
150#endif
151    "
152    lds     %2,fpscr
153    fmov    @r4+,dr0
154    fmov    @r4+,dr2
155    fmov    @r4+,dr4
156    fmov    @r4+,dr6
157    fmov    @r4+,dr8
158    fmov    @r4+,dr10
159    fmov    @r4+,dr12
160    fmov    @r4+,dr14
161    lds.l   @r4+,fpul
162    lds.l   @r4+,fpscr
163    " :
164    : "r"(fp_context_ptr), "r"(SH4_FPSCR_PR | SH4_FPSCR_SZ), "r"(SH4_FPSCR_SZ)
165    : "r4", "r0");
166
167#endif
168}
169
170/*  _CPU_Context_switch
171 *
172 *  This routine performs a normal non-FP context switch.
173 */
174
175/*  within __CPU_Context_switch:
176 *  _CPU_Context_switch
177 *  _CPU_Context_restore
178 *
179 *  This routine is generally used only to restart self in an
180 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
181 *
182 * NOTE: It should be safe not to store r4, r5
183 *
184 * NOTE: It is doubtful if r0 is really needed to be stored
185 *
186 * NOTE: gbr is added, but should not be necessary, as it is
187 *      only used globally in this port.
188 */
189
190/*
191 * FIXME: This is an ugly hack, but we wanted to avoid recalculating
192 *        the offset each time Context_Control is changed
193 */
194void __CPU_Context_switch(
195  Context_Control  *run,        /* r4 */
196  Context_Control  *heir        /* r5 */
197)
198{
199
200asm volatile("
201        .global __CPU_Context_switch
202__CPU_Context_switch:
203
204        add     %0,r4
205 
206        stc.l   sr,@-r4
207        stc.l   gbr,@-r4
208        mov.l   r0,@-r4
209        mov.l   r1,@-r4
210        mov.l   r2,@-r4
211        mov.l   r3,@-r4
212
213        mov.l   r6,@-r4
214        mov.l   r7,@-r4
215        mov.l   r8,@-r4
216        mov.l   r9,@-r4
217        mov.l   r10,@-r4
218        mov.l   r11,@-r4
219        mov.l   r12,@-r4
220        mov.l   r13,@-r4
221        mov.l   r14,@-r4
222        sts.l   pr,@-r4
223        sts.l   mach,@-r4
224        sts.l   macl,@-r4
225        mov.l   r15,@-r4
226
227        mov     r5, r4"
228  :: "I" (sizeof(Context_Control))
229  );
230
231  asm volatile("
232        .global __CPU_Context_restore
233__CPU_Context_restore:
234        mov.l   @r4+,r15
235        lds.l   @r4+,macl
236        lds.l   @r4+,mach
237        lds.l   @r4+,pr
238        mov.l   @r4+,r14
239        mov.l   @r4+,r13
240        mov.l   @r4+,r12
241        mov.l   @r4+,r11
242        mov.l   @r4+,r10
243        mov.l   @r4+,r9
244        mov.l   @r4+,r8
245        mov.l   @r4+,r7
246        mov.l   @r4+,r6
247
248        mov.l   @r4+,r3
249        mov.l   @r4+,r2
250        mov.l   @r4+,r1
251        mov.l   @r4+,r0
252        ldc.l   @r4+,gbr
253        ldc.l   @r4+,sr
254
255        rts
256        nop" );
257}
258
259/* 
260 *  This routine provides the RTEMS interrupt management.
261 */
262 
263void __ISR_Handler( unsigned32 vector)
264{
265  register unsigned32 level;
266
267  _CPU_ISR_Disable( level );
268
269  _Thread_Dispatch_disable_level++;
270
271#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
272  if( _ISR_Nest_level == 0 )
273    {
274      /* Install irq stack */
275      _old_stack_ptr = stack_ptr;
276      stack_ptr = _CPU_Interrupt_stack_high;
277    }
278
279#endif
280
281  _ISR_Nest_level++;
282
283  _CPU_ISR_Enable( level );
284
285  /* call isp */
286  if( _ISR_Vector_table[ vector])
287    (*_ISR_Vector_table[ vector ])( vector );
288
289  _CPU_ISR_Disable( level );
290
291  _ISR_Nest_level--;
292
293#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
294
295  if( _ISR_Nest_level == 0 )
296    /* restore old stack pointer */
297    stack_ptr = _old_stack_ptr; 
298#endif
299
300  _Thread_Dispatch_disable_level--;
301
302  _CPU_ISR_Enable( level );
303
304  if ( _Thread_Dispatch_disable_level == 0 )
305    {
306      if(( _Context_Switch_necessary) || (! _ISR_Signals_to_thread_executing))
307        {
308          _ISR_Signals_to_thread_executing = FALSE;
309          _Thread_Dispatch();
310        }
311  }
312}
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