source: rtems/c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c @ 92e57ea2

4.104.114.84.95
Last change on this file since 92e57ea2 was 92e57ea2, checked in by Joel Sherrill <joel.sherrill@…>, on Feb 11, 2003 at 11:42:14 PM

2003-02-11 Joel Sherrill <joel@…>

  • score/cpu_asm.c: Rework logic that decides when to call _Thread_Dispatch. Analysis by Sergei Organov <osv@…> determined that _ISR_Signals_to_thread_executing was not being honored and/or cleared properly.
  • Property mode set to 100644
File size: 7.3 KB
Line 
1/*
2 *  This file contains the basic algorithms for all assembly code used
3 *  in an specific CPU port of RTEMS.  These algorithms must be implemented
4 *  in assembly language
5 *
6 *  NOTE:  This port uses a C file with inline assembler instructions
7 *
8 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
9 *           Bernd Becker (becker@faw.uni-ulm.de)
10 *
11 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
12 *
13 *  This program is distributed in the hope that it will be useful,
14 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
15 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
16 *
17 *
18 *  COPYRIGHT (c) 1998.
19 *  On-Line Applications Research Corporation (OAR).
20 *
21 *  The license and distribution terms for this file may be
22 *  found in the file LICENSE in this distribution or at
23 *  http://www.OARcorp.com/rtems/license.html.
24 *
25 *  $Id$
26 *
27 *  This material may be reproduced by or for the U.S. Government pursuant
28 *  to the copyright license under the clause at DFARS 252.227-7013.  This
29 *  notice must appear in all copies of this file and its derivatives.
30 *
31 */
32
33/*
34 *  This is supposed to be an assembly file.  This means that system.h
35 *  and cpu.h should not be included in a "real" cpu_asm file.  An
36 *  implementation in assembly should include "cpu_asm.h"
37 */
38
39#include <rtems/system.h>
40#include <rtems/score/cpu.h>
41#include <rtems/score/isr.h>
42#include <rtems/score/thread.h>
43#include <rtems/score/sh.h>
44#include <rtems/score/ispsh7750.h>
45#include <rtems/score/iosh7750.h>
46#include <rtems/score/sh4_regs.h>
47#include <rtems/score/sh_io.h>
48
49/* from cpu_isps.c */
50extern proc_ptr         _Hardware_isr_Table[];
51
52#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
53  unsigned long    *_old_stack_ptr;
54#endif
55
56register unsigned long  *stack_ptr asm("r15"); 
57
58/*
59 *  _CPU_Context_save_fp_context
60 *
61 *  This routine is responsible for saving the FP context
62 *  at *fp_context_ptr.  If the point to load the FP context
63 *  from is changed then the pointer is modified by this routine.
64 *
65 *  Sometimes a macro implementation of this is in cpu.h which dereferences
66 *  the ** and a similarly named routine in this file is passed something
67 *  like a (Context_Control_fp *).  The general rule on making this decision
68 *  is to avoid writing assembly language.
69 */
70
71void _CPU_Context_save_fp(
72  void **fp_context_ptr     /* r4 */
73)
74{
75#if SH_HAS_FPU
76 
77asm volatile("\n\
78    mov.l   @%0,r4    \n\
79    add     %1,r4\n\
80    sts.l   fpscr,@-r4\n\
81    sts.l   fpul,@-r4\n\
82    lds     %2,fpscr\n\
83    fmov    dr14,@-r4\n\
84    fmov    dr12,@-r4\n\
85    fmov    dr10,@-r4\n\
86    fmov    dr8,@-r4\n\
87    fmov    dr6,@-r4\n\
88    fmov    dr4,@-r4\n\
89    fmov    dr2,@-r4\n\
90    fmov    dr0,@-r4\n\
91    "
92#ifdef SH4_USE_X_REGISTERS
93    "\
94    lds     %3,fpscr\n\
95    fmov    xd14,@-r4\n\
96    fmov    xd12,@-r4\n\
97    fmov    xd10,@-r4\n\
98    fmov    xd8,@-r4\n\
99    fmov    xd6,@-r4\n\
100    fmov    xd4,@-r4\n\
101    fmov    xd2,@-r4\n\
102    fmov    xd0,@-r4\n\
103    " 
104#endif
105   "lds     %4,fpscr\n\
106   "
107    : 
108    : "r"(fp_context_ptr), "r"(sizeof(Context_Control_fp)), 
109      "r"(SH4_FPSCR_SZ), "r"(SH4_FPSCR_PR | SH4_FPSCR_SZ), "r"(SH4_FPSCR_PR)
110    : "r4", "r0");
111
112#endif
113}
114
115/*
116 *  _CPU_Context_restore_fp_context
117 *
118 *  This routine is responsible for restoring the FP context
119 *  at *fp_context_ptr.  If the point to load the FP context
120 *  from is changed then the pointer is modified by this routine.
121 *
122 *  Sometimes a macro implementation of this is in cpu.h which dereferences
123 *  the ** and a similarly named routine in this file is passed something
124 *  like a (Context_Control_fp *).  The general rule on making this decision
125 *  is to avoid writing assembly language.
126 */
127
128void _CPU_Context_restore_fp(
129  void **fp_context_ptr     /* r4 */
130)
131{
132#if SH_HAS_FPU
133
134asm volatile("\n\
135    mov.l   @%0,r4    \n\
136    "
137#ifdef SH4_USE_X_REGISTERS
138    "\n\
139    lds     %1,fpscr\n\
140    fmov    @r4+,xd0\n\
141    fmov    @r4+,xd2\n\
142    fmov    @r4+,xd4\n\
143    fmov    @r4+,xd6\n\
144    fmov    @r4+,xd8\n\
145    fmov    @r4+,xd10\n\
146    fmov    @r4+,xd12\n\
147    fmov    @r4+,xd14\n\
148    "
149#endif
150    "\n\
151    lds     %2,fpscr\n\
152    fmov    @r4+,dr0\n\
153    fmov    @r4+,dr2\n\
154    fmov    @r4+,dr4\n\
155    fmov    @r4+,dr6\n\
156    fmov    @r4+,dr8\n\
157    fmov    @r4+,dr10\n\
158    fmov    @r4+,dr12\n\
159    fmov    @r4+,dr14\n\
160    lds.l   @r4+,fpul\n\
161    lds.l   @r4+,fpscr\n\
162    " : 
163    : "r"(fp_context_ptr), "r"(SH4_FPSCR_PR | SH4_FPSCR_SZ), "r"(SH4_FPSCR_SZ)
164    : "r4", "r0");
165
166#endif
167}
168
169/*  _CPU_Context_switch
170 *
171 *  This routine performs a normal non-FP context switch.
172 */
173
174/*  within __CPU_Context_switch:
175 *  _CPU_Context_switch
176 *  _CPU_Context_restore
177 *
178 *  This routine is generally used only to restart self in an
179 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
180 *
181 * NOTE: It should be safe not to store r4, r5
182 *
183 * NOTE: It is doubtful if r0 is really needed to be stored
184 *
185 * NOTE: gbr is added, but should not be necessary, as it is
186 *      only used globally in this port.
187 */
188
189/*
190 * FIXME: This is an ugly hack, but we wanted to avoid recalculating
191 *        the offset each time Context_Control is changed
192 */
193void __CPU_Context_switch(
194  Context_Control  *run,        /* r4 */
195  Context_Control  *heir        /* r5 */
196)
197{
198
199asm volatile("\n\
200        .global __CPU_Context_switch\n\
201__CPU_Context_switch:\n\
202\n\
203        add     %0,r4\n\
204  \n\
205        stc.l   sr,@-r4\n\
206        stc.l   gbr,@-r4\n\
207        mov.l   r0,@-r4\n\
208        mov.l   r1,@-r4\n\
209        mov.l   r2,@-r4\n\
210        mov.l   r3,@-r4\n\
211\n\
212        mov.l   r6,@-r4\n\
213        mov.l   r7,@-r4\n\
214        mov.l   r8,@-r4\n\
215        mov.l   r9,@-r4\n\
216        mov.l   r10,@-r4\n\
217        mov.l   r11,@-r4\n\
218        mov.l   r12,@-r4\n\
219        mov.l   r13,@-r4\n\
220        mov.l   r14,@-r4\n\
221        sts.l   pr,@-r4\n\
222        sts.l   mach,@-r4\n\
223        sts.l   macl,@-r4\n\
224        mov.l   r15,@-r4\n\
225\n\
226        mov     r5, r4"
227  :: "I" (sizeof(Context_Control))
228  );
229
230  asm volatile("\n\
231        .global __CPU_Context_restore\n\
232__CPU_Context_restore:\n\
233        mov.l   @r4+,r15\n\
234        lds.l   @r4+,macl\n\
235        lds.l   @r4+,mach\n\
236        lds.l   @r4+,pr\n\
237        mov.l   @r4+,r14\n\
238        mov.l   @r4+,r13\n\
239        mov.l   @r4+,r12\n\
240        mov.l   @r4+,r11\n\
241        mov.l   @r4+,r10\n\
242        mov.l   @r4+,r9\n\
243        mov.l   @r4+,r8\n\
244        mov.l   @r4+,r7\n\
245        mov.l   @r4+,r6\n\
246\n\
247        mov.l   @r4+,r3\n\
248        mov.l   @r4+,r2\n\
249        mov.l   @r4+,r1\n\
250        mov.l   @r4+,r0\n\
251        ldc.l   @r4+,gbr\n\
252        ldc.l   @r4+,sr\n\
253\n\
254        rts\n\
255        nop" );
256}
257
258/* 
259 *  This routine provides the RTEMS interrupt management.
260 */
261 
262void __ISR_Handler( unsigned32 vector)
263{
264  register unsigned32 level;
265
266  _CPU_ISR_Disable( level );
267
268  _Thread_Dispatch_disable_level++;
269
270#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
271  if( _ISR_Nest_level == 0 )
272    {
273      /* Install irq stack */
274      _old_stack_ptr = stack_ptr;
275      stack_ptr = _CPU_Interrupt_stack_high;
276    }
277
278#endif
279
280  _ISR_Nest_level++;
281
282  _CPU_ISR_Enable( level );
283
284  /* call isp */
285  if( _ISR_Vector_table[ vector])
286    (*_ISR_Vector_table[ vector ])( vector );
287
288  _CPU_ISR_Disable( level );
289
290  _Thread_Dispatch_disable_level--;
291
292  _ISR_Nest_level--;
293
294#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
295
296  if( _ISR_Nest_level == 0 )
297    /* restore old stack pointer */
298    stack_ptr = _old_stack_ptr; 
299#endif
300
301  _CPU_ISR_Enable( level );
302
303  if ( _ISR_Nest_level )
304    return;
305
306  if ( _Thread_Dispatch_disable_level ) {
307    _ISR_Signals_to_thread_executing = FALSE;
308    return;
309  }
310
311  if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) {
312    _ISR_Signals_to_thread_executing = FALSE;
313    _Thread_Dispatch();
314  }
315}
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